drivers/gpu/drm/v3d/v3d_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D Graphics Driver
   6  *
   7  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
   8  * For V3D 2.x support, see the VC4 driver.
   9  *
  10  * The V3D GPU includes a tiled render (composed of a bin and render
  11  * pipelines), the TFU (texture formatting unit), and the CSD (compute
  12  * shader dispatch).
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/sched/clock.h>
  23 #include <linux/reset.h>
  24
  25 #include <drm/drm_drv.h>
  26 #include <drm/drm_managed.h>
  27 #include <uapi/drm/v3d_drm.h>
  28
  29 #include "v3d_drv.h"
  30 #include "v3d_regs.h"
  31
  32 #define DRIVER_NAME "v3d"
  33 #define DRIVER_DESC "Broadcom V3D graphics"
  34 #define DRIVER_DATE "20180419"
  35 #define DRIVER_MAJOR 1
  36 #define DRIVER_MINOR 0
  37 #define DRIVER_PATCHLEVEL 0
  38
  39 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
  40                                struct drm_file *file_priv)
  41 {
  42         struct v3d_dev *v3d = to_v3d_dev(dev);
  43         struct drm_v3d_get_param *args = data;
  44         static const u32 reg_map[] = {
  45                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
  46                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
  47                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
  48                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
  49                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
  50                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
  51                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
  52         };
  53
  54         if (args->pad != 0)
  55                 return -EINVAL;
  56
  57         /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
  58          * to explicitly allow it in the "the register in our
  59          * parameter map" check.
  60          */
  61         if (args->param < ARRAY_SIZE(reg_map) &&
  62             (reg_map[args->param] ||
  63              args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
  64                 u32 offset = reg_map[args->param];
  65
  66                 if (args->value != 0)
  67                         return -EINVAL;
  68
  69                 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
  70                     args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
  71                         args->value = V3D_CORE_READ(0, offset);
  72                 } else {
  73                         args->value = V3D_READ(offset);
  74                 }
  75                 return 0;
  76         }
  77
  78         switch (args->param) {
  79         case DRM_V3D_PARAM_SUPPORTS_TFU:
  80                 args->value = 1;
  81                 return 0;
  82         case DRM_V3D_PARAM_SUPPORTS_CSD:
  83                 args->value = v3d_has_csd(v3d);
  84                 return 0;
  85         case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
  86                 args->value = 1;
  87                 return 0;
  88         case DRM_V3D_PARAM_SUPPORTS_PERFMON:
  89                 args->value = (v3d->ver >= 40);
  90                 return 0;
  91         case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
  92                 args->value = 1;
  93                 return 0;
  94         case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE:
  95                 args->value = 1;
  96                 return 0;
  97         case DRM_V3D_PARAM_MAX_PERF_COUNTERS:
  98                 args->value = v3d->max_counters;
  99                 return 0;
 100         default:
 101                 DRM_DEBUG("Unknown parameter %d\n", args->param);
 102                 return -EINVAL;
 103         }
 104 }
 105
 106 static int
 107 v3d_open(struct drm_device *dev, struct drm_file *file)
 108 {
 109         struct v3d_dev *v3d = to_v3d_dev(dev);
 110         struct v3d_file_priv *v3d_priv;
 111         struct drm_gpu_scheduler *sched;
 112         int i;
 113
 114         v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
 115         if (!v3d_priv)
 116                 return -ENOMEM;
 117
 118         v3d_priv->v3d = v3d;
 119
 120         for (i = 0; i < V3D_MAX_QUEUES; i++) {
 121                 sched = &v3d->queue[i].sched;
 122                 drm_sched_entity_init(&v3d_priv->sched_entity[i],
 123                                       DRM_SCHED_PRIORITY_NORMAL, &sched,
 124                                       1, NULL);
 125
 126                 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i]));
 127                 seqcount_init(&v3d_priv->stats[i].lock);
 128         }
 129
 130         v3d_perfmon_open_file(v3d_priv);
 131         file->driver_priv = v3d_priv;
 132
 133         return 0;
 134 }
 135
 136 static void
 137 v3d_postclose(struct drm_device *dev, struct drm_file *file)
 138 {
 139         struct v3d_file_priv *v3d_priv = file->driver_priv;
 140         enum v3d_queue q;
 141
 142         for (q = 0; q < V3D_MAX_QUEUES; q++)
 143                 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
 144
 145         v3d_perfmon_close_file(v3d_priv);
 146         kfree(v3d_priv);
 147 }
 148
 149 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp,
 150                    u64 *active_runtime, u64 *jobs_completed)
 151 {
 152         unsigned int seq;
 153
 154         do {
 155                 seq = read_seqcount_begin(&stats->lock);
 156                 *active_runtime = stats->enabled_ns;
 157                 if (stats->start_ns)
 158                         *active_runtime += timestamp - stats->start_ns;
 159                 *jobs_completed = stats->jobs_completed;
 160         } while (read_seqcount_retry(&stats->lock, seq));
 161 }
 162
 163 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file)
 164 {
 165         struct v3d_file_priv *file_priv = file->driver_priv;
 166         u64 timestamp = local_clock();
 167         enum v3d_queue queue;
 168
 169         for (queue = 0; queue < V3D_MAX_QUEUES; queue++) {
 170                 struct v3d_stats *stats = &file_priv->stats[queue];
 171                 u64 active_runtime, jobs_completed;
 172
 173                 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed);
 174
 175                 /* Note that, in case of a GPU reset, the time spent during an
 176                  * attempt of executing the job is not computed in the runtime.
 177                  */
 178                 drm_printf(p, "drm-engine-%s: \t%llu ns\n",
 179                            v3d_queue_to_string(queue), active_runtime);
 180
 181                 /* Note that we only count jobs that completed. Therefore, jobs
 182                  * that were resubmitted due to a GPU reset are not computed.
 183                  */
 184                 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n",
 185                            v3d_queue_to_string(queue), jobs_completed);
 186         }
 187 }
 188
 189 static const struct file_operations v3d_drm_fops = {
 190         .owner = THIS_MODULE,
 191         DRM_GEM_FOPS,
 192         .show_fdinfo = drm_show_fdinfo,
 193 };
 194
 195 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
 196  * protection between clients.  Note that render nodes would be
 197  * able to submit CLs that could access BOs from clients authenticated
 198  * with the master node.  The TFU doesn't use the GMP, so it would
 199  * need to stay DRM_AUTH until we do buffer size/offset validation.
 200  */
 201 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
 202         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 203         DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
 204         DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
 205         DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
 206         DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
 207         DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
 208         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 209         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 210         DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
 211         DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
 212         DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
 213         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 214         DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW),
 215 };
 216
 217 static const struct drm_driver v3d_drm_driver = {
 218         .driver_features = (DRIVER_GEM |
 219                             DRIVER_RENDER |
 220                             DRIVER_SYNCOBJ),
 221
 222         .open = v3d_open,
 223         .postclose = v3d_postclose,
 224
 225 #if defined(CONFIG_DEBUG_FS)
 226         .debugfs_init = v3d_debugfs_init,
 227 #endif
 228
 229         .gem_create_object = v3d_create_object,
 230         .gem_prime_import_sg_table = v3d_prime_import_sg_table,
 231
 232         .ioctls = v3d_drm_ioctls,
 233         .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
 234         .fops = &v3d_drm_fops,
 235         .show_fdinfo = v3d_show_fdinfo,
 236
 237         .name = DRIVER_NAME,
 238         .desc = DRIVER_DESC,
 239         .date = DRIVER_DATE,
 240         .major = DRIVER_MAJOR,
 241         .minor = DRIVER_MINOR,
 242         .patchlevel = DRIVER_PATCHLEVEL,
 243 };
 244
 245 static const struct of_device_id v3d_of_match[] = {
 246         { .compatible = "brcm,2711-v3d" },
 247         { .compatible = "brcm,2712-v3d" },
 248         { .compatible = "brcm,7268-v3d" },
 249         { .compatible = "brcm,7278-v3d" },
 250         {},
 251 };
 252 MODULE_DEVICE_TABLE(of, v3d_of_match);
 253
 254 static int
 255 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
 256 {
 257         *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);
 258         return PTR_ERR_OR_ZERO(*regs);
 259 }
 260
 261 static int v3d_platform_drm_probe(struct platform_device *pdev)
 262 {
 263         struct device *dev = &pdev->dev;
 264         struct drm_device *drm;
 265         struct v3d_dev *v3d;
 266         int ret;
 267         u32 mmu_debug;
 268         u32 ident1, ident3;
 269         u64 mask;
 270
 271         v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
 272         if (IS_ERR(v3d))
 273                 return PTR_ERR(v3d);
 274
 275         drm = &v3d->drm;
 276
 277         platform_set_drvdata(pdev, drm);
 278
 279         ret = map_regs(v3d, &v3d->hub_regs, "hub");
 280         if (ret)
 281                 return ret;
 282
 283         ret = map_regs(v3d, &v3d->core_regs[0], "core0");
 284         if (ret)
 285                 return ret;
 286
 287         mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
 288         mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
 289         ret = dma_set_mask_and_coherent(dev, mask);
 290         if (ret)
 291                 return ret;
 292
 293         v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
 294
 295         ident1 = V3D_READ(V3D_HUB_IDENT1);
 296         v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 297                     V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
 298         v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 299         WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
 300
 301         ident3 = V3D_READ(V3D_HUB_IDENT3);
 302         v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV);
 303
 304         if (v3d->ver >= 71)
 305                 v3d->max_counters = V3D_V71_NUM_PERFCOUNTERS;
 306         else if (v3d->ver >= 42)
 307                 v3d->max_counters = V3D_V42_NUM_PERFCOUNTERS;
 308         else
 309                 v3d->max_counters = 0;
 310
 311         v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
 312         if (IS_ERR(v3d->reset)) {
 313                 ret = PTR_ERR(v3d->reset);
 314
 315                 if (ret == -EPROBE_DEFER)
 316                         return ret;
 317
 318                 v3d->reset = NULL;
 319                 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
 320                 if (ret) {
 321                         dev_err(dev,
 322                                 "Failed to get reset control or bridge regs\n");
 323                         return ret;
 324                 }
 325         }
 326
 327         if (v3d->ver < 41) {
 328                 ret = map_regs(v3d, &v3d->gca_regs, "gca");
 329                 if (ret)
 330                         return ret;
 331         }
 332
 333         v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
 334                                         GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 335         if (!v3d->mmu_scratch) {
 336                 dev_err(dev, "Failed to allocate MMU scratch page\n");
 337                 return -ENOMEM;
 338         }
 339
 340         ret = v3d_gem_init(drm);
 341         if (ret)
 342                 goto dma_free;
 343
 344         ret = v3d_irq_init(v3d);
 345         if (ret)
 346                 goto gem_destroy;
 347
 348         ret = drm_dev_register(drm, 0);
 349         if (ret)
 350                 goto irq_disable;
 351
 352         ret = v3d_sysfs_init(dev);
 353         if (ret)
 354                 goto drm_unregister;
 355
 356         return 0;
 357
 358 drm_unregister:
 359         drm_dev_unregister(drm);
 360 irq_disable:
 361         v3d_irq_disable(v3d);
 362 gem_destroy:
 363         v3d_gem_destroy(drm);
 364 dma_free:
 365         dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 366         return ret;
 367 }
 368
 369 static void v3d_platform_drm_remove(struct platform_device *pdev)
 370 {
 371         struct drm_device *drm = platform_get_drvdata(pdev);
 372         struct v3d_dev *v3d = to_v3d_dev(drm);
 373         struct device *dev = &pdev->dev;
 374
 375         v3d_sysfs_destroy(dev);
 376
 377         drm_dev_unregister(drm);
 378
 379         v3d_gem_destroy(drm);
 380
 381         dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
 382                     v3d->mmu_scratch_paddr);
 383 }
 384
 385 static struct platform_driver v3d_platform_driver = {
 386         .probe          = v3d_platform_drm_probe,
 387         .remove_new     = v3d_platform_drm_remove,
 388         .driver         = {
 389                 .name   = "v3d",
 390                 .of_match_table = v3d_of_match,
 391         },
 392 };
 393
 394 module_platform_driver(v3d_platform_driver);
 395
 396 MODULE_ALIAS("platform:v3d-drm");
 397 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
 398 MODULE_AUTHOR("Eric Anholt <[email protected]>");
 399 MODULE_LICENSE("GPL v2");