drivers/gpu/drm/bridge/ite-it6505.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bits.h>
   6 #include <linux/debugfs.h>
   7 #include <linux/delay.h>
   8 #include <linux/device.h>
   9 #include <linux/err.h>
  10 #include <linux/extcon.h>
  11 #include <linux/fs.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/i2c.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/types.h>
  21 #include <linux/wait.h>
  22
  23 #include <crypto/hash.h>
  24
  25 #include <drm/display/drm_dp_helper.h>
  26 #include <drm/display/drm_hdcp_helper.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_bridge.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33
  34 #include <sound/hdmi-codec.h>
  35
  36 #define REG_IC_VER 0x04
  37
  38 #define REG_RESET_CTRL 0x05
  39 #define VIDEO_RESET BIT(0)
  40 #define AUDIO_RESET BIT(1)
  41 #define ALL_LOGIC_RESET BIT(2)
  42 #define AUX_RESET BIT(3)
  43 #define HDCP_RESET BIT(4)
  44
  45 #define INT_STATUS_01 0x06
  46 #define INT_MASK_01 0x09
  47 #define INT_HPD_CHANGE 0
  48 #define INT_RECEIVE_HPD_IRQ 1
  49 #define INT_SCDT_CHANGE 2
  50 #define INT_HDCP_FAIL 3
  51 #define INT_HDCP_DONE 4
  52 #define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
  53 #define BIT_INT_HPD INT_HPD_CHANGE
  54 #define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
  55 #define BIT_INT_SCDT INT_SCDT_CHANGE
  56 #define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
  57 #define BIT_INT_HDCP_DONE INT_HDCP_DONE
  58
  59 #define INT_STATUS_02 0x07
  60 #define INT_MASK_02 0x0A
  61 #define INT_AUX_CMD_FAIL 0
  62 #define INT_HDCP_KSV_CHECK 1
  63 #define INT_AUDIO_FIFO_ERROR 2
  64 #define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
  65 #define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
  66 #define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
  67
  68 #define INT_STATUS_03 0x08
  69 #define INT_MASK_03 0x0B
  70 #define INT_LINK_TRAIN_FAIL 4
  71 #define INT_VID_FIFO_ERROR 5
  72 #define INT_IO_LATCH_FIFO_OVERFLOW 7
  73 #define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
  74 #define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
  75 #define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
  76
  77 #define REG_SYSTEM_STS 0x0D
  78 #define INT_STS BIT(0)
  79 #define HPD_STS BIT(1)
  80 #define VIDEO_STB BIT(2)
  81
  82 #define REG_LINK_TRAIN_STS 0x0E
  83 #define LINK_STATE_CR BIT(2)
  84 #define LINK_STATE_EQ BIT(3)
  85 #define LINK_STATE_NORP BIT(4)
  86
  87 #define REG_BANK_SEL 0x0F
  88 #define REG_CLK_CTRL0 0x10
  89 #define M_PCLK_DELAY 0x03
  90
  91 #define REG_AUX_OPT 0x11
  92 #define AUX_AUTO_RST BIT(0)
  93 #define AUX_FIX_FREQ BIT(3)
  94
  95 #define REG_DATA_CTRL0 0x12
  96 #define VIDEO_LATCH_EDGE BIT(4)
  97 #define ENABLE_PCLK_COUNTER BIT(7)
  98
  99 #define REG_PCLK_COUNTER_VALUE 0x13
 100
 101 #define REG_501_FIFO_CTRL 0x15
 102 #define RST_501_FIFO BIT(1)
 103
 104 #define REG_TRAIN_CTRL0 0x16
 105 #define FORCE_LBR BIT(0)
 106 #define LANE_COUNT_MASK 0x06
 107 #define LANE_SWAP BIT(3)
 108 #define SPREAD_AMP_5 BIT(4)
 109 #define FORCE_CR_DONE BIT(5)
 110 #define FORCE_EQ_DONE BIT(6)
 111
 112 #define REG_TRAIN_CTRL1 0x17
 113 #define AUTO_TRAIN BIT(0)
 114 #define MANUAL_TRAIN BIT(1)
 115 #define FORCE_RETRAIN BIT(2)
 116
 117 #define REG_AUX_CTRL 0x23
 118 #define CLR_EDID_FIFO BIT(0)
 119 #define AUX_USER_MODE BIT(1)
 120 #define AUX_NO_SEGMENT_WR BIT(6)
 121 #define AUX_EN_FIFO_READ BIT(7)
 122
 123 #define REG_AUX_ADR_0_7 0x24
 124 #define REG_AUX_ADR_8_15 0x25
 125 #define REG_AUX_ADR_16_19 0x26
 126 #define REG_AUX_OUT_DATA0 0x27
 127
 128 #define REG_AUX_CMD_REQ 0x2B
 129 #define AUX_BUSY BIT(5)
 130
 131 #define REG_AUX_DATA_0_7 0x2C
 132 #define REG_AUX_DATA_8_15 0x2D
 133 #define REG_AUX_DATA_16_23 0x2E
 134 #define REG_AUX_DATA_24_31 0x2F
 135
 136 #define REG_AUX_DATA_FIFO 0x2F
 137
 138 #define REG_AUX_ERROR_STS 0x9F
 139 #define M_AUX_REQ_FAIL 0x03
 140
 141 #define REG_HDCP_CTRL1 0x38
 142 #define HDCP_CP_ENABLE BIT(0)
 143
 144 #define REG_HDCP_TRIGGER 0x39
 145 #define HDCP_TRIGGER_START  BIT(0)
 146 #define HDCP_TRIGGER_CPIRQ  BIT(1)
 147 #define HDCP_TRIGGER_KSV_DONE  BIT(4)
 148 #define HDCP_TRIGGER_KSV_FAIL BIT(5)
 149
 150 #define REG_HDCP_CTRL2 0x3A
 151 #define HDCP_AN_SEL BIT(0)
 152 #define HDCP_AN_GEN BIT(1)
 153 #define HDCP_HW_HPDIRQ_ACT BIT(2)
 154 #define HDCP_EN_M0_READ BIT(5)
 155
 156 #define REG_M0_0_7 0x4C
 157 #define REG_AN_0_7 0x4C
 158 #define REG_SP_CTRL0 0x58
 159 #define REG_IP_CTRL1 0x59
 160 #define REG_IP_CTRL2 0x5A
 161
 162 #define REG_LINK_DRV 0x5C
 163 #define DRV_HS BIT(1)
 164
 165 #define REG_DRV_LN_DATA_SEL 0x5D
 166
 167 #define REG_AUX 0x5E
 168
 169 #define REG_VID_BUS_CTRL0 0x60
 170 #define IN_DDR BIT(2)
 171 #define DDR_CD (0x01 << 6)
 172
 173 #define REG_VID_BUS_CTRL1 0x61
 174 #define TX_FIFO_RESET BIT(1)
 175
 176 #define REG_INPUT_CTRL 0xA0
 177 #define INPUT_HSYNC_POL BIT(0)
 178 #define INPUT_VSYNC_POL BIT(2)
 179 #define INPUT_INTERLACED BIT(4)
 180
 181 #define REG_INPUT_HTOTAL 0xA1
 182 #define REG_INPUT_HACTIVE_START 0xA3
 183 #define REG_INPUT_HACTIVE_WIDTH 0xA5
 184 #define REG_INPUT_HFRONT_PORCH 0xA7
 185 #define REG_INPUT_HSYNC_WIDTH 0xA9
 186 #define REG_INPUT_VTOTAL 0xAB
 187 #define REG_INPUT_VACTIVE_START 0xAD
 188 #define REG_INPUT_VACTIVE_WIDTH 0xAF
 189 #define REG_INPUT_VFRONT_PORCH 0xB1
 190 #define REG_INPUT_VSYNC_WIDTH 0xB3
 191
 192 #define REG_AUDIO_SRC_CTRL 0xB8
 193 #define M_AUDIO_I2S_EN 0x0F
 194 #define EN_I2S0 BIT(0)
 195 #define EN_I2S1 BIT(1)
 196 #define EN_I2S2 BIT(2)
 197 #define EN_I2S3 BIT(3)
 198 #define AUDIO_FIFO_RESET BIT(7)
 199
 200 #define REG_AUDIO_FMT 0xB9
 201 #define REG_AUDIO_FIFO_SEL 0xBA
 202
 203 #define REG_AUDIO_CTRL0 0xBB
 204 #define AUDIO_FULL_PKT BIT(4)
 205 #define AUDIO_16B_BOUND BIT(5)
 206
 207 #define REG_AUDIO_CTRL1 0xBC
 208 #define REG_AUDIO_INPUT_FREQ 0xBE
 209
 210 #define REG_IEC958_STS0 0xBF
 211 #define REG_IEC958_STS1 0xC0
 212 #define REG_IEC958_STS2 0xC1
 213 #define REG_IEC958_STS3 0xC2
 214 #define REG_IEC958_STS4 0xC3
 215
 216 #define REG_HPD_IRQ_TIME 0xC9
 217 #define REG_AUX_DEBUG_MODE 0xCA
 218 #define REG_AUX_OPT2 0xCB
 219 #define REG_HDCP_OPT 0xCE
 220 #define REG_USER_DRV_PRE 0xCF
 221
 222 #define REG_DATA_MUTE_CTRL 0xD3
 223 #define ENABLE_ENHANCED_FRAME BIT(0)
 224 #define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
 225 #define EN_VID_MUTE BIT(4)
 226 #define EN_AUD_MUTE BIT(5)
 227
 228 #define REG_TIME_STMP_CTRL 0xD4
 229 #define EN_ENHANCE_VID_STMP BIT(0)
 230 #define EN_ENHANCE_AUD_STMP BIT(2)
 231 #define M_STAMP_STEP 0x30
 232 #define EN_SSC_GAT BIT(6)
 233
 234 #define REG_INFOFRAME_CTRL 0xE8
 235 #define EN_AVI_PKT BIT(0)
 236 #define EN_AUD_PKT BIT(1)
 237 #define EN_MPG_PKT BIT(2)
 238 #define EN_GEN_PKT BIT(3)
 239 #define EN_VID_TIME_STMP BIT(4)
 240 #define EN_AUD_TIME_STMP BIT(5)
 241 #define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
 242 #define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
 243
 244 #define REG_AUDIO_N_0_7 0xDE
 245 #define REG_AUDIO_N_8_15 0xDF
 246 #define REG_AUDIO_N_16_23 0xE0
 247
 248 #define REG_AVI_INFO_DB1 0xE9
 249 #define REG_AVI_INFO_DB2 0xEA
 250 #define REG_AVI_INFO_DB3 0xEB
 251 #define REG_AVI_INFO_DB4 0xEC
 252 #define REG_AVI_INFO_DB5 0xED
 253 #define REG_AVI_INFO_SUM 0xF6
 254
 255 #define REG_AUD_INFOFRAM_DB1 0xF7
 256 #define REG_AUD_INFOFRAM_DB2 0xF8
 257 #define REG_AUD_INFOFRAM_DB3 0xF9
 258 #define REG_AUD_INFOFRAM_DB4 0xFA
 259 #define REG_AUD_INFOFRAM_SUM 0xFB
 260
 261 /* the following six registers are in bank1 */
 262 #define REG_DRV_0_DB_800_MV 0x17E
 263 #define REG_PRE_0_DB_800_MV 0x17F
 264 #define REG_PRE_3P5_DB_800_MV 0x181
 265 #define REG_SSC_CTRL0 0x188
 266 #define REG_SSC_CTRL1 0x189
 267 #define REG_SSC_CTRL2 0x18A
 268
 269 #define RBR DP_LINK_BW_1_62
 270 #define HBR DP_LINK_BW_2_7
 271 #define HBR2 DP_LINK_BW_5_4
 272 #define HBR3 DP_LINK_BW_8_1
 273
 274 #define DPCD_V_1_1 0x11
 275 #define MISC_VERB 0xF0
 276 #define MISC_VERC 0x70
 277 #define I2S_INPUT_FORMAT_STANDARD 0
 278 #define I2S_INPUT_FORMAT_32BIT 1
 279 #define I2S_INPUT_LEFT_JUSTIFIED 0
 280 #define I2S_INPUT_RIGHT_JUSTIFIED 1
 281 #define I2S_DATA_1T_DELAY 0
 282 #define I2S_DATA_NO_DELAY 1
 283 #define I2S_WS_LEFT_CHANNEL 0
 284 #define I2S_WS_RIGHT_CHANNEL 1
 285 #define I2S_DATA_MSB_FIRST 0
 286 #define I2S_DATA_LSB_FIRST 1
 287 #define WORD_LENGTH_16BIT 0
 288 #define WORD_LENGTH_18BIT 1
 289 #define WORD_LENGTH_20BIT 2
 290 #define WORD_LENGTH_24BIT 3
 291 #define DEBUGFS_DIR_NAME "it6505-debugfs"
 292 #define READ_BUFFER_SIZE 400
 293
 294 /* Vendor option */
 295 #define HDCP_DESIRED 1
 296 #define MAX_LANE_COUNT 4
 297 #define MAX_LINK_RATE HBR
 298 #define AUTO_TRAIN_RETRY 3
 299 #define MAX_HDCP_DOWN_STREAM_COUNT 10
 300 #define MAX_CR_LEVEL 0x03
 301 #define MAX_EQ_LEVEL 0x03
 302 #define AUX_WAIT_TIMEOUT_MS 15
 303 #define AUX_FIFO_MAX_SIZE 32
 304 #define PIXEL_CLK_DELAY 1
 305 #define PIXEL_CLK_INVERSE 0
 306 #define ADJUST_PHASE_THRESHOLD 80000
 307 #define DPI_PIXEL_CLK_MAX 95000
 308 #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
 309 #define DEFAULT_PWR_ON 0
 310 #define DEFAULT_DRV_HOLD 0
 311
 312 #define AUDIO_SELECT I2S
 313 #define AUDIO_TYPE LPCM
 314 #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
 315 #define AUDIO_CHANNEL_COUNT 2
 316 #define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
 317 #define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
 318 #define I2S_DATA_DELAY I2S_DATA_1T_DELAY
 319 #define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
 320 #define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
 321 #define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
 322
 323 enum aux_cmd_type {
 324         CMD_AUX_NATIVE_READ = 0x0,
 325         CMD_AUX_NATIVE_WRITE = 0x5,
 326         CMD_AUX_I2C_EDID_READ = 0xB,
 327 };
 328
 329 enum aux_cmd_reply {
 330         REPLY_ACK,
 331         REPLY_NACK,
 332         REPLY_DEFER,
 333 };
 334
 335 enum link_train_status {
 336         LINK_IDLE,
 337         LINK_BUSY,
 338         LINK_OK,
 339 };
 340
 341 enum hdcp_state {
 342         HDCP_AUTH_IDLE,
 343         HDCP_AUTH_GOING,
 344         HDCP_AUTH_DONE,
 345 };
 346
 347 struct it6505_platform_data {
 348         struct regulator *pwr18;
 349         struct regulator *ovdd;
 350         struct gpio_desc *gpiod_reset;
 351 };
 352
 353 enum it6505_audio_select {
 354         I2S = 0,
 355         SPDIF,
 356 };
 357
 358 enum it6505_audio_sample_rate {
 359         SAMPLE_RATE_24K = 0x6,
 360         SAMPLE_RATE_32K = 0x3,
 361         SAMPLE_RATE_48K = 0x2,
 362         SAMPLE_RATE_96K = 0xA,
 363         SAMPLE_RATE_192K = 0xE,
 364         SAMPLE_RATE_44_1K = 0x0,
 365         SAMPLE_RATE_88_2K = 0x8,
 366         SAMPLE_RATE_176_4K = 0xC,
 367 };
 368
 369 enum it6505_audio_type {
 370         LPCM = 0,
 371         NLPCM,
 372         DSS,
 373 };
 374
 375 struct it6505_audio_data {
 376         enum it6505_audio_select select;
 377         enum it6505_audio_sample_rate sample_rate;
 378         enum it6505_audio_type type;
 379         u8 word_length;
 380         u8 channel_count;
 381         u8 i2s_input_format;
 382         u8 i2s_justified;
 383         u8 i2s_data_delay;
 384         u8 i2s_ws_channel;
 385         u8 i2s_data_sequence;
 386 };
 387
 388 struct it6505_audio_sample_rate_map {
 389         enum it6505_audio_sample_rate rate;
 390         int sample_rate_value;
 391 };
 392
 393 struct it6505_drm_dp_link {
 394         unsigned char revision;
 395         unsigned int rate;
 396         unsigned int num_lanes;
 397         unsigned long capabilities;
 398 };
 399
 400 struct debugfs_entries {
 401         char *name;
 402         const struct file_operations *fops;
 403 };
 404
 405 struct it6505 {
 406         struct drm_dp_aux aux;
 407         struct drm_bridge bridge;
 408         struct device *dev;
 409         struct it6505_drm_dp_link link;
 410         struct it6505_platform_data pdata;
 411         /*
 412          * Mutex protects extcon and interrupt functions from interfering
 413          * each other.
 414          */
 415         struct mutex extcon_lock;
 416         struct mutex mode_lock; /* used to bridge_detect */
 417         struct mutex aux_lock; /* used to aux data transfers */
 418         struct regmap *regmap;
 419         struct drm_display_mode source_output_mode;
 420         struct drm_display_mode video_info;
 421         struct notifier_block event_nb;
 422         struct extcon_dev *extcon;
 423         struct work_struct extcon_wq;
 424         int extcon_state;
 425         enum drm_connector_status connector_status;
 426         enum link_train_status link_state;
 427         struct work_struct link_works;
 428         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 429         u8 lane_count;
 430         u8 link_rate_bw_code;
 431         u8 sink_count;
 432         bool step_train;
 433         bool branch_device;
 434         bool enable_ssc;
 435         bool lane_swap_disabled;
 436         bool lane_swap;
 437         bool powered;
 438         bool hpd_state;
 439         u32 afe_setting;
 440         u32 max_dpi_pixel_clock;
 441         u32 max_lane_count;
 442         enum hdcp_state hdcp_status;
 443         struct delayed_work hdcp_work;
 444         struct work_struct hdcp_wait_ksv_list;
 445         struct completion extcon_completion;
 446         u8 auto_train_retry;
 447         bool hdcp_desired;
 448         bool is_repeater;
 449         u8 hdcp_down_stream_count;
 450         u8 bksvs[DRM_HDCP_KSV_LEN];
 451         u8 sha1_input[HDCP_SHA1_FIFO_LEN];
 452         bool enable_enhanced_frame;
 453         hdmi_codec_plugged_cb plugged_cb;
 454         struct device *codec_dev;
 455         struct delayed_work delayed_audio;
 456         struct it6505_audio_data audio;
 457         struct dentry *debugfs;
 458
 459         /* it6505 driver hold option */
 460         bool enable_drv_hold;
 461
 462         const struct drm_edid *cached_edid;
 463 };
 464
 465 struct it6505_step_train_para {
 466         u8 voltage_swing[MAX_LANE_COUNT];
 467         u8 pre_emphasis[MAX_LANE_COUNT];
 468 };
 469
 470 /*
 471  * Vendor option afe settings for different platforms
 472  * 0: without FPC cable
 473  * 1: with FPC cable
 474  */
 475
 476 static const u8 afe_setting_table[][3] = {
 477         {0x82, 0x00, 0x45},
 478         {0x93, 0x2A, 0x85}
 479 };
 480
 481 static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
 482         {SAMPLE_RATE_24K, 24000},
 483         {SAMPLE_RATE_32K, 32000},
 484         {SAMPLE_RATE_48K, 48000},
 485         {SAMPLE_RATE_96K, 96000},
 486         {SAMPLE_RATE_192K, 192000},
 487         {SAMPLE_RATE_44_1K, 44100},
 488         {SAMPLE_RATE_88_2K, 88200},
 489         {SAMPLE_RATE_176_4K, 176400},
 490 };
 491
 492 static const struct regmap_range it6505_bridge_volatile_ranges[] = {
 493         { .range_min = 0, .range_max = 0x1FF },
 494 };
 495
 496 static const struct regmap_access_table it6505_bridge_volatile_table = {
 497         .yes_ranges = it6505_bridge_volatile_ranges,
 498         .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
 499 };
 500
 501 static const struct regmap_range_cfg it6505_regmap_banks[] = {
 502         {
 503                 .name = "it6505",
 504                 .range_min = 0x00,
 505                 .range_max = 0x1FF,
 506                 .selector_reg = REG_BANK_SEL,
 507                 .selector_mask = 0x1,
 508                 .selector_shift = 0,
 509                 .window_start = 0x00,
 510                 .window_len = 0x100,
 511         },
 512 };
 513
 514 static const struct regmap_config it6505_regmap_config = {
 515         .reg_bits = 8,
 516         .val_bits = 8,
 517         .volatile_table = &it6505_bridge_volatile_table,
 518         .cache_type = REGCACHE_NONE,
 519         .ranges = it6505_regmap_banks,
 520         .num_ranges = ARRAY_SIZE(it6505_regmap_banks),
 521         .max_register = 0x1FF,
 522 };
 523
 524 static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
 525 {
 526         unsigned int value;
 527         int err;
 528         struct device *dev = it6505->dev;
 529
 530         if (!it6505->powered)
 531                 return -ENODEV;
 532
 533         err = regmap_read(it6505->regmap, reg_addr, &value);
 534         if (err < 0) {
 535                 dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
 536                 return err;
 537         }
 538
 539         return value;
 540 }
 541
 542 static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
 543                         unsigned int reg_val)
 544 {
 545         int err;
 546         struct device *dev = it6505->dev;
 547
 548         if (!it6505->powered)
 549                 return -ENODEV;
 550
 551         err = regmap_write(it6505->regmap, reg_addr, reg_val);
 552
 553         if (err < 0) {
 554                 dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
 555                         reg_addr, reg_val, err);
 556                 return err;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
 563                            unsigned int mask, unsigned int value)
 564 {
 565         int err;
 566         struct device *dev = it6505->dev;
 567
 568         if (!it6505->powered)
 569                 return -ENODEV;
 570
 571         err = regmap_update_bits(it6505->regmap, reg, mask, value);
 572         if (err < 0) {
 573                 dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
 574                         reg, value, mask, err);
 575                 return err;
 576         }
 577
 578         return 0;
 579 }
 580
 581 static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
 582                                const char *prefix)
 583 {
 584         struct device *dev = it6505->dev;
 585         int val;
 586
 587         if (!drm_debug_enabled(DRM_UT_DRIVER))
 588                 return;
 589
 590         val = it6505_read(it6505, reg);
 591         if (val < 0)
 592                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
 593                                      prefix, reg, val);
 594         else
 595                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
 596                                      val);
 597 }
 598
 599 static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
 600 {
 601         u8 value;
 602         int ret;
 603         struct device *dev = it6505->dev;
 604
 605         ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
 606         if (ret < 0) {
 607                 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
 608                 return ret;
 609         }
 610         return value;
 611 }
 612
 613 static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
 614                              u8 datain)
 615 {
 616         int ret;
 617         struct device *dev = it6505->dev;
 618
 619         ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
 620         if (ret < 0) {
 621                 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
 622                 return ret;
 623         }
 624         return 0;
 625 }
 626
 627 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
 628 {
 629         int ret;
 630         struct device *dev = it6505->dev;
 631
 632         ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
 633
 634         if (ret < 0)
 635                 return ret;
 636
 637         DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
 638                              num, dpcd);
 639
 640         return 0;
 641 }
 642
 643 static void it6505_dump(struct it6505 *it6505)
 644 {
 645         unsigned int i, j;
 646         u8 regs[16];
 647         struct device *dev = it6505->dev;
 648
 649         for (i = 0; i <= 0xff; i += 16) {
 650                 for (j = 0; j < 16; j++)
 651                         regs[j] = it6505_read(it6505, i + j);
 652
 653                 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
 654         }
 655 }
 656
 657 static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
 658 {
 659         int reg_0d;
 660
 661         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
 662
 663         if (reg_0d < 0)
 664                 return false;
 665
 666         return reg_0d & HPD_STS;
 667 }
 668
 669 static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
 670 {
 671         int val0, val1;
 672
 673         val0 = it6505_read(it6505, reg);
 674         if (val0 < 0)
 675                 return val0;
 676
 677         val1 = it6505_read(it6505, reg + 1);
 678         if (val1 < 0)
 679                 return val1;
 680
 681         return (val1 << 8) | val0;
 682 }
 683
 684 static void it6505_calc_video_info(struct it6505 *it6505)
 685 {
 686         struct device *dev = it6505->dev;
 687         int hsync_pol, vsync_pol, interlaced;
 688         int htotal, hdes, hdew, hfph, hsyncw;
 689         int vtotal, vdes, vdew, vfph, vsyncw;
 690         int rddata, i, pclk, sum = 0;
 691
 692         usleep_range(10000, 15000);
 693         rddata = it6505_read(it6505, REG_INPUT_CTRL);
 694         hsync_pol = rddata & INPUT_HSYNC_POL;
 695         vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
 696         interlaced = (rddata & INPUT_INTERLACED) >> 4;
 697
 698         htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
 699         hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
 700         hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
 701         hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
 702         hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
 703
 704         vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
 705         vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
 706         vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
 707         vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
 708         vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
 709
 710         DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
 711                              hsync_pol, vsync_pol, interlaced);
 712         DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
 713                              hdes, vdes);
 714
 715         for (i = 0; i < 3; i++) {
 716                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 717                                 ENABLE_PCLK_COUNTER);
 718                 usleep_range(10000, 15000);
 719                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 720                                 0x00);
 721                 rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
 722                          0xFFF;
 723
 724                 sum += rddata;
 725         }
 726
 727         if (sum == 0) {
 728                 DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
 729                 return;
 730         }
 731
 732         sum /= 3;
 733         pclk = 13500 * 2048 / sum;
 734         it6505->video_info.clock = pclk;
 735         it6505->video_info.hdisplay = hdew;
 736         it6505->video_info.hsync_start = hdew + hfph;
 737         it6505->video_info.hsync_end = hdew + hfph + hsyncw;
 738         it6505->video_info.htotal = htotal;
 739         it6505->video_info.vdisplay = vdew;
 740         it6505->video_info.vsync_start = vdew + vfph;
 741         it6505->video_info.vsync_end = vdew + vfph + vsyncw;
 742         it6505->video_info.vtotal = vtotal;
 743
 744         DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
 745                              DRM_MODE_ARG(&it6505->video_info));
 746 }
 747
 748 static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
 749                                         struct it6505_drm_dp_link *link,
 750                                         u8 mode)
 751 {
 752         u8 value;
 753         int err;
 754
 755         /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 756         if (link->revision < DPCD_V_1_1)
 757                 return 0;
 758
 759         err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 760         if (err < 0)
 761                 return err;
 762
 763         value &= ~DP_SET_POWER_MASK;
 764         value |= mode;
 765
 766         err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 767         if (err < 0)
 768                 return err;
 769
 770         if (mode == DP_SET_POWER_D0) {
 771                 /*
 772                  * According to the DP 1.1 specification, a "Sink Device must
 773                  * exit the power saving state within 1 ms" (Section 2.5.3.1,
 774                  * Table 5-52, "Sink Control Field" (register 0x600).
 775                  */
 776                 usleep_range(1000, 2000);
 777         }
 778
 779         return 0;
 780 }
 781
 782 static void it6505_clear_int(struct it6505 *it6505)
 783 {
 784         it6505_write(it6505, INT_STATUS_01, 0xFF);
 785         it6505_write(it6505, INT_STATUS_02, 0xFF);
 786         it6505_write(it6505, INT_STATUS_03, 0xFF);
 787 }
 788
 789 static void it6505_int_mask_enable(struct it6505 *it6505)
 790 {
 791         it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
 792                      BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
 793                      BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
 794
 795         it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
 796                      BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
 797
 798         it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
 799                      BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
 800 }
 801
 802 static void it6505_int_mask_disable(struct it6505 *it6505)
 803 {
 804         it6505_write(it6505, INT_MASK_01, 0x00);
 805         it6505_write(it6505, INT_MASK_02, 0x00);
 806         it6505_write(it6505, INT_MASK_03, 0x00);
 807 }
 808
 809 static void it6505_lane_termination_on(struct it6505 *it6505)
 810 {
 811         int regcf;
 812
 813         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 814
 815         if (regcf == MISC_VERB)
 816                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
 817
 818         if (regcf == MISC_VERC) {
 819                 if (it6505->lane_swap) {
 820                         switch (it6505->lane_count) {
 821                         case 1:
 822                         case 2:
 823                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 824                                                 0x0C, 0x08);
 825                                 break;
 826                         default:
 827                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 828                                                 0x0C, 0x0C);
 829                                 break;
 830                         }
 831                 } else {
 832                         switch (it6505->lane_count) {
 833                         case 1:
 834                         case 2:
 835                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 836                                                 0x0C, 0x04);
 837                                 break;
 838                         default:
 839                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 840                                                 0x0C, 0x0C);
 841                                 break;
 842                         }
 843                 }
 844         }
 845 }
 846
 847 static void it6505_lane_termination_off(struct it6505 *it6505)
 848 {
 849         int regcf;
 850
 851         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 852
 853         if (regcf == MISC_VERB)
 854                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 855
 856         if (regcf == MISC_VERC)
 857                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
 858 }
 859
 860 static void it6505_lane_power_on(struct it6505 *it6505)
 861 {
 862         it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
 863                         (it6505->lane_swap ?
 864                                  GENMASK(7, 8 - it6505->lane_count) :
 865                                  GENMASK(3 + it6505->lane_count, 4)) |
 866                                 0x01);
 867 }
 868
 869 static void it6505_lane_power_off(struct it6505 *it6505)
 870 {
 871         it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
 872 }
 873
 874 static void it6505_lane_off(struct it6505 *it6505)
 875 {
 876         it6505_lane_power_off(it6505);
 877         it6505_lane_termination_off(it6505);
 878 }
 879
 880 static void it6505_aux_termination_on(struct it6505 *it6505)
 881 {
 882         int regcf;
 883
 884         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 885
 886         if (regcf == MISC_VERB)
 887                 it6505_lane_termination_on(it6505);
 888
 889         if (regcf == MISC_VERC)
 890                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 891 }
 892
 893 static void it6505_aux_power_on(struct it6505 *it6505)
 894 {
 895         it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
 896 }
 897
 898 static void it6505_aux_on(struct it6505 *it6505)
 899 {
 900         it6505_aux_power_on(it6505);
 901         it6505_aux_termination_on(it6505);
 902 }
 903
 904 static void it6505_aux_reset(struct it6505 *it6505)
 905 {
 906         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
 907         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
 908 }
 909
 910 static void it6505_reset_logic(struct it6505 *it6505)
 911 {
 912         regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
 913         usleep_range(1000, 1500);
 914 }
 915
 916 static bool it6505_aux_op_finished(struct it6505 *it6505)
 917 {
 918         int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
 919
 920         if (reg2b < 0)
 921                 return false;
 922
 923         return (reg2b & AUX_BUSY) == 0;
 924 }
 925
 926 static int it6505_aux_wait(struct it6505 *it6505)
 927 {
 928         int status;
 929         unsigned long timeout;
 930         struct device *dev = it6505->dev;
 931
 932         timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
 933
 934         while (!it6505_aux_op_finished(it6505)) {
 935                 if (time_after(jiffies, timeout)) {
 936                         dev_err(dev, "Timed out waiting AUX to finish");
 937                         return -ETIMEDOUT;
 938                 }
 939                 usleep_range(1000, 2000);
 940         }
 941
 942         status = it6505_read(it6505, REG_AUX_ERROR_STS);
 943         if (status < 0) {
 944                 dev_err(dev, "Failed to read AUX channel: %d", status);
 945                 return status;
 946         }
 947
 948         return 0;
 949 }
 950
 951 static ssize_t it6505_aux_operation(struct it6505 *it6505,
 952                                     enum aux_cmd_type cmd,
 953                                     unsigned int address, u8 *buffer,
 954                                     size_t size, enum aux_cmd_reply *reply)
 955 {
 956         int i, ret;
 957         bool aux_write_check = false;
 958
 959         if (!it6505_get_sink_hpd_status(it6505))
 960                 return -EIO;
 961
 962         /* set AUX user mode */
 963         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
 964
 965 aux_op_start:
 966         if (cmd == CMD_AUX_I2C_EDID_READ) {
 967                 /* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
 968                 size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
 969                 /* Enable AUX FIFO read back and clear FIFO */
 970                 it6505_set_bits(it6505, REG_AUX_CTRL,
 971                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 972                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
 973
 974                 it6505_set_bits(it6505, REG_AUX_CTRL,
 975                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 976                                 AUX_EN_FIFO_READ);
 977         } else {
 978                 /* The DP AUX transmit buffer has 4 bytes. */
 979                 size = min_t(size_t, size, 4);
 980                 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
 981                                 AUX_NO_SEGMENT_WR);
 982         }
 983
 984         /* Start Address[7:0] */
 985         it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
 986         /* Start Address[15:8] */
 987         it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
 988         /* WriteNum[3:0]+StartAdr[19:16] */
 989         it6505_write(it6505, REG_AUX_ADR_16_19,
 990                      ((address >> 16) & 0x0F) | ((size - 1) << 4));
 991
 992         if (cmd == CMD_AUX_NATIVE_WRITE)
 993                 regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
 994                                   size);
 995
 996         /* Aux Fire */
 997         it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
 998
 999         ret = it6505_aux_wait(it6505);
1000         if (ret < 0)
1001                 goto aux_op_err;
1002
1003         ret = it6505_read(it6505, REG_AUX_ERROR_STS);
1004         if (ret < 0)
1005                 goto aux_op_err;
1006
1007         switch ((ret >> 6) & 0x3) {
1008         case 0:
1009                 *reply = REPLY_ACK;
1010                 break;
1011         case 1:
1012                 *reply = REPLY_DEFER;
1013                 ret = -EAGAIN;
1014                 goto aux_op_err;
1015         case 2:
1016                 *reply = REPLY_NACK;
1017                 ret = -EIO;
1018                 goto aux_op_err;
1019         case 3:
1020                 ret = -ETIMEDOUT;
1021                 goto aux_op_err;
1022         }
1023
1024         /* Read back Native Write data */
1025         if (cmd == CMD_AUX_NATIVE_WRITE) {
1026                 aux_write_check = true;
1027                 cmd = CMD_AUX_NATIVE_READ;
1028                 goto aux_op_start;
1029         }
1030
1031         if (cmd == CMD_AUX_I2C_EDID_READ) {
1032                 for (i = 0; i < size; i++) {
1033                         ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1034                         if (ret < 0)
1035                                 goto aux_op_err;
1036                         buffer[i] = ret;
1037                 }
1038         } else {
1039                 for (i = 0; i < size; i++) {
1040                         ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1041                         if (ret < 0)
1042                                 goto aux_op_err;
1043
1044                         if (aux_write_check && buffer[size - 1 - i] != ret) {
1045                                 ret = -EINVAL;
1046                                 goto aux_op_err;
1047                         }
1048
1049                         buffer[size - 1 - i] = ret;
1050                 }
1051         }
1052
1053         ret = i;
1054
1055 aux_op_err:
1056         if (cmd == CMD_AUX_I2C_EDID_READ) {
1057                 /* clear AUX FIFO */
1058                 it6505_set_bits(it6505, REG_AUX_CTRL,
1059                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1060                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1061                 it6505_set_bits(it6505, REG_AUX_CTRL,
1062                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1063         }
1064
1065         /* Leave AUX user mode */
1066         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1067
1068         return ret;
1069 }
1070
1071 static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1072                                       enum aux_cmd_type cmd,
1073                                       unsigned int address, u8 *buffer,
1074                                       size_t size, enum aux_cmd_reply *reply)
1075 {
1076         int i, ret_size, ret = 0, request_size;
1077
1078         mutex_lock(&it6505->aux_lock);
1079         for (i = 0; i < size; i += 4) {
1080                 request_size = min((int)size - i, 4);
1081                 ret_size = it6505_aux_operation(it6505, cmd, address + i,
1082                                                 buffer + i, request_size,
1083                                                 reply);
1084                 if (ret_size < 0) {
1085                         ret = ret_size;
1086                         goto aux_op_err;
1087                 }
1088
1089                 ret += ret_size;
1090         }
1091
1092 aux_op_err:
1093         mutex_unlock(&it6505->aux_lock);
1094         return ret;
1095 }
1096
1097 static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1098                                    struct drm_dp_aux_msg *msg)
1099 {
1100         struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1101         u8 cmd;
1102         bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1103         int ret;
1104         enum aux_cmd_reply reply;
1105
1106         /* IT6505 doesn't support arbitrary I2C read / write. */
1107         if (is_i2c)
1108                 return -EINVAL;
1109
1110         switch (msg->request) {
1111         case DP_AUX_NATIVE_READ:
1112                 cmd = CMD_AUX_NATIVE_READ;
1113                 break;
1114         case DP_AUX_NATIVE_WRITE:
1115                 cmd = CMD_AUX_NATIVE_WRITE;
1116                 break;
1117         default:
1118                 return -EINVAL;
1119         }
1120
1121         ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1122                                      msg->size, &reply);
1123         if (ret < 0)
1124                 return ret;
1125
1126         switch (reply) {
1127         case REPLY_ACK:
1128                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1129                 break;
1130         case REPLY_NACK:
1131                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1132                 break;
1133         case REPLY_DEFER:
1134                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1135                 break;
1136         }
1137
1138         return ret;
1139 }
1140
1141 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1142                                  size_t len)
1143 {
1144         struct it6505 *it6505 = data;
1145         struct device *dev = it6505->dev;
1146         enum aux_cmd_reply reply;
1147         int offset, ret, aux_retry = 100;
1148
1149         it6505_aux_reset(it6505);
1150         DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1151
1152         for (offset = 0; offset < EDID_LENGTH;) {
1153                 ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1154                                              block * EDID_LENGTH + offset,
1155                                              buf + offset, 8, &reply);
1156
1157                 if (ret < 0 && ret != -EAGAIN)
1158                         return ret;
1159
1160                 switch (reply) {
1161                 case REPLY_ACK:
1162                         DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1163                                              buf + offset);
1164                         offset += 8;
1165                         aux_retry = 100;
1166                         break;
1167                 case REPLY_NACK:
1168                         return -EIO;
1169                 case REPLY_DEFER:
1170                         msleep(20);
1171                         if (!(--aux_retry))
1172                                 return -EIO;
1173                 }
1174         }
1175
1176         return 0;
1177 }
1178
1179 static void it6505_variable_config(struct it6505 *it6505)
1180 {
1181         it6505->link_rate_bw_code = HBR;
1182         it6505->lane_count = MAX_LANE_COUNT;
1183         it6505->link_state = LINK_IDLE;
1184         it6505->hdcp_desired = HDCP_DESIRED;
1185         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1186         it6505->audio.select = AUDIO_SELECT;
1187         it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1188         it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1189         it6505->audio.type = AUDIO_TYPE;
1190         it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1191         it6505->audio.i2s_justified = I2S_JUSTIFIED;
1192         it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1193         it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1194         it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1195         it6505->audio.word_length = AUDIO_WORD_LENGTH;
1196         memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1197         memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1198 }
1199
1200 static int it6505_send_video_infoframe(struct it6505 *it6505,
1201                                        struct hdmi_avi_infoframe *frame)
1202 {
1203         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1204         int err;
1205         struct device *dev = it6505->dev;
1206
1207         err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1208         if (err < 0) {
1209                 dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1210                 return err;
1211         }
1212
1213         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1214         if (err)
1215                 return err;
1216
1217         err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1218                                 buffer + HDMI_INFOFRAME_HEADER_SIZE,
1219                                 frame->length);
1220         if (err)
1221                 return err;
1222
1223         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1224                               EN_AVI_PKT);
1225         if (err)
1226                 return err;
1227
1228         return 0;
1229 }
1230
1231 static void it6505_get_extcon_property(struct it6505 *it6505)
1232 {
1233         int err;
1234         union extcon_property_value property;
1235         struct device *dev = it6505->dev;
1236
1237         if (it6505->extcon && !it6505->lane_swap_disabled) {
1238                 err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1239                                           EXTCON_PROP_USB_TYPEC_POLARITY,
1240                                           &property);
1241                 if (err) {
1242                         dev_err(dev, "get property fail!");
1243                         return;
1244                 }
1245                 it6505->lane_swap = property.intval;
1246         }
1247 }
1248
1249 static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1250                                         const struct drm_display_mode *mode)
1251 {
1252         int clock = mode->clock;
1253
1254         it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1255                         clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1256         it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1257                         PIXEL_CLK_INVERSE << 4);
1258 }
1259
1260 static void it6505_link_reset_step_train(struct it6505 *it6505)
1261 {
1262         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1263                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1264         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1265                           DP_TRAINING_PATTERN_DISABLE);
1266 }
1267
1268 static void it6505_init(struct it6505 *it6505)
1269 {
1270         it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1271         it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1272         it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1273         it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1274         it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1275         it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1276
1277         /* chip internal setting, don't modify */
1278         it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1279         it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1280         it6505_write(it6505, REG_AUX_OPT2, 0x17);
1281         it6505_write(it6505, REG_HDCP_OPT, 0x60);
1282         it6505_write(it6505, REG_DATA_MUTE_CTRL,
1283                      EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1284         it6505_write(it6505, REG_TIME_STMP_CTRL,
1285                      EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1286         it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1287         it6505_write(it6505, REG_DRV_0_DB_800_MV,
1288                      afe_setting_table[it6505->afe_setting][0]);
1289         it6505_write(it6505, REG_PRE_0_DB_800_MV,
1290                      afe_setting_table[it6505->afe_setting][1]);
1291         it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1292                      afe_setting_table[it6505->afe_setting][2]);
1293         it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1294         it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1295         it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1296 }
1297
1298 static void it6505_video_disable(struct it6505 *it6505)
1299 {
1300         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1301         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1302         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1303 }
1304
1305 static void it6505_video_reset(struct it6505 *it6505)
1306 {
1307         it6505_link_reset_step_train(it6505);
1308         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1309         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1310
1311         it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, TX_FIFO_RESET);
1312         it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00);
1313
1314         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1315         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1316
1317         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1318         usleep_range(1000, 2000);
1319         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1320 }
1321
1322 static void it6505_update_video_parameter(struct it6505 *it6505,
1323                                           const struct drm_display_mode *mode)
1324 {
1325         it6505_clk_phase_adjustment(it6505, mode);
1326         it6505_video_disable(it6505);
1327 }
1328
1329 static bool it6505_audio_input(struct it6505 *it6505)
1330 {
1331         int reg05, regbe;
1332
1333         reg05 = it6505_read(it6505, REG_RESET_CTRL);
1334         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1335         usleep_range(3000, 4000);
1336         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1337         it6505_write(it6505, REG_RESET_CTRL, reg05);
1338
1339         return regbe != 0xFF;
1340 }
1341
1342 static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1343 {
1344         enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1345         u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1346
1347         /* Channel Status */
1348         it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1349         it6505_write(it6505, REG_IEC958_STS1, 0x00);
1350         it6505_write(it6505, REG_IEC958_STS2, 0x00);
1351         it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1352         it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1353                      audio_word_length_map[it6505->audio.word_length]);
1354 }
1355
1356 static void it6505_setup_audio_format(struct it6505 *it6505)
1357 {
1358         /* I2S MODE */
1359         it6505_write(it6505, REG_AUDIO_FMT,
1360                      (it6505->audio.word_length << 5) |
1361                      (it6505->audio.i2s_data_sequence << 4) |
1362                      (it6505->audio.i2s_ws_channel << 3) |
1363                      (it6505->audio.i2s_data_delay << 2) |
1364                      (it6505->audio.i2s_justified << 1) |
1365                      it6505->audio.i2s_input_format);
1366         if (it6505->audio.select == SPDIF) {
1367                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1368                 /* 0x30 = 128*FS */
1369                 it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1370         } else {
1371                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1372         }
1373
1374         it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1375         it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1376 }
1377
1378 static void it6505_enable_audio_source(struct it6505 *it6505)
1379 {
1380         unsigned int audio_source_count;
1381
1382         audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1383                                  - 1;
1384
1385         audio_source_count |= it6505->audio.select << 4;
1386
1387         it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1388 }
1389
1390 static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1391 {
1392         struct device *dev = it6505->dev;
1393         u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1394
1395         DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1396                              audio_info_ca[it6505->audio.channel_count - 1]);
1397
1398         it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1399                      - 1);
1400         it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1401         it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1402                      audio_info_ca[it6505->audio.channel_count - 1]);
1403         it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1404         it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1405
1406         /* Enable Audio InfoFrame */
1407         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1408                         EN_AUD_CTRL_PKT);
1409 }
1410
1411 static void it6505_disable_audio(struct it6505 *it6505)
1412 {
1413         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1414         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1415         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1416         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1417 }
1418
1419 static void it6505_enable_audio(struct it6505 *it6505)
1420 {
1421         struct device *dev = it6505->dev;
1422         int regbe;
1423
1424         DRM_DEV_DEBUG_DRIVER(dev, "start");
1425         it6505_disable_audio(it6505);
1426
1427         it6505_setup_audio_channel_status(it6505);
1428         it6505_setup_audio_format(it6505);
1429         it6505_enable_audio_source(it6505);
1430         it6505_enable_audio_infoframe(it6505);
1431
1432         it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1433         it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1434         it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1435
1436         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1437                         AUDIO_FIFO_RESET);
1438         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1439         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1440         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1441         DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1442                              regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1443         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1444 }
1445
1446 static bool it6505_use_step_train_check(struct it6505 *it6505)
1447 {
1448         if (it6505->link.revision >= 0x12)
1449                 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1450
1451         return true;
1452 }
1453
1454 static void it6505_parse_link_capabilities(struct it6505 *it6505)
1455 {
1456         struct device *dev = it6505->dev;
1457         struct it6505_drm_dp_link *link = &it6505->link;
1458         int bcaps;
1459
1460         if (it6505->dpcd[0] == 0) {
1461                 dev_err(dev, "DPCD is not initialized");
1462                 return;
1463         }
1464
1465         memset(link, 0, sizeof(*link));
1466
1467         link->revision = it6505->dpcd[0];
1468         link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);
1469         link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1470
1471         if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1472                 link->capabilities = DP_ENHANCED_FRAME_CAP;
1473
1474         DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1475                              link->revision >> 4, link->revision & 0x0F);
1476
1477         DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1478                              link->rate / 100000, link->rate / 1000 % 100);
1479
1480         it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1481         DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1482                              it6505->link_rate_bw_code);
1483         it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1484                                           MAX_LINK_RATE);
1485
1486         it6505->lane_count = link->num_lanes;
1487         DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1488                              it6505->lane_count);
1489         it6505->lane_count = min_t(int, it6505->lane_count,
1490                                    it6505->max_lane_count);
1491
1492         it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1493         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1494                              it6505->branch_device ? "" : "Not ");
1495
1496         it6505->enable_enhanced_frame = link->capabilities;
1497         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1498                              it6505->enable_enhanced_frame ? "" : "Not ");
1499
1500         it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1501                                 DP_MAX_DOWNSPREAD_0_5);
1502         DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1503                              it6505->enable_ssc ? "0.5" : "0",
1504                              it6505->enable_ssc ? "" : "Not ");
1505
1506         it6505->step_train = it6505_use_step_train_check(it6505);
1507         if (it6505->step_train)
1508                 DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1509
1510         bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1511         DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1512         if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1513                 it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1514                 DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1515                                      it6505->is_repeater ? "repeater" :
1516                                      "receiver");
1517         } else {
1518                 DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1519                 it6505->hdcp_desired = false;
1520         }
1521         DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1522                              it6505->hdcp_desired ? "desired" : "undesired");
1523 }
1524
1525 static void it6505_setup_ssc(struct it6505 *it6505)
1526 {
1527         it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1528                         it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1529         if (it6505->enable_ssc) {
1530                 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1531                 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1532                 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1533                 it6505_write(it6505, REG_SP_CTRL0, 0x07);
1534                 it6505_write(it6505, REG_IP_CTRL1, 0x29);
1535                 it6505_write(it6505, REG_IP_CTRL2, 0x03);
1536                 /* Stamp Interrupt Step */
1537                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1538                                 0x10);
1539                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1540                                   DP_SPREAD_AMP_0_5);
1541         } else {
1542                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1543                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1544                                 0x00);
1545         }
1546 }
1547
1548 static inline void it6505_link_rate_setup(struct it6505 *it6505)
1549 {
1550         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1551                         (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1552         it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1553                         (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1554 }
1555
1556 static void it6505_lane_count_setup(struct it6505 *it6505)
1557 {
1558         it6505_get_extcon_property(it6505);
1559         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1560                         it6505->lane_swap ? LANE_SWAP : 0x00);
1561         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1562                         (it6505->lane_count - 1) << 1);
1563 }
1564
1565 static void it6505_link_training_setup(struct it6505 *it6505)
1566 {
1567         struct device *dev = it6505->dev;
1568
1569         if (it6505->enable_enhanced_frame)
1570                 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1571                                 ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1572
1573         it6505_link_rate_setup(it6505);
1574         it6505_lane_count_setup(it6505);
1575         it6505_setup_ssc(it6505);
1576         DRM_DEV_DEBUG_DRIVER(dev,
1577                              "%s, %d lanes, %sable ssc, %sable enhanced frame",
1578                              it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1579                              it6505->lane_count,
1580                              it6505->enable_ssc ? "en" : "dis",
1581                              it6505->enable_enhanced_frame ? "en" : "dis");
1582 }
1583
1584 static bool it6505_link_start_auto_train(struct it6505 *it6505)
1585 {
1586         int timeout = 500, link_training_state;
1587         bool state = false;
1588
1589         mutex_lock(&it6505->aux_lock);
1590         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1591                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1592         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1593         it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1594
1595         while (timeout > 0) {
1596                 usleep_range(1000, 2000);
1597                 link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1598
1599                 if (link_training_state > 0 &&
1600                     (link_training_state & LINK_STATE_NORP)) {
1601                         state = true;
1602                         goto unlock;
1603                 }
1604
1605                 timeout--;
1606         }
1607 unlock:
1608         mutex_unlock(&it6505->aux_lock);
1609
1610         return state;
1611 }
1612
1613 static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1614 {
1615         u8 values[2];
1616         int err;
1617         struct drm_dp_aux *aux = &it6505->aux;
1618
1619         values[0] = it6505->link_rate_bw_code;
1620         values[1] = it6505->lane_count;
1621
1622         if (it6505->enable_enhanced_frame)
1623                 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1624
1625         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1626         if (err < 0)
1627                 return err;
1628
1629         return 0;
1630 }
1631
1632 static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1633 {
1634         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1635 }
1636
1637 static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1638 {
1639         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1640 }
1641
1642 static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1643                                                    u8 lane_count)
1644 {
1645         u8 i;
1646
1647         for (i = 0; i < lane_count; i++) {
1648                 if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1649                         return true;
1650         }
1651
1652         return false;
1653 }
1654
1655 static bool
1656 step_train_lane_voltage_para_set(struct it6505 *it6505,
1657                                  struct it6505_step_train_para
1658                                  *lane_voltage_pre_emphasis,
1659                                  u8 *lane_voltage_pre_emphasis_set)
1660 {
1661         u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1662         u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1663         u8 i;
1664
1665         for (i = 0; i < it6505->lane_count; i++) {
1666                 voltage_swing[i] &= 0x03;
1667                 lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1668                 if (it6505_check_voltage_swing_max(voltage_swing[i]))
1669                         lane_voltage_pre_emphasis_set[i] |=
1670                                 DP_TRAIN_MAX_SWING_REACHED;
1671
1672                 pre_emphasis[i] &= 0x03;
1673                 lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1674                         << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1675                 if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1676                         lane_voltage_pre_emphasis_set[i] |=
1677                                 DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1678                 it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1679                                   lane_voltage_pre_emphasis_set[i]);
1680
1681                 if (lane_voltage_pre_emphasis_set[i] !=
1682                     it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1683                         return false;
1684         }
1685
1686         return true;
1687 }
1688
1689 static bool
1690 it6505_step_cr_train(struct it6505 *it6505,
1691                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1692 {
1693         u8 loop_count = 0, i = 0, j;
1694         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1695         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1696         int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1697         const struct drm_dp_aux *aux = &it6505->aux;
1698
1699         it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1700                           it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1701         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1702                           DP_TRAINING_PATTERN_1);
1703
1704         while (loop_count < 5 && i < 10) {
1705                 i++;
1706                 if (!step_train_lane_voltage_para_set(it6505,
1707                                                       lane_voltage_pre_emphasis,
1708                                                       lane_level_config))
1709                         continue;
1710                 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1711                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1712
1713                 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1714                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1715                                         FORCE_CR_DONE);
1716                         return true;
1717                 }
1718                 DRM_DEV_DEBUG_DRIVER(it6505->dev, "cr not done");
1719
1720                 if (it6505_check_max_voltage_swing_reached(lane_level_config,
1721                                                            it6505->lane_count))
1722                         goto cr_train_fail;
1723
1724                 for (j = 0; j < it6505->lane_count; j++) {
1725                         lane_voltage_pre_emphasis->voltage_swing[j] =
1726                                 drm_dp_get_adjust_request_voltage(link_status,
1727                                                                   j) >>
1728                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1729                         lane_voltage_pre_emphasis->pre_emphasis[j] =
1730                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1731                                                                j) >>
1732                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1733                         if (voltage_swing_adjust ==
1734                              lane_voltage_pre_emphasis->voltage_swing[j] &&
1735                             pre_emphasis_adjust ==
1736                              lane_voltage_pre_emphasis->pre_emphasis[j]) {
1737                                 loop_count++;
1738                                 continue;
1739                         }
1740
1741                         voltage_swing_adjust =
1742                                 lane_voltage_pre_emphasis->voltage_swing[j];
1743                         pre_emphasis_adjust =
1744                                 lane_voltage_pre_emphasis->pre_emphasis[j];
1745                         loop_count = 0;
1746
1747                         if (voltage_swing_adjust + pre_emphasis_adjust >
1748                             MAX_EQ_LEVEL)
1749                                 lane_voltage_pre_emphasis->voltage_swing[j] =
1750                                         MAX_EQ_LEVEL -
1751                                         lane_voltage_pre_emphasis
1752                                                 ->pre_emphasis[j];
1753                 }
1754         }
1755
1756 cr_train_fail:
1757         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1758                           DP_TRAINING_PATTERN_DISABLE);
1759
1760         return false;
1761 }
1762
1763 static bool
1764 it6505_step_eq_train(struct it6505 *it6505,
1765                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1766 {
1767         u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1768         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1769         const struct drm_dp_aux *aux = &it6505->aux;
1770
1771         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1772                           DP_TRAINING_PATTERN_2);
1773
1774         while (loop_count < 6) {
1775                 loop_count++;
1776
1777                 if (!step_train_lane_voltage_para_set(it6505,
1778                                                       lane_voltage_pre_emphasis,
1779                                                       lane_level_config))
1780                         continue;
1781
1782                 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1783                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1784
1785                 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1786                         goto eq_train_fail;
1787
1788                 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1789                         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1790                                           DP_TRAINING_PATTERN_DISABLE);
1791                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1792                                         FORCE_EQ_DONE);
1793                         return true;
1794                 }
1795                 DRM_DEV_DEBUG_DRIVER(it6505->dev, "eq not done");
1796
1797                 for (i = 0; i < it6505->lane_count; i++) {
1798                         lane_voltage_pre_emphasis->voltage_swing[i] =
1799                                 drm_dp_get_adjust_request_voltage(link_status,
1800                                                                   i) >>
1801                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1802                         lane_voltage_pre_emphasis->pre_emphasis[i] =
1803                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1804                                                                i) >>
1805                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1806
1807                         if (lane_voltage_pre_emphasis->voltage_swing[i] +
1808                                     lane_voltage_pre_emphasis->pre_emphasis[i] >
1809                             MAX_EQ_LEVEL)
1810                                 lane_voltage_pre_emphasis->voltage_swing[i] =
1811                                         0x03 - lane_voltage_pre_emphasis
1812                                                        ->pre_emphasis[i];
1813                 }
1814         }
1815
1816 eq_train_fail:
1817         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1818                           DP_TRAINING_PATTERN_DISABLE);
1819         return false;
1820 }
1821
1822 static bool it6505_link_start_step_train(struct it6505 *it6505)
1823 {
1824         int err;
1825         struct it6505_step_train_para lane_voltage_pre_emphasis = {
1826                 .voltage_swing = { 0 },
1827                 .pre_emphasis = { 0 },
1828         };
1829
1830         DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
1831         err = it6505_drm_dp_link_configure(it6505);
1832
1833         if (err < 0)
1834                 return false;
1835         if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1836                 return false;
1837         if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1838                 return false;
1839         return true;
1840 }
1841
1842 static bool it6505_get_video_status(struct it6505 *it6505)
1843 {
1844         int reg_0d;
1845
1846         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1847
1848         if (reg_0d < 0)
1849                 return false;
1850
1851         return reg_0d & VIDEO_STB;
1852 }
1853
1854 static void it6505_reset_hdcp(struct it6505 *it6505)
1855 {
1856         it6505->hdcp_status = HDCP_AUTH_IDLE;
1857         /* Disable CP_Desired */
1858         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1859         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1860 }
1861
1862 static void it6505_start_hdcp(struct it6505 *it6505)
1863 {
1864         struct device *dev = it6505->dev;
1865
1866         DRM_DEV_DEBUG_DRIVER(dev, "start");
1867         it6505_reset_hdcp(it6505);
1868         queue_delayed_work(system_wq, &it6505->hdcp_work,
1869                            msecs_to_jiffies(2400));
1870 }
1871
1872 static void it6505_stop_hdcp(struct it6505 *it6505)
1873 {
1874         it6505_reset_hdcp(it6505);
1875         cancel_delayed_work(&it6505->hdcp_work);
1876 }
1877
1878 static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1879 {
1880         int i, ones = 0;
1881
1882         /* KSV has 20 1's and 20 0's */
1883         for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1884                 ones += hweight8(ksv[i]);
1885         if (ones != 20)
1886                 return false;
1887         return true;
1888 }
1889
1890 static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1891 {
1892         struct device *dev = it6505->dev;
1893         u8 hdcp_bcaps;
1894
1895         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1896         /* Disable CP_Desired */
1897         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1898
1899         usleep_range(1000, 1500);
1900         hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1901         DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1902                              hdcp_bcaps);
1903
1904         if (!hdcp_bcaps)
1905                 return;
1906
1907         /* clear the repeater List Chk Done and fail bit */
1908         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1909                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1910                         0x00);
1911
1912         /* Enable An Generator */
1913         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1914         /* delay1ms(10);*/
1915         usleep_range(10000, 15000);
1916         /* Stop An Generator */
1917         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1918
1919         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1920
1921         it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1922                         HDCP_TRIGGER_START);
1923
1924         it6505->hdcp_status = HDCP_AUTH_GOING;
1925 }
1926
1927 static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1928                               unsigned int size, u8 *output_av)
1929 {
1930         struct shash_desc *desc;
1931         struct crypto_shash *tfm;
1932         int err;
1933         struct device *dev = it6505->dev;
1934
1935         tfm = crypto_alloc_shash("sha1", 0, 0);
1936         if (IS_ERR(tfm)) {
1937                 dev_err(dev, "crypto_alloc_shash sha1 failed");
1938                 return PTR_ERR(tfm);
1939         }
1940         desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1941         if (!desc) {
1942                 crypto_free_shash(tfm);
1943                 return -ENOMEM;
1944         }
1945
1946         desc->tfm = tfm;
1947         err = crypto_shash_digest(desc, sha1_input, size, output_av);
1948         if (err)
1949                 dev_err(dev, "crypto_shash_digest sha1 failed");
1950
1951         crypto_free_shash(tfm);
1952         kfree(desc);
1953         return err;
1954 }
1955
1956 static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1957 {
1958         struct device *dev = it6505->dev;
1959         u8 binfo[2];
1960         int down_stream_count, i, err, msg_count = 0;
1961
1962         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1963                               ARRAY_SIZE(binfo));
1964
1965         if (err < 0) {
1966                 dev_err(dev, "Read binfo value Fail");
1967                 return err;
1968         }
1969
1970         down_stream_count = binfo[0] & 0x7F;
1971         DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1972                              binfo);
1973
1974         if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1975                 dev_err(dev, "HDCP max cascade device exceed");
1976                 return 0;
1977         }
1978
1979         if (!down_stream_count ||
1980             down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1981                 dev_err(dev, "HDCP down stream count Error %d",
1982                         down_stream_count);
1983                 return 0;
1984         }
1985
1986         for (i = 0; i < down_stream_count; i++) {
1987                 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1988                                       (i % 3) * DRM_HDCP_KSV_LEN,
1989                                       sha1_input + msg_count,
1990                                       DRM_HDCP_KSV_LEN);
1991
1992                 if (err < 0)
1993                         return err;
1994
1995                 msg_count += 5;
1996         }
1997
1998         it6505->hdcp_down_stream_count = down_stream_count;
1999         sha1_input[msg_count++] = binfo[0];
2000         sha1_input[msg_count++] = binfo[1];
2001
2002         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
2003                         HDCP_EN_M0_READ);
2004
2005         err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
2006                                sha1_input + msg_count, 8);
2007
2008         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
2009
2010         if (err < 0) {
2011                 dev_err(dev, " Warning, Read M value Fail");
2012                 return err;
2013         }
2014
2015         msg_count += 8;
2016
2017         return msg_count;
2018 }
2019
2020 static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2021 {
2022         struct device *dev = it6505->dev;
2023         u8 av[5][4], bv[5][4];
2024         int i, err;
2025
2026         i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2027         if (i <= 0) {
2028                 dev_err(dev, "SHA-1 Input length error %d", i);
2029                 return false;
2030         }
2031
2032         it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2033
2034         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2035                               sizeof(bv));
2036
2037         if (err < 0) {
2038                 dev_err(dev, "Read V' value Fail");
2039                 return false;
2040         }
2041
2042         for (i = 0; i < 5; i++)
2043                 if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2044                     bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2045                         return false;
2046
2047         DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2048         return true;
2049 }
2050
2051 static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2052 {
2053         struct it6505 *it6505 = container_of(work, struct it6505,
2054                                              hdcp_wait_ksv_list);
2055         struct device *dev = it6505->dev;
2056         unsigned int timeout = 5000;
2057         u8 bstatus = 0;
2058         bool ksv_list_check;
2059
2060         timeout /= 20;
2061         while (timeout > 0) {
2062                 if (!it6505_get_sink_hpd_status(it6505))
2063                         return;
2064
2065                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2066
2067                 if (bstatus & DP_BSTATUS_READY)
2068                         break;
2069
2070                 msleep(20);
2071                 timeout--;
2072         }
2073
2074         if (timeout == 0) {
2075                 DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2076                 goto timeout;
2077         }
2078
2079         ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2080         DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2081                              ksv_list_check ? "pass" : "fail");
2082         if (ksv_list_check) {
2083                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2084                                 HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2085                 return;
2086         }
2087 timeout:
2088         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2089                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2090                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2091 }
2092
2093 static void it6505_hdcp_work(struct work_struct *work)
2094 {
2095         struct it6505 *it6505 = container_of(work, struct it6505,
2096                                              hdcp_work.work);
2097         struct device *dev = it6505->dev;
2098         int ret;
2099         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2100
2101         DRM_DEV_DEBUG_DRIVER(dev, "start");
2102
2103         if (!it6505_get_sink_hpd_status(it6505))
2104                 return;
2105
2106         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2107         DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2108                              (int)sizeof(link_status), link_status);
2109
2110         if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2111             !it6505_get_video_status(it6505)) {
2112                 DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2113                 return;
2114         }
2115
2116         ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2117                               ARRAY_SIZE(it6505->bksvs));
2118         if (ret < 0) {
2119                 dev_err(dev, "fail to get bksv  ret: %d", ret);
2120                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2121                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2122         }
2123
2124         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2125                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2126
2127         if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2128                 dev_err(dev, "Display Port bksv not valid");
2129                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2130                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2131         }
2132
2133         it6505_hdcp_part1_auth(it6505);
2134 }
2135
2136 static void it6505_show_hdcp_info(struct it6505 *it6505)
2137 {
2138         struct device *dev = it6505->dev;
2139         int i;
2140         u8 *sha1 = it6505->sha1_input;
2141
2142         DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2143                              it6505->hdcp_status, it6505->is_repeater);
2144         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2145                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2146
2147         if (it6505->is_repeater) {
2148                 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2149                                      it6505->hdcp_down_stream_count);
2150                 DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2151                                      (int)ARRAY_SIZE(it6505->sha1_input),
2152                                      it6505->sha1_input);
2153                 for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2154                         DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2155                                              DRM_HDCP_KSV_LEN, sha1);
2156                         sha1 += DRM_HDCP_KSV_LEN;
2157                 }
2158                 DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2159                                      sha1, sha1 + 2);
2160         }
2161 }
2162
2163 static void it6505_stop_link_train(struct it6505 *it6505)
2164 {
2165         it6505->link_state = LINK_IDLE;
2166         cancel_work_sync(&it6505->link_works);
2167         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2168 }
2169
2170 static void it6505_link_train_ok(struct it6505 *it6505)
2171 {
2172         struct device *dev = it6505->dev;
2173
2174         it6505->link_state = LINK_OK;
2175         /* disalbe mute enable avi info frame */
2176         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2177         it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2178                         EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2179
2180         if (it6505_audio_input(it6505)) {
2181                 DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2182                 it6505_enable_audio(it6505);
2183         }
2184
2185         if (it6505->hdcp_desired)
2186                 it6505_start_hdcp(it6505);
2187 }
2188
2189 static void it6505_link_step_train_process(struct it6505 *it6505)
2190 {
2191         struct device *dev = it6505->dev;
2192         int ret, i, step_retry = 3;
2193
2194         DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2195
2196         if (it6505->sink_count == 0) {
2197                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2198                                      it6505->sink_count);
2199                 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2200                                 FORCE_EQ_DONE);
2201                 return;
2202         }
2203
2204         if (!it6505->step_train) {
2205                 DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2206                 return;
2207         }
2208
2209         /* step training start here */
2210         for (i = 0; i < step_retry; i++) {
2211                 it6505_link_reset_step_train(it6505);
2212                 ret = it6505_link_start_step_train(it6505);
2213                 DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2214                                      ret ? "pass" : "failed", i + 1);
2215                 if (ret) {
2216                         it6505_link_train_ok(it6505);
2217                         return;
2218                 }
2219         }
2220
2221         DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2222         it6505->link_state = LINK_IDLE;
2223         it6505_video_reset(it6505);
2224 }
2225
2226 static void it6505_link_training_work(struct work_struct *work)
2227 {
2228         struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2229         struct device *dev = it6505->dev;
2230         int ret;
2231
2232         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2233                              it6505->sink_count);
2234
2235         if (!it6505_get_sink_hpd_status(it6505))
2236                 return;
2237
2238         it6505_link_training_setup(it6505);
2239         it6505_reset_hdcp(it6505);
2240         it6505_aux_reset(it6505);
2241
2242         if (it6505->auto_train_retry < 1) {
2243                 it6505_link_step_train_process(it6505);
2244                 return;
2245         }
2246
2247         ret = it6505_link_start_auto_train(it6505);
2248         DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2249                              ret ? "pass" : "failed", it6505->auto_train_retry);
2250
2251         if (ret) {
2252                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2253                 it6505_link_train_ok(it6505);
2254         } else {
2255                 it6505->auto_train_retry--;
2256                 it6505_dump(it6505);
2257         }
2258
2259 }
2260
2261 static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2262 {
2263         enum drm_connector_status status = it6505->connector_status;
2264
2265         if (it6505->plugged_cb && it6505->codec_dev)
2266                 it6505->plugged_cb(it6505->codec_dev,
2267                                    status == connector_status_connected);
2268 }
2269
2270 static void it6505_remove_edid(struct it6505 *it6505)
2271 {
2272         drm_edid_free(it6505->cached_edid);
2273         it6505->cached_edid = NULL;
2274 }
2275
2276 static int it6505_process_hpd_irq(struct it6505 *it6505)
2277 {
2278         struct device *dev = it6505->dev;
2279         int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2280         u8 link_status[DP_LINK_STATUS_SIZE];
2281
2282         if (!it6505_get_sink_hpd_status(it6505)) {
2283                 DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2284                 it6505->sink_count = 0;
2285                 return 0;
2286         }
2287
2288         ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2289         if (ret < 0)
2290                 return ret;
2291
2292         dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2293         DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2294                              dpcd_sink_count, it6505->sink_count);
2295
2296         if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2297                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2298                 it6505->sink_count = dpcd_sink_count;
2299                 it6505_reset_logic(it6505);
2300                 it6505_int_mask_enable(it6505);
2301                 it6505_init(it6505);
2302                 it6505_remove_edid(it6505);
2303                 return 0;
2304         }
2305
2306         dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2307         if (dp_irq_vector < 0)
2308                 return dp_irq_vector;
2309
2310         DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2311
2312         if (dp_irq_vector & DP_CP_IRQ) {
2313                 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2314                                 HDCP_TRIGGER_CPIRQ);
2315
2316                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2317                 if (bstatus < 0)
2318                         return bstatus;
2319
2320                 DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2321         }
2322
2323         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2324         if (ret < 0) {
2325                 dev_err(dev, "Fail to read link status ret: %d", ret);
2326                 return ret;
2327         }
2328
2329         DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2330                              (int)ARRAY_SIZE(link_status), link_status);
2331
2332         if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2333                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2334                 it6505_video_reset(it6505);
2335         }
2336
2337         return 0;
2338 }
2339
2340 static void it6505_irq_hpd(struct it6505 *it6505)
2341 {
2342         struct device *dev = it6505->dev;
2343         int dp_sink_count;
2344
2345         it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2346         DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2347                              it6505->hpd_state ? "high" : "low");
2348
2349         if (it6505->hpd_state) {
2350                 wait_for_completion_timeout(&it6505->extcon_completion,
2351                                             msecs_to_jiffies(1000));
2352                 it6505_aux_on(it6505);
2353                 if (it6505->dpcd[0] == 0) {
2354                         it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2355                                         ARRAY_SIZE(it6505->dpcd));
2356                         it6505_variable_config(it6505);
2357                         it6505_parse_link_capabilities(it6505);
2358                 }
2359                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2360
2361                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2362                                              DP_SET_POWER_D0);
2363                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2364                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2365
2366                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2367                                      it6505->sink_count);
2368
2369                 it6505_lane_termination_on(it6505);
2370                 it6505_lane_power_on(it6505);
2371
2372                 /*
2373                  * for some dongle which issue HPD_irq
2374                  * when sink count change from  0->1
2375                  * it6505 not able to receive HPD_IRQ
2376                  * if HW never go into trainig done
2377                  */
2378
2379                 if (it6505->branch_device && it6505->sink_count == 0)
2380                         schedule_work(&it6505->link_works);
2381
2382                 if (!it6505_get_video_status(it6505))
2383                         it6505_video_reset(it6505);
2384         } else {
2385                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2386                 it6505_remove_edid(it6505);
2387
2388                 if (it6505->hdcp_desired)
2389                         it6505_stop_hdcp(it6505);
2390
2391                 it6505_video_disable(it6505);
2392                 it6505_disable_audio(it6505);
2393                 it6505_stop_link_train(it6505);
2394                 it6505_lane_off(it6505);
2395                 it6505_link_reset_step_train(it6505);
2396         }
2397
2398         if (it6505->bridge.dev)
2399                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2400 }
2401
2402 static void it6505_irq_hpd_irq(struct it6505 *it6505)
2403 {
2404         struct device *dev = it6505->dev;
2405
2406         DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2407
2408         if (it6505_process_hpd_irq(it6505) < 0)
2409                 DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2410 }
2411
2412 static void it6505_irq_scdt(struct it6505 *it6505)
2413 {
2414         struct device *dev = it6505->dev;
2415         bool data;
2416
2417         data = it6505_get_video_status(it6505);
2418         DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2419                              data ? "stable" : "unstable");
2420         it6505_calc_video_info(it6505);
2421         it6505_link_reset_step_train(it6505);
2422
2423         if (data)
2424                 schedule_work(&it6505->link_works);
2425 }
2426
2427 static void it6505_irq_hdcp_done(struct it6505 *it6505)
2428 {
2429         struct device *dev = it6505->dev;
2430
2431         DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2432         it6505->hdcp_status = HDCP_AUTH_DONE;
2433         it6505_show_hdcp_info(it6505);
2434 }
2435
2436 static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2437 {
2438         struct device *dev = it6505->dev;
2439
2440         DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2441         it6505->hdcp_status = HDCP_AUTH_IDLE;
2442         it6505_show_hdcp_info(it6505);
2443         it6505_start_hdcp(it6505);
2444 }
2445
2446 static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2447 {
2448         struct device *dev = it6505->dev;
2449
2450         DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2451 }
2452
2453 static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2454 {
2455         struct device *dev = it6505->dev;
2456
2457         DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2458         schedule_work(&it6505->hdcp_wait_ksv_list);
2459 }
2460
2461 static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2462 {
2463         struct device *dev = it6505->dev;
2464
2465         DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2466
2467         if (it6505_audio_input(it6505))
2468                 it6505_enable_audio(it6505);
2469 }
2470
2471 static void it6505_irq_link_train_fail(struct it6505 *it6505)
2472 {
2473         struct device *dev = it6505->dev;
2474
2475         DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2476         schedule_work(&it6505->link_works);
2477 }
2478
2479 static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2480 {
2481         return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2482 }
2483
2484 static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status)
2485 {
2486         struct device *dev = it6505->dev;
2487         int reg_0d, reg_int03;
2488
2489         /*
2490          * When video SCDT change with video not stable,
2491          * Or video FIFO error, need video reset
2492          */
2493
2494         if ((!it6505_get_video_status(it6505) &&
2495              (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))) ||
2496             (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW,
2497                              (unsigned int *)int_status)) ||
2498             (it6505_test_bit(BIT_INT_VID_FIFO_ERROR,
2499                              (unsigned int *)int_status))) {
2500                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2501                 flush_work(&it6505->link_works);
2502                 it6505_stop_hdcp(it6505);
2503                 it6505_video_reset(it6505);
2504
2505                 usleep_range(10000, 11000);
2506
2507                 /*
2508                  * Clear FIFO error IRQ to prevent fifo error -> reset loop
2509                  * HW will trigger SCDT change IRQ again when video stable
2510                  */
2511
2512                 reg_int03 = it6505_read(it6505, INT_STATUS_03);
2513                 reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
2514
2515                 reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
2516                 it6505_write(it6505, INT_STATUS_03, reg_int03);
2517
2518                 DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03);
2519                 DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d);
2520
2521                 return;
2522         }
2523
2524         if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *)int_status))
2525                 it6505_irq_scdt(it6505);
2526 }
2527
2528 static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2529 {
2530         struct it6505 *it6505 = data;
2531         struct device *dev = it6505->dev;
2532         static const struct {
2533                 int bit;
2534                 void (*handler)(struct it6505 *it6505);
2535         } irq_vec[] = {
2536                 { BIT_INT_HPD, it6505_irq_hpd },
2537                 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2538                 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2539                 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2540                 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2541                 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2542                 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2543                 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2544         };
2545         int int_status[3], i;
2546
2547         if (it6505->enable_drv_hold || !it6505->powered)
2548                 return IRQ_HANDLED;
2549
2550         pm_runtime_get_sync(dev);
2551
2552         int_status[0] = it6505_read(it6505, INT_STATUS_01);
2553         int_status[1] = it6505_read(it6505, INT_STATUS_02);
2554         int_status[2] = it6505_read(it6505, INT_STATUS_03);
2555
2556         it6505_write(it6505, INT_STATUS_01, int_status[0]);
2557         it6505_write(it6505, INT_STATUS_02, int_status[1]);
2558         it6505_write(it6505, INT_STATUS_03, int_status[2]);
2559
2560         DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2561         DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2562         DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2563         it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2564
2565         if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2566                 irq_vec[0].handler(it6505);
2567
2568         if (it6505->hpd_state) {
2569                 for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2570                         if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2571                                 irq_vec[i].handler(it6505);
2572                 }
2573                 it6505_irq_video_handler(it6505, (unsigned int *)int_status);
2574         }
2575
2576         pm_runtime_put_sync(dev);
2577
2578         return IRQ_HANDLED;
2579 }
2580
2581 static int it6505_poweron(struct it6505 *it6505)
2582 {
2583         struct device *dev = it6505->dev;
2584         struct it6505_platform_data *pdata = &it6505->pdata;
2585         int err;
2586
2587         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2588
2589         if (it6505->powered) {
2590                 DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2591                 return 0;
2592         }
2593
2594         if (pdata->pwr18) {
2595                 err = regulator_enable(pdata->pwr18);
2596                 if (err) {
2597                         DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2598                                              err);
2599                         return err;
2600                 }
2601         }
2602
2603         if (pdata->ovdd) {
2604                 /* time interval between IVDD and OVDD at least be 1ms */
2605                 usleep_range(1000, 2000);
2606                 err = regulator_enable(pdata->ovdd);
2607                 if (err) {
2608                         regulator_disable(pdata->pwr18);
2609                         return err;
2610                 }
2611         }
2612         /* time interval between OVDD and SYSRSTN at least be 10ms */
2613         if (pdata->gpiod_reset) {
2614                 usleep_range(10000, 20000);
2615                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2616                 usleep_range(1000, 2000);
2617                 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2618                 usleep_range(25000, 35000);
2619         }
2620
2621         it6505->powered = true;
2622         it6505_reset_logic(it6505);
2623         it6505_int_mask_enable(it6505);
2624         it6505_init(it6505);
2625         it6505_lane_off(it6505);
2626
2627         return 0;
2628 }
2629
2630 static int it6505_poweroff(struct it6505 *it6505)
2631 {
2632         struct device *dev = it6505->dev;
2633         struct it6505_platform_data *pdata = &it6505->pdata;
2634         int err;
2635
2636         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2637
2638         if (!it6505->powered) {
2639                 DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2640                 return 0;
2641         }
2642
2643         if (pdata->gpiod_reset)
2644                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2645
2646         if (pdata->pwr18) {
2647                 err = regulator_disable(pdata->pwr18);
2648                 if (err)
2649                         return err;
2650         }
2651
2652         if (pdata->ovdd) {
2653                 err = regulator_disable(pdata->ovdd);
2654                 if (err)
2655                         return err;
2656         }
2657
2658         it6505->powered = false;
2659         it6505->sink_count = 0;
2660
2661         return 0;
2662 }
2663
2664 static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2665 {
2666         struct device *dev = it6505->dev;
2667         enum drm_connector_status status = connector_status_disconnected;
2668         int dp_sink_count;
2669
2670         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2671                              it6505->sink_count, it6505->powered);
2672
2673         mutex_lock(&it6505->mode_lock);
2674
2675         if (!it6505->powered)
2676                 goto unlock;
2677
2678         if (it6505->enable_drv_hold) {
2679                 status = it6505->hpd_state ? connector_status_connected :
2680                                              connector_status_disconnected;
2681                 goto unlock;
2682         }
2683
2684         if (it6505->hpd_state) {
2685                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2686                                              DP_SET_POWER_D0);
2687                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2688                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2689                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2690                                      it6505->sink_count, it6505->branch_device);
2691
2692                 if (it6505->branch_device) {
2693                         status = (it6505->sink_count != 0) ?
2694                                  connector_status_connected :
2695                                  connector_status_disconnected;
2696                 } else {
2697                         status = connector_status_connected;
2698                 }
2699         } else {
2700                 it6505->sink_count = 0;
2701                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2702         }
2703
2704 unlock:
2705         if (it6505->connector_status != status) {
2706                 it6505->connector_status = status;
2707                 it6505_plugged_status_to_codec(it6505);
2708         }
2709
2710         mutex_unlock(&it6505->mode_lock);
2711
2712         return status;
2713 }
2714
2715 static int it6505_extcon_notifier(struct notifier_block *self,
2716                                   unsigned long event, void *ptr)
2717 {
2718         struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2719
2720         schedule_work(&it6505->extcon_wq);
2721         return NOTIFY_DONE;
2722 }
2723
2724 static void it6505_extcon_work(struct work_struct *work)
2725 {
2726         struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2727         struct device *dev = it6505->dev;
2728         int state, ret;
2729
2730         if (it6505->enable_drv_hold)
2731                 return;
2732
2733         mutex_lock(&it6505->extcon_lock);
2734
2735         state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2736         DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2737
2738         if (state == it6505->extcon_state || unlikely(state < 0))
2739                 goto unlock;
2740         it6505->extcon_state = state;
2741         if (state) {
2742                 DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2743                 msleep(100);
2744                 ret = pm_runtime_get_sync(dev);
2745
2746                 /*
2747                  * On system resume, extcon_work can be triggered before
2748                  * pm_runtime_force_resume re-enables runtime power management.
2749                  * Handling the error here to make sure the bridge is powered on.
2750                  */
2751                 if (ret < 0)
2752                         it6505_poweron(it6505);
2753
2754                 complete_all(&it6505->extcon_completion);
2755         } else {
2756                 DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2757                 pm_runtime_put_sync(dev);
2758                 reinit_completion(&it6505->extcon_completion);
2759
2760                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2761                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2762                 DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2763         }
2764
2765 unlock:
2766         mutex_unlock(&it6505->extcon_lock);
2767 }
2768
2769 static int it6505_use_notifier_module(struct it6505 *it6505)
2770 {
2771         int ret;
2772         struct device *dev = it6505->dev;
2773
2774         it6505->event_nb.notifier_call = it6505_extcon_notifier;
2775         INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2776         ret = devm_extcon_register_notifier(it6505->dev,
2777                                             it6505->extcon, EXTCON_DISP_DP,
2778                                             &it6505->event_nb);
2779         if (ret) {
2780                 dev_err(dev, "failed to register notifier for DP");
2781                 return ret;
2782         }
2783
2784         schedule_work(&it6505->extcon_wq);
2785
2786         return 0;
2787 }
2788
2789 static void it6505_remove_notifier_module(struct it6505 *it6505)
2790 {
2791         if (it6505->extcon) {
2792                 devm_extcon_unregister_notifier(it6505->dev,
2793                                                 it6505->extcon, EXTCON_DISP_DP,
2794                                                 &it6505->event_nb);
2795
2796                 flush_work(&it6505->extcon_wq);
2797         }
2798 }
2799
2800 static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2801 {
2802         struct it6505 *it6505 = container_of(work, struct it6505,
2803                                              delayed_audio.work);
2804
2805         DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
2806
2807         if (!it6505->powered)
2808                 return;
2809
2810         if (!it6505->enable_drv_hold)
2811                 it6505_enable_audio(it6505);
2812 }
2813
2814 static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2815                                                        struct hdmi_codec_params
2816                                                        *params)
2817 {
2818         struct device *dev = it6505->dev;
2819         int i = 0;
2820
2821         DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2822                              params->sample_rate, params->sample_width,
2823                              params->cea.channels);
2824
2825         if (!it6505->bridge.encoder)
2826                 return -ENODEV;
2827
2828         if (params->cea.channels <= 1 || params->cea.channels > 8) {
2829                 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2830                                      it6505->audio.channel_count);
2831                 return -EINVAL;
2832         }
2833
2834         it6505->audio.channel_count = params->cea.channels;
2835
2836         while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2837                params->sample_rate !=
2838                        audio_sample_rate_map[i].sample_rate_value) {
2839                 i++;
2840         }
2841         if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2842                 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2843                                      params->sample_rate);
2844                 return -EINVAL;
2845         }
2846         it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2847
2848         switch (params->sample_width) {
2849         case 16:
2850                 it6505->audio.word_length = WORD_LENGTH_16BIT;
2851                 break;
2852         case 18:
2853                 it6505->audio.word_length = WORD_LENGTH_18BIT;
2854                 break;
2855         case 20:
2856                 it6505->audio.word_length = WORD_LENGTH_20BIT;
2857                 break;
2858         case 24:
2859         case 32:
2860                 it6505->audio.word_length = WORD_LENGTH_24BIT;
2861                 break;
2862         default:
2863                 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2864                                      params->sample_width);
2865                 return -EINVAL;
2866         }
2867
2868         return 0;
2869 }
2870
2871 static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2872 {
2873         struct it6505 *it6505 = dev_get_drvdata(dev);
2874
2875         if (it6505->powered)
2876                 it6505_disable_audio(it6505);
2877 }
2878
2879 static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2880                                                        void *data,
2881                                                        hdmi_codec_plugged_cb fn,
2882                                                        struct device *codec_dev)
2883 {
2884         struct it6505 *it6505 = data;
2885
2886         it6505->plugged_cb = fn;
2887         it6505->codec_dev = codec_dev;
2888         it6505_plugged_status_to_codec(it6505);
2889
2890         return 0;
2891 }
2892
2893 static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2894 {
2895         return container_of(bridge, struct it6505, bridge);
2896 }
2897
2898 static int it6505_bridge_attach(struct drm_bridge *bridge,
2899                                 enum drm_bridge_attach_flags flags)
2900 {
2901         struct it6505 *it6505 = bridge_to_it6505(bridge);
2902         struct device *dev = it6505->dev;
2903         int ret;
2904
2905         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2906                 DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2907                 return -EINVAL;
2908         }
2909
2910         /* Register aux channel */
2911         it6505->aux.drm_dev = bridge->dev;
2912
2913         ret = drm_dp_aux_register(&it6505->aux);
2914
2915         if (ret < 0) {
2916                 dev_err(dev, "Failed to register aux: %d", ret);
2917                 return ret;
2918         }
2919
2920         if (it6505->extcon) {
2921                 ret = it6505_use_notifier_module(it6505);
2922                 if (ret < 0) {
2923                         dev_err(dev, "use notifier module failed");
2924                         return ret;
2925                 }
2926         }
2927
2928         return 0;
2929 }
2930
2931 static void it6505_bridge_detach(struct drm_bridge *bridge)
2932 {
2933         struct it6505 *it6505 = bridge_to_it6505(bridge);
2934
2935         flush_work(&it6505->link_works);
2936         it6505_remove_notifier_module(it6505);
2937 }
2938
2939 static enum drm_mode_status
2940 it6505_bridge_mode_valid(struct drm_bridge *bridge,
2941                          const struct drm_display_info *info,
2942                          const struct drm_display_mode *mode)
2943 {
2944         struct it6505 *it6505 = bridge_to_it6505(bridge);
2945
2946         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2947                 return MODE_NO_INTERLACE;
2948
2949         if (mode->clock > it6505->max_dpi_pixel_clock)
2950                 return MODE_CLOCK_HIGH;
2951
2952         it6505->video_info.clock = mode->clock;
2953
2954         return MODE_OK;
2955 }
2956
2957 static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2958                                         struct drm_bridge_state *old_state)
2959 {
2960         struct it6505 *it6505 = bridge_to_it6505(bridge);
2961         struct device *dev = it6505->dev;
2962         struct drm_atomic_state *state = old_state->base.state;
2963         struct hdmi_avi_infoframe frame;
2964         struct drm_crtc_state *crtc_state;
2965         struct drm_connector_state *conn_state;
2966         struct drm_display_mode *mode;
2967         struct drm_connector *connector;
2968         int ret;
2969
2970         DRM_DEV_DEBUG_DRIVER(dev, "start");
2971
2972         connector = drm_atomic_get_new_connector_for_encoder(state,
2973                                                              bridge->encoder);
2974
2975         if (WARN_ON(!connector))
2976                 return;
2977
2978         conn_state = drm_atomic_get_new_connector_state(state, connector);
2979
2980         if (WARN_ON(!conn_state))
2981                 return;
2982
2983         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
2984
2985         if (WARN_ON(!crtc_state))
2986                 return;
2987
2988         mode = &crtc_state->adjusted_mode;
2989
2990         if (WARN_ON(!mode))
2991                 return;
2992
2993         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2994                                                        connector,
2995                                                        mode);
2996         if (ret)
2997                 dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2998
2999         it6505_update_video_parameter(it6505, mode);
3000
3001         ret = it6505_send_video_infoframe(it6505, &frame);
3002
3003         if (ret)
3004                 dev_err(dev, "Failed to send AVI infoframe: %d", ret);
3005
3006         it6505_int_mask_enable(it6505);
3007         it6505_video_reset(it6505);
3008
3009         it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
3010                                      DP_SET_POWER_D0);
3011 }
3012
3013 static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
3014                                          struct drm_bridge_state *old_state)
3015 {
3016         struct it6505 *it6505 = bridge_to_it6505(bridge);
3017         struct device *dev = it6505->dev;
3018
3019         DRM_DEV_DEBUG_DRIVER(dev, "start");
3020
3021         if (it6505->powered) {
3022                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
3023                                              DP_SET_POWER_D3);
3024                 it6505_video_disable(it6505);
3025         }
3026 }
3027
3028 static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
3029                                             struct drm_bridge_state *old_state)
3030 {
3031         struct it6505 *it6505 = bridge_to_it6505(bridge);
3032         struct device *dev = it6505->dev;
3033
3034         DRM_DEV_DEBUG_DRIVER(dev, "start");
3035
3036         pm_runtime_get_sync(dev);
3037 }
3038
3039 static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
3040                                               struct drm_bridge_state *old_state)
3041 {
3042         struct it6505 *it6505 = bridge_to_it6505(bridge);
3043         struct device *dev = it6505->dev;
3044
3045         DRM_DEV_DEBUG_DRIVER(dev, "start");
3046
3047         pm_runtime_put_sync(dev);
3048 }
3049
3050 static enum drm_connector_status
3051 it6505_bridge_detect(struct drm_bridge *bridge)
3052 {
3053         struct it6505 *it6505 = bridge_to_it6505(bridge);
3054
3055         return it6505_detect(it6505);
3056 }
3057
3058 static const struct drm_edid *it6505_bridge_edid_read(struct drm_bridge *bridge,
3059                                                       struct drm_connector *connector)
3060 {
3061         struct it6505 *it6505 = bridge_to_it6505(bridge);
3062         struct device *dev = it6505->dev;
3063
3064         if (!it6505->cached_edid) {
3065                 it6505->cached_edid = drm_edid_read_custom(connector,
3066                                                            it6505_get_edid_block,
3067                                                            it6505);
3068
3069                 if (!it6505->cached_edid) {
3070                         DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3071                         return NULL;
3072                 }
3073         }
3074
3075         return drm_edid_dup(it6505->cached_edid);
3076 }
3077
3078 static const struct drm_bridge_funcs it6505_bridge_funcs = {
3079         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3080         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3081         .atomic_reset = drm_atomic_helper_bridge_reset,
3082         .attach = it6505_bridge_attach,
3083         .detach = it6505_bridge_detach,
3084         .mode_valid = it6505_bridge_mode_valid,
3085         .atomic_enable = it6505_bridge_atomic_enable,
3086         .atomic_disable = it6505_bridge_atomic_disable,
3087         .atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3088         .atomic_post_disable = it6505_bridge_atomic_post_disable,
3089         .detect = it6505_bridge_detect,
3090         .edid_read = it6505_bridge_edid_read,
3091 };
3092
3093 static __maybe_unused int it6505_bridge_resume(struct device *dev)
3094 {
3095         struct it6505 *it6505 = dev_get_drvdata(dev);
3096
3097         return it6505_poweron(it6505);
3098 }
3099
3100 static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3101 {
3102         struct it6505 *it6505 = dev_get_drvdata(dev);
3103
3104         return it6505_poweroff(it6505);
3105 }
3106
3107 static const struct dev_pm_ops it6505_bridge_pm_ops = {
3108         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3109         SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3110 };
3111
3112 static int it6505_init_pdata(struct it6505 *it6505)
3113 {
3114         struct it6505_platform_data *pdata = &it6505->pdata;
3115         struct device *dev = it6505->dev;
3116
3117         /* 1.0V digital core power regulator  */
3118         pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3119         if (IS_ERR(pdata->pwr18)) {
3120                 dev_err(dev, "pwr18 regulator not found");
3121                 return PTR_ERR(pdata->pwr18);
3122         }
3123
3124         pdata->ovdd = devm_regulator_get(dev, "ovdd");
3125         if (IS_ERR(pdata->ovdd)) {
3126                 dev_err(dev, "ovdd regulator not found");
3127                 return PTR_ERR(pdata->ovdd);
3128         }
3129
3130         pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3131         if (IS_ERR(pdata->gpiod_reset)) {
3132                 dev_err(dev, "gpiod_reset gpio not found");
3133                 return PTR_ERR(pdata->gpiod_reset);
3134         }
3135
3136         return 0;
3137 }
3138
3139 static int it6505_get_data_lanes_count(const struct device_node *endpoint,
3140                                        const unsigned int min,
3141                                        const unsigned int max)
3142 {
3143         int ret;
3144
3145         ret = of_property_count_u32_elems(endpoint, "data-lanes");
3146         if (ret < 0)
3147                 return ret;
3148
3149         if (ret < min || ret > max)
3150                 return -EINVAL;
3151
3152         return ret;
3153 }
3154
3155 static void it6505_parse_dt(struct it6505 *it6505)
3156 {
3157         struct device *dev = it6505->dev;
3158         struct device_node *np = dev->of_node, *ep = NULL;
3159         int len;
3160         u64 link_frequencies;
3161         u32 data_lanes[4];
3162         u32 *afe_setting = &it6505->afe_setting;
3163         u32 *max_lane_count = &it6505->max_lane_count;
3164         u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
3165
3166         it6505->lane_swap_disabled =
3167                 device_property_read_bool(dev, "no-laneswap");
3168
3169         if (it6505->lane_swap_disabled)
3170                 it6505->lane_swap = false;
3171
3172         if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3173                 if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3174                         dev_err(dev, "afe setting error, use default");
3175                         *afe_setting = 0;
3176                 }
3177         } else {
3178                 *afe_setting = 0;
3179         }
3180
3181         ep = of_graph_get_endpoint_by_regs(np, 1, 0);
3182         of_node_put(ep);
3183
3184         if (ep) {
3185                 len = it6505_get_data_lanes_count(ep, 1, 4);
3186
3187                 if (len > 0 && len != 3) {
3188                         of_property_read_u32_array(ep, "data-lanes",
3189                                                    data_lanes, len);
3190                         *max_lane_count = len;
3191                 } else {
3192                         *max_lane_count = MAX_LANE_COUNT;
3193                         dev_err(dev, "error data-lanes, use default");
3194                 }
3195         } else {
3196                 *max_lane_count = MAX_LANE_COUNT;
3197                 dev_err(dev, "error endpoint, use default");
3198         }
3199
3200         ep = of_graph_get_endpoint_by_regs(np, 0, 0);
3201         of_node_put(ep);
3202
3203         if (ep) {
3204                 len = of_property_read_variable_u64_array(ep,
3205                                                           "link-frequencies",
3206                                                           &link_frequencies, 0,
3207                                                           1);
3208                 if (len >= 0) {
3209                         do_div(link_frequencies, 1000);
3210                         if (link_frequencies > 297000) {
3211                                 dev_err(dev,
3212                                         "max pixel clock error, use default");
3213                                 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3214                         } else {
3215                                 *max_dpi_pixel_clock = link_frequencies;
3216                         }
3217                 } else {
3218                         dev_err(dev, "error link frequencies, use default");
3219                         *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3220                 }
3221         } else {
3222                 dev_err(dev, "error endpoint, use default");
3223                 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3224         }
3225
3226         DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
3227                              it6505->afe_setting, it6505->max_lane_count);
3228         DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
3229                              it6505->max_dpi_pixel_clock);
3230 }
3231
3232 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3233                                            size_t len, loff_t *ppos)
3234 {
3235         struct it6505 *it6505 = file->private_data;
3236         struct drm_display_mode *vid;
3237         u8 read_buf[READ_BUFFER_SIZE];
3238         u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3239         ssize_t ret, count;
3240
3241         if (!it6505)
3242                 return -ENODEV;
3243
3244         it6505_calc_video_info(it6505);
3245         vid = &it6505->video_info;
3246         str += scnprintf(str, end - str, "---video timing---\n");
3247         str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3248                          vid->clock / 1000, vid->clock % 1000);
3249         str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3250         str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3251         str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3252                          vid->hsync_start - vid->hdisplay);
3253         str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3254                          vid->hsync_end - vid->hsync_start);
3255         str += scnprintf(str, end - str, "HBackPorch:%d\n",
3256                          vid->htotal - vid->hsync_end);
3257         str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3258         str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3259         str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3260                          vid->vsync_start - vid->vdisplay);
3261         str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3262                          vid->vsync_end - vid->vsync_start);
3263         str += scnprintf(str, end - str, "VBackPorch:%d\n",
3264                          vid->vtotal - vid->vsync_end);
3265
3266         count = str - read_buf;
3267         ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3268
3269         return ret;
3270 }
3271
3272 static int force_power_on_off_debugfs_write(void *data, u64 value)
3273 {
3274         struct it6505 *it6505 = data;
3275
3276         if (!it6505)
3277                 return -ENODEV;
3278
3279         if (value)
3280                 it6505_poweron(it6505);
3281         else
3282                 it6505_poweroff(it6505);
3283
3284         return 0;
3285 }
3286
3287 static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3288 {
3289         struct it6505 *it6505 = data;
3290
3291         if (!it6505)
3292                 return -ENODEV;
3293
3294         *buf = it6505->enable_drv_hold;
3295
3296         return 0;
3297 }
3298
3299 static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3300 {
3301         struct it6505 *it6505 = data;
3302
3303         if (!it6505)
3304                 return -ENODEV;
3305
3306         it6505->enable_drv_hold = drv_hold;
3307
3308         if (it6505->enable_drv_hold) {
3309                 it6505_int_mask_disable(it6505);
3310         } else {
3311                 it6505_clear_int(it6505);
3312                 it6505_int_mask_enable(it6505);
3313
3314                 if (it6505->powered) {
3315                         it6505->connector_status =
3316                                         it6505_get_sink_hpd_status(it6505) ?
3317                                         connector_status_connected :
3318                                         connector_status_disconnected;
3319                 } else {
3320                         it6505->connector_status =
3321                                         connector_status_disconnected;
3322                 }
3323         }
3324
3325         return 0;
3326 }
3327
3328 static const struct file_operations receive_timing_fops = {
3329         .owner = THIS_MODULE,
3330         .open = simple_open,
3331         .read = receive_timing_debugfs_show,
3332         .llseek = default_llseek,
3333 };
3334
3335 DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3336                          force_power_on_off_debugfs_write, "%llu\n");
3337
3338 DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3339                          enable_drv_hold_debugfs_write, "%llu\n");
3340
3341 static const struct debugfs_entries debugfs_entry[] = {
3342         { "receive_timing", &receive_timing_fops },
3343         { "force_power_on_off", &fops_force_power },
3344         { "enable_drv_hold", &fops_enable_drv_hold },
3345         { NULL, NULL },
3346 };
3347
3348 static void debugfs_create_files(struct it6505 *it6505)
3349 {
3350         int i = 0;
3351
3352         while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3353                 debugfs_create_file(debugfs_entry[i].name, 0644,
3354                                     it6505->debugfs, it6505,
3355                                     debugfs_entry[i].fops);
3356                 i++;
3357         }
3358 }
3359
3360 static void debugfs_init(struct it6505 *it6505)
3361 {
3362         struct device *dev = it6505->dev;
3363
3364         it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3365
3366         if (IS_ERR(it6505->debugfs)) {
3367                 dev_err(dev, "failed to create debugfs root");
3368                 return;
3369         }
3370
3371         debugfs_create_files(it6505);
3372 }
3373
3374 static void it6505_debugfs_remove(struct it6505 *it6505)
3375 {
3376         debugfs_remove_recursive(it6505->debugfs);
3377 }
3378
3379 static void it6505_shutdown(struct i2c_client *client)
3380 {
3381         struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3382
3383         if (it6505->powered)
3384                 it6505_lane_off(it6505);
3385 }
3386
3387 static int it6505_i2c_probe(struct i2c_client *client)
3388 {
3389         struct it6505 *it6505;
3390         struct device *dev = &client->dev;
3391         struct extcon_dev *extcon;
3392         int err, intp_irq;
3393
3394         it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3395         if (!it6505)
3396                 return -ENOMEM;
3397
3398         mutex_init(&it6505->extcon_lock);
3399         mutex_init(&it6505->mode_lock);
3400         mutex_init(&it6505->aux_lock);
3401
3402         it6505->bridge.of_node = client->dev.of_node;
3403         it6505->connector_status = connector_status_disconnected;
3404         it6505->dev = &client->dev;
3405         i2c_set_clientdata(client, it6505);
3406
3407         /* get extcon device from DTS */
3408         extcon = extcon_get_edev_by_phandle(dev, 0);
3409         if (PTR_ERR(extcon) == -EPROBE_DEFER)
3410                 return -EPROBE_DEFER;
3411         if (IS_ERR(extcon)) {
3412                 dev_err(dev, "can not get extcon device!");
3413                 return PTR_ERR(extcon);
3414         }
3415
3416         it6505->extcon = extcon;
3417
3418         it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3419         if (IS_ERR(it6505->regmap)) {
3420                 dev_err(dev, "regmap i2c init failed");
3421                 err = PTR_ERR(it6505->regmap);
3422                 return err;
3423         }
3424
3425         err = it6505_init_pdata(it6505);
3426         if (err) {
3427                 dev_err(dev, "Failed to initialize pdata: %d", err);
3428                 return err;
3429         }
3430
3431         it6505_parse_dt(it6505);
3432
3433         intp_irq = client->irq;
3434
3435         if (!intp_irq) {
3436                 dev_err(dev, "Failed to get INTP IRQ");
3437                 err = -ENODEV;
3438                 return err;
3439         }
3440
3441         err = devm_request_threaded_irq(&client->dev, intp_irq, NULL,
3442                                         it6505_int_threaded_handler,
3443                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3444                                         "it6505-intp", it6505);
3445         if (err) {
3446                 dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3447                 return err;
3448         }
3449
3450         INIT_WORK(&it6505->link_works, it6505_link_training_work);
3451         INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3452         INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3453         init_completion(&it6505->extcon_completion);
3454         memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3455         it6505->powered = false;
3456         it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3457
3458         if (DEFAULT_PWR_ON)
3459                 it6505_poweron(it6505);
3460
3461         DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3462         debugfs_init(it6505);
3463         pm_runtime_enable(dev);
3464
3465         it6505->aux.name = "DP-AUX";
3466         it6505->aux.dev = dev;
3467         it6505->aux.transfer = it6505_aux_transfer;
3468         drm_dp_aux_init(&it6505->aux);
3469
3470         it6505->bridge.funcs = &it6505_bridge_funcs;
3471         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3472         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3473                              DRM_BRIDGE_OP_HPD;
3474         drm_bridge_add(&it6505->bridge);
3475
3476         return 0;
3477 }
3478
3479 static void it6505_i2c_remove(struct i2c_client *client)
3480 {
3481         struct it6505 *it6505 = i2c_get_clientdata(client);
3482
3483         drm_bridge_remove(&it6505->bridge);
3484         drm_dp_aux_unregister(&it6505->aux);
3485         it6505_debugfs_remove(it6505);
3486         it6505_poweroff(it6505);
3487         it6505_remove_edid(it6505);
3488 }
3489
3490 static const struct i2c_device_id it6505_id[] = {
3491         { "it6505", 0 },
3492         { }
3493 };
3494
3495 MODULE_DEVICE_TABLE(i2c, it6505_id);
3496
3497 static const struct of_device_id it6505_of_match[] = {
3498         { .compatible = "ite,it6505" },
3499         { }
3500 };
3501
3502 static struct i2c_driver it6505_i2c_driver = {
3503         .driver = {
3504                 .name = "it6505",
3505                 .of_match_table = it6505_of_match,
3506                 .pm = &it6505_bridge_pm_ops,
3507         },
3508         .probe = it6505_i2c_probe,
3509         .remove = it6505_i2c_remove,
3510         .shutdown = it6505_shutdown,
3511         .id_table = it6505_id,
3512 };
3513
3514 module_i2c_driver(it6505_i2c_driver);
3515
3516 MODULE_AUTHOR("Allen Chen <[email protected]>");
3517 MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3518 MODULE_LICENSE("GPL v2");