drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
  32
  33 enum smu_event_type {
  34         SMU_EVENT_RESET_COMPLETE = 0,
  35 };
  36
  37 struct amd_vce_state {
  38         /* vce clocks */
  39         u32 evclk;
  40         u32 ecclk;
  41         /* gpu clocks */
  42         u32 sclk;
  43         u32 mclk;
  44         u8 clk_idx;
  45         u8 pstate;
  46 };
  47
  48
  49 enum amd_dpm_forced_level {
  50         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  51         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  52         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  53         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  58         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  59         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  60 };
  61
  62 enum amd_pm_state_type {
  63         /* not used for dpm */
  64         POWER_STATE_TYPE_DEFAULT,
  65         POWER_STATE_TYPE_POWERSAVE,
  66         /* user selectable states */
  67         POWER_STATE_TYPE_BATTERY,
  68         POWER_STATE_TYPE_BALANCED,
  69         POWER_STATE_TYPE_PERFORMANCE,
  70         /* internal states */
  71         POWER_STATE_TYPE_INTERNAL_UVD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  74         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  75         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  76         POWER_STATE_TYPE_INTERNAL_BOOT,
  77         POWER_STATE_TYPE_INTERNAL_THERMAL,
  78         POWER_STATE_TYPE_INTERNAL_ACPI,
  79         POWER_STATE_TYPE_INTERNAL_ULV,
  80         POWER_STATE_TYPE_INTERNAL_3DPERF,
  81 };
  82
  83 #define AMD_MAX_VCE_LEVELS 6
  84
  85 enum amd_vce_level {
  86         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  87         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  88         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  89         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  90         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  91         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  92 };
  93
  94 enum amd_fan_ctrl_mode {
  95         AMD_FAN_CTRL_NONE = 0,
  96         AMD_FAN_CTRL_MANUAL = 1,
  97         AMD_FAN_CTRL_AUTO = 2,
  98 };
  99
 100 enum pp_clock_type {
 101         PP_SCLK,
 102         PP_MCLK,
 103         PP_PCIE,
 104         PP_SOCCLK,
 105         PP_FCLK,
 106         PP_DCEFCLK,
 107         PP_VCLK,
 108         PP_VCLK1,
 109         PP_DCLK,
 110         PP_DCLK1,
 111         OD_SCLK,
 112         OD_MCLK,
 113         OD_VDDC_CURVE,
 114         OD_RANGE,
 115         OD_VDDGFX_OFFSET,
 116         OD_CCLK,
 117         OD_FAN_CURVE,
 118         OD_ACOUSTIC_LIMIT,
 119         OD_ACOUSTIC_TARGET,
 120         OD_FAN_TARGET_TEMPERATURE,
 121         OD_FAN_MINIMUM_PWM,
 122 };
 123
 124 enum amd_pp_sensors {
 125         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 126         AMDGPU_PP_SENSOR_CPU_CLK,
 127         AMDGPU_PP_SENSOR_VDDNB,
 128         AMDGPU_PP_SENSOR_VDDGFX,
 129         AMDGPU_PP_SENSOR_UVD_VCLK,
 130         AMDGPU_PP_SENSOR_UVD_DCLK,
 131         AMDGPU_PP_SENSOR_VCE_ECCLK,
 132         AMDGPU_PP_SENSOR_GPU_LOAD,
 133         AMDGPU_PP_SENSOR_MEM_LOAD,
 134         AMDGPU_PP_SENSOR_GFX_MCLK,
 135         AMDGPU_PP_SENSOR_GPU_TEMP,
 136         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 137         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 138         AMDGPU_PP_SENSOR_MEM_TEMP,
 139         AMDGPU_PP_SENSOR_VCE_POWER,
 140         AMDGPU_PP_SENSOR_UVD_POWER,
 141         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 142         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 143         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 144         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 145         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 146         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 147         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 148         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 149         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 150         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 151         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 152         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 153         AMDGPU_PP_SENSOR_VCN_LOAD,
 154 };
 155
 156 enum amd_pp_task {
 157         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 158         AMD_PP_TASK_ENABLE_USER_STATE,
 159         AMD_PP_TASK_READJUST_POWER_STATE,
 160         AMD_PP_TASK_COMPLETE_INIT,
 161         AMD_PP_TASK_MAX
 162 };
 163
 164 enum PP_SMC_POWER_PROFILE {
 165         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 166         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 167         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 168         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 169         PP_SMC_POWER_PROFILE_VR           = 0x4,
 170         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 171         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 172         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 173         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 174         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 175         PP_SMC_POWER_PROFILE_COUNT,
 176 };
 177
 178 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 179
 180
 181
 182 enum {
 183         PP_GROUP_UNKNOWN = 0,
 184         PP_GROUP_GFX = 1,
 185         PP_GROUP_SYS,
 186         PP_GROUP_MAX
 187 };
 188
 189 enum PP_OD_DPM_TABLE_COMMAND {
 190         PP_OD_EDIT_SCLK_VDDC_TABLE,
 191         PP_OD_EDIT_MCLK_VDDC_TABLE,
 192         PP_OD_EDIT_CCLK_VDDC_TABLE,
 193         PP_OD_EDIT_VDDC_CURVE,
 194         PP_OD_RESTORE_DEFAULT_TABLE,
 195         PP_OD_COMMIT_DPM_TABLE,
 196         PP_OD_EDIT_VDDGFX_OFFSET,
 197         PP_OD_EDIT_FAN_CURVE,
 198         PP_OD_EDIT_ACOUSTIC_LIMIT,
 199         PP_OD_EDIT_ACOUSTIC_TARGET,
 200         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 201         PP_OD_EDIT_FAN_MINIMUM_PWM,
 202 };
 203
 204 struct pp_states_info {
 205         uint32_t nums;
 206         uint32_t states[16];
 207 };
 208
 209 enum PP_HWMON_TEMP {
 210         PP_TEMP_EDGE = 0,
 211         PP_TEMP_JUNCTION,
 212         PP_TEMP_MEM,
 213         PP_TEMP_MAX
 214 };
 215
 216 enum pp_mp1_state {
 217         PP_MP1_STATE_NONE,
 218         PP_MP1_STATE_SHUTDOWN,
 219         PP_MP1_STATE_UNLOAD,
 220         PP_MP1_STATE_RESET,
 221 };
 222
 223 enum pp_df_cstate {
 224         DF_CSTATE_DISALLOW = 0,
 225         DF_CSTATE_ALLOW,
 226 };
 227
 228 /**
 229  * DOC: amdgpu_pp_power
 230  *
 231  * APU power is managed to system-level requirements through the PPT
 232  * (package power tracking) feature. PPT is intended to limit power to the
 233  * requirements of the power source and could be dynamically updated to
 234  * maximize APU performance within the system power budget.
 235  *
 236  * Two types of power measurement can be requested, where supported, with
 237  * :c:type:`enum pp_power_type <pp_power_type>`.
 238  */
 239
 240 /**
 241  * enum pp_power_limit_level - Used to query the power limits
 242  *
 243  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 244  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 245  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 246  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 247  */
 248 enum pp_power_limit_level {
 249         PP_PWR_LIMIT_MIN = -1,
 250         PP_PWR_LIMIT_CURRENT,
 251         PP_PWR_LIMIT_DEFAULT,
 252         PP_PWR_LIMIT_MAX,
 253 };
 254
 255 /**
 256  * enum pp_power_type - Used to specify the type of the requested power
 257  *
 258  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 259  * moving average of APU power (default ~5000 ms).
 260  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 261  * where supported.
 262  */
 263 enum pp_power_type {
 264         PP_PWR_TYPE_SUSTAINED,
 265         PP_PWR_TYPE_FAST,
 266 };
 267
 268 enum pp_xgmi_plpd_mode {
 269         XGMI_PLPD_NONE = -1,
 270         XGMI_PLPD_DISALLOW,
 271         XGMI_PLPD_DEFAULT,
 272         XGMI_PLPD_OPTIMIZED,
 273         XGMI_PLPD_COUNT,
 274 };
 275
 276 enum pp_pm_policy {
 277         PP_PM_POLICY_NONE = -1,
 278         PP_PM_POLICY_SOC_PSTATE = 0,
 279         PP_PM_POLICY_XGMI_PLPD,
 280         PP_PM_POLICY_NUM,
 281 };
 282
 283 enum pp_policy_soc_pstate {
 284         SOC_PSTATE_DEFAULT = 0,
 285         SOC_PSTATE_0,
 286         SOC_PSTATE_1,
 287         SOC_PSTATE_2,
 288         SOC_PSTAT_COUNT,
 289 };
 290
 291 #define PP_POLICY_MAX_LEVELS 5
 292
 293 #define PP_GROUP_MASK        0xF0000000
 294 #define PP_GROUP_SHIFT       28
 295
 296 #define PP_BLOCK_MASK        0x0FFFFF00
 297 #define PP_BLOCK_SHIFT       8
 298
 299 #define PP_BLOCK_GFX_CG         0x01
 300 #define PP_BLOCK_GFX_MG         0x02
 301 #define PP_BLOCK_GFX_3D         0x04
 302 #define PP_BLOCK_GFX_RLC        0x08
 303 #define PP_BLOCK_GFX_CP         0x10
 304 #define PP_BLOCK_SYS_BIF        0x01
 305 #define PP_BLOCK_SYS_MC         0x02
 306 #define PP_BLOCK_SYS_ROM        0x04
 307 #define PP_BLOCK_SYS_DRM        0x08
 308 #define PP_BLOCK_SYS_HDP        0x10
 309 #define PP_BLOCK_SYS_SDMA       0x20
 310
 311 #define PP_STATE_MASK           0x0000000F
 312 #define PP_STATE_SHIFT          0
 313 #define PP_STATE_SUPPORT_MASK   0x000000F0
 314 #define PP_STATE_SUPPORT_SHIFT  0
 315
 316 #define PP_STATE_CG             0x01
 317 #define PP_STATE_LS             0x02
 318 #define PP_STATE_DS             0x04
 319 #define PP_STATE_SD             0x08
 320 #define PP_STATE_SUPPORT_CG     0x10
 321 #define PP_STATE_SUPPORT_LS     0x20
 322 #define PP_STATE_SUPPORT_DS     0x40
 323 #define PP_STATE_SUPPORT_SD     0x80
 324
 325 #define PP_CG_MSG_ID(group, block, support, state) \
 326                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 327                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 328
 329 #define XGMI_MODE_PSTATE_D3 0
 330 #define XGMI_MODE_PSTATE_D0 1
 331
 332 #define NUM_HBM_INSTANCES 4
 333 #define NUM_XGMI_LINKS 8
 334 #define MAX_GFX_CLKS 8
 335 #define MAX_CLKS 4
 336 #define NUM_VCN 4
 337 #define NUM_JPEG_ENG 32
 338
 339 struct seq_file;
 340 enum amd_pp_clock_type;
 341 struct amd_pp_simple_clock_info;
 342 struct amd_pp_display_configuration;
 343 struct amd_pp_clock_info;
 344 struct pp_display_clock_request;
 345 struct pp_clock_levels_with_voltage;
 346 struct pp_clock_levels_with_latency;
 347 struct amd_pp_clocks;
 348 struct pp_smu_wm_range_sets;
 349 struct pp_smu_nv_clock_table;
 350 struct dpm_clocks;
 351
 352 struct amd_pm_funcs {
 353 /* export for dpm on ci and si */
 354         int (*pre_set_power_state)(void *handle);
 355         int (*set_power_state)(void *handle);
 356         void (*post_set_power_state)(void *handle);
 357         void (*display_configuration_changed)(void *handle);
 358         void (*print_power_state)(void *handle, void *ps);
 359         bool (*vblank_too_short)(void *handle);
 360         void (*enable_bapm)(void *handle, bool enable);
 361         int (*check_state_equal)(void *handle,
 362                                 void  *cps,
 363                                 void  *rps,
 364                                 bool  *equal);
 365 /* export for sysfs */
 366         int (*set_fan_control_mode)(void *handle, u32 mode);
 367         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 368         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 369         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 370         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 371         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 372         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 373         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 374         int (*get_sclk_od)(void *handle);
 375         int (*set_sclk_od)(void *handle, uint32_t value);
 376         int (*get_mclk_od)(void *handle);
 377         int (*set_mclk_od)(void *handle, uint32_t value);
 378         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 379         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 380         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 381         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 382         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 383         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 384         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 385         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 386         int (*get_pp_table)(void *handle, char **table);
 387         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 388         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 389         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 390 /* export to amdgpu */
 391         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 392         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 393                         enum amd_pm_state_type *user_state);
 394         int (*load_firmware)(void *handle);
 395         int (*wait_for_fw_loading_complete)(void *handle);
 396         int (*set_powergating_by_smu)(void *handle,
 397                                 uint32_t block_type, bool gate);
 398         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 399         int (*set_power_limit)(void *handle, uint32_t n);
 400         int (*get_power_limit)(void *handle, uint32_t *limit,
 401                         enum pp_power_limit_level pp_limit_level,
 402                         enum pp_power_type power_type);
 403         int (*get_power_profile_mode)(void *handle, char *buf);
 404         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 405         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 406         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 407                                   long *input, uint32_t size);
 408         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 409         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 410         int (*gfx_state_change_set)(void *handle, uint32_t state);
 411 /* export to DC */
 412         u32 (*get_sclk)(void *handle, bool low);
 413         u32 (*get_mclk)(void *handle, bool low);
 414         int (*display_configuration_change)(void *handle,
 415                 const struct amd_pp_display_configuration *input);
 416         int (*get_display_power_level)(void *handle,
 417                 struct amd_pp_simple_clock_info *output);
 418         int (*get_current_clocks)(void *handle,
 419                 struct amd_pp_clock_info *clocks);
 420         int (*get_clock_by_type)(void *handle,
 421                 enum amd_pp_clock_type type,
 422                 struct amd_pp_clocks *clocks);
 423         int (*get_clock_by_type_with_latency)(void *handle,
 424                 enum amd_pp_clock_type type,
 425                 struct pp_clock_levels_with_latency *clocks);
 426         int (*get_clock_by_type_with_voltage)(void *handle,
 427                 enum amd_pp_clock_type type,
 428                 struct pp_clock_levels_with_voltage *clocks);
 429         int (*set_watermarks_for_clocks_ranges)(void *handle,
 430                                                 void *clock_ranges);
 431         int (*display_clock_voltage_request)(void *handle,
 432                                 struct pp_display_clock_request *clock);
 433         int (*get_display_mode_validation_clocks)(void *handle,
 434                 struct amd_pp_simple_clock_info *clocks);
 435         int (*notify_smu_enable_pwe)(void *handle);
 436         int (*enable_mgpu_fan_boost)(void *handle);
 437         int (*set_active_display_count)(void *handle, uint32_t count);
 438         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 439         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 440         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 441         int (*get_asic_baco_capability)(void *handle);
 442         int (*get_asic_baco_state)(void *handle, int *state);
 443         int (*set_asic_baco_state)(void *handle, int state);
 444         int (*get_ppfeature_status)(void *handle, char *buf);
 445         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 446         int (*asic_reset_mode_2)(void *handle);
 447         int (*asic_reset_enable_gfx_features)(void *handle);
 448         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 449         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 450         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 451         ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
 452         int (*set_watermarks_for_clock_ranges)(void *handle,
 453                                                struct pp_smu_wm_range_sets *ranges);
 454         int (*display_disable_memory_clock_switch)(void *handle,
 455                                                    bool disable_memory_clock_switch);
 456         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 457                                                 struct pp_smu_nv_clock_table *max_clocks);
 458         int (*get_uclk_dpm_states)(void *handle,
 459                                    unsigned int *clock_values_in_khz,
 460                                    unsigned int *num_states);
 461         int (*get_dpm_clock_table)(void *handle,
 462                                    struct dpm_clocks *clock_table);
 463         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 464         void (*pm_compute_clocks)(void *handle);
 465         int (*notify_rlc_state)(void *handle, bool en);
 466 };
 467
 468 struct metrics_table_header {
 469         uint16_t                        structure_size;
 470         uint8_t                         format_revision;
 471         uint8_t                         content_revision;
 472 };
 473
 474 /*
 475  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 476  * Use gpu_metrics_v1_1 or later instead.
 477  */
 478 struct gpu_metrics_v1_0 {
 479         struct metrics_table_header     common_header;
 480
 481         /* Driver attached timestamp (in ns) */
 482         uint64_t                        system_clock_counter;
 483
 484         /* Temperature */
 485         uint16_t                        temperature_edge;
 486         uint16_t                        temperature_hotspot;
 487         uint16_t                        temperature_mem;
 488         uint16_t                        temperature_vrgfx;
 489         uint16_t                        temperature_vrsoc;
 490         uint16_t                        temperature_vrmem;
 491
 492         /* Utilization */
 493         uint16_t                        average_gfx_activity;
 494         uint16_t                        average_umc_activity; // memory controller
 495         uint16_t                        average_mm_activity; // UVD or VCN
 496
 497         /* Power/Energy */
 498         uint16_t                        average_socket_power;
 499         uint32_t                        energy_accumulator;
 500
 501         /* Average clocks */
 502         uint16_t                        average_gfxclk_frequency;
 503         uint16_t                        average_socclk_frequency;
 504         uint16_t                        average_uclk_frequency;
 505         uint16_t                        average_vclk0_frequency;
 506         uint16_t                        average_dclk0_frequency;
 507         uint16_t                        average_vclk1_frequency;
 508         uint16_t                        average_dclk1_frequency;
 509
 510         /* Current clocks */
 511         uint16_t                        current_gfxclk;
 512         uint16_t                        current_socclk;
 513         uint16_t                        current_uclk;
 514         uint16_t                        current_vclk0;
 515         uint16_t                        current_dclk0;
 516         uint16_t                        current_vclk1;
 517         uint16_t                        current_dclk1;
 518
 519         /* Throttle status */
 520         uint32_t                        throttle_status;
 521
 522         /* Fans */
 523         uint16_t                        current_fan_speed;
 524
 525         /* Link width/speed */
 526         uint8_t                         pcie_link_width;
 527         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 528 };
 529
 530 struct gpu_metrics_v1_1 {
 531         struct metrics_table_header     common_header;
 532
 533         /* Temperature */
 534         uint16_t                        temperature_edge;
 535         uint16_t                        temperature_hotspot;
 536         uint16_t                        temperature_mem;
 537         uint16_t                        temperature_vrgfx;
 538         uint16_t                        temperature_vrsoc;
 539         uint16_t                        temperature_vrmem;
 540
 541         /* Utilization */
 542         uint16_t                        average_gfx_activity;
 543         uint16_t                        average_umc_activity; // memory controller
 544         uint16_t                        average_mm_activity; // UVD or VCN
 545
 546         /* Power/Energy */
 547         uint16_t                        average_socket_power;
 548         uint64_t                        energy_accumulator;
 549
 550         /* Driver attached timestamp (in ns) */
 551         uint64_t                        system_clock_counter;
 552
 553         /* Average clocks */
 554         uint16_t                        average_gfxclk_frequency;
 555         uint16_t                        average_socclk_frequency;
 556         uint16_t                        average_uclk_frequency;
 557         uint16_t                        average_vclk0_frequency;
 558         uint16_t                        average_dclk0_frequency;
 559         uint16_t                        average_vclk1_frequency;
 560         uint16_t                        average_dclk1_frequency;
 561
 562         /* Current clocks */
 563         uint16_t                        current_gfxclk;
 564         uint16_t                        current_socclk;
 565         uint16_t                        current_uclk;
 566         uint16_t                        current_vclk0;
 567         uint16_t                        current_dclk0;
 568         uint16_t                        current_vclk1;
 569         uint16_t                        current_dclk1;
 570
 571         /* Throttle status */
 572         uint32_t                        throttle_status;
 573
 574         /* Fans */
 575         uint16_t                        current_fan_speed;
 576
 577         /* Link width/speed */
 578         uint16_t                        pcie_link_width;
 579         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 580
 581         uint16_t                        padding;
 582
 583         uint32_t                        gfx_activity_acc;
 584         uint32_t                        mem_activity_acc;
 585
 586         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 587 };
 588
 589 struct gpu_metrics_v1_2 {
 590         struct metrics_table_header     common_header;
 591
 592         /* Temperature */
 593         uint16_t                        temperature_edge;
 594         uint16_t                        temperature_hotspot;
 595         uint16_t                        temperature_mem;
 596         uint16_t                        temperature_vrgfx;
 597         uint16_t                        temperature_vrsoc;
 598         uint16_t                        temperature_vrmem;
 599
 600         /* Utilization */
 601         uint16_t                        average_gfx_activity;
 602         uint16_t                        average_umc_activity; // memory controller
 603         uint16_t                        average_mm_activity; // UVD or VCN
 604
 605         /* Power/Energy */
 606         uint16_t                        average_socket_power;
 607         uint64_t                        energy_accumulator;
 608
 609         /* Driver attached timestamp (in ns) */
 610         uint64_t                        system_clock_counter;
 611
 612         /* Average clocks */
 613         uint16_t                        average_gfxclk_frequency;
 614         uint16_t                        average_socclk_frequency;
 615         uint16_t                        average_uclk_frequency;
 616         uint16_t                        average_vclk0_frequency;
 617         uint16_t                        average_dclk0_frequency;
 618         uint16_t                        average_vclk1_frequency;
 619         uint16_t                        average_dclk1_frequency;
 620
 621         /* Current clocks */
 622         uint16_t                        current_gfxclk;
 623         uint16_t                        current_socclk;
 624         uint16_t                        current_uclk;
 625         uint16_t                        current_vclk0;
 626         uint16_t                        current_dclk0;
 627         uint16_t                        current_vclk1;
 628         uint16_t                        current_dclk1;
 629
 630         /* Throttle status (ASIC dependent) */
 631         uint32_t                        throttle_status;
 632
 633         /* Fans */
 634         uint16_t                        current_fan_speed;
 635
 636         /* Link width/speed */
 637         uint16_t                        pcie_link_width;
 638         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 639
 640         uint16_t                        padding;
 641
 642         uint32_t                        gfx_activity_acc;
 643         uint32_t                        mem_activity_acc;
 644
 645         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 646
 647         /* PMFW attached timestamp (10ns resolution) */
 648         uint64_t                        firmware_timestamp;
 649 };
 650
 651 struct gpu_metrics_v1_3 {
 652         struct metrics_table_header     common_header;
 653
 654         /* Temperature */
 655         uint16_t                        temperature_edge;
 656         uint16_t                        temperature_hotspot;
 657         uint16_t                        temperature_mem;
 658         uint16_t                        temperature_vrgfx;
 659         uint16_t                        temperature_vrsoc;
 660         uint16_t                        temperature_vrmem;
 661
 662         /* Utilization */
 663         uint16_t                        average_gfx_activity;
 664         uint16_t                        average_umc_activity; // memory controller
 665         uint16_t                        average_mm_activity; // UVD or VCN
 666
 667         /* Power/Energy */
 668         uint16_t                        average_socket_power;
 669         uint64_t                        energy_accumulator;
 670
 671         /* Driver attached timestamp (in ns) */
 672         uint64_t                        system_clock_counter;
 673
 674         /* Average clocks */
 675         uint16_t                        average_gfxclk_frequency;
 676         uint16_t                        average_socclk_frequency;
 677         uint16_t                        average_uclk_frequency;
 678         uint16_t                        average_vclk0_frequency;
 679         uint16_t                        average_dclk0_frequency;
 680         uint16_t                        average_vclk1_frequency;
 681         uint16_t                        average_dclk1_frequency;
 682
 683         /* Current clocks */
 684         uint16_t                        current_gfxclk;
 685         uint16_t                        current_socclk;
 686         uint16_t                        current_uclk;
 687         uint16_t                        current_vclk0;
 688         uint16_t                        current_dclk0;
 689         uint16_t                        current_vclk1;
 690         uint16_t                        current_dclk1;
 691
 692         /* Throttle status */
 693         uint32_t                        throttle_status;
 694
 695         /* Fans */
 696         uint16_t                        current_fan_speed;
 697
 698         /* Link width/speed */
 699         uint16_t                        pcie_link_width;
 700         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 701
 702         uint16_t                        padding;
 703
 704         uint32_t                        gfx_activity_acc;
 705         uint32_t                        mem_activity_acc;
 706
 707         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 708
 709         /* PMFW attached timestamp (10ns resolution) */
 710         uint64_t                        firmware_timestamp;
 711
 712         /* Voltage (mV) */
 713         uint16_t                        voltage_soc;
 714         uint16_t                        voltage_gfx;
 715         uint16_t                        voltage_mem;
 716
 717         uint16_t                        padding1;
 718
 719         /* Throttle status (ASIC independent) */
 720         uint64_t                        indep_throttle_status;
 721 };
 722
 723 struct gpu_metrics_v1_4 {
 724         struct metrics_table_header     common_header;
 725
 726         /* Temperature (Celsius) */
 727         uint16_t                        temperature_hotspot;
 728         uint16_t                        temperature_mem;
 729         uint16_t                        temperature_vrsoc;
 730
 731         /* Power (Watts) */
 732         uint16_t                        curr_socket_power;
 733
 734         /* Utilization (%) */
 735         uint16_t                        average_gfx_activity;
 736         uint16_t                        average_umc_activity; // memory controller
 737         uint16_t                        vcn_activity[NUM_VCN];
 738
 739         /* Energy (15.259uJ (2^-16) units) */
 740         uint64_t                        energy_accumulator;
 741
 742         /* Driver attached timestamp (in ns) */
 743         uint64_t                        system_clock_counter;
 744
 745         /* Throttle status */
 746         uint32_t                        throttle_status;
 747
 748         /* Clock Lock Status. Each bit corresponds to clock instance */
 749         uint32_t                        gfxclk_lock_status;
 750
 751         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 752         uint16_t                        pcie_link_width;
 753         uint16_t                        pcie_link_speed;
 754
 755         /* XGMI bus width and bitrate (in Gbps) */
 756         uint16_t                        xgmi_link_width;
 757         uint16_t                        xgmi_link_speed;
 758
 759         /* Utilization Accumulated (%) */
 760         uint32_t                        gfx_activity_acc;
 761         uint32_t                        mem_activity_acc;
 762
 763         /*PCIE accumulated bandwidth (GB/sec) */
 764         uint64_t                        pcie_bandwidth_acc;
 765
 766         /*PCIE instantaneous bandwidth (GB/sec) */
 767         uint64_t                        pcie_bandwidth_inst;
 768
 769         /* PCIE L0 to recovery state transition accumulated count */
 770         uint64_t                        pcie_l0_to_recov_count_acc;
 771
 772         /* PCIE replay accumulated count */
 773         uint64_t                        pcie_replay_count_acc;
 774
 775         /* PCIE replay rollover accumulated count */
 776         uint64_t                        pcie_replay_rover_count_acc;
 777
 778         /* XGMI accumulated data transfer size(KiloBytes) */
 779         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 780         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 781
 782         /* PMFW attached timestamp (10ns resolution) */
 783         uint64_t                        firmware_timestamp;
 784
 785         /* Current clocks (Mhz) */
 786         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 787         uint16_t                        current_socclk[MAX_CLKS];
 788         uint16_t                        current_vclk0[MAX_CLKS];
 789         uint16_t                        current_dclk0[MAX_CLKS];
 790         uint16_t                        current_uclk;
 791
 792         uint16_t                        padding;
 793 };
 794
 795 struct gpu_metrics_v1_5 {
 796         struct metrics_table_header     common_header;
 797
 798         /* Temperature (Celsius) */
 799         uint16_t                        temperature_hotspot;
 800         uint16_t                        temperature_mem;
 801         uint16_t                        temperature_vrsoc;
 802
 803         /* Power (Watts) */
 804         uint16_t                        curr_socket_power;
 805
 806         /* Utilization (%) */
 807         uint16_t                        average_gfx_activity;
 808         uint16_t                        average_umc_activity; // memory controller
 809         uint16_t                        vcn_activity[NUM_VCN];
 810         uint16_t                        jpeg_activity[NUM_JPEG_ENG];
 811
 812         /* Energy (15.259uJ (2^-16) units) */
 813         uint64_t                        energy_accumulator;
 814
 815         /* Driver attached timestamp (in ns) */
 816         uint64_t                        system_clock_counter;
 817
 818         /* Throttle status */
 819         uint32_t                        throttle_status;
 820
 821         /* Clock Lock Status. Each bit corresponds to clock instance */
 822         uint32_t                        gfxclk_lock_status;
 823
 824         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 825         uint16_t                        pcie_link_width;
 826         uint16_t                        pcie_link_speed;
 827
 828         /* XGMI bus width and bitrate (in Gbps) */
 829         uint16_t                        xgmi_link_width;
 830         uint16_t                        xgmi_link_speed;
 831
 832         /* Utilization Accumulated (%) */
 833         uint32_t                        gfx_activity_acc;
 834         uint32_t                        mem_activity_acc;
 835
 836         /*PCIE accumulated bandwidth (GB/sec) */
 837         uint64_t                        pcie_bandwidth_acc;
 838
 839         /*PCIE instantaneous bandwidth (GB/sec) */
 840         uint64_t                        pcie_bandwidth_inst;
 841
 842         /* PCIE L0 to recovery state transition accumulated count */
 843         uint64_t                        pcie_l0_to_recov_count_acc;
 844
 845         /* PCIE replay accumulated count */
 846         uint64_t                        pcie_replay_count_acc;
 847
 848         /* PCIE replay rollover accumulated count */
 849         uint64_t                        pcie_replay_rover_count_acc;
 850
 851         /* PCIE NAK sent  accumulated count */
 852         uint32_t                        pcie_nak_sent_count_acc;
 853
 854         /* PCIE NAK received accumulated count */
 855         uint32_t                        pcie_nak_rcvd_count_acc;
 856
 857         /* XGMI accumulated data transfer size(KiloBytes) */
 858         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 859         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 860
 861         /* PMFW attached timestamp (10ns resolution) */
 862         uint64_t                        firmware_timestamp;
 863
 864         /* Current clocks (Mhz) */
 865         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 866         uint16_t                        current_socclk[MAX_CLKS];
 867         uint16_t                        current_vclk0[MAX_CLKS];
 868         uint16_t                        current_dclk0[MAX_CLKS];
 869         uint16_t                        current_uclk;
 870
 871         uint16_t                        padding;
 872 };
 873
 874 /*
 875  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 876  * Use gpu_metrics_v2_1 or later instead.
 877  */
 878 struct gpu_metrics_v2_0 {
 879         struct metrics_table_header     common_header;
 880
 881         /* Driver attached timestamp (in ns) */
 882         uint64_t                        system_clock_counter;
 883
 884         /* Temperature */
 885         uint16_t                        temperature_gfx; // gfx temperature on APUs
 886         uint16_t                        temperature_soc; // soc temperature on APUs
 887         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 888         uint16_t                        temperature_l3[2];
 889
 890         /* Utilization */
 891         uint16_t                        average_gfx_activity;
 892         uint16_t                        average_mm_activity; // UVD or VCN
 893
 894         /* Power/Energy */
 895         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 896         uint16_t                        average_cpu_power;
 897         uint16_t                        average_soc_power;
 898         uint16_t                        average_gfx_power;
 899         uint16_t                        average_core_power[8]; // CPU core power on APUs
 900
 901         /* Average clocks */
 902         uint16_t                        average_gfxclk_frequency;
 903         uint16_t                        average_socclk_frequency;
 904         uint16_t                        average_uclk_frequency;
 905         uint16_t                        average_fclk_frequency;
 906         uint16_t                        average_vclk_frequency;
 907         uint16_t                        average_dclk_frequency;
 908
 909         /* Current clocks */
 910         uint16_t                        current_gfxclk;
 911         uint16_t                        current_socclk;
 912         uint16_t                        current_uclk;
 913         uint16_t                        current_fclk;
 914         uint16_t                        current_vclk;
 915         uint16_t                        current_dclk;
 916         uint16_t                        current_coreclk[8]; // CPU core clocks
 917         uint16_t                        current_l3clk[2];
 918
 919         /* Throttle status */
 920         uint32_t                        throttle_status;
 921
 922         /* Fans */
 923         uint16_t                        fan_pwm;
 924
 925         uint16_t                        padding;
 926 };
 927
 928 struct gpu_metrics_v2_1 {
 929         struct metrics_table_header     common_header;
 930
 931         /* Temperature */
 932         uint16_t                        temperature_gfx; // gfx temperature on APUs
 933         uint16_t                        temperature_soc; // soc temperature on APUs
 934         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 935         uint16_t                        temperature_l3[2];
 936
 937         /* Utilization */
 938         uint16_t                        average_gfx_activity;
 939         uint16_t                        average_mm_activity; // UVD or VCN
 940
 941         /* Driver attached timestamp (in ns) */
 942         uint64_t                        system_clock_counter;
 943
 944         /* Power/Energy */
 945         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 946         uint16_t                        average_cpu_power;
 947         uint16_t                        average_soc_power;
 948         uint16_t                        average_gfx_power;
 949         uint16_t                        average_core_power[8]; // CPU core power on APUs
 950
 951         /* Average clocks */
 952         uint16_t                        average_gfxclk_frequency;
 953         uint16_t                        average_socclk_frequency;
 954         uint16_t                        average_uclk_frequency;
 955         uint16_t                        average_fclk_frequency;
 956         uint16_t                        average_vclk_frequency;
 957         uint16_t                        average_dclk_frequency;
 958
 959         /* Current clocks */
 960         uint16_t                        current_gfxclk;
 961         uint16_t                        current_socclk;
 962         uint16_t                        current_uclk;
 963         uint16_t                        current_fclk;
 964         uint16_t                        current_vclk;
 965         uint16_t                        current_dclk;
 966         uint16_t                        current_coreclk[8]; // CPU core clocks
 967         uint16_t                        current_l3clk[2];
 968
 969         /* Throttle status */
 970         uint32_t                        throttle_status;
 971
 972         /* Fans */
 973         uint16_t                        fan_pwm;
 974
 975         uint16_t                        padding[3];
 976 };
 977
 978 struct gpu_metrics_v2_2 {
 979         struct metrics_table_header     common_header;
 980
 981         /* Temperature */
 982         uint16_t                        temperature_gfx; // gfx temperature on APUs
 983         uint16_t                        temperature_soc; // soc temperature on APUs
 984         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 985         uint16_t                        temperature_l3[2];
 986
 987         /* Utilization */
 988         uint16_t                        average_gfx_activity;
 989         uint16_t                        average_mm_activity; // UVD or VCN
 990
 991         /* Driver attached timestamp (in ns) */
 992         uint64_t                        system_clock_counter;
 993
 994         /* Power/Energy */
 995         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 996         uint16_t                        average_cpu_power;
 997         uint16_t                        average_soc_power;
 998         uint16_t                        average_gfx_power;
 999         uint16_t                        average_core_power[8]; // CPU core power on APUs
1000
1001         /* Average clocks */
1002         uint16_t                        average_gfxclk_frequency;
1003         uint16_t                        average_socclk_frequency;
1004         uint16_t                        average_uclk_frequency;
1005         uint16_t                        average_fclk_frequency;
1006         uint16_t                        average_vclk_frequency;
1007         uint16_t                        average_dclk_frequency;
1008
1009         /* Current clocks */
1010         uint16_t                        current_gfxclk;
1011         uint16_t                        current_socclk;
1012         uint16_t                        current_uclk;
1013         uint16_t                        current_fclk;
1014         uint16_t                        current_vclk;
1015         uint16_t                        current_dclk;
1016         uint16_t                        current_coreclk[8]; // CPU core clocks
1017         uint16_t                        current_l3clk[2];
1018
1019         /* Throttle status (ASIC dependent) */
1020         uint32_t                        throttle_status;
1021
1022         /* Fans */
1023         uint16_t                        fan_pwm;
1024
1025         uint16_t                        padding[3];
1026
1027         /* Throttle status (ASIC independent) */
1028         uint64_t                        indep_throttle_status;
1029 };
1030
1031 struct gpu_metrics_v2_3 {
1032         struct metrics_table_header     common_header;
1033
1034         /* Temperature */
1035         uint16_t                        temperature_gfx; // gfx temperature on APUs
1036         uint16_t                        temperature_soc; // soc temperature on APUs
1037         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1038         uint16_t                        temperature_l3[2];
1039
1040         /* Utilization */
1041         uint16_t                        average_gfx_activity;
1042         uint16_t                        average_mm_activity; // UVD or VCN
1043
1044         /* Driver attached timestamp (in ns) */
1045         uint64_t                        system_clock_counter;
1046
1047         /* Power/Energy */
1048         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1049         uint16_t                        average_cpu_power;
1050         uint16_t                        average_soc_power;
1051         uint16_t                        average_gfx_power;
1052         uint16_t                        average_core_power[8]; // CPU core power on APUs
1053
1054         /* Average clocks */
1055         uint16_t                        average_gfxclk_frequency;
1056         uint16_t                        average_socclk_frequency;
1057         uint16_t                        average_uclk_frequency;
1058         uint16_t                        average_fclk_frequency;
1059         uint16_t                        average_vclk_frequency;
1060         uint16_t                        average_dclk_frequency;
1061
1062         /* Current clocks */
1063         uint16_t                        current_gfxclk;
1064         uint16_t                        current_socclk;
1065         uint16_t                        current_uclk;
1066         uint16_t                        current_fclk;
1067         uint16_t                        current_vclk;
1068         uint16_t                        current_dclk;
1069         uint16_t                        current_coreclk[8]; // CPU core clocks
1070         uint16_t                        current_l3clk[2];
1071
1072         /* Throttle status (ASIC dependent) */
1073         uint32_t                        throttle_status;
1074
1075         /* Fans */
1076         uint16_t                        fan_pwm;
1077
1078         uint16_t                        padding[3];
1079
1080         /* Throttle status (ASIC independent) */
1081         uint64_t                        indep_throttle_status;
1082
1083         /* Average Temperature */
1084         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
1085         uint16_t                        average_temperature_soc; // average soc temperature on APUs
1086         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
1087         uint16_t                        average_temperature_l3[2];
1088 };
1089
1090 struct gpu_metrics_v2_4 {
1091         struct metrics_table_header     common_header;
1092
1093         /* Temperature (unit: centi-Celsius) */
1094         uint16_t                        temperature_gfx;
1095         uint16_t                        temperature_soc;
1096         uint16_t                        temperature_core[8];
1097         uint16_t                        temperature_l3[2];
1098
1099         /* Utilization (unit: centi) */
1100         uint16_t                        average_gfx_activity;
1101         uint16_t                        average_mm_activity;
1102
1103         /* Driver attached timestamp (in ns) */
1104         uint64_t                        system_clock_counter;
1105
1106         /* Power/Energy (unit: mW) */
1107         uint16_t                        average_socket_power;
1108         uint16_t                        average_cpu_power;
1109         uint16_t                        average_soc_power;
1110         uint16_t                        average_gfx_power;
1111         uint16_t                        average_core_power[8];
1112
1113         /* Average clocks (unit: MHz) */
1114         uint16_t                        average_gfxclk_frequency;
1115         uint16_t                        average_socclk_frequency;
1116         uint16_t                        average_uclk_frequency;
1117         uint16_t                        average_fclk_frequency;
1118         uint16_t                        average_vclk_frequency;
1119         uint16_t                        average_dclk_frequency;
1120
1121         /* Current clocks (unit: MHz) */
1122         uint16_t                        current_gfxclk;
1123         uint16_t                        current_socclk;
1124         uint16_t                        current_uclk;
1125         uint16_t                        current_fclk;
1126         uint16_t                        current_vclk;
1127         uint16_t                        current_dclk;
1128         uint16_t                        current_coreclk[8];
1129         uint16_t                        current_l3clk[2];
1130
1131         /* Throttle status (ASIC dependent) */
1132         uint32_t                        throttle_status;
1133
1134         /* Fans */
1135         uint16_t                        fan_pwm;
1136
1137         uint16_t                        padding[3];
1138
1139         /* Throttle status (ASIC independent) */
1140         uint64_t                        indep_throttle_status;
1141
1142         /* Average Temperature (unit: centi-Celsius) */
1143         uint16_t                        average_temperature_gfx;
1144         uint16_t                        average_temperature_soc;
1145         uint16_t                        average_temperature_core[8];
1146         uint16_t                        average_temperature_l3[2];
1147
1148         /* Power/Voltage (unit: mV) */
1149         uint16_t                        average_cpu_voltage;
1150         uint16_t                        average_soc_voltage;
1151         uint16_t                        average_gfx_voltage;
1152
1153         /* Power/Current (unit: mA) */
1154         uint16_t                        average_cpu_current;
1155         uint16_t                        average_soc_current;
1156         uint16_t                        average_gfx_current;
1157 };
1158
1159 struct gpu_metrics_v3_0 {
1160         struct metrics_table_header     common_header;
1161
1162         /* Temperature */
1163         /* gfx temperature on APUs */
1164         uint16_t                        temperature_gfx;
1165         /* soc temperature on APUs */
1166         uint16_t                        temperature_soc;
1167         /* CPU core temperature on APUs */
1168         uint16_t                        temperature_core[16];
1169         /* skin temperature on APUs */
1170         uint16_t                        temperature_skin;
1171
1172         /* Utilization */
1173         /* time filtered GFX busy % [0-100] */
1174         uint16_t                        average_gfx_activity;
1175         /* time filtered VCN busy % [0-100] */
1176         uint16_t                        average_vcn_activity;
1177         /* time filtered IPU per-column busy % [0-100] */
1178         uint16_t                        average_ipu_activity[8];
1179         /* time filtered per-core C0 residency % [0-100]*/
1180         uint16_t                        average_core_c0_activity[16];
1181         /* time filtered DRAM read bandwidth [MB/sec] */
1182         uint16_t                        average_dram_reads;
1183         /* time filtered DRAM write bandwidth [MB/sec] */
1184         uint16_t                        average_dram_writes;
1185         /* time filtered IPU read bandwidth [MB/sec] */
1186         uint16_t                        average_ipu_reads;
1187         /* time filtered IPU write bandwidth [MB/sec] */
1188         uint16_t                        average_ipu_writes;
1189
1190         /* Driver attached timestamp (in ns) */
1191         uint64_t                        system_clock_counter;
1192
1193         /* Power/Energy */
1194         /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1195         uint32_t                        average_socket_power;
1196         /* time filtered IPU power [mW] */
1197         uint16_t                        average_ipu_power;
1198         /* time filtered APU power [mW] */
1199         uint32_t                        average_apu_power;
1200         /* time filtered GFX power [mW] */
1201         uint32_t                        average_gfx_power;
1202         /* time filtered dGPU power [mW] */
1203         uint32_t                        average_dgpu_power;
1204         /* time filtered sum of core power across all cores in the socket [mW] */
1205         uint32_t                        average_all_core_power;
1206         /* calculated core power [mW] */
1207         uint16_t                        average_core_power[16];
1208         /* time filtered total system power [mW] */
1209         uint16_t                        average_sys_power;
1210         /* maximum IRM defined STAPM power limit [mW] */
1211         uint16_t                        stapm_power_limit;
1212         /* time filtered STAPM power limit [mW] */
1213         uint16_t                        current_stapm_power_limit;
1214
1215         /* time filtered clocks [MHz] */
1216         uint16_t                        average_gfxclk_frequency;
1217         uint16_t                        average_socclk_frequency;
1218         uint16_t                        average_vpeclk_frequency;
1219         uint16_t                        average_ipuclk_frequency;
1220         uint16_t                        average_fclk_frequency;
1221         uint16_t                        average_vclk_frequency;
1222         uint16_t                        average_uclk_frequency;
1223         uint16_t                        average_mpipu_frequency;
1224
1225         /* Current clocks */
1226         /* target core frequency [MHz] */
1227         uint16_t                        current_coreclk[16];
1228         /* CCLK frequency limit enforced on classic cores [MHz] */
1229         uint16_t                        current_core_maxfreq;
1230         /* GFXCLK frequency limit enforced on GFX [MHz] */
1231         uint16_t                        current_gfx_maxfreq;
1232
1233         /* Throttle Residency (ASIC dependent) */
1234         uint32_t                        throttle_residency_prochot;
1235         uint32_t                        throttle_residency_spl;
1236         uint32_t                        throttle_residency_fppt;
1237         uint32_t                        throttle_residency_sppt;
1238         uint32_t                        throttle_residency_thm_core;
1239         uint32_t                        throttle_residency_thm_gfx;
1240         uint32_t                        throttle_residency_thm_soc;
1241
1242         /* Metrics table alpha filter time constant [us] */
1243         uint32_t                        time_filter_alphavalue;
1244 };
1245
1246 struct amdgpu_pmmetrics_header {
1247         uint16_t structure_size;
1248         uint16_t pad;
1249         uint32_t mp1_ip_discovery_version;
1250         uint32_t pmfw_version;
1251         uint32_t pmmetrics_version;
1252 };
1253
1254 struct amdgpu_pm_metrics {
1255         struct amdgpu_pmmetrics_header common_header;
1256
1257         uint8_t data[];
1258 };
1259
1260 #endif