drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_cs.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "soc15_hw_ip.h"
  32 #include "vcn_v2_0.h"
  33 #include "mmsch_v4_0.h"
  34 #include "vcn_v4_0.h"
  35
  36 #include "vcn/vcn_4_0_0_offset.h"
  37 #include "vcn/vcn_4_0_0_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  39
  40 #include <drm/drm_drv.h>
  41
  42 #define mmUVD_DPG_LMA_CTL                                                       regUVD_DPG_LMA_CTL
  43 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                              regUVD_DPG_LMA_CTL_BASE_IDX
  44 #define mmUVD_DPG_LMA_DATA                                                      regUVD_DPG_LMA_DATA
  45 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                             regUVD_DPG_LMA_DATA_BASE_IDX
  46
  47 #define VCN_VID_SOC_ADDRESS_2_0                                                 0x1fb00
  48 #define VCN1_VID_SOC_ADDRESS_3_0                                                0x48300
  49
  50 #define VCN_HARVEST_MMSCH                                                               0
  51
  52 #define RDECODE_MSG_CREATE                                                      0x00000000
  53 #define RDECODE_MESSAGE_CREATE                                                  0x00000001
  54
  55 static int amdgpu_ih_clientid_vcns[] = {
  56         SOC15_IH_CLIENTID_VCN,
  57         SOC15_IH_CLIENTID_VCN1
  58 };
  59
  60 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
  61 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
  62 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  63 static int vcn_v4_0_set_powergating_state(void *handle,
  64         enum amd_powergating_state state);
  65 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
  66         int inst_idx, struct dpg_pause_state *new_state);
  67 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
  68 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  69
  70 /**
  71  * vcn_v4_0_early_init - set function pointers and load microcode
  72  *
  73  * @handle: amdgpu_device pointer
  74  *
  75  * Set ring and irq function pointers
  76  * Load microcode from filesystem
  77  */
  78 static int vcn_v4_0_early_init(void *handle)
  79 {
  80         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  81         int i;
  82
  83         if (amdgpu_sriov_vf(adev)) {
  84                 adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
  85                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  86                         if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
  87                                 adev->vcn.harvest_config |= 1 << i;
  88                                 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
  89                         }
  90                 }
  91         }
  92
  93         /* re-use enc ring as unified ring */
  94         adev->vcn.num_enc_rings = 1;
  95
  96         vcn_v4_0_set_unified_ring_funcs(adev);
  97         vcn_v4_0_set_irq_funcs(adev);
  98         vcn_v4_0_set_ras_funcs(adev);
  99
 100         return amdgpu_vcn_early_init(adev);
 101 }
 102
 103 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
 104 {
 105         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 106
 107         fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 108         fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 109         fw_shared->sq.is_enabled = 1;
 110
 111         fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
 112         fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
 113                 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
 114
 115         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
 116             IP_VERSION(4, 0, 2)) {
 117                 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;
 118                 fw_shared->drm_key_wa.method =
 119                         AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;
 120         }
 121
 122         if (amdgpu_vcnfw_log)
 123                 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
 124
 125         return 0;
 126 }
 127
 128 /**
 129  * vcn_v4_0_sw_init - sw init for VCN block
 130  *
 131  * @handle: amdgpu_device pointer
 132  *
 133  * Load firmware and sw initialization
 134  */
 135 static int vcn_v4_0_sw_init(void *handle)
 136 {
 137         struct amdgpu_ring *ring;
 138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 139         int i, r;
 140
 141         r = amdgpu_vcn_sw_init(adev);
 142         if (r)
 143                 return r;
 144
 145         amdgpu_vcn_setup_ucode(adev);
 146
 147         r = amdgpu_vcn_resume(adev);
 148         if (r)
 149                 return r;
 150
 151         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 152                 if (adev->vcn.harvest_config & (1 << i))
 153                         continue;
 154
 155                 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
 156                 if (i == 0)
 157                         atomic_set(&adev->vcn.inst[i].sched_score, 1);
 158                 else
 159                         atomic_set(&adev->vcn.inst[i].sched_score, 0);
 160
 161                 /* VCN UNIFIED TRAP */
 162                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 163                                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 164                 if (r)
 165                         return r;
 166
 167                 /* VCN POISON TRAP */
 168                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 169                                 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
 170                 if (r)
 171                         return r;
 172
 173                 ring = &adev->vcn.inst[i].ring_enc[0];
 174                 ring->use_doorbell = true;
 175                 if (amdgpu_sriov_vf(adev))
 176                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
 177                 else
 178                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
 179                 ring->vm_hub = AMDGPU_MMHUB0(0);
 180                 sprintf(ring->name, "vcn_unified_%d", i);
 181
 182                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 183                                                 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
 184                 if (r)
 185                         return r;
 186
 187                 vcn_v4_0_fw_shared_init(adev, i);
 188         }
 189
 190         if (amdgpu_sriov_vf(adev)) {
 191                 r = amdgpu_virt_alloc_mm_table(adev);
 192                 if (r)
 193                         return r;
 194         }
 195
 196         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 197                 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
 198
 199         r = amdgpu_vcn_ras_sw_init(adev);
 200         if (r)
 201                 return r;
 202
 203         return 0;
 204 }
 205
 206 /**
 207  * vcn_v4_0_sw_fini - sw fini for VCN block
 208  *
 209  * @handle: amdgpu_device pointer
 210  *
 211  * VCN suspend and free up sw allocation
 212  */
 213 static int vcn_v4_0_sw_fini(void *handle)
 214 {
 215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 216         int i, r, idx;
 217
 218         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 219                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 220                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 221
 222                         if (adev->vcn.harvest_config & (1 << i))
 223                                 continue;
 224
 225                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 226                         fw_shared->present_flag_0 = 0;
 227                         fw_shared->sq.is_enabled = 0;
 228                 }
 229
 230                 drm_dev_exit(idx);
 231         }
 232
 233         if (amdgpu_sriov_vf(adev))
 234                 amdgpu_virt_free_mm_table(adev);
 235
 236         r = amdgpu_vcn_suspend(adev);
 237         if (r)
 238                 return r;
 239
 240         r = amdgpu_vcn_sw_fini(adev);
 241
 242         return r;
 243 }
 244
 245 /**
 246  * vcn_v4_0_hw_init - start and test VCN block
 247  *
 248  * @handle: amdgpu_device pointer
 249  *
 250  * Initialize the hardware, boot up the VCPU and do some testing
 251  */
 252 static int vcn_v4_0_hw_init(void *handle)
 253 {
 254         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 255         struct amdgpu_ring *ring;
 256         int i, r;
 257
 258         if (amdgpu_sriov_vf(adev)) {
 259                 r = vcn_v4_0_start_sriov(adev);
 260                 if (r)
 261                         return r;
 262
 263                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 264                         if (adev->vcn.harvest_config & (1 << i))
 265                                 continue;
 266
 267                         ring = &adev->vcn.inst[i].ring_enc[0];
 268                         ring->wptr = 0;
 269                         ring->wptr_old = 0;
 270                         vcn_v4_0_unified_ring_set_wptr(ring);
 271                         ring->sched.ready = true;
 272                 }
 273         } else {
 274                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 275                         if (adev->vcn.harvest_config & (1 << i))
 276                                 continue;
 277
 278                         ring = &adev->vcn.inst[i].ring_enc[0];
 279
 280                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 281                                         ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
 282
 283                         r = amdgpu_ring_test_helper(ring);
 284                         if (r)
 285                                 return r;
 286                 }
 287         }
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * vcn_v4_0_hw_fini - stop the hardware block
 294  *
 295  * @handle: amdgpu_device pointer
 296  *
 297  * Stop the VCN block, mark ring as not ready any more
 298  */
 299 static int vcn_v4_0_hw_fini(void *handle)
 300 {
 301         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 302         int i;
 303
 304         cancel_delayed_work_sync(&adev->vcn.idle_work);
 305
 306         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 307                 if (adev->vcn.harvest_config & (1 << i))
 308                         continue;
 309                 if (!amdgpu_sriov_vf(adev)) {
 310                         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 311                         (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 312                                 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
 313                         vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 314                         }
 315                 }
 316                 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 317                         amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
 318         }
 319
 320         return 0;
 321 }
 322
 323 /**
 324  * vcn_v4_0_suspend - suspend VCN block
 325  *
 326  * @handle: amdgpu_device pointer
 327  *
 328  * HW fini and suspend VCN block
 329  */
 330 static int vcn_v4_0_suspend(void *handle)
 331 {
 332         int r;
 333         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 334
 335         r = vcn_v4_0_hw_fini(adev);
 336         if (r)
 337                 return r;
 338
 339         r = amdgpu_vcn_suspend(adev);
 340
 341         return r;
 342 }
 343
 344 /**
 345  * vcn_v4_0_resume - resume VCN block
 346  *
 347  * @handle: amdgpu_device pointer
 348  *
 349  * Resume firmware and hw init VCN block
 350  */
 351 static int vcn_v4_0_resume(void *handle)
 352 {
 353         int r;
 354         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 355
 356         r = amdgpu_vcn_resume(adev);
 357         if (r)
 358                 return r;
 359
 360         r = vcn_v4_0_hw_init(adev);
 361
 362         return r;
 363 }
 364
 365 /**
 366  * vcn_v4_0_mc_resume - memory controller programming
 367  *
 368  * @adev: amdgpu_device pointer
 369  * @inst: instance number
 370  *
 371  * Let the VCN memory controller know it's offsets
 372  */
 373 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
 374 {
 375         uint32_t offset, size;
 376         const struct common_firmware_header *hdr;
 377
 378         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
 379         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 380
 381         /* cache window 0: fw */
 382         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 383                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 384                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 385                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 386                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 387                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 388                 offset = 0;
 389         } else {
 390                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 391                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 392                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 393                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 394                 offset = size;
 395                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 396         }
 397         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
 398
 399         /* cache window 1: stack */
 400         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 401                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 402         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 403                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 404         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 405         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 406
 407         /* cache window 2: context */
 408         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 409                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 410         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 411                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 412         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 413         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 414
 415         /* non-cache window */
 416         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 417                 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 418         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 419                 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 420         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 421         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
 422                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 423 }
 424
 425 /**
 426  * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
 427  *
 428  * @adev: amdgpu_device pointer
 429  * @inst_idx: instance number index
 430  * @indirect: indirectly write sram
 431  *
 432  * Let the VCN memory controller know it's offsets with dpg mode
 433  */
 434 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 435 {
 436         uint32_t offset, size;
 437         const struct common_firmware_header *hdr;
 438         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 439         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 440
 441         /* cache window 0: fw */
 442         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 443                 if (!indirect) {
 444                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 445                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 446                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 447                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 448                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 449                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 450                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 451                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 452                 } else {
 453                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 454                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 455                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 456                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 457                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 458                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 459                 }
 460                 offset = 0;
 461         } else {
 462                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 463                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 464                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 465                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 466                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 467                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 468                 offset = size;
 469                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 470                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 471                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 472         }
 473
 474         if (!indirect)
 475                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 476                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 477         else
 478                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 479                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 480
 481         /* cache window 1: stack */
 482         if (!indirect) {
 483                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 484                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 485                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 486                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 487                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 488                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 489                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 490                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 491         } else {
 492                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 493                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 494                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 495                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 496                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 497                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 498         }
 499         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 500                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 501
 502         /* cache window 2: context */
 503         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 504                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 505                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 506         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 507                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 508                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 509         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 510                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 511         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 512                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 513
 514         /* non-cache window */
 515         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 516                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 517                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 518         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 519                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 520                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 521         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 522                         VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 523         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 524                         VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
 525                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 526
 527         /* VCN global tiling registers */
 528         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 529                 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 530 }
 531
 532 /**
 533  * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
 534  *
 535  * @adev: amdgpu_device pointer
 536  * @inst: instance number
 537  *
 538  * Disable static power gating for VCN block
 539  */
 540 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 541 {
 542         uint32_t data = 0;
 543
 544         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 545                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 546                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 547                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 548                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 549                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 550                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 551                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 552                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 553                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 554                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 555                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 556                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 557                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 558                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 559
 560                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 561                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
 562                         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
 563         } else {
 564                 uint32_t value;
 565
 566                 value = (inst) ? 0x2200800 : 0;
 567                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 568                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 569                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 570                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 571                         | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 572                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 573                         | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 574                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 575                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 576                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 577                         | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 578                         | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 579                         | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 580                         | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 581
 582                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 583                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value,  0x3F3FFFFF);
 584         }
 585
 586         data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 587         data &= ~0x103;
 588         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 589                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 590                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 591
 592         WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 593
 594         return;
 595 }
 596
 597 /**
 598  * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
 599  *
 600  * @adev: amdgpu_device pointer
 601  * @inst: instance number
 602  *
 603  * Enable static power gating for VCN block
 604  */
 605 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 606 {
 607         uint32_t data;
 608
 609         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 610                 /* Before power off, this indicator has to be turned on */
 611                 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 612                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 613                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 614                 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 615
 616                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 617                         | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 618                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 619                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 620                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 621                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 622                         | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 623                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 624                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 625                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 626                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 627                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 628                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 629                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 630                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 631
 632                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 633                         | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
 634                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 635                         | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
 636                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 637                         | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
 638                         | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
 639                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 640                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 641                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 642                         | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
 643                         | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
 644                         | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
 645                         | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
 646                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
 647         }
 648
 649         return;
 650 }
 651
 652 /**
 653  * vcn_v4_0_disable_clock_gating - disable VCN clock gating
 654  *
 655  * @adev: amdgpu_device pointer
 656  * @inst: instance number
 657  *
 658  * Disable clock gating for VCN block
 659  */
 660 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
 661 {
 662         uint32_t data;
 663
 664         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 665                 return;
 666
 667         /* VCN disable CGC */
 668         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 669         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 670         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 671         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 672         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 673
 674         data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
 675         data &= ~(UVD_CGC_GATE__SYS_MASK
 676                 | UVD_CGC_GATE__UDEC_MASK
 677                 | UVD_CGC_GATE__MPEG2_MASK
 678                 | UVD_CGC_GATE__REGS_MASK
 679                 | UVD_CGC_GATE__RBC_MASK
 680                 | UVD_CGC_GATE__LMI_MC_MASK
 681                 | UVD_CGC_GATE__LMI_UMC_MASK
 682                 | UVD_CGC_GATE__IDCT_MASK
 683                 | UVD_CGC_GATE__MPRD_MASK
 684                 | UVD_CGC_GATE__MPC_MASK
 685                 | UVD_CGC_GATE__LBSI_MASK
 686                 | UVD_CGC_GATE__LRBBM_MASK
 687                 | UVD_CGC_GATE__UDEC_RE_MASK
 688                 | UVD_CGC_GATE__UDEC_CM_MASK
 689                 | UVD_CGC_GATE__UDEC_IT_MASK
 690                 | UVD_CGC_GATE__UDEC_DB_MASK
 691                 | UVD_CGC_GATE__UDEC_MP_MASK
 692                 | UVD_CGC_GATE__WCB_MASK
 693                 | UVD_CGC_GATE__VCPU_MASK
 694                 | UVD_CGC_GATE__MMSCH_MASK);
 695
 696         WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
 697         SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);
 698
 699         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 700         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 701                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 702                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 703                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 704                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 705                 | UVD_CGC_CTRL__SYS_MODE_MASK
 706                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 707                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 708                 | UVD_CGC_CTRL__REGS_MODE_MASK
 709                 | UVD_CGC_CTRL__RBC_MODE_MASK
 710                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 711                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 712                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 713                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 714                 | UVD_CGC_CTRL__MPC_MODE_MASK
 715                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 716                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 717                 | UVD_CGC_CTRL__WCB_MODE_MASK
 718                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 719                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 720         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 721
 722         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
 723         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 724                 | UVD_SUVD_CGC_GATE__SIT_MASK
 725                 | UVD_SUVD_CGC_GATE__SMP_MASK
 726                 | UVD_SUVD_CGC_GATE__SCM_MASK
 727                 | UVD_SUVD_CGC_GATE__SDB_MASK
 728                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 729                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 730                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 731                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 732                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 733                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 734                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 735                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 736                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 737                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 738                 | UVD_SUVD_CGC_GATE__ENT_MASK
 739                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 740                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 741                 | UVD_SUVD_CGC_GATE__SITE_MASK
 742                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 743                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 744                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 745                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 746                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 747         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
 748
 749         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 750         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 751                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 752                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 753                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 754                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 755                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 756                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 757                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 758                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 759                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 760         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 761 }
 762
 763 /**
 764  * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 765  *
 766  * @adev: amdgpu_device pointer
 767  * @sram_sel: sram select
 768  * @inst_idx: instance number index
 769  * @indirect: indirectly write sram
 770  *
 771  * Disable clock gating for VCN block with dpg mode
 772  */
 773 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 774       int inst_idx, uint8_t indirect)
 775 {
 776         uint32_t reg_data = 0;
 777
 778         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 779                 return;
 780
 781         /* enable sw clock gating control */
 782         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 783         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 784         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 785         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 786                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 787                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 788                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 789                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 790                  UVD_CGC_CTRL__SYS_MODE_MASK |
 791                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 792                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 793                  UVD_CGC_CTRL__REGS_MODE_MASK |
 794                  UVD_CGC_CTRL__RBC_MODE_MASK |
 795                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 796                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 797                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 798                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 799                  UVD_CGC_CTRL__MPC_MODE_MASK |
 800                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 801                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 802                  UVD_CGC_CTRL__WCB_MODE_MASK |
 803                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 804         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 805                 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 806
 807         /* turn off clock gating */
 808         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 809                 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
 810
 811         /* turn on SUVD clock gating */
 812         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 813                 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 814
 815         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 816         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 817                 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 818 }
 819
 820 /**
 821  * vcn_v4_0_enable_clock_gating - enable VCN clock gating
 822  *
 823  * @adev: amdgpu_device pointer
 824  * @inst: instance number
 825  *
 826  * Enable clock gating for VCN block
 827  */
 828 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
 829 {
 830         uint32_t data;
 831
 832         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 833                 return;
 834
 835         /* enable VCN CGC */
 836         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 837         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 838         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 839         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 840         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 841
 842         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 843         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 844                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 845                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 846                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 847                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 848                 | UVD_CGC_CTRL__SYS_MODE_MASK
 849                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 850                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 851                 | UVD_CGC_CTRL__REGS_MODE_MASK
 852                 | UVD_CGC_CTRL__RBC_MODE_MASK
 853                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 854                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 855                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 856                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 857                 | UVD_CGC_CTRL__MPC_MODE_MASK
 858                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 859                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 860                 | UVD_CGC_CTRL__WCB_MODE_MASK
 861                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 862                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 863         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 864
 865         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 866         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 867                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 868                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 869                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 870                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 871                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 872                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 873                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 874                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 875                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 876         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 877 }
 878
 879 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
 880                                 bool indirect)
 881 {
 882         uint32_t tmp;
 883
 884         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 885                 return;
 886
 887         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
 888               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
 889               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
 890               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
 891         WREG32_SOC15_DPG_MODE(inst_idx,
 892                               SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
 893                               tmp, 0, indirect);
 894
 895         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 896         WREG32_SOC15_DPG_MODE(inst_idx,
 897                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
 898                               tmp, 0, indirect);
 899 }
 900
 901 /**
 902  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
 903  *
 904  * @adev: amdgpu_device pointer
 905  * @inst_idx: instance number index
 906  * @indirect: indirectly write sram
 907  *
 908  * Start VCN block with dpg mode
 909  */
 910 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 911 {
 912         volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 913         struct amdgpu_ring *ring;
 914         uint32_t tmp;
 915
 916         /* disable register anti-hang mechanism */
 917         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
 918                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 919         /* enable dynamic power gating mode */
 920         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
 921         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 922         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 923         WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
 924
 925         if (indirect)
 926                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 927
 928         /* enable clock gating */
 929         vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 930
 931         /* enable VCPU clock */
 932         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 933         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
 934         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 935                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 936
 937         /* disable master interupt */
 938         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 939                 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
 940
 941         /* setup regUVD_LMI_CTRL */
 942         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 943                 UVD_LMI_CTRL__REQ_MODE_MASK |
 944                 UVD_LMI_CTRL__CRC_RESET_MASK |
 945                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 946                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 947                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 948                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 949                 0x00100000L);
 950         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 951                 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
 952
 953         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 954                 VCN, inst_idx, regUVD_MPC_CNTL),
 955                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 956
 957         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 958                 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
 959                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 960                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 961                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 962                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 963
 964         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 965                 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
 966                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 967                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 968                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 969                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 970
 971         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 972                 VCN, inst_idx, regUVD_MPC_SET_MUX),
 973                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 974                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 975                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 976
 977         vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
 978
 979         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 980         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 981         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 982                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 983
 984         /* enable LMI MC and UMC channels */
 985         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
 986         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 987                 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
 988
 989         vcn_v4_0_enable_ras(adev, inst_idx, indirect);
 990
 991         /* enable master interrupt */
 992         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 993                 VCN, inst_idx, regUVD_MASTINT_EN),
 994                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 995
 996
 997         if (indirect)
 998                 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
 999
1000         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1001
1002         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
1003         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1004         WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
1005
1006         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1007         tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1008         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1009         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1010         WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1011         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1012
1013         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
1014         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
1015         ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1016
1017         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1018         tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1019         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1020         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1021
1022         WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
1023                         ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1024                         VCN_RB1_DB_CTRL__EN_MASK);
1025
1026         return 0;
1027 }
1028
1029
1030 /**
1031  * vcn_v4_0_start - VCN start
1032  *
1033  * @adev: amdgpu_device pointer
1034  *
1035  * Start VCN block
1036  */
1037 static int vcn_v4_0_start(struct amdgpu_device *adev)
1038 {
1039         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1040         struct amdgpu_ring *ring;
1041         uint32_t tmp;
1042         int i, j, k, r;
1043
1044         if (adev->pm.dpm_enabled)
1045                 amdgpu_dpm_enable_uvd(adev, true);
1046
1047         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1048                 if (adev->vcn.harvest_config & (1 << i))
1049                         continue;
1050
1051                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1052
1053                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1054                         r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1055                         continue;
1056                 }
1057
1058                 /* disable VCN power gating */
1059                 vcn_v4_0_disable_static_power_gating(adev, i);
1060
1061                 /* set VCN status busy */
1062                 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1063                 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
1064
1065                 /*SW clock gating */
1066                 vcn_v4_0_disable_clock_gating(adev, i);
1067
1068                 /* enable VCPU clock */
1069                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1070                                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1071
1072                 /* disable master interrupt */
1073                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
1074                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1075
1076                 /* enable LMI MC and UMC channels */
1077                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
1078                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1079
1080                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1081                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1082                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1083                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1084
1085                 /* setup regUVD_LMI_CTRL */
1086                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1087                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1088                                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1089                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1090                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1091                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1092
1093                 /* setup regUVD_MPC_CNTL */
1094                 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1095                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1096                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1097                 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1098
1099                 /* setup UVD_MPC_SET_MUXA0 */
1100                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1101                                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1102                                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1103                                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1104                                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1105
1106                 /* setup UVD_MPC_SET_MUXB0 */
1107                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1108                                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1109                                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1110                                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1111                                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1112
1113                 /* setup UVD_MPC_SET_MUX */
1114                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1115                                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1116                                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1117                                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1118
1119                 vcn_v4_0_mc_resume(adev, i);
1120
1121                 /* VCN global tiling registers */
1122                 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1123                                 adev->gfx.config.gb_addr_config);
1124
1125                 /* unblock VCPU register access */
1126                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1127                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1128
1129                 /* release VCPU reset to boot */
1130                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1131                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1132
1133                 for (j = 0; j < 10; ++j) {
1134                         uint32_t status;
1135
1136                         for (k = 0; k < 100; ++k) {
1137                                 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1138                                 if (status & 2)
1139                                         break;
1140                                 mdelay(10);
1141                                 if (amdgpu_emu_mode == 1)
1142                                         msleep(1);
1143                         }
1144
1145                         if (amdgpu_emu_mode == 1) {
1146                                 r = -1;
1147                                 if (status & 2) {
1148                                         r = 0;
1149                                         break;
1150                                 }
1151                         } else {
1152                                 r = 0;
1153                                 if (status & 2)
1154                                         break;
1155
1156                                 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
1157                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1158                                                         UVD_VCPU_CNTL__BLK_RST_MASK,
1159                                                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1160                                 mdelay(10);
1161                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1162                                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1163
1164                                 mdelay(10);
1165                                 r = -1;
1166                         }
1167                 }
1168
1169                 if (r) {
1170                         dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1171                         return r;
1172                 }
1173
1174                 /* enable master interrupt */
1175                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1176                                 UVD_MASTINT_EN__VCPU_EN_MASK,
1177                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1178
1179                 /* clear the busy bit of VCN_STATUS */
1180                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1181                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1182
1183                 ring = &adev->vcn.inst[i].ring_enc[0];
1184                 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1185                                 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1186                                 VCN_RB1_DB_CTRL__EN_MASK);
1187
1188                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1189                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1190                 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1191
1192                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1193                 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1194                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1195                 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1196                 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1197                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1198
1199                 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1200                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1201                 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1202
1203                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1204                 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1205                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1206                 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1207         }
1208
1209         return 0;
1210 }
1211
1212 static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc)
1213 {
1214         struct amdgpu_vcn_rb_metadata *rb_metadata = NULL;
1215         uint8_t *rb_ptr = (uint8_t *)ring_enc->ring;
1216
1217         rb_ptr += ring_enc->ring_size;
1218         rb_metadata = (struct amdgpu_vcn_rb_metadata *)rb_ptr;
1219
1220         memset(rb_metadata, 0, sizeof(struct amdgpu_vcn_rb_metadata));
1221         rb_metadata->size = sizeof(struct amdgpu_vcn_rb_metadata);
1222         rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1223         rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG);
1224         rb_metadata->version = 1;
1225         rb_metadata->ring_id = vcn_inst & 0xFF;
1226
1227         return 0;
1228 }
1229
1230 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
1231 {
1232         int i;
1233         struct amdgpu_ring *ring_enc;
1234         uint64_t cache_addr;
1235         uint64_t rb_enc_addr;
1236         uint64_t ctx_addr;
1237         uint32_t param, resp, expected;
1238         uint32_t offset, cache_size;
1239         uint32_t tmp, timeout;
1240
1241         struct amdgpu_mm_table *table = &adev->virt.mm_table;
1242         uint32_t *table_loc;
1243         uint32_t table_size;
1244         uint32_t size, size_dw;
1245         uint32_t init_status;
1246         uint32_t enabled_vcn;
1247
1248         struct mmsch_v4_0_cmd_direct_write
1249                 direct_wt = { {0} };
1250         struct mmsch_v4_0_cmd_direct_read_modify_write
1251                 direct_rd_mod_wt = { {0} };
1252         struct mmsch_v4_0_cmd_end end = { {0} };
1253         struct mmsch_v4_0_init_header header;
1254
1255         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1256         volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1257
1258         direct_wt.cmd_header.command_type =
1259                 MMSCH_COMMAND__DIRECT_REG_WRITE;
1260         direct_rd_mod_wt.cmd_header.command_type =
1261                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1262         end.cmd_header.command_type =
1263                 MMSCH_COMMAND__END;
1264
1265         header.version = MMSCH_VERSION;
1266         header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
1267         for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
1268                 header.inst[i].init_status = 0;
1269                 header.inst[i].table_offset = 0;
1270                 header.inst[i].table_size = 0;
1271         }
1272
1273         table_loc = (uint32_t *)table->cpu_addr;
1274         table_loc += header.total_size;
1275         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1276                 if (adev->vcn.harvest_config & (1 << i))
1277                         continue;
1278
1279                 // Must re/init fw_shared at beginning
1280                 vcn_v4_0_fw_shared_init(adev, i);
1281
1282                 table_size = 0;
1283
1284                 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1285                         regUVD_STATUS),
1286                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1287
1288                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
1289
1290                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1291                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1292                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1293                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1294                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1295                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1296                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1297                         offset = 0;
1298                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1299                                 regUVD_VCPU_CACHE_OFFSET0),
1300                                 0);
1301                 } else {
1302                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1303                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1304                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1305                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1306                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1307                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1308                         offset = cache_size;
1309                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1310                                 regUVD_VCPU_CACHE_OFFSET0),
1311                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1312                 }
1313
1314                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1315                         regUVD_VCPU_CACHE_SIZE0),
1316                         cache_size);
1317
1318                 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1319                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1320                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1321                         lower_32_bits(cache_addr));
1322                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1323                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1324                         upper_32_bits(cache_addr));
1325                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1326                         regUVD_VCPU_CACHE_OFFSET1),
1327                         0);
1328                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1329                         regUVD_VCPU_CACHE_SIZE1),
1330                         AMDGPU_VCN_STACK_SIZE);
1331
1332                 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1333                         AMDGPU_VCN_STACK_SIZE;
1334                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1335                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1336                         lower_32_bits(cache_addr));
1337                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1338                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1339                         upper_32_bits(cache_addr));
1340                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1341                         regUVD_VCPU_CACHE_OFFSET2),
1342                         0);
1343                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1344                         regUVD_VCPU_CACHE_SIZE2),
1345                         AMDGPU_VCN_CONTEXT_SIZE);
1346
1347                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1348                 rb_setup = &fw_shared->rb_setup;
1349
1350                 ring_enc = &adev->vcn.inst[i].ring_enc[0];
1351                 ring_enc->wptr = 0;
1352                 rb_enc_addr = ring_enc->gpu_addr;
1353
1354                 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1355                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1356
1357                 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) {
1358                         vcn_v4_0_init_ring_metadata(adev, i, ring_enc);
1359
1360                         memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SETUP);
1361                         if (!(adev->vcn.harvest_config & (1 << 0))) {
1362                                 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
1363                                 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
1364                                 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4;
1365                         }
1366                         if (!(adev->vcn.harvest_config & (1 << 1))) {
1367                                 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
1368                                 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
1369                                 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4;
1370                         }
1371                         fw_shared->decouple.is_enabled = 1;
1372                         fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG);
1373                 } else {
1374                         rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1375                         rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1376                         rb_setup->rb_size = ring_enc->ring_size / 4;
1377                 }
1378
1379                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1380                         regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1381                         lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1382                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1383                         regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1384                         upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1385                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1386                         regUVD_VCPU_NONCACHE_SIZE0),
1387                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1388
1389                 /* add end packet */
1390                 MMSCH_V4_0_INSERT_END();
1391
1392                 /* refine header */
1393                 header.inst[i].init_status = 0;
1394                 header.inst[i].table_offset = header.total_size;
1395                 header.inst[i].table_size = table_size;
1396                 header.total_size += table_size;
1397         }
1398
1399         /* Update init table header in memory */
1400         size = sizeof(struct mmsch_v4_0_init_header);
1401         table_loc = (uint32_t *)table->cpu_addr;
1402         memcpy((void *)table_loc, &header, size);
1403
1404         /* message MMSCH (in VCN[0]) to initialize this client
1405          * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1406          * of memory descriptor location
1407          */
1408         ctx_addr = table->gpu_addr;
1409         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1410         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1411
1412         /* 2, update vmid of descriptor */
1413         tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
1414         tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1415         /* use domain0 for MM scheduler */
1416         tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1417         WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
1418
1419         /* 3, notify mmsch about the size of this descriptor */
1420         size = header.total_size;
1421         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
1422
1423         /* 4, set resp to zero */
1424         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
1425
1426         /* 5, kick off the initialization and wait until
1427          * MMSCH_VF_MAILBOX_RESP becomes non-zero
1428          */
1429         param = 0x00000001;
1430         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
1431         tmp = 0;
1432         timeout = 1000;
1433         resp = 0;
1434         expected = MMSCH_VF_MAILBOX_RESP__OK;
1435         while (resp != expected) {
1436                 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
1437                 if (resp != 0)
1438                         break;
1439
1440                 udelay(10);
1441                 tmp = tmp + 10;
1442                 if (tmp >= timeout) {
1443                         DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1444                                 " waiting for regMMSCH_VF_MAILBOX_RESP "\
1445                                 "(expected=0x%08x, readback=0x%08x)\n",
1446                                 tmp, expected, resp);
1447                         return -EBUSY;
1448                 }
1449         }
1450         enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1451         init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
1452         if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1453         && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
1454                 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1455                         "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1456
1457         return 0;
1458 }
1459
1460 /**
1461  * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1462  *
1463  * @adev: amdgpu_device pointer
1464  * @inst_idx: instance number index
1465  *
1466  * Stop VCN block with dpg mode
1467  */
1468 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1469 {
1470         struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1471         uint32_t tmp;
1472
1473         vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state);
1474         /* Wait for power status to be 1 */
1475         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1476                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1477
1478         /* wait for read ptr to be equal to write ptr */
1479         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1480         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1481
1482         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1483                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1484
1485         /* disable dynamic power gating mode */
1486         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1487                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1488 }
1489
1490 /**
1491  * vcn_v4_0_stop - VCN stop
1492  *
1493  * @adev: amdgpu_device pointer
1494  *
1495  * Stop VCN block
1496  */
1497 static int vcn_v4_0_stop(struct amdgpu_device *adev)
1498 {
1499         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1500         uint32_t tmp;
1501         int i, r = 0;
1502
1503         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1504                 if (adev->vcn.harvest_config & (1 << i))
1505                         continue;
1506
1507                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1508                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1509
1510                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1511                         vcn_v4_0_stop_dpg_mode(adev, i);
1512                         continue;
1513                 }
1514
1515                 /* wait for vcn idle */
1516                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1517                 if (r)
1518                         return r;
1519
1520                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1521                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1522                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1523                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1524                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1525                 if (r)
1526                         return r;
1527
1528                 /* disable LMI UMC channel */
1529                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1530                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1531                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1532                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1533                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1534                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1535                 if (r)
1536                         return r;
1537
1538                 /* block VCPU register access */
1539                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1540                                 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1541                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1542
1543                 /* reset VCPU */
1544                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1545                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1546                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1547
1548                 /* disable VCPU clock */
1549                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1550                                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1551
1552                 /* apply soft reset */
1553                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1554                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1555                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1556                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1557                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1558                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1559
1560                 /* clear status */
1561                 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1562
1563                 /* apply HW clock gating */
1564                 vcn_v4_0_enable_clock_gating(adev, i);
1565
1566                 /* enable VCN power gating */
1567                 vcn_v4_0_enable_static_power_gating(adev, i);
1568         }
1569
1570         if (adev->pm.dpm_enabled)
1571                 amdgpu_dpm_enable_uvd(adev, false);
1572
1573         return 0;
1574 }
1575
1576 /**
1577  * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
1578  *
1579  * @adev: amdgpu_device pointer
1580  * @inst_idx: instance number index
1581  * @new_state: pause state
1582  *
1583  * Pause dpg mode for VCN block
1584  */
1585 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1586       struct dpg_pause_state *new_state)
1587 {
1588         uint32_t reg_data = 0;
1589         int ret_code;
1590
1591         /* pause/unpause if state is changed */
1592         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1593                 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1594                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1595                 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1596                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1597
1598                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1599                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1600                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1601
1602                         if (!ret_code) {
1603                                 /* pause DPG */
1604                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1605                                 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1606
1607                                 /* wait for ACK */
1608                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1609                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1610                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1611
1612                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1613                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1614                         }
1615                 } else {
1616                         /* unpause dpg, no need to wait */
1617                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1618                         WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1619                 }
1620                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1621         }
1622
1623         return 0;
1624 }
1625
1626 /**
1627  * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
1628  *
1629  * @ring: amdgpu_ring pointer
1630  *
1631  * Returns the current hardware unified read pointer
1632  */
1633 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
1634 {
1635         struct amdgpu_device *adev = ring->adev;
1636
1637         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1638                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1639
1640         return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1641 }
1642
1643 /**
1644  * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
1645  *
1646  * @ring: amdgpu_ring pointer
1647  *
1648  * Returns the current hardware unified write pointer
1649  */
1650 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
1651 {
1652         struct amdgpu_device *adev = ring->adev;
1653
1654         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1655                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1656
1657         if (ring->use_doorbell)
1658                 return *ring->wptr_cpu_addr;
1659         else
1660                 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1661 }
1662
1663 /**
1664  * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
1665  *
1666  * @ring: amdgpu_ring pointer
1667  *
1668  * Commits the enc write pointer to the hardware
1669  */
1670 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
1671 {
1672         struct amdgpu_device *adev = ring->adev;
1673
1674         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1675                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1676
1677         if (ring->use_doorbell) {
1678                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1679                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1680         } else {
1681                 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1682         }
1683 }
1684
1685 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
1686                                 struct amdgpu_job *job)
1687 {
1688         struct drm_gpu_scheduler **scheds;
1689
1690         /* The create msg must be in the first IB submitted */
1691         if (atomic_read(&job->base.entity->fence_seq))
1692                 return -EINVAL;
1693
1694         /* if VCN0 is harvested, we can't support AV1 */
1695         if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1696                 return -EINVAL;
1697
1698         scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1699                 [AMDGPU_RING_PRIO_0].sched;
1700         drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1701         return 0;
1702 }
1703
1704 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1705                             uint64_t addr)
1706 {
1707         struct ttm_operation_ctx ctx = { false, false };
1708         struct amdgpu_bo_va_mapping *map;
1709         uint32_t *msg, num_buffers;
1710         struct amdgpu_bo *bo;
1711         uint64_t start, end;
1712         unsigned int i;
1713         void *ptr;
1714         int r;
1715
1716         addr &= AMDGPU_GMC_HOLE_MASK;
1717         r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1718         if (r) {
1719                 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
1720                 return r;
1721         }
1722
1723         start = map->start * AMDGPU_GPU_PAGE_SIZE;
1724         end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1725         if (addr & 0x7) {
1726                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1727                 return -EINVAL;
1728         }
1729
1730         bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1731         amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1732         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1733         if (r) {
1734                 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1735                 return r;
1736         }
1737
1738         r = amdgpu_bo_kmap(bo, &ptr);
1739         if (r) {
1740                 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1741                 return r;
1742         }
1743
1744         msg = ptr + addr - start;
1745
1746         /* Check length */
1747         if (msg[1] > end - addr) {
1748                 r = -EINVAL;
1749                 goto out;
1750         }
1751
1752         if (msg[3] != RDECODE_MSG_CREATE)
1753                 goto out;
1754
1755         num_buffers = msg[2];
1756         for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1757                 uint32_t offset, size, *create;
1758
1759                 if (msg[0] != RDECODE_MESSAGE_CREATE)
1760                         continue;
1761
1762                 offset = msg[1];
1763                 size = msg[2];
1764
1765                 if (offset + size > end) {
1766                         r = -EINVAL;
1767                         goto out;
1768                 }
1769
1770                 create = ptr + addr + offset - start;
1771
1772                 /* H264, HEVC and VP9 can run on any instance */
1773                 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1774                         continue;
1775
1776                 r = vcn_v4_0_limit_sched(p, job);
1777                 if (r)
1778                         goto out;
1779         }
1780
1781 out:
1782         amdgpu_bo_kunmap(bo);
1783         return r;
1784 }
1785
1786 #define RADEON_VCN_ENGINE_TYPE_ENCODE                   (0x00000002)
1787 #define RADEON_VCN_ENGINE_TYPE_DECODE                   (0x00000003)
1788
1789 #define RADEON_VCN_ENGINE_INFO                          (0x30000001)
1790 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET               16
1791
1792 #define RENCODE_ENCODE_STANDARD_AV1                     2
1793 #define RENCODE_IB_PARAM_SESSION_INIT                   0x00000003
1794 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET        64
1795
1796 /* return the offset in ib if id is found, -1 otherwise
1797  * to speed up the searching we only search upto max_offset
1798  */
1799 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1800 {
1801         int i;
1802
1803         for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1804                 if (ib->ptr[i + 1] == id)
1805                         return i;
1806         }
1807         return -1;
1808 }
1809
1810 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1811                                            struct amdgpu_job *job,
1812                                            struct amdgpu_ib *ib)
1813 {
1814         struct amdgpu_ring *ring = amdgpu_job_ring(job);
1815         struct amdgpu_vcn_decode_buffer *decode_buffer;
1816         uint64_t addr;
1817         uint32_t val;
1818         int idx;
1819
1820         /* The first instance can decode anything */
1821         if (!ring->me)
1822                 return 0;
1823
1824         /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1825         idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1826                         RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1827         if (idx < 0) /* engine info is missing */
1828                 return 0;
1829
1830         val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1831         if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1832                 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
1833
1834                 if (!(decode_buffer->valid_buf_flag  & 0x1))
1835                         return 0;
1836
1837                 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1838                         decode_buffer->msg_buffer_address_lo;
1839                 return vcn_v4_0_dec_msg(p, job, addr);
1840         } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1841                 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1842                         RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1843                 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1844                         return vcn_v4_0_limit_sched(p, job);
1845         }
1846         return 0;
1847 }
1848
1849 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
1850         .type = AMDGPU_RING_TYPE_VCN_ENC,
1851         .align_mask = 0x3f,
1852         .nop = VCN_ENC_CMD_NO_OP,
1853         .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata),
1854         .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1855         .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1856         .set_wptr = vcn_v4_0_unified_ring_set_wptr,
1857         .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
1858         .emit_frame_size =
1859                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1860                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1861                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1862                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1863                 1, /* vcn_v2_0_enc_ring_insert_end */
1864         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1865         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1866         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1867         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1868         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1869         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1870         .insert_nop = amdgpu_ring_insert_nop,
1871         .insert_end = vcn_v2_0_enc_ring_insert_end,
1872         .pad_ib = amdgpu_ring_generic_pad_ib,
1873         .begin_use = amdgpu_vcn_ring_begin_use,
1874         .end_use = amdgpu_vcn_ring_end_use,
1875         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1876         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1877         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1878 };
1879
1880 /**
1881  * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
1882  *
1883  * @adev: amdgpu_device pointer
1884  *
1885  * Set unified ring functions
1886  */
1887 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
1888 {
1889         int i;
1890
1891         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1892                 if (adev->vcn.harvest_config & (1 << i))
1893                         continue;
1894
1895                 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))
1896                         vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
1897
1898                 adev->vcn.inst[i].ring_enc[0].funcs =
1899                        (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
1900                 adev->vcn.inst[i].ring_enc[0].me = i;
1901         }
1902 }
1903
1904 /**
1905  * vcn_v4_0_is_idle - check VCN block is idle
1906  *
1907  * @handle: amdgpu_device pointer
1908  *
1909  * Check whether VCN block is idle
1910  */
1911 static bool vcn_v4_0_is_idle(void *handle)
1912 {
1913         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1914         int i, ret = 1;
1915
1916         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1917                 if (adev->vcn.harvest_config & (1 << i))
1918                         continue;
1919
1920                 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1921         }
1922
1923         return ret;
1924 }
1925
1926 /**
1927  * vcn_v4_0_wait_for_idle - wait for VCN block idle
1928  *
1929  * @handle: amdgpu_device pointer
1930  *
1931  * Wait for VCN block idle
1932  */
1933 static int vcn_v4_0_wait_for_idle(void *handle)
1934 {
1935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1936         int i, ret = 0;
1937
1938         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1939                 if (adev->vcn.harvest_config & (1 << i))
1940                         continue;
1941
1942                 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1943                         UVD_STATUS__IDLE);
1944                 if (ret)
1945                         return ret;
1946         }
1947
1948         return ret;
1949 }
1950
1951 /**
1952  * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
1953  *
1954  * @handle: amdgpu_device pointer
1955  * @state: clock gating state
1956  *
1957  * Set VCN block clockgating state
1958  */
1959 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
1960 {
1961         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1962         bool enable = state == AMD_CG_STATE_GATE;
1963         int i;
1964
1965         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1966                 if (adev->vcn.harvest_config & (1 << i))
1967                         continue;
1968
1969                 if (enable) {
1970                         if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
1971                                 return -EBUSY;
1972                         vcn_v4_0_enable_clock_gating(adev, i);
1973                 } else {
1974                         vcn_v4_0_disable_clock_gating(adev, i);
1975                 }
1976         }
1977
1978         return 0;
1979 }
1980
1981 /**
1982  * vcn_v4_0_set_powergating_state - set VCN block powergating state
1983  *
1984  * @handle: amdgpu_device pointer
1985  * @state: power gating state
1986  *
1987  * Set VCN block powergating state
1988  */
1989 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
1990 {
1991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1992         int ret;
1993
1994         /* for SRIOV, guest should not control VCN Power-gating
1995          * MMSCH FW should control Power-gating and clock-gating
1996          * guest should avoid touching CGC and PG
1997          */
1998         if (amdgpu_sriov_vf(adev)) {
1999                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2000                 return 0;
2001         }
2002
2003         if (state == adev->vcn.cur_state)
2004                 return 0;
2005
2006         if (state == AMD_PG_STATE_GATE)
2007                 ret = vcn_v4_0_stop(adev);
2008         else
2009                 ret = vcn_v4_0_start(adev);
2010
2011         if (!ret)
2012                 adev->vcn.cur_state = state;
2013
2014         return ret;
2015 }
2016
2017 /**
2018  * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state
2019  *
2020  * @adev: amdgpu_device pointer
2021  * @source: interrupt sources
2022  * @type: interrupt types
2023  * @state: interrupt states
2024  *
2025  * Set VCN block RAS interrupt state
2026  */
2027 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
2028         struct amdgpu_irq_src *source,
2029         unsigned int type,
2030         enum amdgpu_interrupt_state state)
2031 {
2032         return 0;
2033 }
2034
2035 /**
2036  * vcn_v4_0_process_interrupt - process VCN block interrupt
2037  *
2038  * @adev: amdgpu_device pointer
2039  * @source: interrupt sources
2040  * @entry: interrupt entry from clients and sources
2041  *
2042  * Process VCN block interrupt
2043  */
2044 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
2045       struct amdgpu_iv_entry *entry)
2046 {
2047         uint32_t ip_instance;
2048
2049         if (amdgpu_sriov_is_vcn_rb_decouple(adev)) {
2050                 ip_instance = entry->ring_id;
2051         } else {
2052                 switch (entry->client_id) {
2053                 case SOC15_IH_CLIENTID_VCN:
2054                         ip_instance = 0;
2055                         break;
2056                 case SOC15_IH_CLIENTID_VCN1:
2057                         ip_instance = 1;
2058                         break;
2059                 default:
2060                         DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2061                         return 0;
2062                 }
2063         }
2064
2065         DRM_DEBUG("IH: VCN TRAP\n");
2066
2067         switch (entry->src_id) {
2068         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2069                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2070                 break;
2071         default:
2072                 DRM_ERROR("Unhandled interrupt: %d %d\n",
2073                           entry->src_id, entry->src_data[0]);
2074                 break;
2075         }
2076
2077         return 0;
2078 }
2079
2080 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
2081         .process = vcn_v4_0_process_interrupt,
2082 };
2083
2084 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {
2085         .set = vcn_v4_0_set_ras_interrupt_state,
2086         .process = amdgpu_vcn_process_poison_irq,
2087 };
2088
2089 /**
2090  * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
2091  *
2092  * @adev: amdgpu_device pointer
2093  *
2094  * Set VCN block interrupt irq functions
2095  */
2096 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2097 {
2098         int i;
2099
2100         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2101                 if (adev->vcn.harvest_config & (1 << i))
2102                         continue;
2103
2104                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2105                 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
2106
2107                 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
2108                 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
2109         }
2110 }
2111
2112 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
2113         .name = "vcn_v4_0",
2114         .early_init = vcn_v4_0_early_init,
2115         .late_init = NULL,
2116         .sw_init = vcn_v4_0_sw_init,
2117         .sw_fini = vcn_v4_0_sw_fini,
2118         .hw_init = vcn_v4_0_hw_init,
2119         .hw_fini = vcn_v4_0_hw_fini,
2120         .suspend = vcn_v4_0_suspend,
2121         .resume = vcn_v4_0_resume,
2122         .is_idle = vcn_v4_0_is_idle,
2123         .wait_for_idle = vcn_v4_0_wait_for_idle,
2124         .check_soft_reset = NULL,
2125         .pre_soft_reset = NULL,
2126         .soft_reset = NULL,
2127         .post_soft_reset = NULL,
2128         .set_clockgating_state = vcn_v4_0_set_clockgating_state,
2129         .set_powergating_state = vcn_v4_0_set_powergating_state,
2130         .dump_ip_state = NULL,
2131         .print_ip_state = NULL,
2132 };
2133
2134 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
2135         .type = AMD_IP_BLOCK_TYPE_VCN,
2136         .major = 4,
2137         .minor = 0,
2138         .rev = 0,
2139         .funcs = &vcn_v4_0_ip_funcs,
2140 };
2141
2142 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
2143                         uint32_t instance, uint32_t sub_block)
2144 {
2145         uint32_t poison_stat = 0, reg_value = 0;
2146
2147         switch (sub_block) {
2148         case AMDGPU_VCN_V4_0_VCPU_VCODEC:
2149                 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2150                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2151                 break;
2152         default:
2153                 break;
2154         }
2155
2156         if (poison_stat)
2157                 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2158                         instance, sub_block);
2159
2160         return poison_stat;
2161 }
2162
2163 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
2164 {
2165         uint32_t inst, sub;
2166         uint32_t poison_stat = 0;
2167
2168         for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2169                 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)
2170                         poison_stat +=
2171                                 vcn_v4_0_query_poison_by_instance(adev, inst, sub);
2172
2173         return !!poison_stat;
2174 }
2175
2176 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {
2177         .query_poison_status = vcn_v4_0_query_ras_poison_status,
2178 };
2179
2180 static struct amdgpu_vcn_ras vcn_v4_0_ras = {
2181         .ras_block = {
2182                 .hw_ops = &vcn_v4_0_ras_hw_ops,
2183                 .ras_late_init = amdgpu_vcn_ras_late_init,
2184         },
2185 };
2186
2187 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2188 {
2189         switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2190         case IP_VERSION(4, 0, 0):
2191                 adev->vcn.ras = &vcn_v4_0_ras;
2192                 break;
2193         default:
2194                 break;
2195         }
2196 }