drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_PM_H__
  25 #define __AMDGPU_PM_H__
  26
  27 struct cg_flag_name {
  28         u64 flag;
  29         const char *name;
  30 };
  31
  32 enum amdgpu_device_attr_flags {
  33         ATTR_FLAG_BASIC = (1 << 0),
  34         ATTR_FLAG_ONEVF = (1 << 16),
  35 };
  36
  37 #define ATTR_FLAG_TYPE_MASK     (0x0000ffff)
  38 #define ATTR_FLAG_MODE_MASK     (0xffff0000)
  39 #define ATTR_FLAG_MASK_ALL      (0xffffffff)
  40
  41 enum amdgpu_device_attr_states {
  42         ATTR_STATE_UNSUPPORTED = 0,
  43         ATTR_STATE_SUPPORTED,
  44 };
  45
  46 enum amdgpu_device_attr_id {
  47         device_attr_id__unknown = -1,
  48         device_attr_id__power_dpm_state = 0,
  49         device_attr_id__power_dpm_force_performance_level,
  50         device_attr_id__pp_num_states,
  51         device_attr_id__pp_cur_state,
  52         device_attr_id__pp_force_state,
  53         device_attr_id__pp_table,
  54         device_attr_id__pp_dpm_sclk,
  55         device_attr_id__pp_dpm_mclk,
  56         device_attr_id__pp_dpm_socclk,
  57         device_attr_id__pp_dpm_fclk,
  58         device_attr_id__pp_dpm_vclk,
  59         device_attr_id__pp_dpm_vclk1,
  60         device_attr_id__pp_dpm_dclk,
  61         device_attr_id__pp_dpm_dclk1,
  62         device_attr_id__pp_dpm_dcefclk,
  63         device_attr_id__pp_dpm_pcie,
  64         device_attr_id__pp_sclk_od,
  65         device_attr_id__pp_mclk_od,
  66         device_attr_id__pp_power_profile_mode,
  67         device_attr_id__pp_od_clk_voltage,
  68         device_attr_id__gpu_busy_percent,
  69         device_attr_id__mem_busy_percent,
  70         device_attr_id__vcn_busy_percent,
  71         device_attr_id__pcie_bw,
  72         device_attr_id__pp_features,
  73         device_attr_id__unique_id,
  74         device_attr_id__thermal_throttling_logging,
  75         device_attr_id__apu_thermal_cap,
  76         device_attr_id__gpu_metrics,
  77         device_attr_id__smartshift_apu_power,
  78         device_attr_id__smartshift_dgpu_power,
  79         device_attr_id__smartshift_bias,
  80         device_attr_id__pm_metrics,
  81         device_attr_id__count,
  82 };
  83
  84 struct amdgpu_device_attr {
  85         struct device_attribute dev_attr;
  86         enum amdgpu_device_attr_id attr_id;
  87         enum amdgpu_device_attr_flags flags;
  88         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
  89                            uint32_t mask, enum amdgpu_device_attr_states *states);
  90
  91 };
  92
  93 struct amdgpu_device_attr_entry {
  94         struct list_head entry;
  95         struct amdgpu_device_attr *attr;
  96 };
  97
  98 #define to_amdgpu_device_attr(_dev_attr) \
  99         container_of(_dev_attr, struct amdgpu_device_attr, dev_attr)
 100
 101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...)  \
 102         { .dev_attr = __ATTR(_name, _mode, _show, _store),              \
 103           .attr_id = device_attr_id__##_name,                           \
 104           .flags = _flags,                                              \
 105           ##__VA_ARGS__, }
 106
 107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...)                   \
 108         __AMDGPU_DEVICE_ATTR(_name, _mode,                              \
 109                              amdgpu_get_##_name, amdgpu_set_##_name,    \
 110                              _flags, ##__VA_ARGS__)
 111
 112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...)                       \
 113         AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR,                    \
 114                            _flags, ##__VA_ARGS__)
 115
 116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...)                       \
 117         __AMDGPU_DEVICE_ATTR(_name, S_IRUGO,                            \
 118                              amdgpu_get_##_name, NULL,                  \
 119                              _flags, ##__VA_ARGS__)
 120
 121 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
 122 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev);
 123 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
 124 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev);
 125
 126 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
 127
 128 #endif