drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #include <linux/sched.h>
  42 #include <rdma/ib_user_verbs.h>
  43 #include <rdma/ib_addr.h>
  44 #include <rdma/ib_cache.h>
  45 #include <linux/mlx5/port.h>
  46 #include <linux/mlx5/vport.h>
  47 #include <rdma/ib_smi.h>
  48 #include <rdma/ib_umem.h>
  49 #include <linux/in.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/mlx5/fs.h>
  52 #include "user.h"
  53 #include "mlx5_ib.h"
  54
  55 #define DRIVER_NAME "mlx5_ib"
  56 #define DRIVER_VERSION "2.2-1"
  57 #define DRIVER_RELDATE  "Feb 2014"
  58
  59 MODULE_AUTHOR("Eli Cohen <[email protected]>");
  60 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  61 MODULE_LICENSE("Dual BSD/GPL");
  62 MODULE_VERSION(DRIVER_VERSION);
  63
  64 static int deprecated_prof_sel = 2;
  65 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  66 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  67
  68 static char mlx5_version[] =
  69         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  70         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  71
  72 enum {
  73         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  74 };
  75
  76 static enum rdma_link_layer
  77 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  78 {
  79         switch (port_type_cap) {
  80         case MLX5_CAP_PORT_TYPE_IB:
  81                 return IB_LINK_LAYER_INFINIBAND;
  82         case MLX5_CAP_PORT_TYPE_ETH:
  83                 return IB_LINK_LAYER_ETHERNET;
  84         default:
  85                 return IB_LINK_LAYER_UNSPECIFIED;
  86         }
  87 }
  88
  89 static enum rdma_link_layer
  90 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  91 {
  92         struct mlx5_ib_dev *dev = to_mdev(device);
  93         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  94
  95         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  96 }
  97
  98 static int mlx5_netdev_event(struct notifier_block *this,
  99                              unsigned long event, void *ptr)
 100 {
 101         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 102         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 103                                                  roce.nb);
 104
 105         if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
 106                 return NOTIFY_DONE;
 107
 108         write_lock(&ibdev->roce.netdev_lock);
 109         if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 110                 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
 111         write_unlock(&ibdev->roce.netdev_lock);
 112
 113         return NOTIFY_DONE;
 114 }
 115
 116 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 117                                              u8 port_num)
 118 {
 119         struct mlx5_ib_dev *ibdev = to_mdev(device);
 120         struct net_device *ndev;
 121
 122         /* Ensure ndev does not disappear before we invoke dev_hold()
 123          */
 124         read_lock(&ibdev->roce.netdev_lock);
 125         ndev = ibdev->roce.netdev;
 126         if (ndev)
 127                 dev_hold(ndev);
 128         read_unlock(&ibdev->roce.netdev_lock);
 129
 130         return ndev;
 131 }
 132
 133 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 134                                 struct ib_port_attr *props)
 135 {
 136         struct mlx5_ib_dev *dev = to_mdev(device);
 137         struct net_device *ndev;
 138         enum ib_mtu ndev_ib_mtu;
 139         u16 qkey_viol_cntr;
 140
 141         memset(props, 0, sizeof(*props));
 142
 143         props->port_cap_flags  |= IB_PORT_CM_SUP;
 144         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 145
 146         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 147                                                 roce_address_table_size);
 148         props->max_mtu          = IB_MTU_4096;
 149         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 150         props->pkey_tbl_len     = 1;
 151         props->state            = IB_PORT_DOWN;
 152         props->phys_state       = 3;
 153
 154         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 155         props->qkey_viol_cntr = qkey_viol_cntr;
 156
 157         ndev = mlx5_ib_get_netdev(device, port_num);
 158         if (!ndev)
 159                 return 0;
 160
 161         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 162                 props->state      = IB_PORT_ACTIVE;
 163                 props->phys_state = 5;
 164         }
 165
 166         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 167
 168         dev_put(ndev);
 169
 170         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 171
 172         props->active_width     = IB_WIDTH_4X;  /* TODO */
 173         props->active_speed     = IB_SPEED_QDR; /* TODO */
 174
 175         return 0;
 176 }
 177
 178 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 179                                      const struct ib_gid_attr *attr,
 180                                      void *mlx5_addr)
 181 {
 182 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 183         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 184                                                source_l3_address);
 185         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 186                                                source_mac_47_32);
 187
 188         if (!gid)
 189                 return;
 190
 191         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 192
 193         if (is_vlan_dev(attr->ndev)) {
 194                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 195                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 196         }
 197
 198         switch (attr->gid_type) {
 199         case IB_GID_TYPE_IB:
 200                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 201                 break;
 202         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 203                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 204                 break;
 205
 206         default:
 207                 WARN_ON(true);
 208         }
 209
 210         if (attr->gid_type != IB_GID_TYPE_IB) {
 211                 if (ipv6_addr_v4mapped((void *)gid))
 212                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 213                                     MLX5_ROCE_L3_TYPE_IPV4);
 214                 else
 215                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 216                                     MLX5_ROCE_L3_TYPE_IPV6);
 217         }
 218
 219         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 220             !ipv6_addr_v4mapped((void *)gid))
 221                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 222         else
 223                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 224 }
 225
 226 static int set_roce_addr(struct ib_device *device, u8 port_num,
 227                          unsigned int index,
 228                          const union ib_gid *gid,
 229                          const struct ib_gid_attr *attr)
 230 {
 231         struct mlx5_ib_dev *dev = to_mdev(device);
 232         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)];
 233         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
 234         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 235         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 236
 237         if (ll != IB_LINK_LAYER_ETHERNET)
 238                 return -EINVAL;
 239
 240         memset(in, 0, sizeof(in));
 241
 242         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 243
 244         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 245         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 246
 247         memset(out, 0, sizeof(out));
 248         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 249 }
 250
 251 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 252                            unsigned int index, const union ib_gid *gid,
 253                            const struct ib_gid_attr *attr,
 254                            __always_unused void **context)
 255 {
 256         return set_roce_addr(device, port_num, index, gid, attr);
 257 }
 258
 259 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 260                            unsigned int index, __always_unused void **context)
 261 {
 262         return set_roce_addr(device, port_num, index, NULL, NULL);
 263 }
 264
 265 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 266                                int index)
 267 {
 268         struct ib_gid_attr attr;
 269         union ib_gid gid;
 270
 271         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 272                 return 0;
 273
 274         if (!attr.ndev)
 275                 return 0;
 276
 277         dev_put(attr.ndev);
 278
 279         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 280                 return 0;
 281
 282         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 283 }
 284
 285 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 286 {
 287         return !dev->mdev->issi;
 288 }
 289
 290 enum {
 291         MLX5_VPORT_ACCESS_METHOD_MAD,
 292         MLX5_VPORT_ACCESS_METHOD_HCA,
 293         MLX5_VPORT_ACCESS_METHOD_NIC,
 294 };
 295
 296 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 297 {
 298         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 299                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 300
 301         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 302             IB_LINK_LAYER_ETHERNET)
 303                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 304
 305         return MLX5_VPORT_ACCESS_METHOD_HCA;
 306 }
 307
 308 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 309                             struct ib_device_attr *props)
 310 {
 311         u8 tmp;
 312         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 313         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 314         u8 atomic_req_8B_endianness_mode =
 315                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 316
 317         /* Check if HW supports 8 bytes standard atomic operations and capable
 318          * of host endianness respond
 319          */
 320         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 321         if (((atomic_operations & tmp) == tmp) &&
 322             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 323             (atomic_req_8B_endianness_mode)) {
 324                 props->atomic_cap = IB_ATOMIC_HCA;
 325         } else {
 326                 props->atomic_cap = IB_ATOMIC_NONE;
 327         }
 328 }
 329
 330 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 331                                         __be64 *sys_image_guid)
 332 {
 333         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 334         struct mlx5_core_dev *mdev = dev->mdev;
 335         u64 tmp;
 336         int err;
 337
 338         switch (mlx5_get_vport_access_method(ibdev)) {
 339         case MLX5_VPORT_ACCESS_METHOD_MAD:
 340                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 341                                                             sys_image_guid);
 342
 343         case MLX5_VPORT_ACCESS_METHOD_HCA:
 344                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 345                 break;
 346
 347         case MLX5_VPORT_ACCESS_METHOD_NIC:
 348                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 349                 break;
 350
 351         default:
 352                 return -EINVAL;
 353         }
 354
 355         if (!err)
 356                 *sys_image_guid = cpu_to_be64(tmp);
 357
 358         return err;
 359
 360 }
 361
 362 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 363                                 u16 *max_pkeys)
 364 {
 365         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 366         struct mlx5_core_dev *mdev = dev->mdev;
 367
 368         switch (mlx5_get_vport_access_method(ibdev)) {
 369         case MLX5_VPORT_ACCESS_METHOD_MAD:
 370                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 371
 372         case MLX5_VPORT_ACCESS_METHOD_HCA:
 373         case MLX5_VPORT_ACCESS_METHOD_NIC:
 374                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 375                                                 pkey_table_size));
 376                 return 0;
 377
 378         default:
 379                 return -EINVAL;
 380         }
 381 }
 382
 383 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 384                                 u32 *vendor_id)
 385 {
 386         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 387
 388         switch (mlx5_get_vport_access_method(ibdev)) {
 389         case MLX5_VPORT_ACCESS_METHOD_MAD:
 390                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 391
 392         case MLX5_VPORT_ACCESS_METHOD_HCA:
 393         case MLX5_VPORT_ACCESS_METHOD_NIC:
 394                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 395
 396         default:
 397                 return -EINVAL;
 398         }
 399 }
 400
 401 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 402                                 __be64 *node_guid)
 403 {
 404         u64 tmp;
 405         int err;
 406
 407         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 408         case MLX5_VPORT_ACCESS_METHOD_MAD:
 409                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 410
 411         case MLX5_VPORT_ACCESS_METHOD_HCA:
 412                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 413                 break;
 414
 415         case MLX5_VPORT_ACCESS_METHOD_NIC:
 416                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 417                 break;
 418
 419         default:
 420                 return -EINVAL;
 421         }
 422
 423         if (!err)
 424                 *node_guid = cpu_to_be64(tmp);
 425
 426         return err;
 427 }
 428
 429 struct mlx5_reg_node_desc {
 430         u8      desc[64];
 431 };
 432
 433 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 434 {
 435         struct mlx5_reg_node_desc in;
 436
 437         if (mlx5_use_mad_ifc(dev))
 438                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 439
 440         memset(&in, 0, sizeof(in));
 441
 442         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 443                                     sizeof(struct mlx5_reg_node_desc),
 444                                     MLX5_REG_NODE_DESC, 0, 0);
 445 }
 446
 447 static int mlx5_ib_query_device(struct ib_device *ibdev,
 448                                 struct ib_device_attr *props,
 449                                 struct ib_udata *uhw)
 450 {
 451         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 452         struct mlx5_core_dev *mdev = dev->mdev;
 453         int err = -ENOMEM;
 454         int max_rq_sg;
 455         int max_sq_sg;
 456         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 457
 458         if (uhw->inlen || uhw->outlen)
 459                 return -EINVAL;
 460
 461         memset(props, 0, sizeof(*props));
 462         err = mlx5_query_system_image_guid(ibdev,
 463                                            &props->sys_image_guid);
 464         if (err)
 465                 return err;
 466
 467         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 468         if (err)
 469                 return err;
 470
 471         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 472         if (err)
 473                 return err;
 474
 475         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 476                 (fw_rev_min(dev->mdev) << 16) |
 477                 fw_rev_sub(dev->mdev);
 478         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 479                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 480                 IB_DEVICE_SYS_IMAGE_GUID                |
 481                 IB_DEVICE_RC_RNR_NAK_GEN;
 482
 483         if (MLX5_CAP_GEN(mdev, pkv))
 484                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 485         if (MLX5_CAP_GEN(mdev, qkv))
 486                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 487         if (MLX5_CAP_GEN(mdev, apm))
 488                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 489         if (MLX5_CAP_GEN(mdev, xrc))
 490                 props->device_cap_flags |= IB_DEVICE_XRC;
 491         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 492         if (MLX5_CAP_GEN(mdev, sho)) {
 493                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 494                 /* At this stage no support for signature handover */
 495                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 496                                       IB_PROT_T10DIF_TYPE_2 |
 497                                       IB_PROT_T10DIF_TYPE_3;
 498                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 499                                        IB_GUARD_T10DIF_CSUM;
 500         }
 501         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 502                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 503
 504         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 505             (MLX5_CAP_ETH(dev->mdev, csum_cap)))
 506                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 507
 508         props->vendor_part_id      = mdev->pdev->device;
 509         props->hw_ver              = mdev->pdev->revision;
 510
 511         props->max_mr_size         = ~0ull;
 512         props->page_size_cap       = ~(min_page_size - 1);
 513         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 514         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 515         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 516                      sizeof(struct mlx5_wqe_data_seg);
 517         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 518                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 519                      sizeof(struct mlx5_wqe_data_seg);
 520         props->max_sge = min(max_rq_sg, max_sq_sg);
 521         props->max_sge_rd = props->max_sge;
 522         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 523         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 524         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 525         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 526         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 527         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 528         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 529         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 530         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 531         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 532         props->max_srq_sge         = max_rq_sg - 1;
 533         props->max_fast_reg_page_list_len = (unsigned int)-1;
 534         get_atomic_caps(dev, props);
 535         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 536         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 537         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 538         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 539                                            props->max_mcast_grp;
 540         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 541         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 542         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 543
 544 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 545         if (MLX5_CAP_GEN(mdev, pg))
 546                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 547         props->odp_caps = dev->odp_caps;
 548 #endif
 549
 550         if (MLX5_CAP_GEN(mdev, cd))
 551                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 552
 553         return 0;
 554 }
 555
 556 enum mlx5_ib_width {
 557         MLX5_IB_WIDTH_1X        = 1 << 0,
 558         MLX5_IB_WIDTH_2X        = 1 << 1,
 559         MLX5_IB_WIDTH_4X        = 1 << 2,
 560         MLX5_IB_WIDTH_8X        = 1 << 3,
 561         MLX5_IB_WIDTH_12X       = 1 << 4
 562 };
 563
 564 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 565                                   u8 *ib_width)
 566 {
 567         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 568         int err = 0;
 569
 570         if (active_width & MLX5_IB_WIDTH_1X) {
 571                 *ib_width = IB_WIDTH_1X;
 572         } else if (active_width & MLX5_IB_WIDTH_2X) {
 573                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 574                             (int)active_width);
 575                 err = -EINVAL;
 576         } else if (active_width & MLX5_IB_WIDTH_4X) {
 577                 *ib_width = IB_WIDTH_4X;
 578         } else if (active_width & MLX5_IB_WIDTH_8X) {
 579                 *ib_width = IB_WIDTH_8X;
 580         } else if (active_width & MLX5_IB_WIDTH_12X) {
 581                 *ib_width = IB_WIDTH_12X;
 582         } else {
 583                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 584                             (int)active_width);
 585                 err = -EINVAL;
 586         }
 587
 588         return err;
 589 }
 590
 591 static int mlx5_mtu_to_ib_mtu(int mtu)
 592 {
 593         switch (mtu) {
 594         case 256: return 1;
 595         case 512: return 2;
 596         case 1024: return 3;
 597         case 2048: return 4;
 598         case 4096: return 5;
 599         default:
 600                 pr_warn("invalid mtu\n");
 601                 return -1;
 602         }
 603 }
 604
 605 enum ib_max_vl_num {
 606         __IB_MAX_VL_0           = 1,
 607         __IB_MAX_VL_0_1         = 2,
 608         __IB_MAX_VL_0_3         = 3,
 609         __IB_MAX_VL_0_7         = 4,
 610         __IB_MAX_VL_0_14        = 5,
 611 };
 612
 613 enum mlx5_vl_hw_cap {
 614         MLX5_VL_HW_0    = 1,
 615         MLX5_VL_HW_0_1  = 2,
 616         MLX5_VL_HW_0_2  = 3,
 617         MLX5_VL_HW_0_3  = 4,
 618         MLX5_VL_HW_0_4  = 5,
 619         MLX5_VL_HW_0_5  = 6,
 620         MLX5_VL_HW_0_6  = 7,
 621         MLX5_VL_HW_0_7  = 8,
 622         MLX5_VL_HW_0_14 = 15
 623 };
 624
 625 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 626                                 u8 *max_vl_num)
 627 {
 628         switch (vl_hw_cap) {
 629         case MLX5_VL_HW_0:
 630                 *max_vl_num = __IB_MAX_VL_0;
 631                 break;
 632         case MLX5_VL_HW_0_1:
 633                 *max_vl_num = __IB_MAX_VL_0_1;
 634                 break;
 635         case MLX5_VL_HW_0_3:
 636                 *max_vl_num = __IB_MAX_VL_0_3;
 637                 break;
 638         case MLX5_VL_HW_0_7:
 639                 *max_vl_num = __IB_MAX_VL_0_7;
 640                 break;
 641         case MLX5_VL_HW_0_14:
 642                 *max_vl_num = __IB_MAX_VL_0_14;
 643                 break;
 644
 645         default:
 646                 return -EINVAL;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 653                                struct ib_port_attr *props)
 654 {
 655         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 656         struct mlx5_core_dev *mdev = dev->mdev;
 657         struct mlx5_hca_vport_context *rep;
 658         int max_mtu;
 659         int oper_mtu;
 660         int err;
 661         u8 ib_link_width_oper;
 662         u8 vl_hw_cap;
 663
 664         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 665         if (!rep) {
 666                 err = -ENOMEM;
 667                 goto out;
 668         }
 669
 670         memset(props, 0, sizeof(*props));
 671
 672         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 673         if (err)
 674                 goto out;
 675
 676         props->lid              = rep->lid;
 677         props->lmc              = rep->lmc;
 678         props->sm_lid           = rep->sm_lid;
 679         props->sm_sl            = rep->sm_sl;
 680         props->state            = rep->vport_state;
 681         props->phys_state       = rep->port_physical_state;
 682         props->port_cap_flags   = rep->cap_mask1;
 683         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 684         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 685         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 686         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 687         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 688         props->subnet_timeout   = rep->subnet_timeout;
 689         props->init_type_reply  = rep->init_type_reply;
 690
 691         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 692         if (err)
 693                 goto out;
 694
 695         err = translate_active_width(ibdev, ib_link_width_oper,
 696                                      &props->active_width);
 697         if (err)
 698                 goto out;
 699         err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
 700                                          port);
 701         if (err)
 702                 goto out;
 703
 704         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 705
 706         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 707
 708         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 709
 710         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 711
 712         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 713         if (err)
 714                 goto out;
 715
 716         err = translate_max_vl_num(ibdev, vl_hw_cap,
 717                                    &props->max_vl_num);
 718 out:
 719         kfree(rep);
 720         return err;
 721 }
 722
 723 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 724                        struct ib_port_attr *props)
 725 {
 726         switch (mlx5_get_vport_access_method(ibdev)) {
 727         case MLX5_VPORT_ACCESS_METHOD_MAD:
 728                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 729
 730         case MLX5_VPORT_ACCESS_METHOD_HCA:
 731                 return mlx5_query_hca_port(ibdev, port, props);
 732
 733         case MLX5_VPORT_ACCESS_METHOD_NIC:
 734                 return mlx5_query_port_roce(ibdev, port, props);
 735
 736         default:
 737                 return -EINVAL;
 738         }
 739 }
 740
 741 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 742                              union ib_gid *gid)
 743 {
 744         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 745         struct mlx5_core_dev *mdev = dev->mdev;
 746
 747         switch (mlx5_get_vport_access_method(ibdev)) {
 748         case MLX5_VPORT_ACCESS_METHOD_MAD:
 749                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 750
 751         case MLX5_VPORT_ACCESS_METHOD_HCA:
 752                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 753
 754         default:
 755                 return -EINVAL;
 756         }
 757
 758 }
 759
 760 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 761                               u16 *pkey)
 762 {
 763         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 764         struct mlx5_core_dev *mdev = dev->mdev;
 765
 766         switch (mlx5_get_vport_access_method(ibdev)) {
 767         case MLX5_VPORT_ACCESS_METHOD_MAD:
 768                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 769
 770         case MLX5_VPORT_ACCESS_METHOD_HCA:
 771         case MLX5_VPORT_ACCESS_METHOD_NIC:
 772                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 773                                                  pkey);
 774         default:
 775                 return -EINVAL;
 776         }
 777 }
 778
 779 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 780                                  struct ib_device_modify *props)
 781 {
 782         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 783         struct mlx5_reg_node_desc in;
 784         struct mlx5_reg_node_desc out;
 785         int err;
 786
 787         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 788                 return -EOPNOTSUPP;
 789
 790         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 791                 return 0;
 792
 793         /*
 794          * If possible, pass node desc to FW, so it can generate
 795          * a 144 trap.  If cmd fails, just ignore.
 796          */
 797         memcpy(&in, props->node_desc, 64);
 798         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 799                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 800         if (err)
 801                 return err;
 802
 803         memcpy(ibdev->node_desc, props->node_desc, 64);
 804
 805         return err;
 806 }
 807
 808 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 809                                struct ib_port_modify *props)
 810 {
 811         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 812         struct ib_port_attr attr;
 813         u32 tmp;
 814         int err;
 815
 816         mutex_lock(&dev->cap_mask_mutex);
 817
 818         err = mlx5_ib_query_port(ibdev, port, &attr);
 819         if (err)
 820                 goto out;
 821
 822         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 823                 ~props->clr_port_cap_mask;
 824
 825         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 826
 827 out:
 828         mutex_unlock(&dev->cap_mask_mutex);
 829         return err;
 830 }
 831
 832 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 833                                                   struct ib_udata *udata)
 834 {
 835         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 836         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 837         struct mlx5_ib_alloc_ucontext_resp resp = {};
 838         struct mlx5_ib_ucontext *context;
 839         struct mlx5_uuar_info *uuari;
 840         struct mlx5_uar *uars;
 841         int gross_uuars;
 842         int num_uars;
 843         int ver;
 844         int uuarn;
 845         int err;
 846         int i;
 847         size_t reqlen;
 848         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 849                                      max_cqe_version);
 850
 851         if (!dev->ib_active)
 852                 return ERR_PTR(-EAGAIN);
 853
 854         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 855                 return ERR_PTR(-EINVAL);
 856
 857         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 858         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 859                 ver = 0;
 860         else if (reqlen >= min_req_v2)
 861                 ver = 2;
 862         else
 863                 return ERR_PTR(-EINVAL);
 864
 865         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 866         if (err)
 867                 return ERR_PTR(err);
 868
 869         if (req.flags)
 870                 return ERR_PTR(-EINVAL);
 871
 872         if (req.total_num_uuars > MLX5_MAX_UUARS)
 873                 return ERR_PTR(-ENOMEM);
 874
 875         if (req.total_num_uuars == 0)
 876                 return ERR_PTR(-EINVAL);
 877
 878         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 879                 return ERR_PTR(-EOPNOTSUPP);
 880
 881         if (reqlen > sizeof(req) &&
 882             !ib_is_udata_cleared(udata, sizeof(req),
 883                                  reqlen - sizeof(req)))
 884                 return ERR_PTR(-EOPNOTSUPP);
 885
 886         req.total_num_uuars = ALIGN(req.total_num_uuars,
 887                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
 888         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
 889                 return ERR_PTR(-EINVAL);
 890
 891         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
 892         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
 893         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
 894         resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
 895         resp.cache_line_size = L1_CACHE_BYTES;
 896         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
 897         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
 898         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 899         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 900         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
 901         resp.cqe_version = min_t(__u8,
 902                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
 903                                  req.max_cqe_version);
 904         resp.response_length = min(offsetof(typeof(resp), response_length) +
 905                                    sizeof(resp.response_length), udata->outlen);
 906
 907         context = kzalloc(sizeof(*context), GFP_KERNEL);
 908         if (!context)
 909                 return ERR_PTR(-ENOMEM);
 910
 911         uuari = &context->uuari;
 912         mutex_init(&uuari->lock);
 913         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
 914         if (!uars) {
 915                 err = -ENOMEM;
 916                 goto out_ctx;
 917         }
 918
 919         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
 920                                 sizeof(*uuari->bitmap),
 921                                 GFP_KERNEL);
 922         if (!uuari->bitmap) {
 923                 err = -ENOMEM;
 924                 goto out_uar_ctx;
 925         }
 926         /*
 927          * clear all fast path uuars
 928          */
 929         for (i = 0; i < gross_uuars; i++) {
 930                 uuarn = i & 3;
 931                 if (uuarn == 2 || uuarn == 3)
 932                         set_bit(i, uuari->bitmap);
 933         }
 934
 935         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
 936         if (!uuari->count) {
 937                 err = -ENOMEM;
 938                 goto out_bitmap;
 939         }
 940
 941         for (i = 0; i < num_uars; i++) {
 942                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
 943                 if (err)
 944                         goto out_count;
 945         }
 946
 947 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 948         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
 949 #endif
 950
 951         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
 952                 err = mlx5_core_alloc_transport_domain(dev->mdev,
 953                                                        &context->tdn);
 954                 if (err)
 955                         goto out_uars;
 956         }
 957
 958         INIT_LIST_HEAD(&context->db_page_list);
 959         mutex_init(&context->db_page_mutex);
 960
 961         resp.tot_uuars = req.total_num_uuars;
 962         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
 963
 964         if (field_avail(typeof(resp), cqe_version, udata->outlen))
 965                 resp.response_length += sizeof(resp.cqe_version);
 966
 967         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
 968                 resp.comp_mask |=
 969                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
 970                 resp.hca_core_clock_offset =
 971                         offsetof(struct mlx5_init_seg, internal_timer_h) %
 972                         PAGE_SIZE;
 973                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
 974                                         sizeof(resp.reserved2) +
 975                                         sizeof(resp.reserved3);
 976         }
 977
 978         err = ib_copy_to_udata(udata, &resp, resp.response_length);
 979         if (err)
 980                 goto out_td;
 981
 982         uuari->ver = ver;
 983         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
 984         uuari->uars = uars;
 985         uuari->num_uars = num_uars;
 986         context->cqe_version = resp.cqe_version;
 987
 988         return &context->ibucontext;
 989
 990 out_td:
 991         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
 992                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
 993
 994 out_uars:
 995         for (i--; i >= 0; i--)
 996                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
 997 out_count:
 998         kfree(uuari->count);
 999
1000 out_bitmap:
1001         kfree(uuari->bitmap);
1002
1003 out_uar_ctx:
1004         kfree(uars);
1005
1006 out_ctx:
1007         kfree(context);
1008         return ERR_PTR(err);
1009 }
1010
1011 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1012 {
1013         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1014         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1015         struct mlx5_uuar_info *uuari = &context->uuari;
1016         int i;
1017
1018         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1019                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1020
1021         for (i = 0; i < uuari->num_uars; i++) {
1022                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1023                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1024         }
1025
1026         kfree(uuari->count);
1027         kfree(uuari->bitmap);
1028         kfree(uuari->uars);
1029         kfree(context);
1030
1031         return 0;
1032 }
1033
1034 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1035 {
1036         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1037 }
1038
1039 static int get_command(unsigned long offset)
1040 {
1041         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1042 }
1043
1044 static int get_arg(unsigned long offset)
1045 {
1046         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1047 }
1048
1049 static int get_index(unsigned long offset)
1050 {
1051         return get_arg(offset);
1052 }
1053
1054 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1055 {
1056         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1057         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1058         struct mlx5_uuar_info *uuari = &context->uuari;
1059         unsigned long command;
1060         unsigned long idx;
1061         phys_addr_t pfn;
1062
1063         command = get_command(vma->vm_pgoff);
1064         switch (command) {
1065         case MLX5_IB_MMAP_REGULAR_PAGE:
1066                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1067                         return -EINVAL;
1068
1069                 idx = get_index(vma->vm_pgoff);
1070                 if (idx >= uuari->num_uars)
1071                         return -EINVAL;
1072
1073                 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1074                 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1075                             (unsigned long long)pfn);
1076
1077                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1078                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1079                                        PAGE_SIZE, vma->vm_page_prot))
1080                         return -EAGAIN;
1081
1082                 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1083                             vma->vm_start,
1084                             (unsigned long long)pfn << PAGE_SHIFT);
1085                 break;
1086
1087         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1088                 return -ENOSYS;
1089
1090         case MLX5_IB_MMAP_CORE_CLOCK:
1091                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1092                         return -EINVAL;
1093
1094                 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1095                         return -EPERM;
1096
1097                 /* Don't expose to user-space information it shouldn't have */
1098                 if (PAGE_SIZE > 4096)
1099                         return -EOPNOTSUPP;
1100
1101                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1102                 pfn = (dev->mdev->iseg_base +
1103                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1104                         PAGE_SHIFT;
1105                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1106                                        PAGE_SIZE, vma->vm_page_prot))
1107                         return -EAGAIN;
1108
1109                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1110                             vma->vm_start,
1111                             (unsigned long long)pfn << PAGE_SHIFT);
1112                 break;
1113
1114         default:
1115                 return -EINVAL;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1122                                       struct ib_ucontext *context,
1123                                       struct ib_udata *udata)
1124 {
1125         struct mlx5_ib_alloc_pd_resp resp;
1126         struct mlx5_ib_pd *pd;
1127         int err;
1128
1129         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1130         if (!pd)
1131                 return ERR_PTR(-ENOMEM);
1132
1133         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1134         if (err) {
1135                 kfree(pd);
1136                 return ERR_PTR(err);
1137         }
1138
1139         if (context) {
1140                 resp.pdn = pd->pdn;
1141                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1142                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1143                         kfree(pd);
1144                         return ERR_PTR(-EFAULT);
1145                 }
1146         }
1147
1148         return &pd->ibpd;
1149 }
1150
1151 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1152 {
1153         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1154         struct mlx5_ib_pd *mpd = to_mpd(pd);
1155
1156         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1157         kfree(mpd);
1158
1159         return 0;
1160 }
1161
1162 static bool outer_header_zero(u32 *match_criteria)
1163 {
1164         int size = MLX5_ST_SZ_BYTES(fte_match_param);
1165         char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1166                                              outer_headers);
1167
1168         return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1169                                                   outer_headers_c + 1,
1170                                                   size - 1);
1171 }
1172
1173 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1174                            union ib_flow_spec *ib_spec)
1175 {
1176         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1177                                              outer_headers);
1178         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1179                                              outer_headers);
1180         switch (ib_spec->type) {
1181         case IB_FLOW_SPEC_ETH:
1182                 if (ib_spec->size != sizeof(ib_spec->eth))
1183                         return -EINVAL;
1184
1185                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1186                                              dmac_47_16),
1187                                 ib_spec->eth.mask.dst_mac);
1188                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1189                                              dmac_47_16),
1190                                 ib_spec->eth.val.dst_mac);
1191
1192                 if (ib_spec->eth.mask.vlan_tag) {
1193                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1194                                  vlan_tag, 1);
1195                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1196                                  vlan_tag, 1);
1197
1198                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1199                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1200                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1201                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1202
1203                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1204                                  first_cfi,
1205                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1206                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1207                                  first_cfi,
1208                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1209
1210                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1211                                  first_prio,
1212                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1213                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1214                                  first_prio,
1215                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1216                 }
1217                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1218                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1219                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1220                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1221                 break;
1222         case IB_FLOW_SPEC_IPV4:
1223                 if (ib_spec->size != sizeof(ib_spec->ipv4))
1224                         return -EINVAL;
1225
1226                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1227                          ethertype, 0xffff);
1228                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1229                          ethertype, ETH_P_IP);
1230
1231                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1232                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1233                        &ib_spec->ipv4.mask.src_ip,
1234                        sizeof(ib_spec->ipv4.mask.src_ip));
1235                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1236                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1237                        &ib_spec->ipv4.val.src_ip,
1238                        sizeof(ib_spec->ipv4.val.src_ip));
1239                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1240                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1241                        &ib_spec->ipv4.mask.dst_ip,
1242                        sizeof(ib_spec->ipv4.mask.dst_ip));
1243                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1244                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1245                        &ib_spec->ipv4.val.dst_ip,
1246                        sizeof(ib_spec->ipv4.val.dst_ip));
1247                 break;
1248         case IB_FLOW_SPEC_TCP:
1249                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1250                         return -EINVAL;
1251
1252                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1253                          0xff);
1254                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1255                          IPPROTO_TCP);
1256
1257                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1258                          ntohs(ib_spec->tcp_udp.mask.src_port));
1259                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1260                          ntohs(ib_spec->tcp_udp.val.src_port));
1261
1262                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1263                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1264                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1265                          ntohs(ib_spec->tcp_udp.val.dst_port));
1266                 break;
1267         case IB_FLOW_SPEC_UDP:
1268                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1269                         return -EINVAL;
1270
1271                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1272                          0xff);
1273                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1274                          IPPROTO_UDP);
1275
1276                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1277                          ntohs(ib_spec->tcp_udp.mask.src_port));
1278                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1279                          ntohs(ib_spec->tcp_udp.val.src_port));
1280
1281                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1282                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1283                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1284                          ntohs(ib_spec->tcp_udp.val.dst_port));
1285                 break;
1286         default:
1287                 return -EINVAL;
1288         }
1289
1290         return 0;
1291 }
1292
1293 /* If a flow could catch both multicast and unicast packets,
1294  * it won't fall into the multicast flow steering table and this rule
1295  * could steal other multicast packets.
1296  */
1297 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1298 {
1299         struct ib_flow_spec_eth *eth_spec;
1300
1301         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1302             ib_attr->size < sizeof(struct ib_flow_attr) +
1303             sizeof(struct ib_flow_spec_eth) ||
1304             ib_attr->num_of_specs < 1)
1305                 return false;
1306
1307         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1308         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1309             eth_spec->size != sizeof(*eth_spec))
1310                 return false;
1311
1312         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1313                is_multicast_ether_addr(eth_spec->val.dst_mac);
1314 }
1315
1316 static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1317 {
1318         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1319         bool has_ipv4_spec = false;
1320         bool eth_type_ipv4 = true;
1321         unsigned int spec_index;
1322
1323         /* Validate that ethertype is correct */
1324         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1325                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1326                     ib_spec->eth.mask.ether_type) {
1327                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1328                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1329                                 eth_type_ipv4 = false;
1330                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1331                         has_ipv4_spec = true;
1332                 }
1333                 ib_spec = (void *)ib_spec + ib_spec->size;
1334         }
1335         return !has_ipv4_spec || eth_type_ipv4;
1336 }
1337
1338 static void put_flow_table(struct mlx5_ib_dev *dev,
1339                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1340 {
1341         prio->refcount -= !!ft_added;
1342         if (!prio->refcount) {
1343                 mlx5_destroy_flow_table(prio->flow_table);
1344                 prio->flow_table = NULL;
1345         }
1346 }
1347
1348 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1349 {
1350         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1351         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1352                                                           struct mlx5_ib_flow_handler,
1353                                                           ibflow);
1354         struct mlx5_ib_flow_handler *iter, *tmp;
1355
1356         mutex_lock(&dev->flow_db.lock);
1357
1358         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1359                 mlx5_del_flow_rule(iter->rule);
1360                 list_del(&iter->list);
1361                 kfree(iter);
1362         }
1363
1364         mlx5_del_flow_rule(handler->rule);
1365         put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1366         mutex_unlock(&dev->flow_db.lock);
1367
1368         kfree(handler);
1369
1370         return 0;
1371 }
1372
1373 #define MLX5_FS_MAX_TYPES        10
1374 #define MLX5_FS_MAX_ENTRIES      32000UL
1375 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1376                                                 struct ib_flow_attr *flow_attr)
1377 {
1378         struct mlx5_flow_namespace *ns = NULL;
1379         struct mlx5_ib_flow_prio *prio;
1380         struct mlx5_flow_table *ft;
1381         int num_entries;
1382         int num_groups;
1383         int priority;
1384         int err = 0;
1385
1386         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1387                 if (flow_is_multicast_only(flow_attr))
1388                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1389                 else
1390                         priority = flow_attr->priority;
1391                 ns = mlx5_get_flow_namespace(dev->mdev,
1392                                              MLX5_FLOW_NAMESPACE_BYPASS);
1393                 num_entries = MLX5_FS_MAX_ENTRIES;
1394                 num_groups = MLX5_FS_MAX_TYPES;
1395                 prio = &dev->flow_db.prios[priority];
1396         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1397                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1398                 ns = mlx5_get_flow_namespace(dev->mdev,
1399                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1400                 build_leftovers_ft_param(&priority,
1401                                          &num_entries,
1402                                          &num_groups);
1403                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1404         }
1405
1406         if (!ns)
1407                 return ERR_PTR(-ENOTSUPP);
1408
1409         ft = prio->flow_table;
1410         if (!ft) {
1411                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1412                                                          num_entries,
1413                                                          num_groups);
1414
1415                 if (!IS_ERR(ft)) {
1416                         prio->refcount = 0;
1417                         prio->flow_table = ft;
1418                 } else {
1419                         err = PTR_ERR(ft);
1420                 }
1421         }
1422
1423         return err ? ERR_PTR(err) : prio;
1424 }
1425
1426 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1427                                                      struct mlx5_ib_flow_prio *ft_prio,
1428                                                      struct ib_flow_attr *flow_attr,
1429                                                      struct mlx5_flow_destination *dst)
1430 {
1431         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1432         struct mlx5_ib_flow_handler *handler;
1433         void *ib_flow = flow_attr + 1;
1434         u8 match_criteria_enable = 0;
1435         unsigned int spec_index;
1436         u32 *match_c;
1437         u32 *match_v;
1438         int err = 0;
1439
1440         if (!is_valid_attr(flow_attr))
1441                 return ERR_PTR(-EINVAL);
1442
1443         match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1444         match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1445         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1446         if (!handler || !match_c || !match_v) {
1447                 err = -ENOMEM;
1448                 goto free;
1449         }
1450
1451         INIT_LIST_HEAD(&handler->list);
1452
1453         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1454                 err = parse_flow_attr(match_c, match_v, ib_flow);
1455                 if (err < 0)
1456                         goto free;
1457
1458                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1459         }
1460
1461         /* Outer header support only */
1462         match_criteria_enable = (!outer_header_zero(match_c)) << 0;
1463         handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1464                                            match_c, match_v,
1465                                            MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
1466                                            MLX5_FS_DEFAULT_FLOW_TAG,
1467                                            dst);
1468
1469         if (IS_ERR(handler->rule)) {
1470                 err = PTR_ERR(handler->rule);
1471                 goto free;
1472         }
1473
1474         handler->prio = ft_prio - dev->flow_db.prios;
1475
1476         ft_prio->flow_table = ft;
1477 free:
1478         if (err)
1479                 kfree(handler);
1480         kfree(match_c);
1481         kfree(match_v);
1482         return err ? ERR_PTR(err) : handler;
1483 }
1484
1485 enum {
1486         LEFTOVERS_MC,
1487         LEFTOVERS_UC,
1488 };
1489
1490 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1491                                                           struct mlx5_ib_flow_prio *ft_prio,
1492                                                           struct ib_flow_attr *flow_attr,
1493                                                           struct mlx5_flow_destination *dst)
1494 {
1495         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1496         struct mlx5_ib_flow_handler *handler = NULL;
1497
1498         static struct {
1499                 struct ib_flow_attr     flow_attr;
1500                 struct ib_flow_spec_eth eth_flow;
1501         } leftovers_specs[] = {
1502                 [LEFTOVERS_MC] = {
1503                         .flow_attr = {
1504                                 .num_of_specs = 1,
1505                                 .size = sizeof(leftovers_specs[0])
1506                         },
1507                         .eth_flow = {
1508                                 .type = IB_FLOW_SPEC_ETH,
1509                                 .size = sizeof(struct ib_flow_spec_eth),
1510                                 .mask = {.dst_mac = {0x1} },
1511                                 .val =  {.dst_mac = {0x1} }
1512                         }
1513                 },
1514                 [LEFTOVERS_UC] = {
1515                         .flow_attr = {
1516                                 .num_of_specs = 1,
1517                                 .size = sizeof(leftovers_specs[0])
1518                         },
1519                         .eth_flow = {
1520                                 .type = IB_FLOW_SPEC_ETH,
1521                                 .size = sizeof(struct ib_flow_spec_eth),
1522                                 .mask = {.dst_mac = {0x1} },
1523                                 .val = {.dst_mac = {} }
1524                         }
1525                 }
1526         };
1527
1528         handler = create_flow_rule(dev, ft_prio,
1529                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1530                                    dst);
1531         if (!IS_ERR(handler) &&
1532             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1533                 handler_ucast = create_flow_rule(dev, ft_prio,
1534                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1535                                                  dst);
1536                 if (IS_ERR(handler_ucast)) {
1537                         kfree(handler);
1538                         handler = handler_ucast;
1539                 } else {
1540                         list_add(&handler_ucast->list, &handler->list);
1541                 }
1542         }
1543
1544         return handler;
1545 }
1546
1547 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1548                                            struct ib_flow_attr *flow_attr,
1549                                            int domain)
1550 {
1551         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1552         struct mlx5_ib_flow_handler *handler = NULL;
1553         struct mlx5_flow_destination *dst = NULL;
1554         struct mlx5_ib_flow_prio *ft_prio;
1555         int err;
1556
1557         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1558                 return ERR_PTR(-ENOSPC);
1559
1560         if (domain != IB_FLOW_DOMAIN_USER ||
1561             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1562             flow_attr->flags)
1563                 return ERR_PTR(-EINVAL);
1564
1565         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1566         if (!dst)
1567                 return ERR_PTR(-ENOMEM);
1568
1569         mutex_lock(&dev->flow_db.lock);
1570
1571         ft_prio = get_flow_table(dev, flow_attr);
1572         if (IS_ERR(ft_prio)) {
1573                 err = PTR_ERR(ft_prio);
1574                 goto unlock;
1575         }
1576
1577         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1578         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1579
1580         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1581                 handler = create_flow_rule(dev, ft_prio, flow_attr,
1582                                            dst);
1583         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1584                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1585                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1586                                                 dst);
1587         } else {
1588                 err = -EINVAL;
1589                 goto destroy_ft;
1590         }
1591
1592         if (IS_ERR(handler)) {
1593                 err = PTR_ERR(handler);
1594                 handler = NULL;
1595                 goto destroy_ft;
1596         }
1597
1598         ft_prio->refcount++;
1599         mutex_unlock(&dev->flow_db.lock);
1600         kfree(dst);
1601
1602         return &handler->ibflow;
1603
1604 destroy_ft:
1605         put_flow_table(dev, ft_prio, false);
1606 unlock:
1607         mutex_unlock(&dev->flow_db.lock);
1608         kfree(dst);
1609         kfree(handler);
1610         return ERR_PTR(err);
1611 }
1612
1613 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1614 {
1615         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1616         int err;
1617
1618         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
1619         if (err)
1620                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1621                              ibqp->qp_num, gid->raw);
1622
1623         return err;
1624 }
1625
1626 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1627 {
1628         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1629         int err;
1630
1631         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
1632         if (err)
1633                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1634                              ibqp->qp_num, gid->raw);
1635
1636         return err;
1637 }
1638
1639 static int init_node_data(struct mlx5_ib_dev *dev)
1640 {
1641         int err;
1642
1643         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
1644         if (err)
1645                 return err;
1646
1647         dev->mdev->rev_id = dev->mdev->pdev->revision;
1648
1649         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
1650 }
1651
1652 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1653                              char *buf)
1654 {
1655         struct mlx5_ib_dev *dev =
1656                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1657
1658         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
1659 }
1660
1661 static ssize_t show_reg_pages(struct device *device,
1662                               struct device_attribute *attr, char *buf)
1663 {
1664         struct mlx5_ib_dev *dev =
1665                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1666
1667         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
1668 }
1669
1670 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1671                         char *buf)
1672 {
1673         struct mlx5_ib_dev *dev =
1674                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1675         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
1676 }
1677
1678 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1679                            char *buf)
1680 {
1681         struct mlx5_ib_dev *dev =
1682                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1683         return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1684                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
1685 }
1686
1687 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1688                         char *buf)
1689 {
1690         struct mlx5_ib_dev *dev =
1691                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1692         return sprintf(buf, "%x\n", dev->mdev->rev_id);
1693 }
1694
1695 static ssize_t show_board(struct device *device, struct device_attribute *attr,
1696                           char *buf)
1697 {
1698         struct mlx5_ib_dev *dev =
1699                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1700         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
1701                        dev->mdev->board_id);
1702 }
1703
1704 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
1705 static DEVICE_ATTR(fw_ver,   S_IRUGO, show_fw_ver, NULL);
1706 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
1707 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
1708 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1709 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1710
1711 static struct device_attribute *mlx5_class_attributes[] = {
1712         &dev_attr_hw_rev,
1713         &dev_attr_fw_ver,
1714         &dev_attr_hca_type,
1715         &dev_attr_board_id,
1716         &dev_attr_fw_pages,
1717         &dev_attr_reg_pages,
1718 };
1719
1720 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
1721                           enum mlx5_dev_event event, unsigned long param)
1722 {
1723         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
1724         struct ib_event ibev;
1725
1726         u8 port = 0;
1727
1728         switch (event) {
1729         case MLX5_DEV_EVENT_SYS_ERROR:
1730                 ibdev->ib_active = false;
1731                 ibev.event = IB_EVENT_DEVICE_FATAL;
1732                 break;
1733
1734         case MLX5_DEV_EVENT_PORT_UP:
1735                 ibev.event = IB_EVENT_PORT_ACTIVE;
1736                 port = (u8)param;
1737                 break;
1738
1739         case MLX5_DEV_EVENT_PORT_DOWN:
1740                 ibev.event = IB_EVENT_PORT_ERR;
1741                 port = (u8)param;
1742                 break;
1743
1744         case MLX5_DEV_EVENT_PORT_INITIALIZED:
1745                 /* not used by ULPs */
1746                 return;
1747
1748         case MLX5_DEV_EVENT_LID_CHANGE:
1749                 ibev.event = IB_EVENT_LID_CHANGE;
1750                 port = (u8)param;
1751                 break;
1752
1753         case MLX5_DEV_EVENT_PKEY_CHANGE:
1754                 ibev.event = IB_EVENT_PKEY_CHANGE;
1755                 port = (u8)param;
1756                 break;
1757
1758         case MLX5_DEV_EVENT_GUID_CHANGE:
1759                 ibev.event = IB_EVENT_GID_CHANGE;
1760                 port = (u8)param;
1761                 break;
1762
1763         case MLX5_DEV_EVENT_CLIENT_REREG:
1764                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
1765                 port = (u8)param;
1766                 break;
1767         }
1768
1769         ibev.device           = &ibdev->ib_dev;
1770         ibev.element.port_num = port;
1771
1772         if (port < 1 || port > ibdev->num_ports) {
1773                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1774                 return;
1775         }
1776
1777         if (ibdev->ib_active)
1778                 ib_dispatch_event(&ibev);
1779 }
1780
1781 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1782 {
1783         int port;
1784
1785         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
1786                 mlx5_query_ext_port_caps(dev, port);
1787 }
1788
1789 static int get_port_caps(struct mlx5_ib_dev *dev)
1790 {
1791         struct ib_device_attr *dprops = NULL;
1792         struct ib_port_attr *pprops = NULL;
1793         int err = -ENOMEM;
1794         int port;
1795         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
1796
1797         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1798         if (!pprops)
1799                 goto out;
1800
1801         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1802         if (!dprops)
1803                 goto out;
1804
1805         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
1806         if (err) {
1807                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1808                 goto out;
1809         }
1810
1811         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
1812                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1813                 if (err) {
1814                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
1815                                      port, err);
1816                         break;
1817                 }
1818                 dev->mdev->port_caps[port - 1].pkey_table_len =
1819                                                 dprops->max_pkeys;
1820                 dev->mdev->port_caps[port - 1].gid_table_len =
1821                                                 pprops->gid_tbl_len;
1822                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1823                             dprops->max_pkeys, pprops->gid_tbl_len);
1824         }
1825
1826 out:
1827         kfree(pprops);
1828         kfree(dprops);
1829
1830         return err;
1831 }
1832
1833 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1834 {
1835         int err;
1836
1837         err = mlx5_mr_cache_cleanup(dev);
1838         if (err)
1839                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1840
1841         mlx5_ib_destroy_qp(dev->umrc.qp);
1842         ib_destroy_cq(dev->umrc.cq);
1843         ib_dealloc_pd(dev->umrc.pd);
1844 }
1845
1846 enum {
1847         MAX_UMR_WR = 128,
1848 };
1849
1850 static int create_umr_res(struct mlx5_ib_dev *dev)
1851 {
1852         struct ib_qp_init_attr *init_attr = NULL;
1853         struct ib_qp_attr *attr = NULL;
1854         struct ib_pd *pd;
1855         struct ib_cq *cq;
1856         struct ib_qp *qp;
1857         struct ib_cq_init_attr cq_attr = {};
1858         int ret;
1859
1860         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1861         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1862         if (!attr || !init_attr) {
1863                 ret = -ENOMEM;
1864                 goto error_0;
1865         }
1866
1867         pd = ib_alloc_pd(&dev->ib_dev);
1868         if (IS_ERR(pd)) {
1869                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1870                 ret = PTR_ERR(pd);
1871                 goto error_0;
1872         }
1873
1874         cq_attr.cqe = 128;
1875         cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1876                           &cq_attr);
1877         if (IS_ERR(cq)) {
1878                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1879                 ret = PTR_ERR(cq);
1880                 goto error_2;
1881         }
1882         ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1883
1884         init_attr->send_cq = cq;
1885         init_attr->recv_cq = cq;
1886         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1887         init_attr->cap.max_send_wr = MAX_UMR_WR;
1888         init_attr->cap.max_send_sge = 1;
1889         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1890         init_attr->port_num = 1;
1891         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1892         if (IS_ERR(qp)) {
1893                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1894                 ret = PTR_ERR(qp);
1895                 goto error_3;
1896         }
1897         qp->device     = &dev->ib_dev;
1898         qp->real_qp    = qp;
1899         qp->uobject    = NULL;
1900         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
1901
1902         attr->qp_state = IB_QPS_INIT;
1903         attr->port_num = 1;
1904         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1905                                 IB_QP_PORT, NULL);
1906         if (ret) {
1907                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1908                 goto error_4;
1909         }
1910
1911         memset(attr, 0, sizeof(*attr));
1912         attr->qp_state = IB_QPS_RTR;
1913         attr->path_mtu = IB_MTU_256;
1914
1915         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1916         if (ret) {
1917                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1918                 goto error_4;
1919         }
1920
1921         memset(attr, 0, sizeof(*attr));
1922         attr->qp_state = IB_QPS_RTS;
1923         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1924         if (ret) {
1925                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1926                 goto error_4;
1927         }
1928
1929         dev->umrc.qp = qp;
1930         dev->umrc.cq = cq;
1931         dev->umrc.pd = pd;
1932
1933         sema_init(&dev->umrc.sem, MAX_UMR_WR);
1934         ret = mlx5_mr_cache_init(dev);
1935         if (ret) {
1936                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1937                 goto error_4;
1938         }
1939
1940         kfree(attr);
1941         kfree(init_attr);
1942
1943         return 0;
1944
1945 error_4:
1946         mlx5_ib_destroy_qp(qp);
1947
1948 error_3:
1949         ib_destroy_cq(cq);
1950
1951 error_2:
1952         ib_dealloc_pd(pd);
1953
1954 error_0:
1955         kfree(attr);
1956         kfree(init_attr);
1957         return ret;
1958 }
1959
1960 static int create_dev_resources(struct mlx5_ib_resources *devr)
1961 {
1962         struct ib_srq_init_attr attr;
1963         struct mlx5_ib_dev *dev;
1964         struct ib_cq_init_attr cq_attr = {.cqe = 1};
1965         int ret = 0;
1966
1967         dev = container_of(devr, struct mlx5_ib_dev, devr);
1968
1969         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1970         if (IS_ERR(devr->p0)) {
1971                 ret = PTR_ERR(devr->p0);
1972                 goto error0;
1973         }
1974         devr->p0->device  = &dev->ib_dev;
1975         devr->p0->uobject = NULL;
1976         atomic_set(&devr->p0->usecnt, 0);
1977
1978         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
1979         if (IS_ERR(devr->c0)) {
1980                 ret = PTR_ERR(devr->c0);
1981                 goto error1;
1982         }
1983         devr->c0->device        = &dev->ib_dev;
1984         devr->c0->uobject       = NULL;
1985         devr->c0->comp_handler  = NULL;
1986         devr->c0->event_handler = NULL;
1987         devr->c0->cq_context    = NULL;
1988         atomic_set(&devr->c0->usecnt, 0);
1989
1990         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1991         if (IS_ERR(devr->x0)) {
1992                 ret = PTR_ERR(devr->x0);
1993                 goto error2;
1994         }
1995         devr->x0->device = &dev->ib_dev;
1996         devr->x0->inode = NULL;
1997         atomic_set(&devr->x0->usecnt, 0);
1998         mutex_init(&devr->x0->tgt_qp_mutex);
1999         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2000
2001         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2002         if (IS_ERR(devr->x1)) {
2003                 ret = PTR_ERR(devr->x1);
2004                 goto error3;
2005         }
2006         devr->x1->device = &dev->ib_dev;
2007         devr->x1->inode = NULL;
2008         atomic_set(&devr->x1->usecnt, 0);
2009         mutex_init(&devr->x1->tgt_qp_mutex);
2010         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2011
2012         memset(&attr, 0, sizeof(attr));
2013         attr.attr.max_sge = 1;
2014         attr.attr.max_wr = 1;
2015         attr.srq_type = IB_SRQT_XRC;
2016         attr.ext.xrc.cq = devr->c0;
2017         attr.ext.xrc.xrcd = devr->x0;
2018
2019         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2020         if (IS_ERR(devr->s0)) {
2021                 ret = PTR_ERR(devr->s0);
2022                 goto error4;
2023         }
2024         devr->s0->device        = &dev->ib_dev;
2025         devr->s0->pd            = devr->p0;
2026         devr->s0->uobject       = NULL;
2027         devr->s0->event_handler = NULL;
2028         devr->s0->srq_context   = NULL;
2029         devr->s0->srq_type      = IB_SRQT_XRC;
2030         devr->s0->ext.xrc.xrcd  = devr->x0;
2031         devr->s0->ext.xrc.cq    = devr->c0;
2032         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2033         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2034         atomic_inc(&devr->p0->usecnt);
2035         atomic_set(&devr->s0->usecnt, 0);
2036
2037         memset(&attr, 0, sizeof(attr));
2038         attr.attr.max_sge = 1;
2039         attr.attr.max_wr = 1;
2040         attr.srq_type = IB_SRQT_BASIC;
2041         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2042         if (IS_ERR(devr->s1)) {
2043                 ret = PTR_ERR(devr->s1);
2044                 goto error5;
2045         }
2046         devr->s1->device        = &dev->ib_dev;
2047         devr->s1->pd            = devr->p0;
2048         devr->s1->uobject       = NULL;
2049         devr->s1->event_handler = NULL;
2050         devr->s1->srq_context   = NULL;
2051         devr->s1->srq_type      = IB_SRQT_BASIC;
2052         devr->s1->ext.xrc.cq    = devr->c0;
2053         atomic_inc(&devr->p0->usecnt);
2054         atomic_set(&devr->s0->usecnt, 0);
2055
2056         return 0;
2057
2058 error5:
2059         mlx5_ib_destroy_srq(devr->s0);
2060 error4:
2061         mlx5_ib_dealloc_xrcd(devr->x1);
2062 error3:
2063         mlx5_ib_dealloc_xrcd(devr->x0);
2064 error2:
2065         mlx5_ib_destroy_cq(devr->c0);
2066 error1:
2067         mlx5_ib_dealloc_pd(devr->p0);
2068 error0:
2069         return ret;
2070 }
2071
2072 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2073 {
2074         mlx5_ib_destroy_srq(devr->s1);
2075         mlx5_ib_destroy_srq(devr->s0);
2076         mlx5_ib_dealloc_xrcd(devr->x0);
2077         mlx5_ib_dealloc_xrcd(devr->x1);
2078         mlx5_ib_destroy_cq(devr->c0);
2079         mlx5_ib_dealloc_pd(devr->p0);
2080 }
2081
2082 static u32 get_core_cap_flags(struct ib_device *ibdev)
2083 {
2084         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2085         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2086         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2087         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2088         u32 ret = 0;
2089
2090         if (ll == IB_LINK_LAYER_INFINIBAND)
2091                 return RDMA_CORE_PORT_IBA_IB;
2092
2093         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2094                 return 0;
2095
2096         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2097                 return 0;
2098
2099         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2100                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2101
2102         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2103                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2104
2105         return ret;
2106 }
2107
2108 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2109                                struct ib_port_immutable *immutable)
2110 {
2111         struct ib_port_attr attr;
2112         int err;
2113
2114         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2115         if (err)
2116                 return err;
2117
2118         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2119         immutable->gid_tbl_len = attr.gid_tbl_len;
2120         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2121         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2122
2123         return 0;
2124 }
2125
2126 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2127 {
2128         int err;
2129
2130         dev->roce.nb.notifier_call = mlx5_netdev_event;
2131         err = register_netdevice_notifier(&dev->roce.nb);
2132         if (err)
2133                 return err;
2134
2135         err = mlx5_nic_vport_enable_roce(dev->mdev);
2136         if (err)
2137                 goto err_unregister_netdevice_notifier;
2138
2139         return 0;
2140
2141 err_unregister_netdevice_notifier:
2142         unregister_netdevice_notifier(&dev->roce.nb);
2143         return err;
2144 }
2145
2146 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2147 {
2148         mlx5_nic_vport_disable_roce(dev->mdev);
2149         unregister_netdevice_notifier(&dev->roce.nb);
2150 }
2151
2152 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2153 {
2154         struct mlx5_ib_dev *dev;
2155         enum rdma_link_layer ll;
2156         int port_type_cap;
2157         int err;
2158         int i;
2159
2160         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2161         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2162
2163         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2164                 return NULL;
2165
2166         printk_once(KERN_INFO "%s", mlx5_version);
2167
2168         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2169         if (!dev)
2170                 return NULL;
2171
2172         dev->mdev = mdev;
2173
2174         rwlock_init(&dev->roce.netdev_lock);
2175         err = get_port_caps(dev);
2176         if (err)
2177                 goto err_dealloc;
2178
2179         if (mlx5_use_mad_ifc(dev))
2180                 get_ext_port_caps(dev);
2181
2182         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2183
2184         strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2185         dev->ib_dev.owner               = THIS_MODULE;
2186         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2187         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2188         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2189         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2190         dev->ib_dev.num_comp_vectors    =
2191                 dev->mdev->priv.eq_table.num_comp_vectors;
2192         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2193
2194         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2195         dev->ib_dev.uverbs_cmd_mask     =
2196                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2197                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2198                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2199                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2200                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2201                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2202                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2203                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2204                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2205                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2206                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2207                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2208                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2209                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2210                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2211                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2212                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2213                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2214                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2215                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2216                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2217                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2218                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2219         dev->ib_dev.uverbs_ex_cmd_mask =
2220                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2221                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
2222                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2223
2224         dev->ib_dev.query_device        = mlx5_ib_query_device;
2225         dev->ib_dev.query_port          = mlx5_ib_query_port;
2226         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
2227         if (ll == IB_LINK_LAYER_ETHERNET)
2228                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
2229         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
2230         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
2231         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
2232         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
2233         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
2234         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
2235         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
2236         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
2237         dev->ib_dev.mmap                = mlx5_ib_mmap;
2238         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
2239         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
2240         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
2241         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
2242         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
2243         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
2244         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
2245         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
2246         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
2247         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
2248         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
2249         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
2250         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
2251         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
2252         dev->ib_dev.post_send           = mlx5_ib_post_send;
2253         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
2254         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
2255         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
2256         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
2257         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
2258         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
2259         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
2260         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
2261         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
2262         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
2263         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
2264         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
2265         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
2266         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
2267         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
2268         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
2269         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
2270
2271         mlx5_ib_internal_fill_odp_caps(dev);
2272
2273         if (MLX5_CAP_GEN(mdev, xrc)) {
2274                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2275                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2276                 dev->ib_dev.uverbs_cmd_mask |=
2277                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2278                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2279         }
2280
2281         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
2282             IB_LINK_LAYER_ETHERNET) {
2283                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2284                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2285                 dev->ib_dev.uverbs_ex_cmd_mask |=
2286                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2287                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2288         }
2289         err = init_node_data(dev);
2290         if (err)
2291                 goto err_dealloc;
2292
2293         mutex_init(&dev->flow_db.lock);
2294         mutex_init(&dev->cap_mask_mutex);
2295
2296         if (ll == IB_LINK_LAYER_ETHERNET) {
2297                 err = mlx5_enable_roce(dev);
2298                 if (err)
2299                         goto err_dealloc;
2300         }
2301
2302         err = create_dev_resources(&dev->devr);
2303         if (err)
2304                 goto err_disable_roce;
2305
2306         err = mlx5_ib_odp_init_one(dev);
2307         if (err)
2308                 goto err_rsrc;
2309
2310         err = ib_register_device(&dev->ib_dev, NULL);
2311         if (err)
2312                 goto err_odp;
2313
2314         err = create_umr_res(dev);
2315         if (err)
2316                 goto err_dev;
2317
2318         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
2319                 err = device_create_file(&dev->ib_dev.dev,
2320                                          mlx5_class_attributes[i]);
2321                 if (err)
2322                         goto err_umrc;
2323         }
2324
2325         dev->ib_active = true;
2326
2327         return dev;
2328
2329 err_umrc:
2330         destroy_umrc_res(dev);
2331
2332 err_dev:
2333         ib_unregister_device(&dev->ib_dev);
2334
2335 err_odp:
2336         mlx5_ib_odp_remove_one(dev);
2337
2338 err_rsrc:
2339         destroy_dev_resources(&dev->devr);
2340
2341 err_disable_roce:
2342         if (ll == IB_LINK_LAYER_ETHERNET)
2343                 mlx5_disable_roce(dev);
2344
2345 err_dealloc:
2346         ib_dealloc_device((struct ib_device *)dev);
2347
2348         return NULL;
2349 }
2350
2351 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
2352 {
2353         struct mlx5_ib_dev *dev = context;
2354         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
2355
2356         ib_unregister_device(&dev->ib_dev);
2357         destroy_umrc_res(dev);
2358         mlx5_ib_odp_remove_one(dev);
2359         destroy_dev_resources(&dev->devr);
2360         if (ll == IB_LINK_LAYER_ETHERNET)
2361                 mlx5_disable_roce(dev);
2362         ib_dealloc_device(&dev->ib_dev);
2363 }
2364
2365 static struct mlx5_interface mlx5_ib_interface = {
2366         .add            = mlx5_ib_add,
2367         .remove         = mlx5_ib_remove,
2368         .event          = mlx5_ib_event,
2369         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
2370 };
2371
2372 static int __init mlx5_ib_init(void)
2373 {
2374         int err;
2375
2376         if (deprecated_prof_sel != 2)
2377                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2378
2379         err = mlx5_ib_odp_init();
2380         if (err)
2381                 return err;
2382
2383         err = mlx5_register_interface(&mlx5_ib_interface);
2384         if (err)
2385                 goto clean_odp;
2386
2387         return err;
2388
2389 clean_odp:
2390         mlx5_ib_odp_cleanup();
2391         return err;
2392 }
2393
2394 static void __exit mlx5_ib_cleanup(void)
2395 {
2396         mlx5_unregister_interface(&mlx5_ib_interface);
2397         mlx5_ib_odp_cleanup();
2398 }
2399
2400 module_init(mlx5_ib_init);
2401 module_exit(mlx5_ib_cleanup);