drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include <drm/drm_vblank.h>
  27 #include <drm/drm_atomic_helper.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm_psr.h"
  32 #include "amdgpu_dm_replay.h"
  33 #include "amdgpu_dm_crtc.h"
  34 #include "amdgpu_dm_plane.h"
  35 #include "amdgpu_dm_trace.h"
  36 #include "amdgpu_dm_debugfs.h"
  37
  38 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
  39 {
  40         struct drm_crtc *crtc = &acrtc->base;
  41         struct drm_device *dev = crtc->dev;
  42         unsigned long flags;
  43
  44         drm_crtc_handle_vblank(crtc);
  45
  46         spin_lock_irqsave(&dev->event_lock, flags);
  47
  48         /* Send completion event for cursor-only commits */
  49         if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
  50                 drm_crtc_send_vblank_event(crtc, acrtc->event);
  51                 drm_crtc_vblank_put(crtc);
  52                 acrtc->event = NULL;
  53         }
  54
  55         spin_unlock_irqrestore(&dev->event_lock, flags);
  56 }
  57
  58 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
  59                              struct dc_stream_state *new_stream,
  60                              struct dc_stream_state *old_stream)
  61 {
  62         return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
  63 }
  64
  65 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
  66
  67 {
  68         return acrtc->dm_irq_params.freesync_config.state ==
  69                        VRR_STATE_ACTIVE_VARIABLE ||
  70                acrtc->dm_irq_params.freesync_config.state ==
  71                        VRR_STATE_ACTIVE_FIXED;
  72 }
  73
  74 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
  75 {
  76         enum dc_irq_source irq_source;
  77         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  78         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
  79         int rc;
  80
  81         if (acrtc->otg_inst == -1)
  82                 return 0;
  83
  84         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
  85
  86         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
  87
  88         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
  89                       acrtc->crtc_id, enable ? "en" : "dis", rc);
  90         return rc;
  91 }
  92
  93 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
  94 {
  95         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
  96                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
  97 }
  98
  99 /**
 100  * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
 101  *
 102  * @vblank_work:    is a pointer to a struct vblank_control_work object.
 103  * @vblank_enabled: indicates whether the DRM vblank counter is currently
 104  *                  enabled (true) or disabled (false).
 105  * @allow_sr_entry: represents whether entry into the self-refresh mode is
 106  *                  allowed (true) or not allowed (false).
 107  *
 108  * The DRM vblank counter enable/disable action is used as the trigger to enable
 109  * or disable various panel self-refresh features:
 110  *
 111  * Panel Replay and PSR SU
 112  * - Enable when:
 113  *      - vblank counter is disabled
 114  *      - entry is allowed: usermode demonstrates an adequate number of fast
 115  *        commits)
 116  *     - CRC capture window isn't active
 117  * - Keep enabled even when vblank counter gets enabled
 118  *
 119  * PSR1
 120  * - Enable condition same as above
 121  * - Disable when vblank counter is enabled
 122  */
 123 static void amdgpu_dm_crtc_set_panel_sr_feature(
 124         struct vblank_control_work *vblank_work,
 125         bool vblank_enabled, bool allow_sr_entry)
 126 {
 127         struct dc_link *link = vblank_work->stream->link;
 128         bool is_sr_active = (link->replay_settings.replay_allow_active ||
 129                                  link->psr_settings.psr_allow_active);
 130         bool is_crc_window_active = false;
 131
 132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 133         is_crc_window_active =
 134                 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
 135 #endif
 136
 137         if (link->replay_settings.replay_feature_enabled &&
 138                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
 139                 amdgpu_dm_replay_enable(vblank_work->stream, true);
 140         } else if (vblank_enabled) {
 141                 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
 142                         amdgpu_dm_psr_disable(vblank_work->stream);
 143         } else if (link->psr_settings.psr_feature_enabled &&
 144                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
 145
 146                 struct amdgpu_dm_connector *aconn =
 147                         (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
 148
 149                 if (!aconn->disallow_edp_enter_psr)
 150                         amdgpu_dm_psr_enable(vblank_work->stream);
 151         }
 152 }
 153
 154 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 155 {
 156         struct vblank_control_work *vblank_work =
 157                 container_of(work, struct vblank_control_work, work);
 158         struct amdgpu_display_manager *dm = vblank_work->dm;
 159
 160         mutex_lock(&dm->dc_lock);
 161
 162         if (vblank_work->enable)
 163                 dm->active_vblank_irq_count++;
 164         else if (dm->active_vblank_irq_count)
 165                 dm->active_vblank_irq_count--;
 166
 167         dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
 168
 169         DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
 170
 171         /*
 172          * Control PSR based on vblank requirements from OS
 173          *
 174          * If panel supports PSR SU, there's no need to disable PSR when OS is
 175          * submitting fast atomic commits (we infer this by whether the OS
 176          * requests vblank events). Fast atomic commits will simply trigger a
 177          * full-frame-update (FFU); a specific case of selective-update (SU)
 178          * where the SU region is the full hactive*vactive region. See
 179          * fill_dc_dirty_rects().
 180          */
 181         if (vblank_work->stream && vblank_work->stream->link) {
 182                 amdgpu_dm_crtc_set_panel_sr_feature(
 183                         vblank_work, vblank_work->enable,
 184                         vblank_work->acrtc->dm_irq_params.allow_psr_entry ||
 185                         vblank_work->stream->link->replay_settings.replay_feature_enabled);
 186         }
 187
 188         mutex_unlock(&dm->dc_lock);
 189
 190         dc_stream_release(vblank_work->stream);
 191
 192         kfree(vblank_work);
 193 }
 194
 195 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
 196 {
 197         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 198         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 199         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
 200         struct amdgpu_display_manager *dm = &adev->dm;
 201         struct vblank_control_work *work;
 202         int rc = 0;
 203
 204         if (acrtc->otg_inst == -1)
 205                 goto skip;
 206
 207         if (enable) {
 208                 /* vblank irq on -> Only need vupdate irq in vrr mode */
 209                 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
 210                         rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
 211         } else {
 212                 /* vblank irq off -> vupdate irq off */
 213                 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
 214         }
 215
 216         if (rc)
 217                 return rc;
 218
 219         rc = (enable)
 220                 ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)
 221                 : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);
 222
 223         if (rc)
 224                 return rc;
 225
 226 skip:
 227         if (amdgpu_in_reset(adev))
 228                 return 0;
 229
 230         if (dm->vblank_control_workqueue) {
 231                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 232                 if (!work)
 233                         return -ENOMEM;
 234
 235                 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
 236                 work->dm = dm;
 237                 work->acrtc = acrtc;
 238                 work->enable = enable;
 239
 240                 if (acrtc_state->stream) {
 241                         dc_stream_retain(acrtc_state->stream);
 242                         work->stream = acrtc_state->stream;
 243                 }
 244
 245                 queue_work(dm->vblank_control_workqueue, &work->work);
 246         }
 247
 248         return 0;
 249 }
 250
 251 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
 252 {
 253         return amdgpu_dm_crtc_set_vblank(crtc, true);
 254 }
 255
 256 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
 257 {
 258         amdgpu_dm_crtc_set_vblank(crtc, false);
 259 }
 260
 261 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
 262                                   struct drm_crtc_state *state)
 263 {
 264         struct dm_crtc_state *cur = to_dm_crtc_state(state);
 265
 266         /* TODO Destroy dc_stream objects are stream object is flattened */
 267         if (cur->stream)
 268                 dc_stream_release(cur->stream);
 269
 270
 271         __drm_atomic_helper_crtc_destroy_state(state);
 272
 273
 274         kfree(state);
 275 }
 276
 277 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
 278 {
 279         struct dm_crtc_state *state, *cur;
 280
 281         cur = to_dm_crtc_state(crtc->state);
 282
 283         if (WARN_ON(!crtc->state))
 284                 return NULL;
 285
 286         state = kzalloc(sizeof(*state), GFP_KERNEL);
 287         if (!state)
 288                 return NULL;
 289
 290         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 291
 292         if (cur->stream) {
 293                 state->stream = cur->stream;
 294                 dc_stream_retain(state->stream);
 295         }
 296
 297         state->active_planes = cur->active_planes;
 298         state->vrr_infopacket = cur->vrr_infopacket;
 299         state->abm_level = cur->abm_level;
 300         state->vrr_supported = cur->vrr_supported;
 301         state->freesync_config = cur->freesync_config;
 302         state->cm_has_degamma = cur->cm_has_degamma;
 303         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 304         state->regamma_tf = cur->regamma_tf;
 305         state->crc_skip_count = cur->crc_skip_count;
 306         state->mpo_requested = cur->mpo_requested;
 307         /* TODO Duplicate dc_stream after objects are stream object is flattened */
 308
 309         return &state->base;
 310 }
 311
 312 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
 313 {
 314         drm_crtc_cleanup(crtc);
 315         kfree(crtc);
 316 }
 317
 318 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
 319 {
 320         struct dm_crtc_state *state;
 321
 322         if (crtc->state)
 323                 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
 324
 325         state = kzalloc(sizeof(*state), GFP_KERNEL);
 326         if (WARN_ON(!state))
 327                 return;
 328
 329         __drm_atomic_helper_crtc_reset(crtc, &state->base);
 330 }
 331
 332 #ifdef CONFIG_DEBUG_FS
 333 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
 334 {
 335         crtc_debugfs_init(crtc);
 336
 337         return 0;
 338 }
 339 #endif
 340
 341 #ifdef AMD_PRIVATE_COLOR
 342 /**
 343  * dm_crtc_additional_color_mgmt - enable additional color properties
 344  * @crtc: DRM CRTC
 345  *
 346  * This function lets the driver enable post-blending CRTC regamma transfer
 347  * function property in addition to DRM CRTC gamma LUT. Default value means
 348  * linear transfer function, which is the default CRTC gamma LUT behaviour
 349  * without this property.
 350  */
 351 static void
 352 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
 353 {
 354         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 355
 356         if (adev->dm.dc->caps.color.mpc.ogam_ram)
 357                 drm_object_attach_property(&crtc->base,
 358                                            adev->mode_info.regamma_tf_property,
 359                                            AMDGPU_TRANSFER_FUNCTION_DEFAULT);
 360 }
 361
 362 static int
 363 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
 364                                    struct drm_crtc_state *state,
 365                                    struct drm_property *property,
 366                                    uint64_t val)
 367 {
 368         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 369         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
 370
 371         if (property == adev->mode_info.regamma_tf_property) {
 372                 if (acrtc_state->regamma_tf != val) {
 373                         acrtc_state->regamma_tf = val;
 374                         acrtc_state->base.color_mgmt_changed |= 1;
 375                 }
 376         } else {
 377                 drm_dbg_atomic(crtc->dev,
 378                                "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
 379                                crtc->base.id, crtc->name,
 380                                property->base.id, property->name);
 381                 return -EINVAL;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int
 388 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
 389                                    const struct drm_crtc_state *state,
 390                                    struct drm_property *property,
 391                                    uint64_t *val)
 392 {
 393         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 394         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
 395
 396         if (property == adev->mode_info.regamma_tf_property)
 397                 *val = acrtc_state->regamma_tf;
 398         else
 399                 return -EINVAL;
 400
 401         return 0;
 402 }
 403 #endif
 404
 405 /* Implemented only the options currently available for the driver */
 406 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 407         .reset = amdgpu_dm_crtc_reset_state,
 408         .destroy = amdgpu_dm_crtc_destroy,
 409         .set_config = drm_atomic_helper_set_config,
 410         .page_flip = drm_atomic_helper_page_flip,
 411         .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
 412         .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
 413         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
 414         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
 415         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
 416         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
 417         .enable_vblank = amdgpu_dm_crtc_enable_vblank,
 418         .disable_vblank = amdgpu_dm_crtc_disable_vblank,
 419         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 420 #if defined(CONFIG_DEBUG_FS)
 421         .late_register = amdgpu_dm_crtc_late_register,
 422 #endif
 423 #ifdef AMD_PRIVATE_COLOR
 424         .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
 425         .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
 426 #endif
 427 };
 428
 429 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
 430 {
 431 }
 432
 433 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
 434 {
 435         struct drm_atomic_state *state = new_crtc_state->state;
 436         struct drm_plane *plane;
 437         int num_active = 0;
 438
 439         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
 440                 struct drm_plane_state *new_plane_state;
 441
 442                 /* Cursor planes are "fake". */
 443                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 444                         continue;
 445
 446                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
 447
 448                 if (!new_plane_state) {
 449                         /*
 450                          * The plane is enable on the CRTC and hasn't changed
 451                          * state. This means that it previously passed
 452                          * validation and is therefore enabled.
 453                          */
 454                         num_active += 1;
 455                         continue;
 456                 }
 457
 458                 /* We need a framebuffer to be considered enabled. */
 459                 num_active += (new_plane_state->fb != NULL);
 460         }
 461
 462         return num_active;
 463 }
 464
 465 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
 466                                                      struct drm_crtc_state *new_crtc_state)
 467 {
 468         struct dm_crtc_state *dm_new_crtc_state =
 469                 to_dm_crtc_state(new_crtc_state);
 470
 471         dm_new_crtc_state->active_planes = 0;
 472
 473         if (!dm_new_crtc_state->stream)
 474                 return;
 475
 476         dm_new_crtc_state->active_planes =
 477                 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
 478 }
 479
 480 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
 481                                       const struct drm_display_mode *mode,
 482                                       struct drm_display_mode *adjusted_mode)
 483 {
 484         return true;
 485 }
 486
 487 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 488                                               struct drm_atomic_state *state)
 489 {
 490         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 491                                                                                 crtc);
 492         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 493         struct dc *dc = adev->dm.dc;
 494         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 495         int ret = -EINVAL;
 496
 497         trace_amdgpu_dm_crtc_atomic_check(crtc_state);
 498
 499         amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
 500
 501         if (WARN_ON(unlikely(!dm_crtc_state->stream &&
 502                         amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
 503                 return ret;
 504         }
 505
 506         /*
 507          * We require the primary plane to be enabled whenever the CRTC is, otherwise
 508          * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
 509          * planes are disabled, which is not supported by the hardware. And there is legacy
 510          * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
 511          */
 512         if (crtc_state->enable &&
 513                 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
 514                 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
 515                 return -EINVAL;
 516         }
 517
 518         /*
 519          * Only allow async flips for fast updates that don't change the FB
 520          * pitch, the DCC state, rotation, etc.
 521          */
 522         if (crtc_state->async_flip &&
 523             dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
 524                 drm_dbg_atomic(crtc->dev,
 525                                "[CRTC:%d:%s] async flips are only supported for fast updates\n",
 526                                crtc->base.id, crtc->name);
 527                 return -EINVAL;
 528         }
 529
 530         /* In some use cases, like reset, no stream is attached */
 531         if (!dm_crtc_state->stream)
 532                 return 0;
 533
 534         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
 535                 return 0;
 536
 537         DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
 538         return ret;
 539 }
 540
 541 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
 542         .disable = amdgpu_dm_crtc_helper_disable,
 543         .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
 544         .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
 545         .get_scanout_position = amdgpu_crtc_get_scanout_position,
 546 };
 547
 548 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 549                                struct drm_plane *plane,
 550                                uint32_t crtc_index)
 551 {
 552         struct amdgpu_crtc *acrtc = NULL;
 553         struct drm_plane *cursor_plane;
 554         bool is_dcn;
 555         int res = -ENOMEM;
 556
 557         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
 558         if (!cursor_plane)
 559                 goto fail;
 560
 561         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
 562         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
 563
 564         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
 565         if (!acrtc)
 566                 goto fail;
 567
 568         res = drm_crtc_init_with_planes(
 569                         dm->ddev,
 570                         &acrtc->base,
 571                         plane,
 572                         cursor_plane,
 573                         &amdgpu_dm_crtc_funcs, NULL);
 574
 575         if (res)
 576                 goto fail;
 577
 578         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
 579
 580         /* Create (reset) the plane state */
 581         if (acrtc->base.funcs->reset)
 582                 acrtc->base.funcs->reset(&acrtc->base);
 583
 584         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
 585         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
 586
 587         acrtc->crtc_id = crtc_index;
 588         acrtc->base.enabled = false;
 589         acrtc->otg_inst = -1;
 590
 591         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
 592
 593         /* Don't enable DRM CRTC degamma property for DCE since it doesn't
 594          * support programmable degamma anywhere.
 595          */
 596         is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
 597         drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
 598                                    true, MAX_COLOR_LUT_ENTRIES);
 599
 600         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
 601
 602 #ifdef AMD_PRIVATE_COLOR
 603         dm_crtc_additional_color_mgmt(&acrtc->base);
 604 #endif
 605         return 0;
 606
 607 fail:
 608         kfree(acrtc);
 609         kfree(cursor_plane);
 610         return res;
 611 }
 612