drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/drm_crtc.h>
  27 #include <drm/drm_vblank.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "dc.h"
  32 #include "amdgpu_securedisplay.h"
  33
  34 static const char *const pipe_crc_sources[] = {
  35         "none",
  36         "crtc",
  37         "crtc dither",
  38         "dprx",
  39         "dprx dither",
  40         "auto",
  41 };
  42
  43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
  44 {
  45         if (!source || !strcmp(source, "none"))
  46                 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
  47         if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
  48                 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
  49         if (!strcmp(source, "dprx"))
  50                 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
  51         if (!strcmp(source, "crtc dither"))
  52                 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
  53         if (!strcmp(source, "dprx dither"))
  54                 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
  55
  56         return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
  57 }
  58
  59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
  60 {
  61         return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
  62                (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
  63 }
  64
  65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
  66 {
  67         return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
  68                (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
  69 }
  70
  71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
  72 {
  73         return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
  74                (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
  75                (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
  76 }
  77
  78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
  79                                                   size_t *count)
  80 {
  81         *count = ARRAY_SIZE(pipe_crc_sources);
  82         return pipe_crc_sources;
  83 }
  84
  85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream)
  87 {
  88         struct drm_device *drm_dev = crtc->dev;
  89         struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm;
  90         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  91         bool was_activated;
  92
  93         spin_lock_irq(&drm_dev->event_lock);
  94         was_activated = acrtc->dm_irq_params.window_param.activated;
  95         acrtc->dm_irq_params.window_param.x_start = 0;
  96         acrtc->dm_irq_params.window_param.y_start = 0;
  97         acrtc->dm_irq_params.window_param.x_end = 0;
  98         acrtc->dm_irq_params.window_param.y_end = 0;
  99         acrtc->dm_irq_params.window_param.activated = false;
 100         acrtc->dm_irq_params.window_param.update_win = false;
 101         acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
 102         spin_unlock_irq(&drm_dev->event_lock);
 103
 104         /* Disable secure_display if it was enabled */
 105         if (was_activated) {
 106                 /* stop ROI update on this crtc */
 107                 flush_work(&dm->secure_display_ctxs[crtc->index].notify_ta_work);
 108                 flush_work(&dm->secure_display_ctxs[crtc->index].forward_roi_work);
 109                 dc_stream_forward_crc_window(stream, NULL, true);
 110         }
 111 }
 112
 113 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
 114 {
 115         struct secure_display_context *secure_display_ctx;
 116         struct psp_context *psp;
 117         struct ta_securedisplay_cmd *securedisplay_cmd;
 118         struct drm_crtc *crtc;
 119         struct dc_stream_state *stream;
 120         uint8_t phy_inst;
 121         int ret;
 122
 123         secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work);
 124         crtc = secure_display_ctx->crtc;
 125
 126         if (!crtc)
 127                 return;
 128
 129         psp = &drm_to_adev(crtc->dev)->psp;
 130
 131         if (!psp->securedisplay_context.context.initialized) {
 132                 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n");
 133                 return;
 134         }
 135
 136         stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
 137         phy_inst = stream->link->link_enc_hw_inst;
 138
 139         /* need lock for multiple crtcs to use the command buffer */
 140         mutex_lock(&psp->securedisplay_context.mutex);
 141
 142         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
 143                                                 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
 144
 145         securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst;
 146
 147         /* PSP TA is expected to finish data transmission over I2C within current frame,
 148          * even there are up to 4 crtcs request to send in this frame.
 149          */
 150         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
 151
 152         if (!ret) {
 153                 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS)
 154                         psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
 155         }
 156
 157         mutex_unlock(&psp->securedisplay_context.mutex);
 158 }
 159
 160 static void
 161 amdgpu_dm_forward_crc_window(struct work_struct *work)
 162 {
 163         struct secure_display_context *secure_display_ctx;
 164         struct amdgpu_display_manager *dm;
 165         struct drm_crtc *crtc;
 166         struct dc_stream_state *stream;
 167
 168         secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work);
 169         crtc = secure_display_ctx->crtc;
 170
 171         if (!crtc)
 172                 return;
 173
 174         dm = &drm_to_adev(crtc->dev)->dm;
 175         stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
 176
 177         mutex_lock(&dm->dc_lock);
 178         dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false);
 179         mutex_unlock(&dm->dc_lock);
 180 }
 181
 182 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
 183 {
 184         struct drm_device *drm_dev = crtc->dev;
 185         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 186         bool ret = false;
 187
 188         spin_lock_irq(&drm_dev->event_lock);
 189         ret = acrtc->dm_irq_params.window_param.activated;
 190         spin_unlock_irq(&drm_dev->event_lock);
 191
 192         return ret;
 193 }
 194 #endif
 195
 196 int
 197 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
 198                                  size_t *values_cnt)
 199 {
 200         enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
 201
 202         if (source < 0) {
 203                 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
 204                                  src_name, crtc->index);
 205                 return -EINVAL;
 206         }
 207
 208         *values_cnt = 3;
 209         return 0;
 210 }
 211
 212 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 213                                         struct dm_crtc_state *dm_crtc_state,
 214                                         enum amdgpu_dm_pipe_crc_source source)
 215 {
 216         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 217         struct dc_stream_state *stream_state = dm_crtc_state->stream;
 218         bool enable = amdgpu_dm_is_valid_crc_source(source);
 219         int ret = 0;
 220
 221         /* Configuration will be deferred to stream enable. */
 222         if (!stream_state)
 223                 return -EINVAL;
 224
 225         mutex_lock(&adev->dm.dc_lock);
 226
 227         /* Enable or disable CRTC CRC generation */
 228         if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
 229                 if (!dc_stream_configure_crc(stream_state->ctx->dc,
 230                                              stream_state, NULL, enable, enable)) {
 231                         ret = -EINVAL;
 232                         goto unlock;
 233                 }
 234         }
 235
 236         /* Configure dithering */
 237         if (!dm_need_crc_dither(source)) {
 238                 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
 239                 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
 240                                             DYN_EXPANSION_DISABLE);
 241         } else {
 242                 dc_stream_set_dither_option(stream_state,
 243                                             DITHER_OPTION_DEFAULT);
 244                 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
 245                                             DYN_EXPANSION_AUTO);
 246         }
 247
 248 unlock:
 249         mutex_unlock(&adev->dm.dc_lock);
 250
 251         return ret;
 252 }
 253
 254 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 255 {
 256         enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
 257         enum amdgpu_dm_pipe_crc_source cur_crc_src;
 258         struct drm_crtc_commit *commit;
 259         struct dm_crtc_state *crtc_state;
 260         struct drm_device *drm_dev = crtc->dev;
 261         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 262         struct drm_dp_aux *aux = NULL;
 263         bool enable = false;
 264         bool enabled = false;
 265         int ret = 0;
 266
 267         if (source < 0) {
 268                 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
 269                                  src_name, crtc->index);
 270                 return -EINVAL;
 271         }
 272
 273         ret = drm_modeset_lock(&crtc->mutex, NULL);
 274         if (ret)
 275                 return ret;
 276
 277         spin_lock(&crtc->commit_lock);
 278         commit = list_first_entry_or_null(&crtc->commit_list,
 279                                           struct drm_crtc_commit, commit_entry);
 280         if (commit)
 281                 drm_crtc_commit_get(commit);
 282         spin_unlock(&crtc->commit_lock);
 283
 284         if (commit) {
 285                 /*
 286                  * Need to wait for all outstanding programming to complete
 287                  * in commit tail since it can modify CRC related fields and
 288                  * hardware state. Since we're holding the CRTC lock we're
 289                  * guaranteed that no other commit work can be queued off
 290                  * before we modify the state below.
 291                  */
 292                 ret = wait_for_completion_interruptible_timeout(
 293                         &commit->hw_done, 10 * HZ);
 294                 if (ret)
 295                         goto cleanup;
 296         }
 297
 298         enable = amdgpu_dm_is_valid_crc_source(source);
 299         crtc_state = to_dm_crtc_state(crtc->state);
 300         spin_lock_irq(&drm_dev->event_lock);
 301         cur_crc_src = acrtc->dm_irq_params.crc_src;
 302         spin_unlock_irq(&drm_dev->event_lock);
 303
 304         /*
 305          * USER REQ SRC | CURRENT SRC | BEHAVIOR
 306          * -----------------------------
 307          * None         | None        | Do nothing
 308          * None         | CRTC        | Disable CRTC CRC, set default to dither
 309          * None         | DPRX        | Disable DPRX CRC, need 'aux', set default to dither
 310          * None         | CRTC DITHER | Disable CRTC CRC
 311          * None         | DPRX DITHER | Disable DPRX CRC, need 'aux'
 312          * CRTC         | XXXX        | Enable CRTC CRC, no dither
 313          * DPRX         | XXXX        | Enable DPRX CRC, need 'aux', no dither
 314          * CRTC DITHER  | XXXX        | Enable CRTC CRC, set dither
 315          * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
 316          */
 317         if (dm_is_crc_source_dprx(source) ||
 318             (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
 319              dm_is_crc_source_dprx(cur_crc_src))) {
 320                 struct amdgpu_dm_connector *aconn = NULL;
 321                 struct drm_connector *connector;
 322                 struct drm_connector_list_iter conn_iter;
 323
 324                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 325                 drm_for_each_connector_iter(connector, &conn_iter) {
 326                         if (!connector->state || connector->state->crtc != crtc)
 327                                 continue;
 328
 329                         if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 330                                 continue;
 331
 332                         aconn = to_amdgpu_dm_connector(connector);
 333                         break;
 334                 }
 335                 drm_connector_list_iter_end(&conn_iter);
 336
 337                 if (!aconn) {
 338                         DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
 339                         ret = -EINVAL;
 340                         goto cleanup;
 341                 }
 342
 343                 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux;
 344
 345                 if (!aux) {
 346                         DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
 347                         ret = -EINVAL;
 348                         goto cleanup;
 349                 }
 350
 351                 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
 352                                 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) {
 353                         DRM_DEBUG_DRIVER("No DP connector available for CRC source\n");
 354                         ret = -EINVAL;
 355                         goto cleanup;
 356                 }
 357
 358         }
 359
 360 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 361         /* Reset secure_display when we change crc source from debugfs */
 362         amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
 363 #endif
 364
 365         if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
 366                 ret = -EINVAL;
 367                 goto cleanup;
 368         }
 369
 370         /*
 371          * Reading the CRC requires the vblank interrupt handler to be
 372          * enabled. Keep a reference until CRC capture stops.
 373          */
 374         enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
 375         if (!enabled && enable) {
 376                 ret = drm_crtc_vblank_get(crtc);
 377                 if (ret)
 378                         goto cleanup;
 379
 380                 if (dm_is_crc_source_dprx(source)) {
 381                         if (drm_dp_start_crc(aux, crtc)) {
 382                                 DRM_DEBUG_DRIVER("dp start crc failed\n");
 383                                 ret = -EINVAL;
 384                                 goto cleanup;
 385                         }
 386                 }
 387         } else if (enabled && !enable) {
 388                 drm_crtc_vblank_put(crtc);
 389                 if (dm_is_crc_source_dprx(source)) {
 390                         if (drm_dp_stop_crc(aux)) {
 391                                 DRM_DEBUG_DRIVER("dp stop crc failed\n");
 392                                 ret = -EINVAL;
 393                                 goto cleanup;
 394                         }
 395                 }
 396         }
 397
 398         spin_lock_irq(&drm_dev->event_lock);
 399         acrtc->dm_irq_params.crc_src = source;
 400         spin_unlock_irq(&drm_dev->event_lock);
 401
 402         /* Reset crc_skipped on dm state */
 403         crtc_state->crc_skip_count = 0;
 404
 405 cleanup:
 406         if (commit)
 407                 drm_crtc_commit_put(commit);
 408
 409         drm_modeset_unlock(&crtc->mutex);
 410
 411         return ret;
 412 }
 413
 414 /**
 415  * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
 416  * @crtc: DRM CRTC object.
 417  *
 418  * This function should be called at the end of a vblank, when the fb has been
 419  * fully processed through the pipe.
 420  */
 421 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
 422 {
 423         struct dm_crtc_state *crtc_state;
 424         struct dc_stream_state *stream_state;
 425         struct drm_device *drm_dev = NULL;
 426         enum amdgpu_dm_pipe_crc_source cur_crc_src;
 427         struct amdgpu_crtc *acrtc = NULL;
 428         uint32_t crcs[3];
 429         unsigned long flags;
 430
 431         if (crtc == NULL)
 432                 return;
 433
 434         crtc_state = to_dm_crtc_state(crtc->state);
 435         stream_state = crtc_state->stream;
 436         acrtc = to_amdgpu_crtc(crtc);
 437         drm_dev = crtc->dev;
 438
 439         spin_lock_irqsave(&drm_dev->event_lock, flags);
 440         cur_crc_src = acrtc->dm_irq_params.crc_src;
 441         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 442
 443         /* Early return if CRC capture is not enabled. */
 444         if (!amdgpu_dm_is_valid_crc_source(cur_crc_src))
 445                 return;
 446
 447         /*
 448          * Since flipping and crc enablement happen asynchronously, we - more
 449          * often than not - will be returning an 'uncooked' crc on first frame.
 450          * Probably because hw isn't ready yet. For added security, skip the
 451          * first two CRC values.
 452          */
 453         if (crtc_state->crc_skip_count < 2) {
 454                 crtc_state->crc_skip_count += 1;
 455                 return;
 456         }
 457
 458         if (dm_is_crc_source_crtc(cur_crc_src)) {
 459                 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
 460                                        &crcs[0], &crcs[1], &crcs[2]))
 461                         return;
 462
 463                 drm_crtc_add_crc_entry(crtc, true,
 464                                        drm_crtc_accurate_vblank_count(crtc), crcs);
 465         }
 466 }
 467
 468 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 469 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
 470 {
 471         struct drm_device *drm_dev = NULL;
 472         enum amdgpu_dm_pipe_crc_source cur_crc_src;
 473         struct amdgpu_crtc *acrtc = NULL;
 474         struct amdgpu_device *adev = NULL;
 475         struct secure_display_context *secure_display_ctx = NULL;
 476         unsigned long flags1;
 477
 478         if (crtc == NULL)
 479                 return;
 480
 481         acrtc = to_amdgpu_crtc(crtc);
 482         adev = drm_to_adev(crtc->dev);
 483         drm_dev = crtc->dev;
 484
 485         spin_lock_irqsave(&drm_dev->event_lock, flags1);
 486         cur_crc_src = acrtc->dm_irq_params.crc_src;
 487
 488         /* Early return if CRC capture is not enabled. */
 489         if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) ||
 490                 !dm_is_crc_source_crtc(cur_crc_src))
 491                 goto cleanup;
 492
 493         if (!acrtc->dm_irq_params.window_param.activated)
 494                 goto cleanup;
 495
 496         if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
 497                 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
 498                 goto cleanup;
 499         }
 500
 501         secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id];
 502         if (WARN_ON(secure_display_ctx->crtc != crtc)) {
 503                 /* We have set the crtc when creating secure_display_context,
 504                  * don't expect it to be changed here.
 505                  */
 506                 secure_display_ctx->crtc = crtc;
 507         }
 508
 509         if (acrtc->dm_irq_params.window_param.update_win) {
 510                 /* prepare work for dmub to update ROI */
 511                 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start;
 512                 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start;
 513                 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end -
 514                                                                 acrtc->dm_irq_params.window_param.x_start;
 515                 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end -
 516                                                                 acrtc->dm_irq_params.window_param.y_start;
 517                 schedule_work(&secure_display_ctx->forward_roi_work);
 518
 519                 acrtc->dm_irq_params.window_param.update_win = false;
 520
 521                 /* Statically skip 1 frame, because we may need to wait below things
 522                  * before sending ROI to dmub:
 523                  * 1. We defer the work by using system workqueue.
 524                  * 2. We may need to wait for dc_lock before accessing dmub.
 525                  */
 526                 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;
 527
 528         } else {
 529                 /* prepare work for psp to read ROI/CRC and send to I2C */
 530                 schedule_work(&secure_display_ctx->notify_ta_work);
 531         }
 532
 533 cleanup:
 534         spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
 535 }
 536
 537 struct secure_display_context *
 538 amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
 539 {
 540         struct secure_display_context *secure_display_ctxs = NULL;
 541         int i;
 542
 543         secure_display_ctxs = kcalloc(adev->mode_info.num_crtc,
 544                                       sizeof(struct secure_display_context),
 545                                       GFP_KERNEL);
 546
 547         if (!secure_display_ctxs)
 548                 return NULL;
 549
 550         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 551                 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window);
 552                 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
 553                 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base;
 554         }
 555
 556         return secure_display_ctxs;
 557 }
 558 #endif