drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_uvd.h"
  31 #include "vid.h"
  32 #include "uvd/uvd_5_0_d.h"
  33 #include "uvd/uvd_5_0_sh_mask.h"
  34 #include "oss/oss_2_0_d.h"
  35 #include "oss/oss_2_0_sh_mask.h"
  36 #include "bif/bif_5_0_d.h"
  37 #include "vi.h"
  38 #include "smu/smu_7_1_2_d.h"
  39 #include "smu/smu_7_1_2_sh_mask.h"
  40 #include "ivsrcid/ivsrcid_vislands30.h"
  41
  42 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  43 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int uvd_v5_0_start(struct amdgpu_device *adev);
  45 static void uvd_v5_0_stop(struct amdgpu_device *adev);
  46 static int uvd_v5_0_set_clockgating_state(void *handle,
  47                                           enum amd_clockgating_state state);
  48 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
  49                                  bool enable);
  50 /**
  51  * uvd_v5_0_ring_get_rptr - get read pointer
  52  *
  53  * @ring: amdgpu_ring pointer
  54  *
  55  * Returns the current hardware read pointer
  56  */
  57 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         return RREG32(mmUVD_RBC_RB_RPTR);
  62 }
  63
  64 /**
  65  * uvd_v5_0_ring_get_wptr - get write pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware write pointer
  70  */
  71 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32(mmUVD_RBC_RB_WPTR);
  76 }
  77
  78 /**
  79  * uvd_v5_0_ring_set_wptr - set write pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Commits the write pointer to the hardware
  84  */
  85 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  90 }
  91
  92 static int uvd_v5_0_early_init(void *handle)
  93 {
  94         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  95         adev->uvd.num_uvd_inst = 1;
  96
  97         uvd_v5_0_set_ring_funcs(adev);
  98         uvd_v5_0_set_irq_funcs(adev);
  99
 100         return 0;
 101 }
 102
 103 static int uvd_v5_0_sw_init(void *handle)
 104 {
 105         struct amdgpu_ring *ring;
 106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 107         int r;
 108
 109         /* UVD TRAP */
 110         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 111         if (r)
 112                 return r;
 113
 114         r = amdgpu_uvd_sw_init(adev);
 115         if (r)
 116                 return r;
 117
 118         ring = &adev->uvd.inst->ring;
 119         sprintf(ring->name, "uvd");
 120         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 121         if (r)
 122                 return r;
 123
 124         r = amdgpu_uvd_resume(adev);
 125         if (r)
 126                 return r;
 127
 128         r = amdgpu_uvd_entity_init(adev);
 129
 130         return r;
 131 }
 132
 133 static int uvd_v5_0_sw_fini(void *handle)
 134 {
 135         int r;
 136         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 137
 138         r = amdgpu_uvd_suspend(adev);
 139         if (r)
 140                 return r;
 141
 142         return amdgpu_uvd_sw_fini(adev);
 143 }
 144
 145 /**
 146  * uvd_v5_0_hw_init - start and test UVD block
 147  *
 148  * @adev: amdgpu_device pointer
 149  *
 150  * Initialize the hardware, boot up the VCPU and do some testing
 151  */
 152 static int uvd_v5_0_hw_init(void *handle)
 153 {
 154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 155         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 156         uint32_t tmp;
 157         int r;
 158
 159         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 160         uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 161         uvd_v5_0_enable_mgcg(adev, true);
 162
 163         r = amdgpu_ring_test_helper(ring);
 164         if (r)
 165                 goto done;
 166
 167         r = amdgpu_ring_alloc(ring, 10);
 168         if (r) {
 169                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 170                 goto done;
 171         }
 172
 173         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 174         amdgpu_ring_write(ring, tmp);
 175         amdgpu_ring_write(ring, 0xFFFFF);
 176
 177         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 178         amdgpu_ring_write(ring, tmp);
 179         amdgpu_ring_write(ring, 0xFFFFF);
 180
 181         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 182         amdgpu_ring_write(ring, tmp);
 183         amdgpu_ring_write(ring, 0xFFFFF);
 184
 185         /* Clear timeout status bits */
 186         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 187         amdgpu_ring_write(ring, 0x8);
 188
 189         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 190         amdgpu_ring_write(ring, 3);
 191
 192         amdgpu_ring_commit(ring);
 193
 194 done:
 195         if (!r)
 196                 DRM_INFO("UVD initialized successfully.\n");
 197
 198         return r;
 199
 200 }
 201
 202 /**
 203  * uvd_v5_0_hw_fini - stop the hardware block
 204  *
 205  * @adev: amdgpu_device pointer
 206  *
 207  * Stop the UVD block, mark ring as not ready any more
 208  */
 209 static int uvd_v5_0_hw_fini(void *handle)
 210 {
 211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 212         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 213
 214         if (RREG32(mmUVD_STATUS) != 0)
 215                 uvd_v5_0_stop(adev);
 216
 217         ring->sched.ready = false;
 218
 219         return 0;
 220 }
 221
 222 static int uvd_v5_0_suspend(void *handle)
 223 {
 224         int r;
 225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 226
 227         r = uvd_v5_0_hw_fini(adev);
 228         if (r)
 229                 return r;
 230         uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
 231
 232         return amdgpu_uvd_suspend(adev);
 233 }
 234
 235 static int uvd_v5_0_resume(void *handle)
 236 {
 237         int r;
 238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 239
 240         r = amdgpu_uvd_resume(adev);
 241         if (r)
 242                 return r;
 243
 244         return uvd_v5_0_hw_init(adev);
 245 }
 246
 247 /**
 248  * uvd_v5_0_mc_resume - memory controller programming
 249  *
 250  * @adev: amdgpu_device pointer
 251  *
 252  * Let the UVD memory controller know it's offsets
 253  */
 254 static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
 255 {
 256         uint64_t offset;
 257         uint32_t size;
 258
 259         /* programm memory controller bits 0-27 */
 260         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 261                         lower_32_bits(adev->uvd.inst->gpu_addr));
 262         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 263                         upper_32_bits(adev->uvd.inst->gpu_addr));
 264
 265         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 266         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 267         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 268         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 269
 270         offset += size;
 271         size = AMDGPU_UVD_HEAP_SIZE;
 272         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 273         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 274
 275         offset += size;
 276         size = AMDGPU_UVD_STACK_SIZE +
 277                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 278         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 279         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 280
 281         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 282         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 283         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 284 }
 285
 286 /**
 287  * uvd_v5_0_start - start UVD block
 288  *
 289  * @adev: amdgpu_device pointer
 290  *
 291  * Setup and start the UVD block
 292  */
 293 static int uvd_v5_0_start(struct amdgpu_device *adev)
 294 {
 295         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 296         uint32_t rb_bufsz, tmp;
 297         uint32_t lmi_swap_cntl;
 298         uint32_t mp_swap_cntl;
 299         int i, j, r;
 300
 301         /*disable DPG */
 302         WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
 303
 304         /* disable byte swapping */
 305         lmi_swap_cntl = 0;
 306         mp_swap_cntl = 0;
 307
 308         uvd_v5_0_mc_resume(adev);
 309
 310         /* disable interupt */
 311         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 312
 313         /* stall UMC and register bus before resetting VCPU */
 314         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 315         mdelay(1);
 316
 317         /* put LMI, VCPU, RBC etc... into reset */
 318         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 319                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 320                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 321                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 322                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 323         mdelay(5);
 324
 325         /* take UVD block out of reset */
 326         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 327         mdelay(5);
 328
 329         /* initialize UVD memory controller */
 330         WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 331                              (1 << 21) | (1 << 9) | (1 << 20));
 332
 333 #ifdef __BIG_ENDIAN
 334         /* swap (8 in 32) RB and IB */
 335         lmi_swap_cntl = 0xa;
 336         mp_swap_cntl = 0;
 337 #endif
 338         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 339         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 340
 341         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 342         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 343         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 344         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 345         WREG32(mmUVD_MPC_SET_ALU, 0);
 346         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 347
 348         /* take all subblocks out of reset, except VCPU */
 349         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 350         mdelay(5);
 351
 352         /* enable VCPU clock */
 353         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 354
 355         /* enable UMC */
 356         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 357
 358         /* boot up the VCPU */
 359         WREG32(mmUVD_SOFT_RESET, 0);
 360         mdelay(10);
 361
 362         for (i = 0; i < 10; ++i) {
 363                 uint32_t status;
 364                 for (j = 0; j < 100; ++j) {
 365                         status = RREG32(mmUVD_STATUS);
 366                         if (status & 2)
 367                                 break;
 368                         mdelay(10);
 369                 }
 370                 r = 0;
 371                 if (status & 2)
 372                         break;
 373
 374                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 375                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 376                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 377                 mdelay(10);
 378                 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 379                 mdelay(10);
 380                 r = -1;
 381         }
 382
 383         if (r) {
 384                 DRM_ERROR("UVD not responding, giving up!!!\n");
 385                 return r;
 386         }
 387         /* enable master interrupt */
 388         WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
 389
 390         /* clear the bit 4 of UVD_STATUS */
 391         WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
 392
 393         rb_bufsz = order_base_2(ring->ring_size);
 394         tmp = 0;
 395         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 396         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 397         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 398         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 399         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 400         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 401         /* force RBC into idle state */
 402         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 403
 404         /* set the write pointer delay */
 405         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 406
 407         /* set the wb address */
 408         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 409
 410         /* programm the RB_BASE for ring buffer */
 411         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 412                         lower_32_bits(ring->gpu_addr));
 413         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 414                         upper_32_bits(ring->gpu_addr));
 415
 416         /* Initialize the ring buffer's read and write pointers */
 417         WREG32(mmUVD_RBC_RB_RPTR, 0);
 418
 419         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 420         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 421
 422         WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 423
 424         return 0;
 425 }
 426
 427 /**
 428  * uvd_v5_0_stop - stop UVD block
 429  *
 430  * @adev: amdgpu_device pointer
 431  *
 432  * stop the UVD block
 433  */
 434 static void uvd_v5_0_stop(struct amdgpu_device *adev)
 435 {
 436         /* force RBC into idle state */
 437         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 438
 439         /* Stall UMC and register bus before resetting VCPU */
 440         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 441         mdelay(1);
 442
 443         /* put VCPU into reset */
 444         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 445         mdelay(5);
 446
 447         /* disable VCPU clock */
 448         WREG32(mmUVD_VCPU_CNTL, 0x0);
 449
 450         /* Unstall UMC and register bus */
 451         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 452
 453         WREG32(mmUVD_STATUS, 0);
 454 }
 455
 456 /**
 457  * uvd_v5_0_ring_emit_fence - emit an fence & trap command
 458  *
 459  * @ring: amdgpu_ring pointer
 460  * @fence: fence to emit
 461  *
 462  * Write a fence and a trap command to the ring.
 463  */
 464 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 465                                      unsigned flags)
 466 {
 467         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 468
 469         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 470         amdgpu_ring_write(ring, seq);
 471         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 472         amdgpu_ring_write(ring, addr & 0xffffffff);
 473         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 474         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 475         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 476         amdgpu_ring_write(ring, 0);
 477
 478         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 479         amdgpu_ring_write(ring, 0);
 480         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 481         amdgpu_ring_write(ring, 0);
 482         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 483         amdgpu_ring_write(ring, 2);
 484 }
 485
 486 /**
 487  * uvd_v5_0_ring_test_ring - register write test
 488  *
 489  * @ring: amdgpu_ring pointer
 490  *
 491  * Test if we can successfully write to the context register
 492  */
 493 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 494 {
 495         struct amdgpu_device *adev = ring->adev;
 496         uint32_t tmp = 0;
 497         unsigned i;
 498         int r;
 499
 500         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 501         r = amdgpu_ring_alloc(ring, 3);
 502         if (r)
 503                 return r;
 504         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 505         amdgpu_ring_write(ring, 0xDEADBEEF);
 506         amdgpu_ring_commit(ring);
 507         for (i = 0; i < adev->usec_timeout; i++) {
 508                 tmp = RREG32(mmUVD_CONTEXT_ID);
 509                 if (tmp == 0xDEADBEEF)
 510                         break;
 511                 udelay(1);
 512         }
 513
 514         if (i >= adev->usec_timeout)
 515                 r = -ETIMEDOUT;
 516
 517         return r;
 518 }
 519
 520 /**
 521  * uvd_v5_0_ring_emit_ib - execute indirect buffer
 522  *
 523  * @ring: amdgpu_ring pointer
 524  * @ib: indirect buffer to execute
 525  *
 526  * Write ring commands to execute the indirect buffer
 527  */
 528 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 529                                   struct amdgpu_job *job,
 530                                   struct amdgpu_ib *ib,
 531                                   uint32_t flags)
 532 {
 533         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 534         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 535         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 536         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 537         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 538         amdgpu_ring_write(ring, ib->length_dw);
 539 }
 540
 541 static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 542 {
 543         int i;
 544
 545         WARN_ON(ring->wptr % 2 || count % 2);
 546
 547         for (i = 0; i < count / 2; i++) {
 548                 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
 549                 amdgpu_ring_write(ring, 0);
 550         }
 551 }
 552
 553 static bool uvd_v5_0_is_idle(void *handle)
 554 {
 555         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 556
 557         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 558 }
 559
 560 static int uvd_v5_0_wait_for_idle(void *handle)
 561 {
 562         unsigned i;
 563         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 564
 565         for (i = 0; i < adev->usec_timeout; i++) {
 566                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 567                         return 0;
 568         }
 569         return -ETIMEDOUT;
 570 }
 571
 572 static int uvd_v5_0_soft_reset(void *handle)
 573 {
 574         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 575
 576         uvd_v5_0_stop(adev);
 577
 578         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 579                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 580         mdelay(5);
 581
 582         return uvd_v5_0_start(adev);
 583 }
 584
 585 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
 586                                         struct amdgpu_irq_src *source,
 587                                         unsigned type,
 588                                         enum amdgpu_interrupt_state state)
 589 {
 590         // TODO
 591         return 0;
 592 }
 593
 594 static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
 595                                       struct amdgpu_irq_src *source,
 596                                       struct amdgpu_iv_entry *entry)
 597 {
 598         DRM_DEBUG("IH: UVD TRAP\n");
 599         amdgpu_fence_process(&adev->uvd.inst->ring);
 600         return 0;
 601 }
 602
 603 static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
 604 {
 605         uint32_t data1, data3, suvd_flags;
 606
 607         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 608         data3 = RREG32(mmUVD_CGC_GATE);
 609
 610         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 611                      UVD_SUVD_CGC_GATE__SIT_MASK |
 612                      UVD_SUVD_CGC_GATE__SMP_MASK |
 613                      UVD_SUVD_CGC_GATE__SCM_MASK |
 614                      UVD_SUVD_CGC_GATE__SDB_MASK;
 615
 616         if (enable) {
 617                 data3 |= (UVD_CGC_GATE__SYS_MASK     |
 618                         UVD_CGC_GATE__UDEC_MASK      |
 619                         UVD_CGC_GATE__MPEG2_MASK     |
 620                         UVD_CGC_GATE__RBC_MASK       |
 621                         UVD_CGC_GATE__LMI_MC_MASK    |
 622                         UVD_CGC_GATE__IDCT_MASK      |
 623                         UVD_CGC_GATE__MPRD_MASK      |
 624                         UVD_CGC_GATE__MPC_MASK       |
 625                         UVD_CGC_GATE__LBSI_MASK      |
 626                         UVD_CGC_GATE__LRBBM_MASK     |
 627                         UVD_CGC_GATE__UDEC_RE_MASK   |
 628                         UVD_CGC_GATE__UDEC_CM_MASK   |
 629                         UVD_CGC_GATE__UDEC_IT_MASK   |
 630                         UVD_CGC_GATE__UDEC_DB_MASK   |
 631                         UVD_CGC_GATE__UDEC_MP_MASK   |
 632                         UVD_CGC_GATE__WCB_MASK       |
 633                         UVD_CGC_GATE__JPEG_MASK      |
 634                         UVD_CGC_GATE__SCPU_MASK);
 635                 /* only in pg enabled, we can gate clock to vcpu*/
 636                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 637                         data3 |= UVD_CGC_GATE__VCPU_MASK;
 638                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
 639                 data1 |= suvd_flags;
 640         } else {
 641                 data3 = 0;
 642                 data1 = 0;
 643         }
 644
 645         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 646         WREG32(mmUVD_CGC_GATE, data3);
 647 }
 648
 649 static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
 650 {
 651         uint32_t data, data2;
 652
 653         data = RREG32(mmUVD_CGC_CTRL);
 654         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 655
 656
 657         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 658                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 659
 660
 661         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 662                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 663                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 664
 665         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 666                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 667                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 668                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 669                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 670                         UVD_CGC_CTRL__SYS_MODE_MASK |
 671                         UVD_CGC_CTRL__UDEC_MODE_MASK |
 672                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
 673                         UVD_CGC_CTRL__REGS_MODE_MASK |
 674                         UVD_CGC_CTRL__RBC_MODE_MASK |
 675                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 676                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 677                         UVD_CGC_CTRL__IDCT_MODE_MASK |
 678                         UVD_CGC_CTRL__MPRD_MODE_MASK |
 679                         UVD_CGC_CTRL__MPC_MODE_MASK |
 680                         UVD_CGC_CTRL__LBSI_MODE_MASK |
 681                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
 682                         UVD_CGC_CTRL__WCB_MODE_MASK |
 683                         UVD_CGC_CTRL__VCPU_MODE_MASK |
 684                         UVD_CGC_CTRL__JPEG_MODE_MASK |
 685                         UVD_CGC_CTRL__SCPU_MODE_MASK);
 686         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 687                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 688                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 689                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 690                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 691
 692         WREG32(mmUVD_CGC_CTRL, data);
 693         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 694 }
 695
 696 #if 0
 697 static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
 698 {
 699         uint32_t data, data1, cgc_flags, suvd_flags;
 700
 701         data = RREG32(mmUVD_CGC_GATE);
 702         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 703
 704         cgc_flags = UVD_CGC_GATE__SYS_MASK |
 705                                 UVD_CGC_GATE__UDEC_MASK |
 706                                 UVD_CGC_GATE__MPEG2_MASK |
 707                                 UVD_CGC_GATE__RBC_MASK |
 708                                 UVD_CGC_GATE__LMI_MC_MASK |
 709                                 UVD_CGC_GATE__IDCT_MASK |
 710                                 UVD_CGC_GATE__MPRD_MASK |
 711                                 UVD_CGC_GATE__MPC_MASK |
 712                                 UVD_CGC_GATE__LBSI_MASK |
 713                                 UVD_CGC_GATE__LRBBM_MASK |
 714                                 UVD_CGC_GATE__UDEC_RE_MASK |
 715                                 UVD_CGC_GATE__UDEC_CM_MASK |
 716                                 UVD_CGC_GATE__UDEC_IT_MASK |
 717                                 UVD_CGC_GATE__UDEC_DB_MASK |
 718                                 UVD_CGC_GATE__UDEC_MP_MASK |
 719                                 UVD_CGC_GATE__WCB_MASK |
 720                                 UVD_CGC_GATE__VCPU_MASK |
 721                                 UVD_CGC_GATE__SCPU_MASK;
 722
 723         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 724                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 725                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 726                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 727                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 728
 729         data |= cgc_flags;
 730         data1 |= suvd_flags;
 731
 732         WREG32(mmUVD_CGC_GATE, data);
 733         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 734 }
 735 #endif
 736
 737 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
 738                                  bool enable)
 739 {
 740         u32 orig, data;
 741
 742         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 743                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 744                 data |= 0xfff;
 745                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 746
 747                 orig = data = RREG32(mmUVD_CGC_CTRL);
 748                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 749                 if (orig != data)
 750                         WREG32(mmUVD_CGC_CTRL, data);
 751         } else {
 752                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 753                 data &= ~0xfff;
 754                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 755
 756                 orig = data = RREG32(mmUVD_CGC_CTRL);
 757                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 758                 if (orig != data)
 759                         WREG32(mmUVD_CGC_CTRL, data);
 760         }
 761 }
 762
 763 static int uvd_v5_0_set_clockgating_state(void *handle,
 764                                           enum amd_clockgating_state state)
 765 {
 766         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 767         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 768
 769         if (enable) {
 770                 /* wait for STATUS to clear */
 771                 if (uvd_v5_0_wait_for_idle(handle))
 772                         return -EBUSY;
 773                 uvd_v5_0_enable_clock_gating(adev, true);
 774
 775                 /* enable HW gates because UVD is idle */
 776 /*              uvd_v5_0_set_hw_clock_gating(adev); */
 777         } else {
 778                 uvd_v5_0_enable_clock_gating(adev, false);
 779         }
 780
 781         uvd_v5_0_set_sw_clock_gating(adev);
 782         return 0;
 783 }
 784
 785 static int uvd_v5_0_set_powergating_state(void *handle,
 786                                           enum amd_powergating_state state)
 787 {
 788         /* This doesn't actually powergate the UVD block.
 789          * That's done in the dpm code via the SMC.  This
 790          * just re-inits the block as necessary.  The actual
 791          * gating still happens in the dpm code.  We should
 792          * revisit this when there is a cleaner line between
 793          * the smc and the hw blocks
 794          */
 795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 796         int ret = 0;
 797
 798         if (state == AMD_PG_STATE_GATE) {
 799                 uvd_v5_0_stop(adev);
 800         } else {
 801                 ret = uvd_v5_0_start(adev);
 802                 if (ret)
 803                         goto out;
 804         }
 805
 806 out:
 807         return ret;
 808 }
 809
 810 static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
 811 {
 812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 813         int data;
 814
 815         mutex_lock(&adev->pm.mutex);
 816
 817         if (RREG32_SMC(ixCURRENT_PG_STATUS) &
 818                                 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
 819                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
 820                 goto out;
 821         }
 822
 823         /* AMD_CG_SUPPORT_UVD_MGCG */
 824         data = RREG32(mmUVD_CGC_CTRL);
 825         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
 826                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
 827
 828 out:
 829         mutex_unlock(&adev->pm.mutex);
 830 }
 831
 832 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 833         .name = "uvd_v5_0",
 834         .early_init = uvd_v5_0_early_init,
 835         .late_init = NULL,
 836         .sw_init = uvd_v5_0_sw_init,
 837         .sw_fini = uvd_v5_0_sw_fini,
 838         .hw_init = uvd_v5_0_hw_init,
 839         .hw_fini = uvd_v5_0_hw_fini,
 840         .suspend = uvd_v5_0_suspend,
 841         .resume = uvd_v5_0_resume,
 842         .is_idle = uvd_v5_0_is_idle,
 843         .wait_for_idle = uvd_v5_0_wait_for_idle,
 844         .soft_reset = uvd_v5_0_soft_reset,
 845         .set_clockgating_state = uvd_v5_0_set_clockgating_state,
 846         .set_powergating_state = uvd_v5_0_set_powergating_state,
 847         .get_clockgating_state = uvd_v5_0_get_clockgating_state,
 848 };
 849
 850 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
 851         .type = AMDGPU_RING_TYPE_UVD,
 852         .align_mask = 0xf,
 853         .support_64bit_ptrs = false,
 854         .get_rptr = uvd_v5_0_ring_get_rptr,
 855         .get_wptr = uvd_v5_0_ring_get_wptr,
 856         .set_wptr = uvd_v5_0_ring_set_wptr,
 857         .parse_cs = amdgpu_uvd_ring_parse_cs,
 858         .emit_frame_size =
 859                 14, /* uvd_v5_0_ring_emit_fence  x1 no user fence */
 860         .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
 861         .emit_ib = uvd_v5_0_ring_emit_ib,
 862         .emit_fence = uvd_v5_0_ring_emit_fence,
 863         .test_ring = uvd_v5_0_ring_test_ring,
 864         .test_ib = amdgpu_uvd_ring_test_ib,
 865         .insert_nop = uvd_v5_0_ring_insert_nop,
 866         .pad_ib = amdgpu_ring_generic_pad_ib,
 867         .begin_use = amdgpu_uvd_ring_begin_use,
 868         .end_use = amdgpu_uvd_ring_end_use,
 869 };
 870
 871 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
 872 {
 873         adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
 874 }
 875
 876 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
 877         .set = uvd_v5_0_set_interrupt_state,
 878         .process = uvd_v5_0_process_interrupt,
 879 };
 880
 881 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
 882 {
 883         adev->uvd.inst->irq.num_types = 1;
 884         adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
 885 }
 886
 887 const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
 888 {
 889                 .type = AMD_IP_BLOCK_TYPE_UVD,
 890                 .major = 5,
 891                 .minor = 0,
 892                 .rev = 0,
 893                 .funcs = &uvd_v5_0_ip_funcs,
 894 };