drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vcn.h"
  36 #include "soc15d.h"
  37 #include "soc15_common.h"
  38
  39 #include "vcn/vcn_1_0_offset.h"
  40 #include "vcn/vcn_1_0_sh_mask.h"
  41
  42 /* 1 second timeout */
  43 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  44
  45 /* Firmware Names */
  46 #define FIRMWARE_RAVEN          "amdgpu/raven_vcn.bin"
  47 #define FIRMWARE_PICASSO        "amdgpu/picasso_vcn.bin"
  48 #define FIRMWARE_RAVEN2         "amdgpu/raven2_vcn.bin"
  49
  50 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  51 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  52 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  53
  54 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  55
  56 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  57 {
  58         unsigned long bo_size;
  59         const char *fw_name;
  60         const struct common_firmware_header *hdr;
  61         unsigned char fw_check;
  62         int r;
  63
  64         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  65
  66         switch (adev->asic_type) {
  67         case CHIP_RAVEN:
  68                 if (adev->rev_id >= 8)
  69                         fw_name = FIRMWARE_RAVEN2;
  70                 else if (adev->pdev->device == 0x15d8)
  71                         fw_name = FIRMWARE_PICASSO;
  72                 else
  73                         fw_name = FIRMWARE_RAVEN;
  74                 break;
  75         default:
  76                 return -EINVAL;
  77         }
  78
  79         r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
  80         if (r) {
  81                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
  82                         fw_name);
  83                 return r;
  84         }
  85
  86         r = amdgpu_ucode_validate(adev->vcn.fw);
  87         if (r) {
  88                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
  89                         fw_name);
  90                 release_firmware(adev->vcn.fw);
  91                 adev->vcn.fw = NULL;
  92                 return r;
  93         }
  94
  95         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
  96         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
  97
  98         /* Bit 20-23, it is encode major and non-zero for new naming convention.
  99          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 100          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 101          * is zero in old naming convention, this field is always zero so far.
 102          * These four bits are used to tell which naming convention is present.
 103          */
 104         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 105         if (fw_check) {
 106                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 107
 108                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 109                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 110                 enc_major = fw_check;
 111                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 112                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 113                 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
 114                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 115         } else {
 116                 unsigned int version_major, version_minor, family_id;
 117
 118                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 119                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 120                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 121                 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
 122                         version_major, version_minor, family_id);
 123         }
 124
 125         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 126         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 127                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 128         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 129                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
 130                                     &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
 131         if (r) {
 132                 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 133                 return r;
 134         }
 135
 136         return 0;
 137 }
 138
 139 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 140 {
 141         int i;
 142
 143         kvfree(adev->vcn.saved_bo);
 144
 145         amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
 146                               &adev->vcn.gpu_addr,
 147                               (void **)&adev->vcn.cpu_addr);
 148
 149         amdgpu_ring_fini(&adev->vcn.ring_dec);
 150
 151         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 152                 amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
 153
 154         amdgpu_ring_fini(&adev->vcn.ring_jpeg);
 155
 156         release_firmware(adev->vcn.fw);
 157
 158         return 0;
 159 }
 160
 161 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 162 {
 163         unsigned size;
 164         void *ptr;
 165
 166         cancel_delayed_work_sync(&adev->vcn.idle_work);
 167
 168         if (adev->vcn.vcpu_bo == NULL)
 169                 return 0;
 170
 171         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 172         ptr = adev->vcn.cpu_addr;
 173
 174         adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
 175         if (!adev->vcn.saved_bo)
 176                 return -ENOMEM;
 177
 178         memcpy_fromio(adev->vcn.saved_bo, ptr, size);
 179
 180         return 0;
 181 }
 182
 183 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 184 {
 185         unsigned size;
 186         void *ptr;
 187
 188         if (adev->vcn.vcpu_bo == NULL)
 189                 return -EINVAL;
 190
 191         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 192         ptr = adev->vcn.cpu_addr;
 193
 194         if (adev->vcn.saved_bo != NULL) {
 195                 memcpy_toio(ptr, adev->vcn.saved_bo, size);
 196                 kvfree(adev->vcn.saved_bo);
 197                 adev->vcn.saved_bo = NULL;
 198         } else {
 199                 const struct common_firmware_header *hdr;
 200                 unsigned offset;
 201
 202                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 203                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 204                         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 205                         memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
 206                                     le32_to_cpu(hdr->ucode_size_bytes));
 207                         size -= le32_to_cpu(hdr->ucode_size_bytes);
 208                         ptr += le32_to_cpu(hdr->ucode_size_bytes);
 209                 }
 210                 memset_io(ptr, 0, size);
 211         }
 212
 213         return 0;
 214 }
 215
 216 static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
 217                                      struct dpg_pause_state *new_state)
 218 {
 219         int ret_code;
 220         uint32_t reg_data = 0;
 221         uint32_t reg_data2 = 0;
 222         struct amdgpu_ring *ring;
 223
 224         /* pause/unpause if state is changed */
 225         if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
 226                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
 227                         adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
 228                         new_state->fw_based, new_state->jpeg);
 229
 230                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
 231                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
 232
 233                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
 234                         ret_code = 0;
 235
 236                         if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
 237                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
 238                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
 239                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
 240
 241                         if (!ret_code) {
 242                                 /* pause DPG non-jpeg */
 243                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
 244                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
 245                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
 246                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
 247                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
 248
 249                                 /* Restore */
 250                                 ring = &adev->vcn.ring_enc[0];
 251                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 252                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 253                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 254                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 255                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 256
 257                                 ring = &adev->vcn.ring_enc[1];
 258                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 259                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 260                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 261                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 262                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 263
 264                                 ring = &adev->vcn.ring_dec;
 265                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 266                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
 267                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
 268                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
 269                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
 270                         }
 271                 } else {
 272                         /* unpause dpg non-jpeg, no need to wait */
 273                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
 274                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
 275                 }
 276                 adev->vcn.pause_state.fw_based = new_state->fw_based;
 277         }
 278
 279         /* pause/unpause if state is changed */
 280         if (adev->vcn.pause_state.jpeg != new_state->jpeg) {
 281                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
 282                         adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
 283                         new_state->fw_based, new_state->jpeg);
 284
 285                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
 286                         (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
 287
 288                 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
 289                         ret_code = 0;
 290
 291                         if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
 292                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
 293                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
 294                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
 295
 296                         if (!ret_code) {
 297                                 /* Make sure JPRG Snoop is disabled before sending the pause */
 298                                 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 299                                 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
 300                                 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
 301
 302                                 /* pause DPG jpeg */
 303                                 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
 304                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
 305                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
 306                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
 307                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
 308
 309                                 /* Restore */
 310                                 ring = &adev->vcn.ring_jpeg;
 311                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 312                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
 313                                                         UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
 314                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 315                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 316                                                         lower_32_bits(ring->gpu_addr));
 317                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 318                                                         upper_32_bits(ring->gpu_addr));
 319                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
 320                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
 321                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
 322                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 323
 324                                 ring = &adev->vcn.ring_dec;
 325                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 326                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
 327                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
 328                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
 329                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
 330                         }
 331                 } else {
 332                         /* unpause dpg jpeg, no need to wait */
 333                         reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
 334                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
 335                 }
 336                 adev->vcn.pause_state.jpeg = new_state->jpeg;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 343 {
 344         struct amdgpu_device *adev =
 345                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 346         unsigned int fences = 0;
 347         unsigned int i;
 348
 349         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 350                 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
 351         }
 352
 353         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 354                 struct dpg_pause_state new_state;
 355
 356                 if (fences)
 357                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 358                 else
 359                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 360
 361                 if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
 362                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
 363                 else
 364                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
 365
 366                 amdgpu_vcn_pause_dpg_mode(adev, &new_state);
 367         }
 368
 369         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
 370         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
 371
 372         if (fences == 0) {
 373                 amdgpu_gfx_off_ctrl(adev, true);
 374                 if (adev->pm.dpm_enabled)
 375                         amdgpu_dpm_enable_uvd(adev, false);
 376                 else
 377                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 378                                                                AMD_PG_STATE_GATE);
 379         } else {
 380                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 381         }
 382 }
 383
 384 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 385 {
 386         struct amdgpu_device *adev = ring->adev;
 387         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 388
 389         if (set_clocks) {
 390                 amdgpu_gfx_off_ctrl(adev, false);
 391                 if (adev->pm.dpm_enabled)
 392                         amdgpu_dpm_enable_uvd(adev, true);
 393                 else
 394                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 395                                                                AMD_PG_STATE_UNGATE);
 396         }
 397
 398         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 399                 struct dpg_pause_state new_state;
 400                 unsigned int fences = 0;
 401                 unsigned int i;
 402
 403                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 404                         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
 405                 }
 406                 if (fences)
 407                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 408                 else
 409                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 410
 411                 if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
 412                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
 413                 else
 414                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
 415
 416                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 417                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 418                 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
 419                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
 420
 421                 amdgpu_vcn_pause_dpg_mode(adev, &new_state);
 422         }
 423 }
 424
 425 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 426 {
 427         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 428 }
 429
 430 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 431 {
 432         struct amdgpu_device *adev = ring->adev;
 433         uint32_t tmp = 0;
 434         unsigned i;
 435         int r;
 436
 437         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
 438         r = amdgpu_ring_alloc(ring, 3);
 439         if (r)
 440                 return r;
 441
 442         amdgpu_ring_write(ring,
 443                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));
 444         amdgpu_ring_write(ring, 0xDEADBEEF);
 445         amdgpu_ring_commit(ring);
 446         for (i = 0; i < adev->usec_timeout; i++) {
 447                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
 448                 if (tmp == 0xDEADBEEF)
 449                         break;
 450                 udelay(1);
 451         }
 452
 453         if (i >= adev->usec_timeout)
 454                 r = -ETIMEDOUT;
 455
 456         return r;
 457 }
 458
 459 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 460                                    struct amdgpu_bo *bo,
 461                                    struct dma_fence **fence)
 462 {
 463         struct amdgpu_device *adev = ring->adev;
 464         struct dma_fence *f = NULL;
 465         struct amdgpu_job *job;
 466         struct amdgpu_ib *ib;
 467         uint64_t addr;
 468         int i, r;
 469
 470         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 471         if (r)
 472                 goto err;
 473
 474         ib = &job->ibs[0];
 475         addr = amdgpu_bo_gpu_offset(bo);
 476         ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
 477         ib->ptr[1] = addr;
 478         ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
 479         ib->ptr[3] = addr >> 32;
 480         ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
 481         ib->ptr[5] = 0;
 482         for (i = 6; i < 16; i += 2) {
 483                 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
 484                 ib->ptr[i+1] = 0;
 485         }
 486         ib->length_dw = 16;
 487
 488         r = amdgpu_job_submit_direct(job, ring, &f);
 489         if (r)
 490                 goto err_free;
 491
 492         amdgpu_bo_fence(bo, f, false);
 493         amdgpu_bo_unreserve(bo);
 494         amdgpu_bo_unref(&bo);
 495
 496         if (fence)
 497                 *fence = dma_fence_get(f);
 498         dma_fence_put(f);
 499
 500         return 0;
 501
 502 err_free:
 503         amdgpu_job_free(job);
 504
 505 err:
 506         amdgpu_bo_unreserve(bo);
 507         amdgpu_bo_unref(&bo);
 508         return r;
 509 }
 510
 511 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 512                               struct dma_fence **fence)
 513 {
 514         struct amdgpu_device *adev = ring->adev;
 515         struct amdgpu_bo *bo = NULL;
 516         uint32_t *msg;
 517         int r, i;
 518
 519         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 520                                       AMDGPU_GEM_DOMAIN_VRAM,
 521                                       &bo, NULL, (void **)&msg);
 522         if (r)
 523                 return r;
 524
 525         msg[0] = cpu_to_le32(0x00000028);
 526         msg[1] = cpu_to_le32(0x00000038);
 527         msg[2] = cpu_to_le32(0x00000001);
 528         msg[3] = cpu_to_le32(0x00000000);
 529         msg[4] = cpu_to_le32(handle);
 530         msg[5] = cpu_to_le32(0x00000000);
 531         msg[6] = cpu_to_le32(0x00000001);
 532         msg[7] = cpu_to_le32(0x00000028);
 533         msg[8] = cpu_to_le32(0x00000010);
 534         msg[9] = cpu_to_le32(0x00000000);
 535         msg[10] = cpu_to_le32(0x00000007);
 536         msg[11] = cpu_to_le32(0x00000000);
 537         msg[12] = cpu_to_le32(0x00000780);
 538         msg[13] = cpu_to_le32(0x00000440);
 539         for (i = 14; i < 1024; ++i)
 540                 msg[i] = cpu_to_le32(0x0);
 541
 542         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 543 }
 544
 545 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 546                                struct dma_fence **fence)
 547 {
 548         struct amdgpu_device *adev = ring->adev;
 549         struct amdgpu_bo *bo = NULL;
 550         uint32_t *msg;
 551         int r, i;
 552
 553         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 554                                       AMDGPU_GEM_DOMAIN_VRAM,
 555                                       &bo, NULL, (void **)&msg);
 556         if (r)
 557                 return r;
 558
 559         msg[0] = cpu_to_le32(0x00000028);
 560         msg[1] = cpu_to_le32(0x00000018);
 561         msg[2] = cpu_to_le32(0x00000000);
 562         msg[3] = cpu_to_le32(0x00000002);
 563         msg[4] = cpu_to_le32(handle);
 564         msg[5] = cpu_to_le32(0x00000000);
 565         for (i = 6; i < 1024; ++i)
 566                 msg[i] = cpu_to_le32(0x0);
 567
 568         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 569 }
 570
 571 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 572 {
 573         struct dma_fence *fence;
 574         long r;
 575
 576         r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
 577         if (r)
 578                 goto error;
 579
 580         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
 581         if (r)
 582                 goto error;
 583
 584         r = dma_fence_wait_timeout(fence, false, timeout);
 585         if (r == 0)
 586                 r = -ETIMEDOUT;
 587         else if (r > 0)
 588                 r = 0;
 589
 590         dma_fence_put(fence);
 591 error:
 592         return r;
 593 }
 594
 595 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 596 {
 597         struct amdgpu_device *adev = ring->adev;
 598         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 599         unsigned i;
 600         int r;
 601
 602         r = amdgpu_ring_alloc(ring, 16);
 603         if (r)
 604                 return r;
 605
 606         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 607         amdgpu_ring_commit(ring);
 608
 609         for (i = 0; i < adev->usec_timeout; i++) {
 610                 if (amdgpu_ring_get_rptr(ring) != rptr)
 611                         break;
 612                 udelay(1);
 613         }
 614
 615         if (i >= adev->usec_timeout)
 616                 r = -ETIMEDOUT;
 617
 618         return r;
 619 }
 620
 621 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 622                               struct dma_fence **fence)
 623 {
 624         const unsigned ib_size_dw = 16;
 625         struct amdgpu_job *job;
 626         struct amdgpu_ib *ib;
 627         struct dma_fence *f = NULL;
 628         uint64_t dummy;
 629         int i, r;
 630
 631         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 632         if (r)
 633                 return r;
 634
 635         ib = &job->ibs[0];
 636         dummy = ib->gpu_addr + 1024;
 637
 638         ib->length_dw = 0;
 639         ib->ptr[ib->length_dw++] = 0x00000018;
 640         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 641         ib->ptr[ib->length_dw++] = handle;
 642         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 643         ib->ptr[ib->length_dw++] = dummy;
 644         ib->ptr[ib->length_dw++] = 0x0000000b;
 645
 646         ib->ptr[ib->length_dw++] = 0x00000014;
 647         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 648         ib->ptr[ib->length_dw++] = 0x0000001c;
 649         ib->ptr[ib->length_dw++] = 0x00000000;
 650         ib->ptr[ib->length_dw++] = 0x00000000;
 651
 652         ib->ptr[ib->length_dw++] = 0x00000008;
 653         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 654
 655         for (i = ib->length_dw; i < ib_size_dw; ++i)
 656                 ib->ptr[i] = 0x0;
 657
 658         r = amdgpu_job_submit_direct(job, ring, &f);
 659         if (r)
 660                 goto err;
 661
 662         if (fence)
 663                 *fence = dma_fence_get(f);
 664         dma_fence_put(f);
 665
 666         return 0;
 667
 668 err:
 669         amdgpu_job_free(job);
 670         return r;
 671 }
 672
 673 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 674                                 struct dma_fence **fence)
 675 {
 676         const unsigned ib_size_dw = 16;
 677         struct amdgpu_job *job;
 678         struct amdgpu_ib *ib;
 679         struct dma_fence *f = NULL;
 680         uint64_t dummy;
 681         int i, r;
 682
 683         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 684         if (r)
 685                 return r;
 686
 687         ib = &job->ibs[0];
 688         dummy = ib->gpu_addr + 1024;
 689
 690         ib->length_dw = 0;
 691         ib->ptr[ib->length_dw++] = 0x00000018;
 692         ib->ptr[ib->length_dw++] = 0x00000001;
 693         ib->ptr[ib->length_dw++] = handle;
 694         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 695         ib->ptr[ib->length_dw++] = dummy;
 696         ib->ptr[ib->length_dw++] = 0x0000000b;
 697
 698         ib->ptr[ib->length_dw++] = 0x00000014;
 699         ib->ptr[ib->length_dw++] = 0x00000002;
 700         ib->ptr[ib->length_dw++] = 0x0000001c;
 701         ib->ptr[ib->length_dw++] = 0x00000000;
 702         ib->ptr[ib->length_dw++] = 0x00000000;
 703
 704         ib->ptr[ib->length_dw++] = 0x00000008;
 705         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 706
 707         for (i = ib->length_dw; i < ib_size_dw; ++i)
 708                 ib->ptr[i] = 0x0;
 709
 710         r = amdgpu_job_submit_direct(job, ring, &f);
 711         if (r)
 712                 goto err;
 713
 714         if (fence)
 715                 *fence = dma_fence_get(f);
 716         dma_fence_put(f);
 717
 718         return 0;
 719
 720 err:
 721         amdgpu_job_free(job);
 722         return r;
 723 }
 724
 725 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 726 {
 727         struct dma_fence *fence = NULL;
 728         long r;
 729
 730         r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
 731         if (r)
 732                 goto error;
 733
 734         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
 735         if (r)
 736                 goto error;
 737
 738         r = dma_fence_wait_timeout(fence, false, timeout);
 739         if (r == 0)
 740                 r = -ETIMEDOUT;
 741         else if (r > 0)
 742                 r = 0;
 743
 744 error:
 745         dma_fence_put(fence);
 746         return r;
 747 }
 748
 749 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
 750 {
 751         struct amdgpu_device *adev = ring->adev;
 752         uint32_t tmp = 0;
 753         unsigned i;
 754         int r;
 755
 756         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
 757         r = amdgpu_ring_alloc(ring, 3);
 758
 759         if (r)
 760                 return r;
 761
 762         amdgpu_ring_write(ring,
 763                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0));
 764         amdgpu_ring_write(ring, 0xDEADBEEF);
 765         amdgpu_ring_commit(ring);
 766
 767         for (i = 0; i < adev->usec_timeout; i++) {
 768                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
 769                 if (tmp == 0xDEADBEEF)
 770                         break;
 771                 udelay(1);
 772         }
 773
 774         if (i >= adev->usec_timeout)
 775                 r = -ETIMEDOUT;
 776
 777         return r;
 778 }
 779
 780 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 781                 struct dma_fence **fence)
 782 {
 783         struct amdgpu_device *adev = ring->adev;
 784         struct amdgpu_job *job;
 785         struct amdgpu_ib *ib;
 786         struct dma_fence *f = NULL;
 787         const unsigned ib_size_dw = 16;
 788         int i, r;
 789
 790         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 791         if (r)
 792                 return r;
 793
 794         ib = &job->ibs[0];
 795
 796         ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0);
 797         ib->ptr[1] = 0xDEADBEEF;
 798         for (i = 2; i < 16; i += 2) {
 799                 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
 800                 ib->ptr[i+1] = 0;
 801         }
 802         ib->length_dw = 16;
 803
 804         r = amdgpu_job_submit_direct(job, ring, &f);
 805         if (r)
 806                 goto err;
 807
 808         if (fence)
 809                 *fence = dma_fence_get(f);
 810         dma_fence_put(f);
 811
 812         return 0;
 813
 814 err:
 815         amdgpu_job_free(job);
 816         return r;
 817 }
 818
 819 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 820 {
 821         struct amdgpu_device *adev = ring->adev;
 822         uint32_t tmp = 0;
 823         unsigned i;
 824         struct dma_fence *fence = NULL;
 825         long r = 0;
 826
 827         r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
 828         if (r)
 829                 goto error;
 830
 831         r = dma_fence_wait_timeout(fence, false, timeout);
 832         if (r == 0) {
 833                 r = -ETIMEDOUT;
 834                 goto error;
 835         } else if (r < 0) {
 836                 goto error;
 837         } else {
 838                 r = 0;
 839         }
 840
 841         for (i = 0; i < adev->usec_timeout; i++) {
 842                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
 843                 if (tmp == 0xDEADBEEF)
 844                         break;
 845                 udelay(1);
 846         }
 847
 848         if (i >= adev->usec_timeout)
 849                 r = -ETIMEDOUT;
 850
 851         dma_fence_put(fence);
 852 error:
 853         return r;
 854 }