drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include "hwmgr.h"
  41 #define WIDTH_4K 3840
  42
  43 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  44
  45 static const struct cg_flag_name clocks[] = {
  46         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  47         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  51         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  57         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  59         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  62         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  65         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  67         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  68         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  70         {0, NULL},
  71 };
  72
  73 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  74 {
  75         if (adev->pm.dpm_enabled) {
  76                 mutex_lock(&adev->pm.mutex);
  77                 if (power_supply_is_system_supplied() > 0)
  78                         adev->pm.ac_power = true;
  79                 else
  80                         adev->pm.ac_power = false;
  81                 if (adev->powerplay.pp_funcs->enable_bapm)
  82                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  83                 mutex_unlock(&adev->pm.mutex);
  84         }
  85 }
  86
  87 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  88                            void *data, uint32_t *size)
  89 {
  90         int ret = 0;
  91
  92         if (!data || !size)
  93                 return -EINVAL;
  94
  95         if (is_support_sw_smu(adev))
  96                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
  97         else {
  98                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
  99                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 100                                                                     sensor, data, size);
 101                 else
 102                         ret = -EINVAL;
 103         }
 104
 105         return ret;
 106 }
 107
 108 /**
 109  * DOC: power_dpm_state
 110  *
 111  * The power_dpm_state file is a legacy interface and is only provided for
 112  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 113  * certain power related parameters.  The file power_dpm_state is used for this.
 114  * It accepts the following arguments:
 115  *
 116  * - battery
 117  *
 118  * - balanced
 119  *
 120  * - performance
 121  *
 122  * battery
 123  *
 124  * On older GPUs, the vbios provided a special power state for battery
 125  * operation.  Selecting battery switched to this state.  This is no
 126  * longer provided on newer GPUs so the option does nothing in that case.
 127  *
 128  * balanced
 129  *
 130  * On older GPUs, the vbios provided a special power state for balanced
 131  * operation.  Selecting balanced switched to this state.  This is no
 132  * longer provided on newer GPUs so the option does nothing in that case.
 133  *
 134  * performance
 135  *
 136  * On older GPUs, the vbios provided a special power state for performance
 137  * operation.  Selecting performance switched to this state.  This is no
 138  * longer provided on newer GPUs so the option does nothing in that case.
 139  *
 140  */
 141
 142 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 143                                     struct device_attribute *attr,
 144                                     char *buf)
 145 {
 146         struct drm_device *ddev = dev_get_drvdata(dev);
 147         struct amdgpu_device *adev = ddev->dev_private;
 148         enum amd_pm_state_type pm;
 149
 150         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 151                 pm = amdgpu_smu_get_current_power_state(adev);
 152         else if (adev->powerplay.pp_funcs->get_current_power_state)
 153                 pm = amdgpu_dpm_get_current_power_state(adev);
 154         else
 155                 pm = adev->pm.dpm.user_state;
 156
 157         return snprintf(buf, PAGE_SIZE, "%s\n",
 158                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160 }
 161
 162 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 163                                     struct device_attribute *attr,
 164                                     const char *buf,
 165                                     size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = ddev->dev_private;
 169         enum amd_pm_state_type  state;
 170
 171         if (strncmp("battery", buf, strlen("battery")) == 0)
 172                 state = POWER_STATE_TYPE_BATTERY;
 173         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 174                 state = POWER_STATE_TYPE_BALANCED;
 175         else if (strncmp("performance", buf, strlen("performance")) == 0)
 176                 state = POWER_STATE_TYPE_PERFORMANCE;
 177         else {
 178                 count = -EINVAL;
 179                 goto fail;
 180         }
 181
 182         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 183                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 184         } else {
 185                 mutex_lock(&adev->pm.mutex);
 186                 adev->pm.dpm.user_state = state;
 187                 mutex_unlock(&adev->pm.mutex);
 188
 189                 /* Can't set dpm state when the card is off */
 190                 if (!(adev->flags & AMD_IS_PX) ||
 191                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 192                         amdgpu_pm_compute_clocks(adev);
 193         }
 194 fail:
 195         return count;
 196 }
 197
 198
 199 /**
 200  * DOC: power_dpm_force_performance_level
 201  *
 202  * The amdgpu driver provides a sysfs API for adjusting certain power
 203  * related parameters.  The file power_dpm_force_performance_level is
 204  * used for this.  It accepts the following arguments:
 205  *
 206  * - auto
 207  *
 208  * - low
 209  *
 210  * - high
 211  *
 212  * - manual
 213  *
 214  * - profile_standard
 215  *
 216  * - profile_min_sclk
 217  *
 218  * - profile_min_mclk
 219  *
 220  * - profile_peak
 221  *
 222  * auto
 223  *
 224  * When auto is selected, the driver will attempt to dynamically select
 225  * the optimal power profile for current conditions in the driver.
 226  *
 227  * low
 228  *
 229  * When low is selected, the clocks are forced to the lowest power state.
 230  *
 231  * high
 232  *
 233  * When high is selected, the clocks are forced to the highest power state.
 234  *
 235  * manual
 236  *
 237  * When manual is selected, the user can manually adjust which power states
 238  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 239  * and pp_dpm_pcie files and adjust the power state transition heuristics
 240  * via the pp_power_profile_mode sysfs file.
 241  *
 242  * profile_standard
 243  * profile_min_sclk
 244  * profile_min_mclk
 245  * profile_peak
 246  *
 247  * When the profiling modes are selected, clock and power gating are
 248  * disabled and the clocks are set for different profiling cases. This
 249  * mode is recommended for profiling specific work loads where you do
 250  * not want clock or power gating for clock fluctuation to interfere
 251  * with your results. profile_standard sets the clocks to a fixed clock
 252  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 253  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 254  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 255  *
 256  */
 257
 258 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 259                                                 struct device_attribute *attr,
 260                                                                 char *buf)
 261 {
 262         struct drm_device *ddev = dev_get_drvdata(dev);
 263         struct amdgpu_device *adev = ddev->dev_private;
 264         enum amd_dpm_forced_level level = 0xff;
 265
 266         if  ((adev->flags & AMD_IS_PX) &&
 267              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 268                 return snprintf(buf, PAGE_SIZE, "off\n");
 269
 270         if (is_support_sw_smu(adev))
 271                 level = smu_get_performance_level(&adev->smu);
 272         else if (adev->powerplay.pp_funcs->get_performance_level)
 273                 level = amdgpu_dpm_get_performance_level(adev);
 274         else
 275                 level = adev->pm.dpm.forced_level;
 276
 277         return snprintf(buf, PAGE_SIZE, "%s\n",
 278                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 279                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 280                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 281                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 282                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 283                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 284                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 285                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 286                         "unknown");
 287 }
 288
 289 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 290                                                        struct device_attribute *attr,
 291                                                        const char *buf,
 292                                                        size_t count)
 293 {
 294         struct drm_device *ddev = dev_get_drvdata(dev);
 295         struct amdgpu_device *adev = ddev->dev_private;
 296         enum amd_dpm_forced_level level;
 297         enum amd_dpm_forced_level current_level = 0xff;
 298         int ret = 0;
 299
 300         /* Can't force performance level when the card is off */
 301         if  ((adev->flags & AMD_IS_PX) &&
 302              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 303                 return -EINVAL;
 304
 305         if (is_support_sw_smu(adev))
 306                 current_level = smu_get_performance_level(&adev->smu);
 307         else if (adev->powerplay.pp_funcs->get_performance_level)
 308                 current_level = amdgpu_dpm_get_performance_level(adev);
 309
 310         if (strncmp("low", buf, strlen("low")) == 0) {
 311                 level = AMD_DPM_FORCED_LEVEL_LOW;
 312         } else if (strncmp("high", buf, strlen("high")) == 0) {
 313                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 314         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 315                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 316         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 317                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 318         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 319                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 320         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 321                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 322         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 323                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 324         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 325                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 326         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 327                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 328         }  else {
 329                 count = -EINVAL;
 330                 goto fail;
 331         }
 332
 333         if (amdgpu_sriov_vf(adev)) {
 334                 if (amdgim_is_hwperf(adev) &&
 335                     adev->virt.ops->force_dpm_level) {
 336                         mutex_lock(&adev->pm.mutex);
 337                         adev->virt.ops->force_dpm_level(adev, level);
 338                         mutex_unlock(&adev->pm.mutex);
 339                         return count;
 340                 } else {
 341                         return -EINVAL;
 342                 }
 343         }
 344
 345         if (current_level == level)
 346                 return count;
 347
 348         /* profile_exit setting is valid only when current mode is in profile mode */
 349         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 350             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 351             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 352             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 353             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 354                 pr_err("Currently not in any profile mode!\n");
 355                 return -EINVAL;
 356         }
 357
 358         if (is_support_sw_smu(adev)) {
 359                 mutex_lock(&adev->pm.mutex);
 360                 if (adev->pm.dpm.thermal_active) {
 361                         count = -EINVAL;
 362                         mutex_unlock(&adev->pm.mutex);
 363                         goto fail;
 364                 }
 365                 ret = smu_force_performance_level(&adev->smu, level);
 366                 if (ret)
 367                         count = -EINVAL;
 368                 else
 369                         adev->pm.dpm.forced_level = level;
 370                 mutex_unlock(&adev->pm.mutex);
 371         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 372                 mutex_lock(&adev->pm.mutex);
 373                 if (adev->pm.dpm.thermal_active) {
 374                         count = -EINVAL;
 375                         mutex_unlock(&adev->pm.mutex);
 376                         goto fail;
 377                 }
 378                 ret = amdgpu_dpm_force_performance_level(adev, level);
 379                 if (ret)
 380                         count = -EINVAL;
 381                 else
 382                         adev->pm.dpm.forced_level = level;
 383                 mutex_unlock(&adev->pm.mutex);
 384         }
 385
 386 fail:
 387         return count;
 388 }
 389
 390 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 391                 struct device_attribute *attr,
 392                 char *buf)
 393 {
 394         struct drm_device *ddev = dev_get_drvdata(dev);
 395         struct amdgpu_device *adev = ddev->dev_private;
 396         struct pp_states_info data;
 397         int i, buf_len, ret;
 398
 399         if (is_support_sw_smu(adev)) {
 400                 ret = smu_get_power_num_states(&adev->smu, &data);
 401                 if (ret)
 402                         return ret;
 403         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 404                 amdgpu_dpm_get_pp_num_states(adev, &data);
 405
 406         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 407         for (i = 0; i < data.nums; i++)
 408                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 409                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 410                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 411                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 412                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 413
 414         return buf_len;
 415 }
 416
 417 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 418                 struct device_attribute *attr,
 419                 char *buf)
 420 {
 421         struct drm_device *ddev = dev_get_drvdata(dev);
 422         struct amdgpu_device *adev = ddev->dev_private;
 423         struct pp_states_info data;
 424         struct smu_context *smu = &adev->smu;
 425         enum amd_pm_state_type pm = 0;
 426         int i = 0, ret = 0;
 427
 428         if (is_support_sw_smu(adev)) {
 429                 pm = smu_get_current_power_state(smu);
 430                 ret = smu_get_power_num_states(smu, &data);
 431                 if (ret)
 432                         return ret;
 433         } else if (adev->powerplay.pp_funcs->get_current_power_state
 434                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 435                 pm = amdgpu_dpm_get_current_power_state(adev);
 436                 amdgpu_dpm_get_pp_num_states(adev, &data);
 437         }
 438
 439         for (i = 0; i < data.nums; i++) {
 440                 if (pm == data.states[i])
 441                         break;
 442         }
 443
 444         if (i == data.nums)
 445                 i = -EINVAL;
 446
 447         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 448 }
 449
 450 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 451                 struct device_attribute *attr,
 452                 char *buf)
 453 {
 454         struct drm_device *ddev = dev_get_drvdata(dev);
 455         struct amdgpu_device *adev = ddev->dev_private;
 456
 457         if (adev->pp_force_state_enabled)
 458                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 459         else
 460                 return snprintf(buf, PAGE_SIZE, "\n");
 461 }
 462
 463 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 464                 struct device_attribute *attr,
 465                 const char *buf,
 466                 size_t count)
 467 {
 468         struct drm_device *ddev = dev_get_drvdata(dev);
 469         struct amdgpu_device *adev = ddev->dev_private;
 470         enum amd_pm_state_type state = 0;
 471         unsigned long idx;
 472         int ret;
 473
 474         if (strlen(buf) == 1)
 475                 adev->pp_force_state_enabled = false;
 476         else if (is_support_sw_smu(adev))
 477                 adev->pp_force_state_enabled = false;
 478         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 479                         adev->powerplay.pp_funcs->get_pp_num_states) {
 480                 struct pp_states_info data;
 481
 482                 ret = kstrtoul(buf, 0, &idx);
 483                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 484                         count = -EINVAL;
 485                         goto fail;
 486                 }
 487                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 488
 489                 amdgpu_dpm_get_pp_num_states(adev, &data);
 490                 state = data.states[idx];
 491                 /* only set user selected power states */
 492                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 493                     state != POWER_STATE_TYPE_DEFAULT) {
 494                         amdgpu_dpm_dispatch_task(adev,
 495                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 496                         adev->pp_force_state_enabled = true;
 497                 }
 498         }
 499 fail:
 500         return count;
 501 }
 502
 503 /**
 504  * DOC: pp_table
 505  *
 506  * The amdgpu driver provides a sysfs API for uploading new powerplay
 507  * tables.  The file pp_table is used for this.  Reading the file
 508  * will dump the current power play table.  Writing to the file
 509  * will attempt to upload a new powerplay table and re-initialize
 510  * powerplay using that new table.
 511  *
 512  */
 513
 514 static ssize_t amdgpu_get_pp_table(struct device *dev,
 515                 struct device_attribute *attr,
 516                 char *buf)
 517 {
 518         struct drm_device *ddev = dev_get_drvdata(dev);
 519         struct amdgpu_device *adev = ddev->dev_private;
 520         char *table = NULL;
 521         int size;
 522
 523         if (is_support_sw_smu(adev)) {
 524                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 525                 if (size < 0)
 526                         return size;
 527         }
 528         else if (adev->powerplay.pp_funcs->get_pp_table)
 529                 size = amdgpu_dpm_get_pp_table(adev, &table);
 530         else
 531                 return 0;
 532
 533         if (size >= PAGE_SIZE)
 534                 size = PAGE_SIZE - 1;
 535
 536         memcpy(buf, table, size);
 537
 538         return size;
 539 }
 540
 541 static ssize_t amdgpu_set_pp_table(struct device *dev,
 542                 struct device_attribute *attr,
 543                 const char *buf,
 544                 size_t count)
 545 {
 546         struct drm_device *ddev = dev_get_drvdata(dev);
 547         struct amdgpu_device *adev = ddev->dev_private;
 548         int ret = 0;
 549
 550         if (is_support_sw_smu(adev)) {
 551                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 552                 if (ret)
 553                         return ret;
 554         } else if (adev->powerplay.pp_funcs->set_pp_table)
 555                 amdgpu_dpm_set_pp_table(adev, buf, count);
 556
 557         return count;
 558 }
 559
 560 /**
 561  * DOC: pp_od_clk_voltage
 562  *
 563  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 564  * in each power level within a power state.  The pp_od_clk_voltage is used for
 565  * this.
 566  *
 567  * < For Vega10 and previous ASICs >
 568  *
 569  * Reading the file will display:
 570  *
 571  * - a list of engine clock levels and voltages labeled OD_SCLK
 572  *
 573  * - a list of memory clock levels and voltages labeled OD_MCLK
 574  *
 575  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 576  *
 577  * To manually adjust these settings, first select manual using
 578  * power_dpm_force_performance_level. Enter a new value for each
 579  * level by writing a string that contains "s/m level clock voltage" to
 580  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 581  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 582  * 810 mV.  When you have edited all of the states as needed, write
 583  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 584  * default power levels, write "r" (reset) to the file to reset them.
 585  *
 586  *
 587  * < For Vega20 >
 588  *
 589  * Reading the file will display:
 590  *
 591  * - minimum and maximum engine clock labeled OD_SCLK
 592  *
 593  * - maximum memory clock labeled OD_MCLK
 594  *
 595  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 596  *   They can be used to calibrate the sclk voltage curve.
 597  *
 598  * - a list of valid ranges for sclk, mclk, and voltage curve points
 599  *   labeled OD_RANGE
 600  *
 601  * To manually adjust these settings:
 602  *
 603  * - First select manual using power_dpm_force_performance_level
 604  *
 605  * - For clock frequency setting, enter a new value by writing a
 606  *   string that contains "s/m index clock" to the file. The index
 607  *   should be 0 if to set minimum clock. And 1 if to set maximum
 608  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 609  *   "m 1 800" will update maximum mclk to be 800Mhz.
 610  *
 611  *   For sclk voltage curve, enter the new values by writing a
 612  *   string that contains "vc point clock voltage" to the file. The
 613  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 614  *   update point1 with clock set as 300Mhz and voltage as
 615  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 616  *   as 1000Mhz and voltage 1000mV.
 617  *
 618  * - When you have edited all of the states as needed, write "c" (commit)
 619  *   to the file to commit your changes
 620  *
 621  * - If you want to reset to the default power levels, write "r" (reset)
 622  *   to the file to reset them
 623  *
 624  */
 625
 626 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 627                 struct device_attribute *attr,
 628                 const char *buf,
 629                 size_t count)
 630 {
 631         struct drm_device *ddev = dev_get_drvdata(dev);
 632         struct amdgpu_device *adev = ddev->dev_private;
 633         int ret;
 634         uint32_t parameter_size = 0;
 635         long parameter[64];
 636         char buf_cpy[128];
 637         char *tmp_str;
 638         char *sub_str;
 639         const char delimiter[3] = {' ', '\n', '\0'};
 640         uint32_t type;
 641
 642         if (count > 127)
 643                 return -EINVAL;
 644
 645         if (*buf == 's')
 646                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 647         else if (*buf == 'm')
 648                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 649         else if(*buf == 'r')
 650                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 651         else if (*buf == 'c')
 652                 type = PP_OD_COMMIT_DPM_TABLE;
 653         else if (!strncmp(buf, "vc", 2))
 654                 type = PP_OD_EDIT_VDDC_CURVE;
 655         else
 656                 return -EINVAL;
 657
 658         memcpy(buf_cpy, buf, count+1);
 659
 660         tmp_str = buf_cpy;
 661
 662         if (type == PP_OD_EDIT_VDDC_CURVE)
 663                 tmp_str++;
 664         while (isspace(*++tmp_str));
 665
 666         while (tmp_str[0]) {
 667                 sub_str = strsep(&tmp_str, delimiter);
 668                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 669                 if (ret)
 670                         return -EINVAL;
 671                 parameter_size++;
 672
 673                 while (isspace(*tmp_str))
 674                         tmp_str++;
 675         }
 676
 677         if (is_support_sw_smu(adev)) {
 678                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 679                                             parameter, parameter_size);
 680
 681                 if (ret)
 682                         return -EINVAL;
 683         } else {
 684                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 685                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 686                                                 parameter, parameter_size);
 687
 688                 if (ret)
 689                         return -EINVAL;
 690
 691                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 692                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 693                                 amdgpu_dpm_dispatch_task(adev,
 694                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 695                                                 NULL);
 696                                 return count;
 697                         } else {
 698                                 return -EINVAL;
 699                         }
 700                 }
 701         }
 702
 703         return count;
 704 }
 705
 706 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 707                 struct device_attribute *attr,
 708                 char *buf)
 709 {
 710         struct drm_device *ddev = dev_get_drvdata(dev);
 711         struct amdgpu_device *adev = ddev->dev_private;
 712         uint32_t size = 0;
 713
 714         if (is_support_sw_smu(adev)) {
 715                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 716                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 717                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 718                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 719                 return size;
 720         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 721                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 722                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 723                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 724                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 725                 return size;
 726         } else {
 727                 return snprintf(buf, PAGE_SIZE, "\n");
 728         }
 729
 730 }
 731
 732 /**
 733  * DOC: ppfeatures
 734  *
 735  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 736  * features to be enabled. The file ppfeatures is used for this. And
 737  * this is only available for Vega10 and later dGPUs.
 738  *
 739  * Reading back the file will show you the followings:
 740  * - Current ppfeature masks
 741  * - List of the all supported powerplay features with their naming,
 742  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 743  *
 744  * To manually enable or disable a specific feature, just set or clear
 745  * the corresponding bit from original ppfeature masks and input the
 746  * new ppfeature masks.
 747  */
 748 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 749                 struct device_attribute *attr,
 750                 const char *buf,
 751                 size_t count)
 752 {
 753         struct drm_device *ddev = dev_get_drvdata(dev);
 754         struct amdgpu_device *adev = ddev->dev_private;
 755         uint64_t featuremask;
 756         int ret;
 757
 758         ret = kstrtou64(buf, 0, &featuremask);
 759         if (ret)
 760                 return -EINVAL;
 761
 762         pr_debug("featuremask = 0x%llx\n", featuremask);
 763
 764         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 765                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 766                 if (ret)
 767                         return -EINVAL;
 768         }
 769
 770         return count;
 771 }
 772
 773 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 774                 struct device_attribute *attr,
 775                 char *buf)
 776 {
 777         struct drm_device *ddev = dev_get_drvdata(dev);
 778         struct amdgpu_device *adev = ddev->dev_private;
 779
 780         if (adev->powerplay.pp_funcs->get_ppfeature_status)
 781                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 782
 783         return snprintf(buf, PAGE_SIZE, "\n");
 784 }
 785
 786 /**
 787  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 788  * pp_dpm_pcie
 789  *
 790  * The amdgpu driver provides a sysfs API for adjusting what power levels
 791  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 792  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 793  * this.
 794  *
 795  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 796  * Vega10 and later ASICs.
 797  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 798  *
 799  * Reading back the files will show you the available power levels within
 800  * the power state and the clock information for those levels.
 801  *
 802  * To manually adjust these states, first select manual using
 803  * power_dpm_force_performance_level.
 804  * Secondly,Enter a new value for each level by inputing a string that
 805  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 806  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 807  *
 808  * NOTE: change to the dcefclk max dpm level is not supported now
 809  */
 810
 811 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 812                 struct device_attribute *attr,
 813                 char *buf)
 814 {
 815         struct drm_device *ddev = dev_get_drvdata(dev);
 816         struct amdgpu_device *adev = ddev->dev_private;
 817
 818         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 819             adev->virt.ops->get_pp_clk)
 820                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 821
 822         if (is_support_sw_smu(adev))
 823                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 824         else if (adev->powerplay.pp_funcs->print_clock_levels)
 825                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 826         else
 827                 return snprintf(buf, PAGE_SIZE, "\n");
 828 }
 829
 830 /*
 831  * Worst case: 32 bits individually specified, in octal at 12 characters
 832  * per line (+1 for \n).
 833  */
 834 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 835
 836 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 837 {
 838         int ret;
 839         long level;
 840         char *sub_str = NULL;
 841         char *tmp;
 842         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 843         const char delimiter[3] = {' ', '\n', '\0'};
 844         size_t bytes;
 845
 846         *mask = 0;
 847
 848         bytes = min(count, sizeof(buf_cpy) - 1);
 849         memcpy(buf_cpy, buf, bytes);
 850         buf_cpy[bytes] = '\0';
 851         tmp = buf_cpy;
 852         while (tmp[0]) {
 853                 sub_str = strsep(&tmp, delimiter);
 854                 if (strlen(sub_str)) {
 855                         ret = kstrtol(sub_str, 0, &level);
 856                         if (ret)
 857                                 return -EINVAL;
 858                         *mask |= 1 << level;
 859                 } else
 860                         break;
 861         }
 862
 863         return 0;
 864 }
 865
 866 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 867                 struct device_attribute *attr,
 868                 const char *buf,
 869                 size_t count)
 870 {
 871         struct drm_device *ddev = dev_get_drvdata(dev);
 872         struct amdgpu_device *adev = ddev->dev_private;
 873         int ret;
 874         uint32_t mask = 0;
 875
 876         ret = amdgpu_read_mask(buf, count, &mask);
 877         if (ret)
 878                 return ret;
 879
 880         if (is_support_sw_smu(adev))
 881                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 882         else if (adev->powerplay.pp_funcs->force_clock_level)
 883                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 884
 885         if (ret)
 886                 return -EINVAL;
 887
 888         return count;
 889 }
 890
 891 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 892                 struct device_attribute *attr,
 893                 char *buf)
 894 {
 895         struct drm_device *ddev = dev_get_drvdata(dev);
 896         struct amdgpu_device *adev = ddev->dev_private;
 897
 898         if (is_support_sw_smu(adev))
 899                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 900         else if (adev->powerplay.pp_funcs->print_clock_levels)
 901                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 902         else
 903                 return snprintf(buf, PAGE_SIZE, "\n");
 904 }
 905
 906 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 907                 struct device_attribute *attr,
 908                 const char *buf,
 909                 size_t count)
 910 {
 911         struct drm_device *ddev = dev_get_drvdata(dev);
 912         struct amdgpu_device *adev = ddev->dev_private;
 913         int ret;
 914         uint32_t mask = 0;
 915
 916         ret = amdgpu_read_mask(buf, count, &mask);
 917         if (ret)
 918                 return ret;
 919
 920         if (is_support_sw_smu(adev))
 921                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 922         else if (adev->powerplay.pp_funcs->force_clock_level)
 923                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 924
 925         if (ret)
 926                 return -EINVAL;
 927
 928         return count;
 929 }
 930
 931 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 932                 struct device_attribute *attr,
 933                 char *buf)
 934 {
 935         struct drm_device *ddev = dev_get_drvdata(dev);
 936         struct amdgpu_device *adev = ddev->dev_private;
 937
 938         if (is_support_sw_smu(adev))
 939                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 940         else if (adev->powerplay.pp_funcs->print_clock_levels)
 941                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 942         else
 943                 return snprintf(buf, PAGE_SIZE, "\n");
 944 }
 945
 946 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 947                 struct device_attribute *attr,
 948                 const char *buf,
 949                 size_t count)
 950 {
 951         struct drm_device *ddev = dev_get_drvdata(dev);
 952         struct amdgpu_device *adev = ddev->dev_private;
 953         int ret;
 954         uint32_t mask = 0;
 955
 956         ret = amdgpu_read_mask(buf, count, &mask);
 957         if (ret)
 958                 return ret;
 959
 960         if (is_support_sw_smu(adev))
 961                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 962         else if (adev->powerplay.pp_funcs->force_clock_level)
 963                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 964
 965         if (ret)
 966                 return -EINVAL;
 967
 968         return count;
 969 }
 970
 971 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 972                 struct device_attribute *attr,
 973                 char *buf)
 974 {
 975         struct drm_device *ddev = dev_get_drvdata(dev);
 976         struct amdgpu_device *adev = ddev->dev_private;
 977
 978         if (is_support_sw_smu(adev))
 979                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
 980         else if (adev->powerplay.pp_funcs->print_clock_levels)
 981                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 982         else
 983                 return snprintf(buf, PAGE_SIZE, "\n");
 984 }
 985
 986 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 987                 struct device_attribute *attr,
 988                 const char *buf,
 989                 size_t count)
 990 {
 991         struct drm_device *ddev = dev_get_drvdata(dev);
 992         struct amdgpu_device *adev = ddev->dev_private;
 993         int ret;
 994         uint32_t mask = 0;
 995
 996         ret = amdgpu_read_mask(buf, count, &mask);
 997         if (ret)
 998                 return ret;
 999
1000         if (is_support_sw_smu(adev))
1001                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
1002         else if (adev->powerplay.pp_funcs->force_clock_level)
1003                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1004
1005         if (ret)
1006                 return -EINVAL;
1007
1008         return count;
1009 }
1010
1011 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1012                 struct device_attribute *attr,
1013                 char *buf)
1014 {
1015         struct drm_device *ddev = dev_get_drvdata(dev);
1016         struct amdgpu_device *adev = ddev->dev_private;
1017
1018         if (is_support_sw_smu(adev))
1019                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
1020         else if (adev->powerplay.pp_funcs->print_clock_levels)
1021                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1022         else
1023                 return snprintf(buf, PAGE_SIZE, "\n");
1024 }
1025
1026 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1027                 struct device_attribute *attr,
1028                 const char *buf,
1029                 size_t count)
1030 {
1031         struct drm_device *ddev = dev_get_drvdata(dev);
1032         struct amdgpu_device *adev = ddev->dev_private;
1033         int ret;
1034         uint32_t mask = 0;
1035
1036         ret = amdgpu_read_mask(buf, count, &mask);
1037         if (ret)
1038                 return ret;
1039
1040         if (is_support_sw_smu(adev))
1041                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1042         else if (adev->powerplay.pp_funcs->force_clock_level)
1043                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1044
1045         if (ret)
1046                 return -EINVAL;
1047
1048         return count;
1049 }
1050
1051 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1052                 struct device_attribute *attr,
1053                 char *buf)
1054 {
1055         struct drm_device *ddev = dev_get_drvdata(dev);
1056         struct amdgpu_device *adev = ddev->dev_private;
1057
1058         if (is_support_sw_smu(adev))
1059                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1060         else if (adev->powerplay.pp_funcs->print_clock_levels)
1061                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1062         else
1063                 return snprintf(buf, PAGE_SIZE, "\n");
1064 }
1065
1066 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1067                 struct device_attribute *attr,
1068                 const char *buf,
1069                 size_t count)
1070 {
1071         struct drm_device *ddev = dev_get_drvdata(dev);
1072         struct amdgpu_device *adev = ddev->dev_private;
1073         int ret;
1074         uint32_t mask = 0;
1075
1076         ret = amdgpu_read_mask(buf, count, &mask);
1077         if (ret)
1078                 return ret;
1079
1080         if (is_support_sw_smu(adev))
1081                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1082         else if (adev->powerplay.pp_funcs->force_clock_level)
1083                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1084
1085         if (ret)
1086                 return -EINVAL;
1087
1088         return count;
1089 }
1090
1091 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1092                 struct device_attribute *attr,
1093                 char *buf)
1094 {
1095         struct drm_device *ddev = dev_get_drvdata(dev);
1096         struct amdgpu_device *adev = ddev->dev_private;
1097         uint32_t value = 0;
1098
1099         if (is_support_sw_smu(adev))
1100                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1101         else if (adev->powerplay.pp_funcs->get_sclk_od)
1102                 value = amdgpu_dpm_get_sclk_od(adev);
1103
1104         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1105 }
1106
1107 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1108                 struct device_attribute *attr,
1109                 const char *buf,
1110                 size_t count)
1111 {
1112         struct drm_device *ddev = dev_get_drvdata(dev);
1113         struct amdgpu_device *adev = ddev->dev_private;
1114         int ret;
1115         long int value;
1116
1117         ret = kstrtol(buf, 0, &value);
1118
1119         if (ret) {
1120                 count = -EINVAL;
1121                 goto fail;
1122         }
1123
1124         if (is_support_sw_smu(adev)) {
1125                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1126         } else {
1127                 if (adev->powerplay.pp_funcs->set_sclk_od)
1128                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1129
1130                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1131                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1132                 } else {
1133                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1134                         amdgpu_pm_compute_clocks(adev);
1135                 }
1136         }
1137
1138 fail:
1139         return count;
1140 }
1141
1142 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1143                 struct device_attribute *attr,
1144                 char *buf)
1145 {
1146         struct drm_device *ddev = dev_get_drvdata(dev);
1147         struct amdgpu_device *adev = ddev->dev_private;
1148         uint32_t value = 0;
1149
1150         if (is_support_sw_smu(adev))
1151                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1152         else if (adev->powerplay.pp_funcs->get_mclk_od)
1153                 value = amdgpu_dpm_get_mclk_od(adev);
1154
1155         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1156 }
1157
1158 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1159                 struct device_attribute *attr,
1160                 const char *buf,
1161                 size_t count)
1162 {
1163         struct drm_device *ddev = dev_get_drvdata(dev);
1164         struct amdgpu_device *adev = ddev->dev_private;
1165         int ret;
1166         long int value;
1167
1168         ret = kstrtol(buf, 0, &value);
1169
1170         if (ret) {
1171                 count = -EINVAL;
1172                 goto fail;
1173         }
1174
1175         if (is_support_sw_smu(adev)) {
1176                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1177         } else {
1178                 if (adev->powerplay.pp_funcs->set_mclk_od)
1179                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1180
1181                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1182                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1183                 } else {
1184                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1185                         amdgpu_pm_compute_clocks(adev);
1186                 }
1187         }
1188
1189 fail:
1190         return count;
1191 }
1192
1193 /**
1194  * DOC: pp_power_profile_mode
1195  *
1196  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1197  * related to switching between power levels in a power state.  The file
1198  * pp_power_profile_mode is used for this.
1199  *
1200  * Reading this file outputs a list of all of the predefined power profiles
1201  * and the relevant heuristics settings for that profile.
1202  *
1203  * To select a profile or create a custom profile, first select manual using
1204  * power_dpm_force_performance_level.  Writing the number of a predefined
1205  * profile to pp_power_profile_mode will enable those heuristics.  To
1206  * create a custom set of heuristics, write a string of numbers to the file
1207  * starting with the number of the custom profile along with a setting
1208  * for each heuristic parameter.  Due to differences across asic families
1209  * the heuristic parameters vary from family to family.
1210  *
1211  */
1212
1213 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1214                 struct device_attribute *attr,
1215                 char *buf)
1216 {
1217         struct drm_device *ddev = dev_get_drvdata(dev);
1218         struct amdgpu_device *adev = ddev->dev_private;
1219
1220         if (is_support_sw_smu(adev))
1221                 return smu_get_power_profile_mode(&adev->smu, buf);
1222         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1223                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1224
1225         return snprintf(buf, PAGE_SIZE, "\n");
1226 }
1227
1228
1229 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1230                 struct device_attribute *attr,
1231                 const char *buf,
1232                 size_t count)
1233 {
1234         int ret = 0xff;
1235         struct drm_device *ddev = dev_get_drvdata(dev);
1236         struct amdgpu_device *adev = ddev->dev_private;
1237         uint32_t parameter_size = 0;
1238         long parameter[64];
1239         char *sub_str, buf_cpy[128];
1240         char *tmp_str;
1241         uint32_t i = 0;
1242         char tmp[2];
1243         long int profile_mode = 0;
1244         const char delimiter[3] = {' ', '\n', '\0'};
1245
1246         tmp[0] = *(buf);
1247         tmp[1] = '\0';
1248         ret = kstrtol(tmp, 0, &profile_mode);
1249         if (ret)
1250                 goto fail;
1251
1252         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1253                 if (count < 2 || count > 127)
1254                         return -EINVAL;
1255                 while (isspace(*++buf))
1256                         i++;
1257                 memcpy(buf_cpy, buf, count-i);
1258                 tmp_str = buf_cpy;
1259                 while (tmp_str[0]) {
1260                         sub_str = strsep(&tmp_str, delimiter);
1261                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1262                         if (ret) {
1263                                 count = -EINVAL;
1264                                 goto fail;
1265                         }
1266                         parameter_size++;
1267                         while (isspace(*tmp_str))
1268                                 tmp_str++;
1269                 }
1270         }
1271         parameter[parameter_size] = profile_mode;
1272         if (is_support_sw_smu(adev))
1273                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1274         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1275                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1276         if (!ret)
1277                 return count;
1278 fail:
1279         return -EINVAL;
1280 }
1281
1282 /**
1283  * DOC: busy_percent
1284  *
1285  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1286  * is as a percentage.  The file gpu_busy_percent is used for this.
1287  * The SMU firmware computes a percentage of load based on the
1288  * aggregate activity level in the IP cores.
1289  */
1290 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1291                 struct device_attribute *attr,
1292                 char *buf)
1293 {
1294         struct drm_device *ddev = dev_get_drvdata(dev);
1295         struct amdgpu_device *adev = ddev->dev_private;
1296         int r, value, size = sizeof(value);
1297
1298         /* read the IP busy sensor */
1299         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1300                                    (void *)&value, &size);
1301
1302         if (r)
1303                 return r;
1304
1305         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1306 }
1307
1308 /**
1309  * DOC: pcie_bw
1310  *
1311  * The amdgpu driver provides a sysfs API for estimating how much data
1312  * has been received and sent by the GPU in the last second through PCIe.
1313  * The file pcie_bw is used for this.
1314  * The Perf counters count the number of received and sent messages and return
1315  * those values, as well as the maximum payload size of a PCIe packet (mps).
1316  * Note that it is not possible to easily and quickly obtain the size of each
1317  * packet transmitted, so we output the max payload size (mps) to allow for
1318  * quick estimation of the PCIe bandwidth usage
1319  */
1320 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1321                 struct device_attribute *attr,
1322                 char *buf)
1323 {
1324         struct drm_device *ddev = dev_get_drvdata(dev);
1325         struct amdgpu_device *adev = ddev->dev_private;
1326         uint64_t count0, count1;
1327
1328         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1329         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1330                         count0, count1, pcie_get_mps(adev->pdev));
1331 }
1332
1333 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1334 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1335                    amdgpu_get_dpm_forced_performance_level,
1336                    amdgpu_set_dpm_forced_performance_level);
1337 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1338 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1339 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1340                 amdgpu_get_pp_force_state,
1341                 amdgpu_set_pp_force_state);
1342 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1343                 amdgpu_get_pp_table,
1344                 amdgpu_set_pp_table);
1345 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1346                 amdgpu_get_pp_dpm_sclk,
1347                 amdgpu_set_pp_dpm_sclk);
1348 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1349                 amdgpu_get_pp_dpm_mclk,
1350                 amdgpu_set_pp_dpm_mclk);
1351 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1352                 amdgpu_get_pp_dpm_socclk,
1353                 amdgpu_set_pp_dpm_socclk);
1354 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1355                 amdgpu_get_pp_dpm_fclk,
1356                 amdgpu_set_pp_dpm_fclk);
1357 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1358                 amdgpu_get_pp_dpm_dcefclk,
1359                 amdgpu_set_pp_dpm_dcefclk);
1360 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1361                 amdgpu_get_pp_dpm_pcie,
1362                 amdgpu_set_pp_dpm_pcie);
1363 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1364                 amdgpu_get_pp_sclk_od,
1365                 amdgpu_set_pp_sclk_od);
1366 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1367                 amdgpu_get_pp_mclk_od,
1368                 amdgpu_set_pp_mclk_od);
1369 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1370                 amdgpu_get_pp_power_profile_mode,
1371                 amdgpu_set_pp_power_profile_mode);
1372 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1373                 amdgpu_get_pp_od_clk_voltage,
1374                 amdgpu_set_pp_od_clk_voltage);
1375 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1376                 amdgpu_get_busy_percent, NULL);
1377 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1378 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1379                 amdgpu_get_ppfeature_status,
1380                 amdgpu_set_ppfeature_status);
1381
1382 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1383                                       struct device_attribute *attr,
1384                                       char *buf)
1385 {
1386         struct amdgpu_device *adev = dev_get_drvdata(dev);
1387         struct drm_device *ddev = adev->ddev;
1388         int r, temp, size = sizeof(temp);
1389
1390         /* Can't get temperature when the card is off */
1391         if  ((adev->flags & AMD_IS_PX) &&
1392              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1393                 return -EINVAL;
1394
1395         /* get the temperature */
1396         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1397                                    (void *)&temp, &size);
1398         if (r)
1399                 return r;
1400
1401         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1402 }
1403
1404 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1405                                              struct device_attribute *attr,
1406                                              char *buf)
1407 {
1408         struct amdgpu_device *adev = dev_get_drvdata(dev);
1409         int hyst = to_sensor_dev_attr(attr)->index;
1410         int temp;
1411
1412         if (hyst)
1413                 temp = adev->pm.dpm.thermal.min_temp;
1414         else
1415                 temp = adev->pm.dpm.thermal.max_temp;
1416
1417         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1418 }
1419
1420 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1421                                             struct device_attribute *attr,
1422                                             char *buf)
1423 {
1424         struct amdgpu_device *adev = dev_get_drvdata(dev);
1425         u32 pwm_mode = 0;
1426         if (is_support_sw_smu(adev)) {
1427                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1428         } else {
1429                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1430                         return -EINVAL;
1431
1432                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1433         }
1434
1435         return sprintf(buf, "%i\n", pwm_mode);
1436 }
1437
1438 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1439                                             struct device_attribute *attr,
1440                                             const char *buf,
1441                                             size_t count)
1442 {
1443         struct amdgpu_device *adev = dev_get_drvdata(dev);
1444         int err;
1445         int value;
1446
1447         /* Can't adjust fan when the card is off */
1448         if  ((adev->flags & AMD_IS_PX) &&
1449              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1450                 return -EINVAL;
1451
1452         if (is_support_sw_smu(adev)) {
1453                 err = kstrtoint(buf, 10, &value);
1454                 if (err)
1455                         return err;
1456
1457                 smu_set_fan_control_mode(&adev->smu, value);
1458         } else {
1459                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1460                         return -EINVAL;
1461
1462                 err = kstrtoint(buf, 10, &value);
1463                 if (err)
1464                         return err;
1465
1466                 amdgpu_dpm_set_fan_control_mode(adev, value);
1467         }
1468
1469         return count;
1470 }
1471
1472 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1473                                          struct device_attribute *attr,
1474                                          char *buf)
1475 {
1476         return sprintf(buf, "%i\n", 0);
1477 }
1478
1479 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1480                                          struct device_attribute *attr,
1481                                          char *buf)
1482 {
1483         return sprintf(buf, "%i\n", 255);
1484 }
1485
1486 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1487                                      struct device_attribute *attr,
1488                                      const char *buf, size_t count)
1489 {
1490         struct amdgpu_device *adev = dev_get_drvdata(dev);
1491         int err;
1492         u32 value;
1493         u32 pwm_mode;
1494
1495         /* Can't adjust fan when the card is off */
1496         if  ((adev->flags & AMD_IS_PX) &&
1497              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1498                 return -EINVAL;
1499         if (is_support_sw_smu(adev))
1500                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1501         else
1502                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1503         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1504                 pr_info("manual fan speed control should be enabled first\n");
1505                 return -EINVAL;
1506         }
1507
1508         err = kstrtou32(buf, 10, &value);
1509         if (err)
1510                 return err;
1511
1512         value = (value * 100) / 255;
1513
1514         if (is_support_sw_smu(adev)) {
1515                 err = smu_set_fan_speed_percent(&adev->smu, value);
1516                 if (err)
1517                         return err;
1518         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1519                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1520                 if (err)
1521                         return err;
1522         }
1523
1524         return count;
1525 }
1526
1527 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1528                                      struct device_attribute *attr,
1529                                      char *buf)
1530 {
1531         struct amdgpu_device *adev = dev_get_drvdata(dev);
1532         int err;
1533         u32 speed = 0;
1534
1535         /* Can't adjust fan when the card is off */
1536         if  ((adev->flags & AMD_IS_PX) &&
1537              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1538                 return -EINVAL;
1539
1540         if (is_support_sw_smu(adev)) {
1541                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1542                 if (err)
1543                         return err;
1544         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1545                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1546                 if (err)
1547                         return err;
1548         }
1549
1550         speed = (speed * 255) / 100;
1551
1552         return sprintf(buf, "%i\n", speed);
1553 }
1554
1555 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1556                                            struct device_attribute *attr,
1557                                            char *buf)
1558 {
1559         struct amdgpu_device *adev = dev_get_drvdata(dev);
1560         int err;
1561         u32 speed = 0;
1562
1563         /* Can't adjust fan when the card is off */
1564         if  ((adev->flags & AMD_IS_PX) &&
1565              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1566                 return -EINVAL;
1567
1568         if (is_support_sw_smu(adev)) {
1569                 err = smu_get_current_rpm(&adev->smu, &speed);
1570                 if (err)
1571                         return err;
1572         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1573                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1574                 if (err)
1575                         return err;
1576         }
1577
1578         return sprintf(buf, "%i\n", speed);
1579 }
1580
1581 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1582                                          struct device_attribute *attr,
1583                                          char *buf)
1584 {
1585         struct amdgpu_device *adev = dev_get_drvdata(dev);
1586         u32 min_rpm = 0;
1587         u32 size = sizeof(min_rpm);
1588         int r;
1589
1590         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1591                                    (void *)&min_rpm, &size);
1592         if (r)
1593                 return r;
1594
1595         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1596 }
1597
1598 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1599                                          struct device_attribute *attr,
1600                                          char *buf)
1601 {
1602         struct amdgpu_device *adev = dev_get_drvdata(dev);
1603         u32 max_rpm = 0;
1604         u32 size = sizeof(max_rpm);
1605         int r;
1606
1607         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1608                                    (void *)&max_rpm, &size);
1609         if (r)
1610                 return r;
1611
1612         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1613 }
1614
1615 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1616                                            struct device_attribute *attr,
1617                                            char *buf)
1618 {
1619         struct amdgpu_device *adev = dev_get_drvdata(dev);
1620         int err;
1621         u32 rpm = 0;
1622
1623         /* Can't adjust fan when the card is off */
1624         if  ((adev->flags & AMD_IS_PX) &&
1625              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1626                 return -EINVAL;
1627
1628         if (is_support_sw_smu(adev)) {
1629                 err = smu_get_current_rpm(&adev->smu, &rpm);
1630                 if (err)
1631                         return err;
1632         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1633                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1634                 if (err)
1635                         return err;
1636         }
1637
1638         return sprintf(buf, "%i\n", rpm);
1639 }
1640
1641 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1642                                      struct device_attribute *attr,
1643                                      const char *buf, size_t count)
1644 {
1645         struct amdgpu_device *adev = dev_get_drvdata(dev);
1646         int err;
1647         u32 value;
1648         u32 pwm_mode;
1649
1650         if (is_support_sw_smu(adev))
1651                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1652         else
1653                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1654
1655         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1656                 return -ENODATA;
1657
1658         /* Can't adjust fan when the card is off */
1659         if  ((adev->flags & AMD_IS_PX) &&
1660              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1661                 return -EINVAL;
1662
1663         err = kstrtou32(buf, 10, &value);
1664         if (err)
1665                 return err;
1666
1667         if (is_support_sw_smu(adev)) {
1668                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1669                 if (err)
1670                         return err;
1671         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1672                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1673                 if (err)
1674                         return err;
1675         }
1676
1677         return count;
1678 }
1679
1680 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1681                                             struct device_attribute *attr,
1682                                             char *buf)
1683 {
1684         struct amdgpu_device *adev = dev_get_drvdata(dev);
1685         u32 pwm_mode = 0;
1686
1687         if (is_support_sw_smu(adev)) {
1688                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1689         } else {
1690                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1691                         return -EINVAL;
1692
1693                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1694         }
1695         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1696 }
1697
1698 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1699                                             struct device_attribute *attr,
1700                                             const char *buf,
1701                                             size_t count)
1702 {
1703         struct amdgpu_device *adev = dev_get_drvdata(dev);
1704         int err;
1705         int value;
1706         u32 pwm_mode;
1707
1708         /* Can't adjust fan when the card is off */
1709         if  ((adev->flags & AMD_IS_PX) &&
1710              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1711                 return -EINVAL;
1712
1713
1714         err = kstrtoint(buf, 10, &value);
1715         if (err)
1716                 return err;
1717
1718         if (value == 0)
1719                 pwm_mode = AMD_FAN_CTRL_AUTO;
1720         else if (value == 1)
1721                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1722         else
1723                 return -EINVAL;
1724
1725         if (is_support_sw_smu(adev)) {
1726                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1727         } else {
1728                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1729                         return -EINVAL;
1730                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1731         }
1732
1733         return count;
1734 }
1735
1736 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1737                                         struct device_attribute *attr,
1738                                         char *buf)
1739 {
1740         struct amdgpu_device *adev = dev_get_drvdata(dev);
1741         struct drm_device *ddev = adev->ddev;
1742         u32 vddgfx;
1743         int r, size = sizeof(vddgfx);
1744
1745         /* Can't get voltage when the card is off */
1746         if  ((adev->flags & AMD_IS_PX) &&
1747              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1748                 return -EINVAL;
1749
1750         /* get the voltage */
1751         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1752                                    (void *)&vddgfx, &size);
1753         if (r)
1754                 return r;
1755
1756         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1757 }
1758
1759 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1760                                               struct device_attribute *attr,
1761                                               char *buf)
1762 {
1763         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1764 }
1765
1766 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1767                                        struct device_attribute *attr,
1768                                        char *buf)
1769 {
1770         struct amdgpu_device *adev = dev_get_drvdata(dev);
1771         struct drm_device *ddev = adev->ddev;
1772         u32 vddnb;
1773         int r, size = sizeof(vddnb);
1774
1775         /* only APUs have vddnb */
1776         if  (!(adev->flags & AMD_IS_APU))
1777                 return -EINVAL;
1778
1779         /* Can't get voltage when the card is off */
1780         if  ((adev->flags & AMD_IS_PX) &&
1781              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1782                 return -EINVAL;
1783
1784         /* get the voltage */
1785         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1786                                    (void *)&vddnb, &size);
1787         if (r)
1788                 return r;
1789
1790         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1791 }
1792
1793 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1794                                               struct device_attribute *attr,
1795                                               char *buf)
1796 {
1797         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1798 }
1799
1800 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1801                                            struct device_attribute *attr,
1802                                            char *buf)
1803 {
1804         struct amdgpu_device *adev = dev_get_drvdata(dev);
1805         struct drm_device *ddev = adev->ddev;
1806         u32 query = 0;
1807         int r, size = sizeof(u32);
1808         unsigned uw;
1809
1810         /* Can't get power when the card is off */
1811         if  ((adev->flags & AMD_IS_PX) &&
1812              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1813                 return -EINVAL;
1814
1815         /* get the voltage */
1816         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1817                                    (void *)&query, &size);
1818         if (r)
1819                 return r;
1820
1821         /* convert to microwatts */
1822         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1823
1824         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1825 }
1826
1827 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1828                                          struct device_attribute *attr,
1829                                          char *buf)
1830 {
1831         return sprintf(buf, "%i\n", 0);
1832 }
1833
1834 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1835                                          struct device_attribute *attr,
1836                                          char *buf)
1837 {
1838         struct amdgpu_device *adev = dev_get_drvdata(dev);
1839         uint32_t limit = 0;
1840
1841         if (is_support_sw_smu(adev)) {
1842                 smu_get_power_limit(&adev->smu, &limit, true);
1843                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1844         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1845                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1846                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1847         } else {
1848                 return snprintf(buf, PAGE_SIZE, "\n");
1849         }
1850 }
1851
1852 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1853                                          struct device_attribute *attr,
1854                                          char *buf)
1855 {
1856         struct amdgpu_device *adev = dev_get_drvdata(dev);
1857         uint32_t limit = 0;
1858
1859         if (is_support_sw_smu(adev)) {
1860                 smu_get_power_limit(&adev->smu, &limit, false);
1861                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1862         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1863                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1864                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1865         } else {
1866                 return snprintf(buf, PAGE_SIZE, "\n");
1867         }
1868 }
1869
1870
1871 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1872                 struct device_attribute *attr,
1873                 const char *buf,
1874                 size_t count)
1875 {
1876         struct amdgpu_device *adev = dev_get_drvdata(dev);
1877         int err;
1878         u32 value;
1879
1880         err = kstrtou32(buf, 10, &value);
1881         if (err)
1882                 return err;
1883
1884         value = value / 1000000; /* convert to Watt */
1885         if (is_support_sw_smu(adev)) {
1886                 adev->smu.funcs->set_power_limit(&adev->smu, value);
1887         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1888                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1889                 if (err)
1890                         return err;
1891         } else {
1892                 return -EINVAL;
1893         }
1894
1895         return count;
1896 }
1897
1898 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
1899                                       struct device_attribute *attr,
1900                                       char *buf)
1901 {
1902         struct amdgpu_device *adev = dev_get_drvdata(dev);
1903         struct drm_device *ddev = adev->ddev;
1904         uint32_t sclk;
1905         int r, size = sizeof(sclk);
1906
1907         /* Can't get voltage when the card is off */
1908         if  ((adev->flags & AMD_IS_PX) &&
1909              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1910                 return -EINVAL;
1911
1912         /* sanity check PP is enabled */
1913         if (!(adev->powerplay.pp_funcs &&
1914               adev->powerplay.pp_funcs->read_sensor))
1915               return -EINVAL;
1916
1917         /* get the sclk */
1918         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
1919                                    (void *)&sclk, &size);
1920         if (r)
1921                 return r;
1922
1923         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
1924 }
1925
1926 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
1927                                             struct device_attribute *attr,
1928                                             char *buf)
1929 {
1930         return snprintf(buf, PAGE_SIZE, "sclk\n");
1931 }
1932
1933 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
1934                                       struct device_attribute *attr,
1935                                       char *buf)
1936 {
1937         struct amdgpu_device *adev = dev_get_drvdata(dev);
1938         struct drm_device *ddev = adev->ddev;
1939         uint32_t mclk;
1940         int r, size = sizeof(mclk);
1941
1942         /* Can't get voltage when the card is off */
1943         if  ((adev->flags & AMD_IS_PX) &&
1944              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1945                 return -EINVAL;
1946
1947         /* sanity check PP is enabled */
1948         if (!(adev->powerplay.pp_funcs &&
1949               adev->powerplay.pp_funcs->read_sensor))
1950               return -EINVAL;
1951
1952         /* get the sclk */
1953         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
1954                                    (void *)&mclk, &size);
1955         if (r)
1956                 return r;
1957
1958         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
1959 }
1960
1961 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
1962                                             struct device_attribute *attr,
1963                                             char *buf)
1964 {
1965         return snprintf(buf, PAGE_SIZE, "mclk\n");
1966 }
1967
1968 /**
1969  * DOC: hwmon
1970  *
1971  * The amdgpu driver exposes the following sensor interfaces:
1972  *
1973  * - GPU temperature (via the on-die sensor)
1974  *
1975  * - GPU voltage
1976  *
1977  * - Northbridge voltage (APUs only)
1978  *
1979  * - GPU power
1980  *
1981  * - GPU fan
1982  *
1983  * - GPU gfx/compute engine clock
1984  *
1985  * - GPU memory clock (dGPU only)
1986  *
1987  * hwmon interfaces for GPU temperature:
1988  *
1989  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1990  *
1991  * - temp1_crit: temperature critical max value in millidegrees Celsius
1992  *
1993  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1994  *
1995  * hwmon interfaces for GPU voltage:
1996  *
1997  * - in0_input: the voltage on the GPU in millivolts
1998  *
1999  * - in1_input: the voltage on the Northbridge in millivolts
2000  *
2001  * hwmon interfaces for GPU power:
2002  *
2003  * - power1_average: average power used by the GPU in microWatts
2004  *
2005  * - power1_cap_min: minimum cap supported in microWatts
2006  *
2007  * - power1_cap_max: maximum cap supported in microWatts
2008  *
2009  * - power1_cap: selected power cap in microWatts
2010  *
2011  * hwmon interfaces for GPU fan:
2012  *
2013  * - pwm1: pulse width modulation fan level (0-255)
2014  *
2015  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2016  *
2017  * - pwm1_min: pulse width modulation fan control minimum level (0)
2018  *
2019  * - pwm1_max: pulse width modulation fan control maximum level (255)
2020  *
2021  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2022  *
2023  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2024  *
2025  * - fan1_input: fan speed in RPM
2026  *
2027  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2028  *
2029  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2030  *
2031  * hwmon interfaces for GPU clocks:
2032  *
2033  * - freq1_input: the gfx/compute clock in hertz
2034  *
2035  * - freq2_input: the memory clock in hertz
2036  *
2037  * You can use hwmon tools like sensors to view this information on your system.
2038  *
2039  */
2040
2041 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
2042 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2043 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2044 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2045 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2046 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2047 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2048 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2049 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2050 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2051 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2052 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2053 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2054 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2055 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2056 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2057 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2058 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2059 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2060 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2061 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2062 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2063 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2064 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2065
2066 static struct attribute *hwmon_attributes[] = {
2067         &sensor_dev_attr_temp1_input.dev_attr.attr,
2068         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2069         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2070         &sensor_dev_attr_pwm1.dev_attr.attr,
2071         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2072         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2073         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2074         &sensor_dev_attr_fan1_input.dev_attr.attr,
2075         &sensor_dev_attr_fan1_min.dev_attr.attr,
2076         &sensor_dev_attr_fan1_max.dev_attr.attr,
2077         &sensor_dev_attr_fan1_target.dev_attr.attr,
2078         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2079         &sensor_dev_attr_in0_input.dev_attr.attr,
2080         &sensor_dev_attr_in0_label.dev_attr.attr,
2081         &sensor_dev_attr_in1_input.dev_attr.attr,
2082         &sensor_dev_attr_in1_label.dev_attr.attr,
2083         &sensor_dev_attr_power1_average.dev_attr.attr,
2084         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2085         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2086         &sensor_dev_attr_power1_cap.dev_attr.attr,
2087         &sensor_dev_attr_freq1_input.dev_attr.attr,
2088         &sensor_dev_attr_freq1_label.dev_attr.attr,
2089         &sensor_dev_attr_freq2_input.dev_attr.attr,
2090         &sensor_dev_attr_freq2_label.dev_attr.attr,
2091         NULL
2092 };
2093
2094 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2095                                         struct attribute *attr, int index)
2096 {
2097         struct device *dev = kobj_to_dev(kobj);
2098         struct amdgpu_device *adev = dev_get_drvdata(dev);
2099         umode_t effective_mode = attr->mode;
2100
2101         /* Skip fan attributes if fan is not present */
2102         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2103             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2104             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2105             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2106             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2107             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2108             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2109             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2110             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2111                 return 0;
2112
2113         /* Skip fan attributes on APU */
2114         if ((adev->flags & AMD_IS_APU) &&
2115             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2116              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2117              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2118              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2119              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2120              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2121              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2122              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2123              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2124                 return 0;
2125
2126         /* Skip limit attributes if DPM is not enabled */
2127         if (!adev->pm.dpm_enabled &&
2128             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2129              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2130              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2131              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2132              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2133              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2134              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2135              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2136              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2137              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2138              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2139                 return 0;
2140
2141         if (!is_support_sw_smu(adev)) {
2142                 /* mask fan attributes if we have no bindings for this asic to expose */
2143                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2144                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2145                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2146                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2147                         effective_mode &= ~S_IRUGO;
2148
2149                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2150                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2151                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2152                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2153                         effective_mode &= ~S_IWUSR;
2154         }
2155
2156         if ((adev->flags & AMD_IS_APU) &&
2157             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2158              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2159              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2160              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2161                 return 0;
2162
2163         if (!is_support_sw_smu(adev)) {
2164                 /* hide max/min values if we can't both query and manage the fan */
2165                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2166                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2167                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2168                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2169                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2170                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2171                         return 0;
2172
2173                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2174                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2175                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2176                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2177                         return 0;
2178         }
2179
2180         /* only APUs have vddnb */
2181         if (!(adev->flags & AMD_IS_APU) &&
2182             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2183              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2184                 return 0;
2185
2186         /* no mclk on APUs */
2187         if ((adev->flags & AMD_IS_APU) &&
2188             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2189              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2190                 return 0;
2191
2192         return effective_mode;
2193 }
2194
2195 static const struct attribute_group hwmon_attrgroup = {
2196         .attrs = hwmon_attributes,
2197         .is_visible = hwmon_attributes_visible,
2198 };
2199
2200 static const struct attribute_group *hwmon_groups[] = {
2201         &hwmon_attrgroup,
2202         NULL
2203 };
2204
2205 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2206 {
2207         struct amdgpu_device *adev =
2208                 container_of(work, struct amdgpu_device,
2209                              pm.dpm.thermal.work);
2210         /* switch to the thermal state */
2211         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2212         int temp, size = sizeof(temp);
2213
2214         if (!adev->pm.dpm_enabled)
2215                 return;
2216
2217         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2218                                     (void *)&temp, &size)) {
2219                 if (temp < adev->pm.dpm.thermal.min_temp)
2220                         /* switch back the user state */
2221                         dpm_state = adev->pm.dpm.user_state;
2222         } else {
2223                 if (adev->pm.dpm.thermal.high_to_low)
2224                         /* switch back the user state */
2225                         dpm_state = adev->pm.dpm.user_state;
2226         }
2227         mutex_lock(&adev->pm.mutex);
2228         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2229                 adev->pm.dpm.thermal_active = true;
2230         else
2231                 adev->pm.dpm.thermal_active = false;
2232         adev->pm.dpm.state = dpm_state;
2233         mutex_unlock(&adev->pm.mutex);
2234
2235         amdgpu_pm_compute_clocks(adev);
2236 }
2237
2238 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2239                                                      enum amd_pm_state_type dpm_state)
2240 {
2241         int i;
2242         struct amdgpu_ps *ps;
2243         u32 ui_class;
2244         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2245                 true : false;
2246
2247         /* check if the vblank period is too short to adjust the mclk */
2248         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2249                 if (amdgpu_dpm_vblank_too_short(adev))
2250                         single_display = false;
2251         }
2252
2253         /* certain older asics have a separare 3D performance state,
2254          * so try that first if the user selected performance
2255          */
2256         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2257                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2258         /* balanced states don't exist at the moment */
2259         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2260                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2261
2262 restart_search:
2263         /* Pick the best power state based on current conditions */
2264         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2265                 ps = &adev->pm.dpm.ps[i];
2266                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2267                 switch (dpm_state) {
2268                 /* user states */
2269                 case POWER_STATE_TYPE_BATTERY:
2270                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2271                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2272                                         if (single_display)
2273                                                 return ps;
2274                                 } else
2275                                         return ps;
2276                         }
2277                         break;
2278                 case POWER_STATE_TYPE_BALANCED:
2279                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2280                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2281                                         if (single_display)
2282                                                 return ps;
2283                                 } else
2284                                         return ps;
2285                         }
2286                         break;
2287                 case POWER_STATE_TYPE_PERFORMANCE:
2288                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2289                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2290                                         if (single_display)
2291                                                 return ps;
2292                                 } else
2293                                         return ps;
2294                         }
2295                         break;
2296                 /* internal states */
2297                 case POWER_STATE_TYPE_INTERNAL_UVD:
2298                         if (adev->pm.dpm.uvd_ps)
2299                                 return adev->pm.dpm.uvd_ps;
2300                         else
2301                                 break;
2302                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2303                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2304                                 return ps;
2305                         break;
2306                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2307                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2308                                 return ps;
2309                         break;
2310                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2311                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2312                                 return ps;
2313                         break;
2314                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2315                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2316                                 return ps;
2317                         break;
2318                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2319                         return adev->pm.dpm.boot_ps;
2320                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2321                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2322                                 return ps;
2323                         break;
2324                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2325                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2326                                 return ps;
2327                         break;
2328                 case POWER_STATE_TYPE_INTERNAL_ULV:
2329                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2330                                 return ps;
2331                         break;
2332                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2333                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2334                                 return ps;
2335                         break;
2336                 default:
2337                         break;
2338                 }
2339         }
2340         /* use a fallback state if we didn't match */
2341         switch (dpm_state) {
2342         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2343                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2344                 goto restart_search;
2345         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2346         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2347         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2348                 if (adev->pm.dpm.uvd_ps) {
2349                         return adev->pm.dpm.uvd_ps;
2350                 } else {
2351                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2352                         goto restart_search;
2353                 }
2354         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2355                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2356                 goto restart_search;
2357         case POWER_STATE_TYPE_INTERNAL_ACPI:
2358                 dpm_state = POWER_STATE_TYPE_BATTERY;
2359                 goto restart_search;
2360         case POWER_STATE_TYPE_BATTERY:
2361         case POWER_STATE_TYPE_BALANCED:
2362         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2363                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2364                 goto restart_search;
2365         default:
2366                 break;
2367         }
2368
2369         return NULL;
2370 }
2371
2372 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2373 {
2374         struct amdgpu_ps *ps;
2375         enum amd_pm_state_type dpm_state;
2376         int ret;
2377         bool equal = false;
2378
2379         /* if dpm init failed */
2380         if (!adev->pm.dpm_enabled)
2381                 return;
2382
2383         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2384                 /* add other state override checks here */
2385                 if ((!adev->pm.dpm.thermal_active) &&
2386                     (!adev->pm.dpm.uvd_active))
2387                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2388         }
2389         dpm_state = adev->pm.dpm.state;
2390
2391         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2392         if (ps)
2393                 adev->pm.dpm.requested_ps = ps;
2394         else
2395                 return;
2396
2397         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2398                 printk("switching from power state:\n");
2399                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2400                 printk("switching to power state:\n");
2401                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2402         }
2403
2404         /* update whether vce is active */
2405         ps->vce_active = adev->pm.dpm.vce_active;
2406         if (adev->powerplay.pp_funcs->display_configuration_changed)
2407                 amdgpu_dpm_display_configuration_changed(adev);
2408
2409         ret = amdgpu_dpm_pre_set_power_state(adev);
2410         if (ret)
2411                 return;
2412
2413         if (adev->powerplay.pp_funcs->check_state_equal) {
2414                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2415                         equal = false;
2416         }
2417
2418         if (equal)
2419                 return;
2420
2421         amdgpu_dpm_set_power_state(adev);
2422         amdgpu_dpm_post_set_power_state(adev);
2423
2424         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2425         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2426
2427         if (adev->powerplay.pp_funcs->force_performance_level) {
2428                 if (adev->pm.dpm.thermal_active) {
2429                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2430                         /* force low perf level for thermal */
2431                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2432                         /* save the user's level */
2433                         adev->pm.dpm.forced_level = level;
2434                 } else {
2435                         /* otherwise, user selected level */
2436                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2437                 }
2438         }
2439 }
2440
2441 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2442 {
2443         int ret = 0;
2444         if (is_support_sw_smu(adev)) {
2445             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2446             if (ret)
2447                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2448                           enable ? "true" : "false", ret);
2449         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2450                 /* enable/disable UVD */
2451                 mutex_lock(&adev->pm.mutex);
2452                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2453                 mutex_unlock(&adev->pm.mutex);
2454         }
2455         /* enable/disable Low Memory PState for UVD (4k videos) */
2456         if (adev->asic_type == CHIP_STONEY &&
2457                 adev->uvd.decode_image_width >= WIDTH_4K) {
2458                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2459
2460                 if (hwmgr && hwmgr->hwmgr_func &&
2461                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2462                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2463                                                                !enable,
2464                                                                true);
2465         }
2466 }
2467
2468 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2469 {
2470         int ret = 0;
2471         if (is_support_sw_smu(adev)) {
2472             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2473             if (ret)
2474                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2475                           enable ? "true" : "false", ret);
2476         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2477                 /* enable/disable VCE */
2478                 mutex_lock(&adev->pm.mutex);
2479                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2480                 mutex_unlock(&adev->pm.mutex);
2481         }
2482 }
2483
2484 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2485 {
2486         int i;
2487
2488         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2489                 return;
2490
2491         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2492                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2493
2494 }
2495
2496 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2497 {
2498         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2499         int ret;
2500
2501         if (adev->pm.sysfs_initialized)
2502                 return 0;
2503
2504         if (adev->pm.dpm_enabled == 0)
2505                 return 0;
2506
2507         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2508                                                                    DRIVER_NAME, adev,
2509                                                                    hwmon_groups);
2510         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2511                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2512                 dev_err(adev->dev,
2513                         "Unable to register hwmon device: %d\n", ret);
2514                 return ret;
2515         }
2516
2517         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2518         if (ret) {
2519                 DRM_ERROR("failed to create device file for dpm state\n");
2520                 return ret;
2521         }
2522         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2523         if (ret) {
2524                 DRM_ERROR("failed to create device file for dpm state\n");
2525                 return ret;
2526         }
2527
2528
2529         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2530         if (ret) {
2531                 DRM_ERROR("failed to create device file pp_num_states\n");
2532                 return ret;
2533         }
2534         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2535         if (ret) {
2536                 DRM_ERROR("failed to create device file pp_cur_state\n");
2537                 return ret;
2538         }
2539         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2540         if (ret) {
2541                 DRM_ERROR("failed to create device file pp_force_state\n");
2542                 return ret;
2543         }
2544         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2545         if (ret) {
2546                 DRM_ERROR("failed to create device file pp_table\n");
2547                 return ret;
2548         }
2549
2550         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2551         if (ret) {
2552                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2553                 return ret;
2554         }
2555         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2556         if (ret) {
2557                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2558                 return ret;
2559         }
2560         if (adev->asic_type >= CHIP_VEGA10) {
2561                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2562                 if (ret) {
2563                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2564                         return ret;
2565                 }
2566                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2567                 if (ret) {
2568                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2569                         return ret;
2570                 }
2571         }
2572         if (adev->asic_type >= CHIP_VEGA20) {
2573                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2574                 if (ret) {
2575                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2576                         return ret;
2577                 }
2578         }
2579         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2580         if (ret) {
2581                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2582                 return ret;
2583         }
2584         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2585         if (ret) {
2586                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2587                 return ret;
2588         }
2589         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2590         if (ret) {
2591                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2592                 return ret;
2593         }
2594         ret = device_create_file(adev->dev,
2595                         &dev_attr_pp_power_profile_mode);
2596         if (ret) {
2597                 DRM_ERROR("failed to create device file "
2598                                 "pp_power_profile_mode\n");
2599                 return ret;
2600         }
2601         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2602             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2603                 ret = device_create_file(adev->dev,
2604                                 &dev_attr_pp_od_clk_voltage);
2605                 if (ret) {
2606                         DRM_ERROR("failed to create device file "
2607                                         "pp_od_clk_voltage\n");
2608                         return ret;
2609                 }
2610         }
2611         ret = device_create_file(adev->dev,
2612                         &dev_attr_gpu_busy_percent);
2613         if (ret) {
2614                 DRM_ERROR("failed to create device file "
2615                                 "gpu_busy_level\n");
2616                 return ret;
2617         }
2618         /* PCIe Perf counters won't work on APU nodes */
2619         if (!(adev->flags & AMD_IS_APU)) {
2620                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2621                 if (ret) {
2622                         DRM_ERROR("failed to create device file pcie_bw\n");
2623                         return ret;
2624                 }
2625         }
2626         ret = amdgpu_debugfs_pm_init(adev);
2627         if (ret) {
2628                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2629                 return ret;
2630         }
2631
2632         if ((adev->asic_type >= CHIP_VEGA10) &&
2633             !(adev->flags & AMD_IS_APU)) {
2634                 ret = device_create_file(adev->dev,
2635                                 &dev_attr_ppfeatures);
2636                 if (ret) {
2637                         DRM_ERROR("failed to create device file "
2638                                         "ppfeatures\n");
2639                         return ret;
2640                 }
2641         }
2642
2643         adev->pm.sysfs_initialized = true;
2644
2645         return 0;
2646 }
2647
2648 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2649 {
2650         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2651
2652         if (adev->pm.dpm_enabled == 0)
2653                 return;
2654
2655         if (adev->pm.int_hwmon_dev)
2656                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2657         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2658         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2659
2660         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2661         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2662         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2663         device_remove_file(adev->dev, &dev_attr_pp_table);
2664
2665         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2666         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2667         if (adev->asic_type >= CHIP_VEGA10) {
2668                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2669                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2670         }
2671         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2672         if (adev->asic_type >= CHIP_VEGA20)
2673                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2674         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2675         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2676         device_remove_file(adev->dev,
2677                         &dev_attr_pp_power_profile_mode);
2678         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2679             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2680                 device_remove_file(adev->dev,
2681                                 &dev_attr_pp_od_clk_voltage);
2682         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2683         if (!(adev->flags & AMD_IS_APU))
2684                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2685         if ((adev->asic_type >= CHIP_VEGA10) &&
2686             !(adev->flags & AMD_IS_APU))
2687                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2688 }
2689
2690 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2691 {
2692         int i = 0;
2693
2694         if (!adev->pm.dpm_enabled)
2695                 return;
2696
2697         if (adev->mode_info.num_crtc)
2698                 amdgpu_display_bandwidth_update(adev);
2699
2700         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2701                 struct amdgpu_ring *ring = adev->rings[i];
2702                 if (ring && ring->sched.ready)
2703                         amdgpu_fence_wait_empty(ring);
2704         }
2705
2706         if (is_support_sw_smu(adev)) {
2707                 struct smu_context *smu = &adev->smu;
2708                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2709                 mutex_lock(&(smu->mutex));
2710                 smu_handle_task(&adev->smu,
2711                                 smu_dpm->dpm_level,
2712                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2713                 mutex_unlock(&(smu->mutex));
2714         } else {
2715                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2716                         if (!amdgpu_device_has_dc_support(adev)) {
2717                                 mutex_lock(&adev->pm.mutex);
2718                                 amdgpu_dpm_get_active_displays(adev);
2719                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2720                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2721                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2722                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2723                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
2724                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
2725                                 if (adev->powerplay.pp_funcs->display_configuration_change)
2726                                         adev->powerplay.pp_funcs->display_configuration_change(
2727                                                                         adev->powerplay.pp_handle,
2728                                                                         &adev->pm.pm_display_cfg);
2729                                 mutex_unlock(&adev->pm.mutex);
2730                         }
2731                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2732                 } else {
2733                         mutex_lock(&adev->pm.mutex);
2734                         amdgpu_dpm_get_active_displays(adev);
2735                         amdgpu_dpm_change_power_state_locked(adev);
2736                         mutex_unlock(&adev->pm.mutex);
2737                 }
2738         }
2739 }
2740
2741 /*
2742  * Debugfs info
2743  */
2744 #if defined(CONFIG_DEBUG_FS)
2745
2746 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2747 {
2748         uint32_t value;
2749         uint64_t value64;
2750         uint32_t query = 0;
2751         int size;
2752
2753         /* GPU Clocks */
2754         size = sizeof(value);
2755         seq_printf(m, "GFX Clocks and Power:\n");
2756         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2757                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2758         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2759                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2760         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2761                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2762         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2763                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2764         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2765                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2766         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2767                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2768         size = sizeof(uint32_t);
2769         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2770                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2771         size = sizeof(value);
2772         seq_printf(m, "\n");
2773
2774         /* GPU Temp */
2775         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2776                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2777
2778         /* GPU Load */
2779         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2780                 seq_printf(m, "GPU Load: %u %%\n", value);
2781         seq_printf(m, "\n");
2782
2783         /* SMC feature mask */
2784         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2785                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2786
2787         /* UVD clocks */
2788         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2789                 if (!value) {
2790                         seq_printf(m, "UVD: Disabled\n");
2791                 } else {
2792                         seq_printf(m, "UVD: Enabled\n");
2793                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2794                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2795                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2796                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2797                 }
2798         }
2799         seq_printf(m, "\n");
2800
2801         /* VCE clocks */
2802         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2803                 if (!value) {
2804                         seq_printf(m, "VCE: Disabled\n");
2805                 } else {
2806                         seq_printf(m, "VCE: Enabled\n");
2807                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2808                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2809                 }
2810         }
2811
2812         return 0;
2813 }
2814
2815 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2816 {
2817         int i;
2818
2819         for (i = 0; clocks[i].flag; i++)
2820                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2821                            (flags & clocks[i].flag) ? "On" : "Off");
2822 }
2823
2824 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2825 {
2826         struct drm_info_node *node = (struct drm_info_node *) m->private;
2827         struct drm_device *dev = node->minor->dev;
2828         struct amdgpu_device *adev = dev->dev_private;
2829         struct drm_device *ddev = adev->ddev;
2830         u32 flags = 0;
2831
2832         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2833         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2834         amdgpu_parse_cg_state(m, flags);
2835         seq_printf(m, "\n");
2836
2837         if (!adev->pm.dpm_enabled) {
2838                 seq_printf(m, "dpm not enabled\n");
2839                 return 0;
2840         }
2841         if  ((adev->flags & AMD_IS_PX) &&
2842              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2843                 seq_printf(m, "PX asic powered off\n");
2844         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2845                 mutex_lock(&adev->pm.mutex);
2846                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2847                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2848                 else
2849                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2850                 mutex_unlock(&adev->pm.mutex);
2851         } else {
2852                 return amdgpu_debugfs_pm_info_pp(m, adev);
2853         }
2854
2855         return 0;
2856 }
2857
2858 static const struct drm_info_list amdgpu_pm_info_list[] = {
2859         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2860 };
2861 #endif
2862
2863 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2864 {
2865 #if defined(CONFIG_DEBUG_FS)
2866         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2867 #else
2868         return 0;
2869 #endif
2870 }