drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <[email protected]>
  25  *    Michel Thierry <[email protected]>
  26  *    Thomas Daniel <[email protected]>
  27  *    Oscar Mateo <[email protected]>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 141
 142 #define GEN8_LR_CONTEXT_ALIGN 4096
 143
 144 #define RING_EXECLIST_QFULL             (1 << 0x2)
 145 #define RING_EXECLIST1_VALID            (1 << 0x3)
 146 #define RING_EXECLIST0_VALID            (1 << 0x4)
 147 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 148 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 149 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 150
 151 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 152 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 154 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 155 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 156 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 157
 158 #define CTX_LRI_HEADER_0                0x01
 159 #define CTX_CONTEXT_CONTROL             0x02
 160 #define CTX_RING_HEAD                   0x04
 161 #define CTX_RING_TAIL                   0x06
 162 #define CTX_RING_BUFFER_START           0x08
 163 #define CTX_RING_BUFFER_CONTROL         0x0a
 164 #define CTX_BB_HEAD_U                   0x0c
 165 #define CTX_BB_HEAD_L                   0x0e
 166 #define CTX_BB_STATE                    0x10
 167 #define CTX_SECOND_BB_HEAD_U            0x12
 168 #define CTX_SECOND_BB_HEAD_L            0x14
 169 #define CTX_SECOND_BB_STATE             0x16
 170 #define CTX_BB_PER_CTX_PTR              0x18
 171 #define CTX_RCS_INDIRECT_CTX            0x1a
 172 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 173 #define CTX_LRI_HEADER_1                0x21
 174 #define CTX_CTX_TIMESTAMP               0x22
 175 #define CTX_PDP3_UDW                    0x24
 176 #define CTX_PDP3_LDW                    0x26
 177 #define CTX_PDP2_UDW                    0x28
 178 #define CTX_PDP2_LDW                    0x2a
 179 #define CTX_PDP1_UDW                    0x2c
 180 #define CTX_PDP1_LDW                    0x2e
 181 #define CTX_PDP0_UDW                    0x30
 182 #define CTX_PDP0_LDW                    0x32
 183 #define CTX_LRI_HEADER_2                0x41
 184 #define CTX_R_PWR_CLK_STATE             0x42
 185 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 186
 187 #define GEN8_CTX_VALID (1<<0)
 188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 191 #define GEN8_CTX_PRIVILEGE (1<<8)
 192 enum {
 193         ADVANCED_CONTEXT = 0,
 194         LEGACY_CONTEXT,
 195         ADVANCED_AD_CONTEXT,
 196         LEGACY_64B_CONTEXT
 197 };
 198 #define GEN8_CTX_MODE_SHIFT 3
 199 enum {
 200         FAULT_AND_HANG = 0,
 201         FAULT_AND_HALT, /* Debug only */
 202         FAULT_AND_STREAM,
 203         FAULT_AND_CONTINUE /* Unsupported */
 204 };
 205 #define GEN8_CTX_ID_SHIFT 32
 206
 207 /**
 208  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 209  * @dev: DRM device.
 210  * @enable_execlists: value of i915.enable_execlists module parameter.
 211  *
 212  * Only certain platforms support Execlists (the prerequisites being
 213  * support for Logical Ring Contexts and Aliasing PPGTT or better),
 214  * and only when enabled via module parameter.
 215  *
 216  * Return: 1 if Execlists is supported and has to be enabled.
 217  */
 218 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 219 {
 220         WARN_ON(i915.enable_ppgtt == -1);
 221
 222         if (enable_execlists == 0)
 223                 return 0;
 224
 225         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 226             i915.use_mmio_flip >= 0)
 227                 return 1;
 228
 229         return 0;
 230 }
 231
 232 /**
 233  * intel_execlists_ctx_id() - get the Execlists Context ID
 234  * @ctx_obj: Logical Ring Context backing object.
 235  *
 236  * Do not confuse with ctx->id! Unfortunately we have a name overload
 237  * here: the old context ID we pass to userspace as a handler so that
 238  * they can refer to a context, and the new context ID we pass to the
 239  * ELSP so that the GPU can inform us of the context status via
 240  * interrupts.
 241  *
 242  * Return: 20-bits globally unique context ID.
 243  */
 244 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 245 {
 246         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 247
 248         /* LRCA is required to be 4K aligned so the more significant 20 bits
 249          * are globally unique */
 250         return lrca >> 12;
 251 }
 252
 253 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
 254 {
 255         uint64_t desc;
 256         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 257
 258         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 259
 260         desc = GEN8_CTX_VALID;
 261         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 262         desc |= GEN8_CTX_L3LLC_COHERENT;
 263         desc |= GEN8_CTX_PRIVILEGE;
 264         desc |= lrca;
 265         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 266
 267         /* TODO: WaDisableLiteRestore when we start using semaphore
 268          * signalling between Command Streamers */
 269         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 270
 271         return desc;
 272 }
 273
 274 static void execlists_elsp_write(struct intel_engine_cs *ring,
 275                                  struct drm_i915_gem_object *ctx_obj0,
 276                                  struct drm_i915_gem_object *ctx_obj1)
 277 {
 278         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 279         uint64_t temp = 0;
 280         uint32_t desc[4];
 281         unsigned long flags;
 282
 283         /* XXX: You must always write both descriptors in the order below. */
 284         if (ctx_obj1)
 285                 temp = execlists_ctx_descriptor(ctx_obj1);
 286         else
 287                 temp = 0;
 288         desc[1] = (u32)(temp >> 32);
 289         desc[0] = (u32)temp;
 290
 291         temp = execlists_ctx_descriptor(ctx_obj0);
 292         desc[3] = (u32)(temp >> 32);
 293         desc[2] = (u32)temp;
 294
 295         /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
 296          * are in progress.
 297          *
 298          * The other problem is that we can't just call gen6_gt_force_wake_get()
 299          * because that function calls intel_runtime_pm_get(), which might sleep.
 300          * Instead, we do the runtime_pm_get/put when creating/destroying requests.
 301          */
 302         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 303         if (dev_priv->uncore.forcewake_count++ == 0)
 304                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
 305         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 306
 307         I915_WRITE(RING_ELSP(ring), desc[1]);
 308         I915_WRITE(RING_ELSP(ring), desc[0]);
 309         I915_WRITE(RING_ELSP(ring), desc[3]);
 310         /* The context is automatically loaded after the following */
 311         I915_WRITE(RING_ELSP(ring), desc[2]);
 312
 313         /* ELSP is a wo register, so use another nearby reg for posting instead */
 314         POSTING_READ(RING_EXECLIST_STATUS(ring));
 315
 316         /* Release Force Wakeup (see the big comment above). */
 317         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 318         if (--dev_priv->uncore.forcewake_count == 0)
 319                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
 320         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 321 }
 322
 323 static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail)
 324 {
 325         struct page *page;
 326         uint32_t *reg_state;
 327
 328         page = i915_gem_object_get_page(ctx_obj, 1);
 329         reg_state = kmap_atomic(page);
 330
 331         reg_state[CTX_RING_TAIL+1] = tail;
 332
 333         kunmap_atomic(reg_state);
 334
 335         return 0;
 336 }
 337
 338 static int execlists_submit_context(struct intel_engine_cs *ring,
 339                                     struct intel_context *to0, u32 tail0,
 340                                     struct intel_context *to1, u32 tail1)
 341 {
 342         struct drm_i915_gem_object *ctx_obj0;
 343         struct drm_i915_gem_object *ctx_obj1 = NULL;
 344
 345         ctx_obj0 = to0->engine[ring->id].state;
 346         BUG_ON(!ctx_obj0);
 347         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 348
 349         execlists_ctx_write_tail(ctx_obj0, tail0);
 350
 351         if (to1) {
 352                 ctx_obj1 = to1->engine[ring->id].state;
 353                 BUG_ON(!ctx_obj1);
 354                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 355
 356                 execlists_ctx_write_tail(ctx_obj1, tail1);
 357         }
 358
 359         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 360
 361         return 0;
 362 }
 363
 364 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 365 {
 366         struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
 367         struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
 368         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 369
 370         assert_spin_locked(&ring->execlist_lock);
 371
 372         if (list_empty(&ring->execlist_queue))
 373                 return;
 374
 375         /* Try to read in pairs */
 376         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 377                                  execlist_link) {
 378                 if (!req0) {
 379                         req0 = cursor;
 380                 } else if (req0->ctx == cursor->ctx) {
 381                         /* Same ctx: ignore first request, as second request
 382                          * will update tail past first request's workload */
 383                         cursor->elsp_submitted = req0->elsp_submitted;
 384                         list_del(&req0->execlist_link);
 385                         queue_work(dev_priv->wq, &req0->work);
 386                         req0 = cursor;
 387                 } else {
 388                         req1 = cursor;
 389                         break;
 390                 }
 391         }
 392
 393         WARN_ON(req1 && req1->elsp_submitted);
 394
 395         WARN_ON(execlists_submit_context(ring, req0->ctx, req0->tail,
 396                                          req1 ? req1->ctx : NULL,
 397                                          req1 ? req1->tail : 0));
 398
 399         req0->elsp_submitted++;
 400         if (req1)
 401                 req1->elsp_submitted++;
 402 }
 403
 404 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 405                                            u32 request_id)
 406 {
 407         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 408         struct intel_ctx_submit_request *head_req;
 409
 410         assert_spin_locked(&ring->execlist_lock);
 411
 412         head_req = list_first_entry_or_null(&ring->execlist_queue,
 413                                             struct intel_ctx_submit_request,
 414                                             execlist_link);
 415
 416         if (head_req != NULL) {
 417                 struct drm_i915_gem_object *ctx_obj =
 418                                 head_req->ctx->engine[ring->id].state;
 419                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 420                         WARN(head_req->elsp_submitted == 0,
 421                              "Never submitted head request\n");
 422
 423                         if (--head_req->elsp_submitted <= 0) {
 424                                 list_del(&head_req->execlist_link);
 425                                 queue_work(dev_priv->wq, &head_req->work);
 426                                 return true;
 427                         }
 428                 }
 429         }
 430
 431         return false;
 432 }
 433
 434 /**
 435  * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
 436  * @ring: Engine Command Streamer to handle.
 437  *
 438  * Check the unread Context Status Buffers and manage the submission of new
 439  * contexts to the ELSP accordingly.
 440  */
 441 void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring)
 442 {
 443         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 444         u32 status_pointer;
 445         u8 read_pointer;
 446         u8 write_pointer;
 447         u32 status;
 448         u32 status_id;
 449         u32 submit_contexts = 0;
 450
 451         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 452
 453         read_pointer = ring->next_context_status_buffer;
 454         write_pointer = status_pointer & 0x07;
 455         if (read_pointer > write_pointer)
 456                 write_pointer += 6;
 457
 458         spin_lock(&ring->execlist_lock);
 459
 460         while (read_pointer < write_pointer) {
 461                 read_pointer++;
 462                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 463                                 (read_pointer % 6) * 8);
 464                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 465                                 (read_pointer % 6) * 8 + 4);
 466
 467                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 468                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 469                                 if (execlists_check_remove_request(ring, status_id))
 470                                         WARN(1, "Lite Restored request removed from queue\n");
 471                         } else
 472                                 WARN(1, "Preemption without Lite Restore\n");
 473                 }
 474
 475                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 476                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 477                         if (execlists_check_remove_request(ring, status_id))
 478                                 submit_contexts++;
 479                 }
 480         }
 481
 482         if (submit_contexts != 0)
 483                 execlists_context_unqueue(ring);
 484
 485         spin_unlock(&ring->execlist_lock);
 486
 487         WARN(submit_contexts > 2, "More than two context complete events?\n");
 488         ring->next_context_status_buffer = write_pointer % 6;
 489
 490         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 491                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 492 }
 493
 494 static void execlists_free_request_task(struct work_struct *work)
 495 {
 496         struct intel_ctx_submit_request *req =
 497                 container_of(work, struct intel_ctx_submit_request, work);
 498         struct drm_device *dev = req->ring->dev;
 499         struct drm_i915_private *dev_priv = dev->dev_private;
 500
 501         intel_runtime_pm_put(dev_priv);
 502
 503         mutex_lock(&dev->struct_mutex);
 504         i915_gem_context_unreference(req->ctx);
 505         mutex_unlock(&dev->struct_mutex);
 506
 507         kfree(req);
 508 }
 509
 510 static int execlists_context_queue(struct intel_engine_cs *ring,
 511                                    struct intel_context *to,
 512                                    u32 tail)
 513 {
 514         struct intel_ctx_submit_request *req = NULL, *cursor;
 515         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 516         unsigned long flags;
 517         int num_elements = 0;
 518
 519         req = kzalloc(sizeof(*req), GFP_KERNEL);
 520         if (req == NULL)
 521                 return -ENOMEM;
 522         req->ctx = to;
 523         i915_gem_context_reference(req->ctx);
 524         req->ring = ring;
 525         req->tail = tail;
 526         INIT_WORK(&req->work, execlists_free_request_task);
 527
 528         intel_runtime_pm_get(dev_priv);
 529
 530         spin_lock_irqsave(&ring->execlist_lock, flags);
 531
 532         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 533                 if (++num_elements > 2)
 534                         break;
 535
 536         if (num_elements > 2) {
 537                 struct intel_ctx_submit_request *tail_req;
 538
 539                 tail_req = list_last_entry(&ring->execlist_queue,
 540                                            struct intel_ctx_submit_request,
 541                                            execlist_link);
 542
 543                 if (to == tail_req->ctx) {
 544                         WARN(tail_req->elsp_submitted != 0,
 545                              "More than 2 already-submitted reqs queued\n");
 546                         list_del(&tail_req->execlist_link);
 547                         queue_work(dev_priv->wq, &tail_req->work);
 548                 }
 549         }
 550
 551         list_add_tail(&req->execlist_link, &ring->execlist_queue);
 552         if (num_elements == 0)
 553                 execlists_context_unqueue(ring);
 554
 555         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 556
 557         return 0;
 558 }
 559
 560 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
 561 {
 562         struct intel_engine_cs *ring = ringbuf->ring;
 563         uint32_t flush_domains;
 564         int ret;
 565
 566         flush_domains = 0;
 567         if (ring->gpu_caches_dirty)
 568                 flush_domains = I915_GEM_GPU_DOMAINS;
 569
 570         ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
 571         if (ret)
 572                 return ret;
 573
 574         ring->gpu_caches_dirty = false;
 575         return 0;
 576 }
 577
 578 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 579                                  struct list_head *vmas)
 580 {
 581         struct intel_engine_cs *ring = ringbuf->ring;
 582         struct i915_vma *vma;
 583         uint32_t flush_domains = 0;
 584         bool flush_chipset = false;
 585         int ret;
 586
 587         list_for_each_entry(vma, vmas, exec_list) {
 588                 struct drm_i915_gem_object *obj = vma->obj;
 589
 590                 ret = i915_gem_object_sync(obj, ring);
 591                 if (ret)
 592                         return ret;
 593
 594                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 595                         flush_chipset |= i915_gem_clflush_object(obj, false);
 596
 597                 flush_domains |= obj->base.write_domain;
 598         }
 599
 600         if (flush_domains & I915_GEM_DOMAIN_GTT)
 601                 wmb();
 602
 603         /* Unconditionally invalidate gpu caches and ensure that we do flush
 604          * any residual writes from the previous batch.
 605          */
 606         return logical_ring_invalidate_all_caches(ringbuf);
 607 }
 608
 609 /**
 610  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 611  * @dev: DRM device.
 612  * @file: DRM file.
 613  * @ring: Engine Command Streamer to submit to.
 614  * @ctx: Context to employ for this submission.
 615  * @args: execbuffer call arguments.
 616  * @vmas: list of vmas.
 617  * @batch_obj: the batchbuffer to submit.
 618  * @exec_start: batchbuffer start virtual address pointer.
 619  * @flags: translated execbuffer call flags.
 620  *
 621  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 622  * away the submission details of the execbuffer ioctl call.
 623  *
 624  * Return: non-zero if the submission fails.
 625  */
 626 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 627                                struct intel_engine_cs *ring,
 628                                struct intel_context *ctx,
 629                                struct drm_i915_gem_execbuffer2 *args,
 630                                struct list_head *vmas,
 631                                struct drm_i915_gem_object *batch_obj,
 632                                u64 exec_start, u32 flags)
 633 {
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 636         int instp_mode;
 637         u32 instp_mask;
 638         int ret;
 639
 640         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 641         instp_mask = I915_EXEC_CONSTANTS_MASK;
 642         switch (instp_mode) {
 643         case I915_EXEC_CONSTANTS_REL_GENERAL:
 644         case I915_EXEC_CONSTANTS_ABSOLUTE:
 645         case I915_EXEC_CONSTANTS_REL_SURFACE:
 646                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 647                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 648                         return -EINVAL;
 649                 }
 650
 651                 if (instp_mode != dev_priv->relative_constants_mode) {
 652                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 653                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 654                                 return -EINVAL;
 655                         }
 656
 657                         /* The HW changed the meaning on this bit on gen6 */
 658                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 659                 }
 660                 break;
 661         default:
 662                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 663                 return -EINVAL;
 664         }
 665
 666         if (args->num_cliprects != 0) {
 667                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 668                 return -EINVAL;
 669         } else {
 670                 if (args->DR4 == 0xffffffff) {
 671                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 672                         args->DR4 = 0;
 673                 }
 674
 675                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 676                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 677                         return -EINVAL;
 678                 }
 679         }
 680
 681         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 682                 DRM_DEBUG("sol reset is gen7 only\n");
 683                 return -EINVAL;
 684         }
 685
 686         ret = execlists_move_to_gpu(ringbuf, vmas);
 687         if (ret)
 688                 return ret;
 689
 690         if (ring == &dev_priv->ring[RCS] &&
 691             instp_mode != dev_priv->relative_constants_mode) {
 692                 ret = intel_logical_ring_begin(ringbuf, 4);
 693                 if (ret)
 694                         return ret;
 695
 696                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 697                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 698                 intel_logical_ring_emit(ringbuf, INSTPM);
 699                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 700                 intel_logical_ring_advance(ringbuf);
 701
 702                 dev_priv->relative_constants_mode = instp_mode;
 703         }
 704
 705         ret = ring->emit_bb_start(ringbuf, exec_start, flags);
 706         if (ret)
 707                 return ret;
 708
 709         i915_gem_execbuffer_move_to_active(vmas, ring);
 710         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 711
 712         return 0;
 713 }
 714
 715 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 716 {
 717         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 718         int ret;
 719
 720         if (!intel_ring_initialized(ring))
 721                 return;
 722
 723         ret = intel_ring_idle(ring);
 724         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 725                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 726                           ring->name, ret);
 727
 728         /* TODO: Is this correct with Execlists enabled? */
 729         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 730         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 731                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 732                 return;
 733         }
 734         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 735 }
 736
 737 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
 738 {
 739         struct intel_engine_cs *ring = ringbuf->ring;
 740         int ret;
 741
 742         if (!ring->gpu_caches_dirty)
 743                 return 0;
 744
 745         ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS);
 746         if (ret)
 747                 return ret;
 748
 749         ring->gpu_caches_dirty = false;
 750         return 0;
 751 }
 752
 753 /**
 754  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 755  * @ringbuf: Logical Ringbuffer to advance.
 756  *
 757  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 758  * really happens during submission is that the context and current tail will be placed
 759  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 760  * point, the tail *inside* the context is updated and the ELSP written to.
 761  */
 762 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
 763 {
 764         struct intel_engine_cs *ring = ringbuf->ring;
 765         struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
 766
 767         intel_logical_ring_advance(ringbuf);
 768
 769         if (intel_ring_stopped(ring))
 770                 return;
 771
 772         execlists_context_queue(ring, ctx, ringbuf->tail);
 773 }
 774
 775 static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
 776                                     struct intel_context *ctx)
 777 {
 778         if (ring->outstanding_lazy_seqno)
 779                 return 0;
 780
 781         if (ring->preallocated_lazy_request == NULL) {
 782                 struct drm_i915_gem_request *request;
 783
 784                 request = kmalloc(sizeof(*request), GFP_KERNEL);
 785                 if (request == NULL)
 786                         return -ENOMEM;
 787
 788                 /* Hold a reference to the context this request belongs to
 789                  * (we will need it when the time comes to emit/retire the
 790                  * request).
 791                  */
 792                 request->ctx = ctx;
 793                 i915_gem_context_reference(request->ctx);
 794
 795                 ring->preallocated_lazy_request = request;
 796         }
 797
 798         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
 799 }
 800
 801 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 802                                      int bytes)
 803 {
 804         struct intel_engine_cs *ring = ringbuf->ring;
 805         struct drm_i915_gem_request *request;
 806         u32 seqno = 0;
 807         int ret;
 808
 809         if (ringbuf->last_retired_head != -1) {
 810                 ringbuf->head = ringbuf->last_retired_head;
 811                 ringbuf->last_retired_head = -1;
 812
 813                 ringbuf->space = intel_ring_space(ringbuf);
 814                 if (ringbuf->space >= bytes)
 815                         return 0;
 816         }
 817
 818         list_for_each_entry(request, &ring->request_list, list) {
 819                 if (__intel_ring_space(request->tail, ringbuf->tail,
 820                                        ringbuf->size) >= bytes) {
 821                         seqno = request->seqno;
 822                         break;
 823                 }
 824         }
 825
 826         if (seqno == 0)
 827                 return -ENOSPC;
 828
 829         ret = i915_wait_seqno(ring, seqno);
 830         if (ret)
 831                 return ret;
 832
 833         i915_gem_retire_requests_ring(ring);
 834         ringbuf->head = ringbuf->last_retired_head;
 835         ringbuf->last_retired_head = -1;
 836
 837         ringbuf->space = intel_ring_space(ringbuf);
 838         return 0;
 839 }
 840
 841 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 842                                        int bytes)
 843 {
 844         struct intel_engine_cs *ring = ringbuf->ring;
 845         struct drm_device *dev = ring->dev;
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         unsigned long end;
 848         int ret;
 849
 850         ret = logical_ring_wait_request(ringbuf, bytes);
 851         if (ret != -ENOSPC)
 852                 return ret;
 853
 854         /* Force the context submission in case we have been skipping it */
 855         intel_logical_ring_advance_and_submit(ringbuf);
 856
 857         /* With GEM the hangcheck timer should kick us out of the loop,
 858          * leaving it early runs the risk of corrupting GEM state (due
 859          * to running on almost untested codepaths). But on resume
 860          * timers don't work yet, so prevent a complete hang in that
 861          * case by choosing an insanely large timeout. */
 862         end = jiffies + 60 * HZ;
 863
 864         do {
 865                 ringbuf->head = I915_READ_HEAD(ring);
 866                 ringbuf->space = intel_ring_space(ringbuf);
 867                 if (ringbuf->space >= bytes) {
 868                         ret = 0;
 869                         break;
 870                 }
 871
 872                 msleep(1);
 873
 874                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 875                         ret = -ERESTARTSYS;
 876                         break;
 877                 }
 878
 879                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 880                                            dev_priv->mm.interruptible);
 881                 if (ret)
 882                         break;
 883
 884                 if (time_after(jiffies, end)) {
 885                         ret = -EBUSY;
 886                         break;
 887                 }
 888         } while (1);
 889
 890         return ret;
 891 }
 892
 893 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
 894 {
 895         uint32_t __iomem *virt;
 896         int rem = ringbuf->size - ringbuf->tail;
 897
 898         if (ringbuf->space < rem) {
 899                 int ret = logical_ring_wait_for_space(ringbuf, rem);
 900
 901                 if (ret)
 902                         return ret;
 903         }
 904
 905         virt = ringbuf->virtual_start + ringbuf->tail;
 906         rem /= 4;
 907         while (rem--)
 908                 iowrite32(MI_NOOP, virt++);
 909
 910         ringbuf->tail = 0;
 911         ringbuf->space = intel_ring_space(ringbuf);
 912
 913         return 0;
 914 }
 915
 916 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
 917 {
 918         int ret;
 919
 920         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
 921                 ret = logical_ring_wrap_buffer(ringbuf);
 922                 if (unlikely(ret))
 923                         return ret;
 924         }
 925
 926         if (unlikely(ringbuf->space < bytes)) {
 927                 ret = logical_ring_wait_for_space(ringbuf, bytes);
 928                 if (unlikely(ret))
 929                         return ret;
 930         }
 931
 932         return 0;
 933 }
 934
 935 /**
 936  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
 937  *
 938  * @ringbuf: Logical ringbuffer.
 939  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
 940  *
 941  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
 942  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
 943  * and also preallocates a request (every workload submission is still mediated through
 944  * requests, same as it did with legacy ringbuffer submission).
 945  *
 946  * Return: non-zero if the ringbuffer is not ready to be written to.
 947  */
 948 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
 949 {
 950         struct intel_engine_cs *ring = ringbuf->ring;
 951         struct drm_device *dev = ring->dev;
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953         int ret;
 954
 955         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 956                                    dev_priv->mm.interruptible);
 957         if (ret)
 958                 return ret;
 959
 960         ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t));
 961         if (ret)
 962                 return ret;
 963
 964         /* Preallocate the olr before touching the ring */
 965         ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx);
 966         if (ret)
 967                 return ret;
 968
 969         ringbuf->space -= num_dwords * sizeof(uint32_t);
 970         return 0;
 971 }
 972
 973 static int gen8_init_common_ring(struct intel_engine_cs *ring)
 974 {
 975         struct drm_device *dev = ring->dev;
 976         struct drm_i915_private *dev_priv = dev->dev_private;
 977
 978         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
 979         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
 980
 981         I915_WRITE(RING_MODE_GEN7(ring),
 982                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
 983                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 984         POSTING_READ(RING_MODE_GEN7(ring));
 985         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
 986
 987         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 988
 989         return 0;
 990 }
 991
 992 static int gen8_init_render_ring(struct intel_engine_cs *ring)
 993 {
 994         struct drm_device *dev = ring->dev;
 995         struct drm_i915_private *dev_priv = dev->dev_private;
 996         int ret;
 997
 998         ret = gen8_init_common_ring(ring);
 999         if (ret)
1000                 return ret;
1001
1002         /* We need to disable the AsyncFlip performance optimisations in order
1003          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1004          * programmed to '1' on all products.
1005          *
1006          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1007          */
1008         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1009
1010         ret = intel_init_pipe_control(ring);
1011         if (ret)
1012                 return ret;
1013
1014         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1015
1016         return ret;
1017 }
1018
1019 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1020                               u64 offset, unsigned flags)
1021 {
1022         bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1023         int ret;
1024
1025         ret = intel_logical_ring_begin(ringbuf, 4);
1026         if (ret)
1027                 return ret;
1028
1029         /* FIXME(BDW): Address space and security selectors. */
1030         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1031         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1032         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1033         intel_logical_ring_emit(ringbuf, MI_NOOP);
1034         intel_logical_ring_advance(ringbuf);
1035
1036         return 0;
1037 }
1038
1039 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1040 {
1041         struct drm_device *dev = ring->dev;
1042         struct drm_i915_private *dev_priv = dev->dev_private;
1043         unsigned long flags;
1044
1045         if (!dev->irq_enabled)
1046                 return false;
1047
1048         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1049         if (ring->irq_refcount++ == 0) {
1050                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1051                 POSTING_READ(RING_IMR(ring->mmio_base));
1052         }
1053         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1054
1055         return true;
1056 }
1057
1058 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1059 {
1060         struct drm_device *dev = ring->dev;
1061         struct drm_i915_private *dev_priv = dev->dev_private;
1062         unsigned long flags;
1063
1064         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1065         if (--ring->irq_refcount == 0) {
1066                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1067                 POSTING_READ(RING_IMR(ring->mmio_base));
1068         }
1069         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1070 }
1071
1072 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1073                            u32 invalidate_domains,
1074                            u32 unused)
1075 {
1076         struct intel_engine_cs *ring = ringbuf->ring;
1077         struct drm_device *dev = ring->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         uint32_t cmd;
1080         int ret;
1081
1082         ret = intel_logical_ring_begin(ringbuf, 4);
1083         if (ret)
1084                 return ret;
1085
1086         cmd = MI_FLUSH_DW + 1;
1087
1088         if (ring == &dev_priv->ring[VCS]) {
1089                 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1090                         cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1091                                 MI_FLUSH_DW_STORE_INDEX |
1092                                 MI_FLUSH_DW_OP_STOREDW;
1093         } else {
1094                 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1095                         cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1096                                 MI_FLUSH_DW_OP_STOREDW;
1097         }
1098
1099         intel_logical_ring_emit(ringbuf, cmd);
1100         intel_logical_ring_emit(ringbuf,
1101                                 I915_GEM_HWS_SCRATCH_ADDR |
1102                                 MI_FLUSH_DW_USE_GTT);
1103         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1104         intel_logical_ring_emit(ringbuf, 0); /* value */
1105         intel_logical_ring_advance(ringbuf);
1106
1107         return 0;
1108 }
1109
1110 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1111                                   u32 invalidate_domains,
1112                                   u32 flush_domains)
1113 {
1114         struct intel_engine_cs *ring = ringbuf->ring;
1115         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1116         u32 flags = 0;
1117         int ret;
1118
1119         flags |= PIPE_CONTROL_CS_STALL;
1120
1121         if (flush_domains) {
1122                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1123                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1124         }
1125
1126         if (invalidate_domains) {
1127                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1128                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1129                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1130                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1131                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1132                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1133                 flags |= PIPE_CONTROL_QW_WRITE;
1134                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1135         }
1136
1137         ret = intel_logical_ring_begin(ringbuf, 6);
1138         if (ret)
1139                 return ret;
1140
1141         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1142         intel_logical_ring_emit(ringbuf, flags);
1143         intel_logical_ring_emit(ringbuf, scratch_addr);
1144         intel_logical_ring_emit(ringbuf, 0);
1145         intel_logical_ring_emit(ringbuf, 0);
1146         intel_logical_ring_emit(ringbuf, 0);
1147         intel_logical_ring_advance(ringbuf);
1148
1149         return 0;
1150 }
1151
1152 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1153 {
1154         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1155 }
1156
1157 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1158 {
1159         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1160 }
1161
1162 static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1163 {
1164         struct intel_engine_cs *ring = ringbuf->ring;
1165         u32 cmd;
1166         int ret;
1167
1168         ret = intel_logical_ring_begin(ringbuf, 6);
1169         if (ret)
1170                 return ret;
1171
1172         cmd = MI_STORE_DWORD_IMM_GEN8;
1173         cmd |= MI_GLOBAL_GTT;
1174
1175         intel_logical_ring_emit(ringbuf, cmd);
1176         intel_logical_ring_emit(ringbuf,
1177                                 (ring->status_page.gfx_addr +
1178                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1179         intel_logical_ring_emit(ringbuf, 0);
1180         intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno);
1181         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1182         intel_logical_ring_emit(ringbuf, MI_NOOP);
1183         intel_logical_ring_advance_and_submit(ringbuf);
1184
1185         return 0;
1186 }
1187
1188 /**
1189  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1190  *
1191  * @ring: Engine Command Streamer.
1192  *
1193  */
1194 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1195 {
1196         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1197
1198         if (!intel_ring_initialized(ring))
1199                 return;
1200
1201         intel_logical_ring_stop(ring);
1202         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1203         ring->preallocated_lazy_request = NULL;
1204         ring->outstanding_lazy_seqno = 0;
1205
1206         if (ring->cleanup)
1207                 ring->cleanup(ring);
1208
1209         i915_cmd_parser_fini_ring(ring);
1210
1211         if (ring->status_page.obj) {
1212                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1213                 ring->status_page.obj = NULL;
1214         }
1215 }
1216
1217 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1218 {
1219         int ret;
1220         struct intel_context *dctx = ring->default_context;
1221         struct drm_i915_gem_object *dctx_obj;
1222
1223         /* Intentionally left blank. */
1224         ring->buffer = NULL;
1225
1226         ring->dev = dev;
1227         INIT_LIST_HEAD(&ring->active_list);
1228         INIT_LIST_HEAD(&ring->request_list);
1229         init_waitqueue_head(&ring->irq_queue);
1230
1231         INIT_LIST_HEAD(&ring->execlist_queue);
1232         spin_lock_init(&ring->execlist_lock);
1233         ring->next_context_status_buffer = 0;
1234
1235         ret = intel_lr_context_deferred_create(dctx, ring);
1236         if (ret)
1237                 return ret;
1238
1239         /* The status page is offset 0 from the context object in LRCs. */
1240         dctx_obj = dctx->engine[ring->id].state;
1241         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj);
1242         ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl));
1243         if (ring->status_page.page_addr == NULL)
1244                 return -ENOMEM;
1245         ring->status_page.obj = dctx_obj;
1246
1247         ret = i915_cmd_parser_init_ring(ring);
1248         if (ret)
1249                 return ret;
1250
1251         if (ring->init) {
1252                 ret = ring->init(ring);
1253                 if (ret)
1254                         return ret;
1255         }
1256
1257         return 0;
1258 }
1259
1260 static int logical_render_ring_init(struct drm_device *dev)
1261 {
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1264
1265         ring->name = "render ring";
1266         ring->id = RCS;
1267         ring->mmio_base = RENDER_RING_BASE;
1268         ring->irq_enable_mask =
1269                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1270         ring->irq_keep_mask =
1271                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1272         if (HAS_L3_DPF(dev))
1273                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1274
1275         ring->init = gen8_init_render_ring;
1276         ring->cleanup = intel_fini_pipe_control;
1277         ring->get_seqno = gen8_get_seqno;
1278         ring->set_seqno = gen8_set_seqno;
1279         ring->emit_request = gen8_emit_request;
1280         ring->emit_flush = gen8_emit_flush_render;
1281         ring->irq_get = gen8_logical_ring_get_irq;
1282         ring->irq_put = gen8_logical_ring_put_irq;
1283         ring->emit_bb_start = gen8_emit_bb_start;
1284
1285         return logical_ring_init(dev, ring);
1286 }
1287
1288 static int logical_bsd_ring_init(struct drm_device *dev)
1289 {
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1292
1293         ring->name = "bsd ring";
1294         ring->id = VCS;
1295         ring->mmio_base = GEN6_BSD_RING_BASE;
1296         ring->irq_enable_mask =
1297                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1298         ring->irq_keep_mask =
1299                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1300
1301         ring->init = gen8_init_common_ring;
1302         ring->get_seqno = gen8_get_seqno;
1303         ring->set_seqno = gen8_set_seqno;
1304         ring->emit_request = gen8_emit_request;
1305         ring->emit_flush = gen8_emit_flush;
1306         ring->irq_get = gen8_logical_ring_get_irq;
1307         ring->irq_put = gen8_logical_ring_put_irq;
1308         ring->emit_bb_start = gen8_emit_bb_start;
1309
1310         return logical_ring_init(dev, ring);
1311 }
1312
1313 static int logical_bsd2_ring_init(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1317
1318         ring->name = "bds2 ring";
1319         ring->id = VCS2;
1320         ring->mmio_base = GEN8_BSD2_RING_BASE;
1321         ring->irq_enable_mask =
1322                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1323         ring->irq_keep_mask =
1324                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1325
1326         ring->init = gen8_init_common_ring;
1327         ring->get_seqno = gen8_get_seqno;
1328         ring->set_seqno = gen8_set_seqno;
1329         ring->emit_request = gen8_emit_request;
1330         ring->emit_flush = gen8_emit_flush;
1331         ring->irq_get = gen8_logical_ring_get_irq;
1332         ring->irq_put = gen8_logical_ring_put_irq;
1333         ring->emit_bb_start = gen8_emit_bb_start;
1334
1335         return logical_ring_init(dev, ring);
1336 }
1337
1338 static int logical_blt_ring_init(struct drm_device *dev)
1339 {
1340         struct drm_i915_private *dev_priv = dev->dev_private;
1341         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1342
1343         ring->name = "blitter ring";
1344         ring->id = BCS;
1345         ring->mmio_base = BLT_RING_BASE;
1346         ring->irq_enable_mask =
1347                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1348         ring->irq_keep_mask =
1349                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1350
1351         ring->init = gen8_init_common_ring;
1352         ring->get_seqno = gen8_get_seqno;
1353         ring->set_seqno = gen8_set_seqno;
1354         ring->emit_request = gen8_emit_request;
1355         ring->emit_flush = gen8_emit_flush;
1356         ring->irq_get = gen8_logical_ring_get_irq;
1357         ring->irq_put = gen8_logical_ring_put_irq;
1358         ring->emit_bb_start = gen8_emit_bb_start;
1359
1360         return logical_ring_init(dev, ring);
1361 }
1362
1363 static int logical_vebox_ring_init(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1367
1368         ring->name = "video enhancement ring";
1369         ring->id = VECS;
1370         ring->mmio_base = VEBOX_RING_BASE;
1371         ring->irq_enable_mask =
1372                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1373         ring->irq_keep_mask =
1374                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1375
1376         ring->init = gen8_init_common_ring;
1377         ring->get_seqno = gen8_get_seqno;
1378         ring->set_seqno = gen8_set_seqno;
1379         ring->emit_request = gen8_emit_request;
1380         ring->emit_flush = gen8_emit_flush;
1381         ring->irq_get = gen8_logical_ring_get_irq;
1382         ring->irq_put = gen8_logical_ring_put_irq;
1383         ring->emit_bb_start = gen8_emit_bb_start;
1384
1385         return logical_ring_init(dev, ring);
1386 }
1387
1388 /**
1389  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1390  * @dev: DRM device.
1391  *
1392  * This function inits the engines for an Execlists submission style (the equivalent in the
1393  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1394  * those engines that are present in the hardware.
1395  *
1396  * Return: non-zero if the initialization failed.
1397  */
1398 int intel_logical_rings_init(struct drm_device *dev)
1399 {
1400         struct drm_i915_private *dev_priv = dev->dev_private;
1401         int ret;
1402
1403         ret = logical_render_ring_init(dev);
1404         if (ret)
1405                 return ret;
1406
1407         if (HAS_BSD(dev)) {
1408                 ret = logical_bsd_ring_init(dev);
1409                 if (ret)
1410                         goto cleanup_render_ring;
1411         }
1412
1413         if (HAS_BLT(dev)) {
1414                 ret = logical_blt_ring_init(dev);
1415                 if (ret)
1416                         goto cleanup_bsd_ring;
1417         }
1418
1419         if (HAS_VEBOX(dev)) {
1420                 ret = logical_vebox_ring_init(dev);
1421                 if (ret)
1422                         goto cleanup_blt_ring;
1423         }
1424
1425         if (HAS_BSD2(dev)) {
1426                 ret = logical_bsd2_ring_init(dev);
1427                 if (ret)
1428                         goto cleanup_vebox_ring;
1429         }
1430
1431         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1432         if (ret)
1433                 goto cleanup_bsd2_ring;
1434
1435         return 0;
1436
1437 cleanup_bsd2_ring:
1438         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1439 cleanup_vebox_ring:
1440         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1441 cleanup_blt_ring:
1442         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1443 cleanup_bsd_ring:
1444         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1445 cleanup_render_ring:
1446         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1447
1448         return ret;
1449 }
1450
1451 static int
1452 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1453                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1454 {
1455         struct drm_i915_gem_object *ring_obj = ringbuf->obj;
1456         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1457         struct page *page;
1458         uint32_t *reg_state;
1459         int ret;
1460
1461         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1462         if (ret) {
1463                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1464                 return ret;
1465         }
1466
1467         ret = i915_gem_object_get_pages(ctx_obj);
1468         if (ret) {
1469                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1470                 return ret;
1471         }
1472
1473         i915_gem_object_pin_pages(ctx_obj);
1474
1475         /* The second page of the context object contains some fields which must
1476          * be set up prior to the first execution. */
1477         page = i915_gem_object_get_page(ctx_obj, 1);
1478         reg_state = kmap_atomic(page);
1479
1480         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1481          * commands followed by (reg, value) pairs. The values we are setting here are
1482          * only for the first context restore: on a subsequent save, the GPU will
1483          * recreate this batchbuffer with new values (including all the missing
1484          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1485         if (ring->id == RCS)
1486                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1487         else
1488                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1489         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1490         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1491         reg_state[CTX_CONTEXT_CONTROL+1] =
1492                         _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1493         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1494         reg_state[CTX_RING_HEAD+1] = 0;
1495         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1496         reg_state[CTX_RING_TAIL+1] = 0;
1497         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1498         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
1499         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1500         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1501                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1502         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1503         reg_state[CTX_BB_HEAD_U+1] = 0;
1504         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1505         reg_state[CTX_BB_HEAD_L+1] = 0;
1506         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1507         reg_state[CTX_BB_STATE+1] = (1<<5);
1508         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1509         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1510         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1511         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1512         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1513         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1514         if (ring->id == RCS) {
1515                 /* TODO: according to BSpec, the register state context
1516                  * for CHV does not have these. OTOH, these registers do
1517                  * exist in CHV. I'm waiting for a clarification */
1518                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1519                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1520                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1521                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1522                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1523                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1524         }
1525         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1526         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1527         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1528         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1529         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1530         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1531         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1532         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1533         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1534         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1535         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1536         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1537         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1538         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1539         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1540         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1541         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1542         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1543         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1544         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1545         if (ring->id == RCS) {
1546                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1547                 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1548                 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1549         }
1550
1551         kunmap_atomic(reg_state);
1552
1553         ctx_obj->dirty = 1;
1554         set_page_dirty(page);
1555         i915_gem_object_unpin_pages(ctx_obj);
1556
1557         return 0;
1558 }
1559
1560 /**
1561  * intel_lr_context_free() - free the LRC specific bits of a context
1562  * @ctx: the LR context to free.
1563  *
1564  * The real context freeing is done in i915_gem_context_free: this only
1565  * takes care of the bits that are LRC related: the per-engine backing
1566  * objects and the logical ringbuffer.
1567  */
1568 void intel_lr_context_free(struct intel_context *ctx)
1569 {
1570         int i;
1571
1572         for (i = 0; i < I915_NUM_RINGS; i++) {
1573                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1574                 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
1575
1576                 if (ctx_obj) {
1577                         intel_destroy_ringbuffer_obj(ringbuf);
1578                         kfree(ringbuf);
1579                         i915_gem_object_ggtt_unpin(ctx_obj);
1580                         drm_gem_object_unreference(&ctx_obj->base);
1581                 }
1582         }
1583 }
1584
1585 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1586 {
1587         int ret = 0;
1588
1589         WARN_ON(INTEL_INFO(ring->dev)->gen != 8);
1590
1591         switch (ring->id) {
1592         case RCS:
1593                 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1594                 break;
1595         case VCS:
1596         case BCS:
1597         case VECS:
1598         case VCS2:
1599                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1600                 break;
1601         }
1602
1603         return ret;
1604 }
1605
1606 /**
1607  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1608  * @ctx: LR context to create.
1609  * @ring: engine to be used with the context.
1610  *
1611  * This function can be called more than once, with different engines, if we plan
1612  * to use the context with them. The context backing objects and the ringbuffers
1613  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1614  * the creation is a deferred call: it's better to make sure first that we need to use
1615  * a given ring with the context.
1616  *
1617  * Return: non-zero on eror.
1618  */
1619 int intel_lr_context_deferred_create(struct intel_context *ctx,
1620                                      struct intel_engine_cs *ring)
1621 {
1622         struct drm_device *dev = ring->dev;
1623         struct drm_i915_gem_object *ctx_obj;
1624         uint32_t context_size;
1625         struct intel_ringbuffer *ringbuf;
1626         int ret;
1627
1628         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1629         if (ctx->engine[ring->id].state)
1630                 return 0;
1631
1632         context_size = round_up(get_lr_context_size(ring), 4096);
1633
1634         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1635         if (IS_ERR(ctx_obj)) {
1636                 ret = PTR_ERR(ctx_obj);
1637                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1638                 return ret;
1639         }
1640
1641         ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1642         if (ret) {
1643                 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret);
1644                 drm_gem_object_unreference(&ctx_obj->base);
1645                 return ret;
1646         }
1647
1648         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1649         if (!ringbuf) {
1650                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1651                                 ring->name);
1652                 i915_gem_object_ggtt_unpin(ctx_obj);
1653                 drm_gem_object_unreference(&ctx_obj->base);
1654                 ret = -ENOMEM;
1655                 return ret;
1656         }
1657
1658         ringbuf->ring = ring;
1659         ringbuf->FIXME_lrc_ctx = ctx;
1660
1661         ringbuf->size = 32 * PAGE_SIZE;
1662         ringbuf->effective_size = ringbuf->size;
1663         ringbuf->head = 0;
1664         ringbuf->tail = 0;
1665         ringbuf->space = ringbuf->size;
1666         ringbuf->last_retired_head = -1;
1667
1668         /* TODO: For now we put this in the mappable region so that we can reuse
1669          * the existing ringbuffer code which ioremaps it. When we start
1670          * creating many contexts, this will no longer work and we must switch
1671          * to a kmapish interface.
1672          */
1673         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1674         if (ret) {
1675                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1676                                 ring->name, ret);
1677                 goto error;
1678         }
1679
1680         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1681         if (ret) {
1682                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1683                 intel_destroy_ringbuffer_obj(ringbuf);
1684                 goto error;
1685         }
1686
1687         ctx->engine[ring->id].ringbuf = ringbuf;
1688         ctx->engine[ring->id].state = ctx_obj;
1689
1690         return 0;
1691
1692 error:
1693         kfree(ringbuf);
1694         i915_gem_object_ggtt_unpin(ctx_obj);
1695         drm_gem_object_unreference(&ctx_obj->base);
1696         return ret;
1697 }