drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  78
  79 static void intel_increase_pllclock(struct drm_device *dev,
  80                                     enum pipe pipe);
  81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  82
  83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  84                                 struct intel_crtc_config *pipe_config);
  85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  86                                    struct intel_crtc_config *pipe_config);
  87
  88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  89                           int x, int y, struct drm_framebuffer *old_fb);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc);
 103 static void chv_prepare_pll(struct intel_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4860000, .max = 6700000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, crtc, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 427                                                 int refclk)
 428 {
 429         struct drm_device *dev = crtc->dev;
 430         const intel_limit_t *limit;
 431
 432         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 433                 if (intel_is_dual_link_lvds(dev)) {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_dual_lvds;
 438                 } else {
 439                         if (refclk == 100000)
 440                                 limit = &intel_limits_ironlake_single_lvds_100m;
 441                         else
 442                                 limit = &intel_limits_ironlake_single_lvds;
 443                 }
 444         } else
 445                 limit = &intel_limits_ironlake_dac;
 446
 447         return limit;
 448 }
 449
 450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 451 {
 452         struct drm_device *dev = crtc->dev;
 453         const intel_limit_t *limit;
 454
 455         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 456                 if (intel_is_dual_link_lvds(dev))
 457                         limit = &intel_limits_g4x_dual_channel_lvds;
 458                 else
 459                         limit = &intel_limits_g4x_single_channel_lvds;
 460         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 461                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 462                 limit = &intel_limits_g4x_hdmi;
 463         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 464                 limit = &intel_limits_g4x_sdvo;
 465         } else /* The option is for other outputs */
 466                 limit = &intel_limits_i9xx_sdvo;
 467
 468         return limit;
 469 }
 470
 471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 472 {
 473         struct drm_device *dev = crtc->dev;
 474         const intel_limit_t *limit;
 475
 476         if (HAS_PCH_SPLIT(dev))
 477                 limit = intel_ironlake_limit(crtc, refclk);
 478         else if (IS_G4X(dev)) {
 479                 limit = intel_g4x_limit(crtc);
 480         } else if (IS_PINEVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 482                         limit = &intel_limits_pineview_lvds;
 483                 else
 484                         limit = &intel_limits_pineview_sdvo;
 485         } else if (IS_CHERRYVIEW(dev)) {
 486                 limit = &intel_limits_chv;
 487         } else if (IS_VALLEYVIEW(dev)) {
 488                 limit = &intel_limits_vlv;
 489         } else if (!IS_GEN2(dev)) {
 490                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 491                         limit = &intel_limits_i9xx_lvds;
 492                 else
 493                         limit = &intel_limits_i9xx_sdvo;
 494         } else {
 495                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 496                         limit = &intel_limits_i8xx_lvds;
 497                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 498                         limit = &intel_limits_i8xx_dvo;
 499                 else
 500                         limit = &intel_limits_i8xx_dac;
 501         }
 502         return limit;
 503 }
 504
 505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 506 static void pineview_clock(int refclk, intel_clock_t *clock)
 507 {
 508         clock->m = clock->m2 + 2;
 509         clock->p = clock->p1 * clock->p2;
 510         if (WARN_ON(clock->n == 0 || clock->p == 0))
 511                 return;
 512         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 513         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 514 }
 515
 516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 517 {
 518         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 519 }
 520
 521 static void i9xx_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = i9xx_dpll_compute_m(clock);
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static void chv_clock(int refclk, intel_clock_t *clock)
 532 {
 533         clock->m = clock->m1 * clock->m2;
 534         clock->p = clock->p1 * clock->p2;
 535         if (WARN_ON(clock->n == 0 || clock->p == 0))
 536                 return;
 537         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 538                         clock->n << 22);
 539         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 553                 INTELPllInvalid("n out of range\n");
 554         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 555                 INTELPllInvalid("p1 out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560
 561         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 562                 if (clock->m1 <= clock->m2)
 563                         INTELPllInvalid("m1 <= m2\n");
 564
 565         if (!IS_VALLEYVIEW(dev)) {
 566                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 567                         INTELPllInvalid("p out of range\n");
 568                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 569                         INTELPllInvalid("m out of range\n");
 570         }
 571
 572         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 573                 INTELPllInvalid("vco out of range\n");
 574         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 575          * connector, etc., rather than just a single range.
 576          */
 577         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 578                 INTELPllInvalid("dot out of range\n");
 579
 580         return true;
 581 }
 582
 583 static bool
 584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 585                     int target, int refclk, intel_clock_t *match_clock,
 586                     intel_clock_t *best_clock)
 587 {
 588         struct drm_device *dev = crtc->dev;
 589         intel_clock_t clock;
 590         int err = target;
 591
 592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 593                 /*
 594                  * For LVDS just rely on its current settings for dual-channel.
 595                  * We haven't figured out how to reliably set up different
 596                  * single/dual channel state, if we even can.
 597                  */
 598                 if (intel_is_dual_link_lvds(dev))
 599                         clock.p2 = limit->p2.p2_fast;
 600                 else
 601                         clock.p2 = limit->p2.p2_slow;
 602         } else {
 603                 if (target < limit->p2.dot_limit)
 604                         clock.p2 = limit->p2.p2_slow;
 605                 else
 606                         clock.p2 = limit->p2.p2_fast;
 607         }
 608
 609         memset(best_clock, 0, sizeof(*best_clock));
 610
 611         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 612              clock.m1++) {
 613                 for (clock.m2 = limit->m2.min;
 614                      clock.m2 <= limit->m2.max; clock.m2++) {
 615                         if (clock.m2 >= clock.m1)
 616                                 break;
 617                         for (clock.n = limit->n.min;
 618                              clock.n <= limit->n.max; clock.n++) {
 619                                 for (clock.p1 = limit->p1.min;
 620                                         clock.p1 <= limit->p1.max; clock.p1++) {
 621                                         int this_err;
 622
 623                                         i9xx_clock(refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627                                         if (match_clock &&
 628                                             clock.p != match_clock->p)
 629                                                 continue;
 630
 631                                         this_err = abs(clock.dot - target);
 632                                         if (this_err < err) {
 633                                                 *best_clock = clock;
 634                                                 err = this_err;
 635                                         }
 636                                 }
 637                         }
 638                 }
 639         }
 640
 641         return (err != target);
 642 }
 643
 644 static bool
 645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 646                    int target, int refclk, intel_clock_t *match_clock,
 647                    intel_clock_t *best_clock)
 648 {
 649         struct drm_device *dev = crtc->dev;
 650         intel_clock_t clock;
 651         int err = target;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 /*
 655                  * For LVDS just rely on its current settings for dual-channel.
 656                  * We haven't figured out how to reliably set up different
 657                  * single/dual channel state, if we even can.
 658                  */
 659                 if (intel_is_dual_link_lvds(dev))
 660                         clock.p2 = limit->p2.p2_fast;
 661                 else
 662                         clock.p2 = limit->p2.p2_slow;
 663         } else {
 664                 if (target < limit->p2.dot_limit)
 665                         clock.p2 = limit->p2.p2_slow;
 666                 else
 667                         clock.p2 = limit->p2.p2_fast;
 668         }
 669
 670         memset(best_clock, 0, sizeof(*best_clock));
 671
 672         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 673              clock.m1++) {
 674                 for (clock.m2 = limit->m2.min;
 675                      clock.m2 <= limit->m2.max; clock.m2++) {
 676                         for (clock.n = limit->n.min;
 677                              clock.n <= limit->n.max; clock.n++) {
 678                                 for (clock.p1 = limit->p1.min;
 679                                         clock.p1 <= limit->p1.max; clock.p1++) {
 680                                         int this_err;
 681
 682                                         pineview_clock(refclk, &clock);
 683                                         if (!intel_PLL_is_valid(dev, limit,
 684                                                                 &clock))
 685                                                 continue;
 686                                         if (match_clock &&
 687                                             clock.p != match_clock->p)
 688                                                 continue;
 689
 690                                         this_err = abs(clock.dot - target);
 691                                         if (this_err < err) {
 692                                                 *best_clock = clock;
 693                                                 err = this_err;
 694                                         }
 695                                 }
 696                         }
 697                 }
 698         }
 699
 700         return (err != target);
 701 }
 702
 703 static bool
 704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 705                    int target, int refclk, intel_clock_t *match_clock,
 706                    intel_clock_t *best_clock)
 707 {
 708         struct drm_device *dev = crtc->dev;
 709         intel_clock_t clock;
 710         int max_n;
 711         bool found;
 712         /* approximately equals target * 0.00585 */
 713         int err_most = (target >> 8) + (target >> 9);
 714         found = false;
 715
 716         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 717                 if (intel_is_dual_link_lvds(dev))
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729         max_n = limit->n.max;
 730         /* based on hardware requirement, prefer smaller n to precision */
 731         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 732                 /* based on hardware requirement, prefere larger m1,m2 */
 733                 for (clock.m1 = limit->m1.max;
 734                      clock.m1 >= limit->m1.min; clock.m1--) {
 735                         for (clock.m2 = limit->m2.max;
 736                              clock.m2 >= limit->m2.min; clock.m2--) {
 737                                 for (clock.p1 = limit->p1.max;
 738                                      clock.p1 >= limit->p1.min; clock.p1--) {
 739                                         int this_err;
 740
 741                                         i9xx_clock(refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745
 746                                         this_err = abs(clock.dot - target);
 747                                         if (this_err < err_most) {
 748                                                 *best_clock = clock;
 749                                                 err_most = this_err;
 750                                                 max_n = clock.n;
 751                                                 found = true;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757         return found;
 758 }
 759
 760 static bool
 761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                    int target, int refclk, intel_clock_t *match_clock,
 763                    intel_clock_t *best_clock)
 764 {
 765         struct drm_device *dev = crtc->dev;
 766         intel_clock_t clock;
 767         unsigned int bestppm = 1000000;
 768         /* min update 19.2 MHz */
 769         int max_n = min(limit->n.max, refclk / 19200);
 770         bool found = false;
 771
 772         target *= 5; /* fast clock */
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         /* based on hardware requirement, prefer smaller n to precision */
 777         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 778                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 779                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 780                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 781                                 clock.p = clock.p1 * clock.p2;
 782                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 783                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 784                                         unsigned int ppm, diff;
 785
 786                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 787                                                                      refclk * clock.m1);
 788
 789                                         vlv_clock(refclk, &clock);
 790
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794
 795                                         diff = abs(clock.dot - target);
 796                                         ppm = div_u64(1000000ULL * diff, target);
 797
 798                                         if (ppm < 100 && clock.p > best_clock->p) {
 799                                                 bestppm = 0;
 800                                                 *best_clock = clock;
 801                                                 found = true;
 802                                         }
 803
 804                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 805                                                 bestppm = ppm;
 806                                                 *best_clock = clock;
 807                                                 found = true;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813
 814         return found;
 815 }
 816
 817 static bool
 818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 819                    int target, int refclk, intel_clock_t *match_clock,
 820                    intel_clock_t *best_clock)
 821 {
 822         struct drm_device *dev = crtc->dev;
 823         intel_clock_t clock;
 824         uint64_t m2;
 825         int found = false;
 826
 827         memset(best_clock, 0, sizeof(*best_clock));
 828
 829         /*
 830          * Based on hardware doc, the n always set to 1, and m1 always
 831          * set to 2.  If requires to support 200Mhz refclk, we need to
 832          * revisit this because n may not 1 anymore.
 833          */
 834         clock.n = 1, clock.m1 = 2;
 835         target *= 5;    /* fast clock */
 836
 837         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 838                 for (clock.p2 = limit->p2.p2_fast;
 839                                 clock.p2 >= limit->p2.p2_slow;
 840                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 841
 842                         clock.p = clock.p1 * clock.p2;
 843
 844                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 845                                         clock.n) << 22, refclk * clock.m1);
 846
 847                         if (m2 > INT_MAX/clock.m1)
 848                                 continue;
 849
 850                         clock.m2 = m2;
 851
 852                         chv_clock(refclk, &clock);
 853
 854                         if (!intel_PLL_is_valid(dev, limit, &clock))
 855                                 continue;
 856
 857                         /* based on hardware requirement, prefer bigger p
 858                          */
 859                         if (clock.p > best_clock->p) {
 860                                 *best_clock = clock;
 861                                 found = true;
 862                         }
 863                 }
 864         }
 865
 866         return found;
 867 }
 868
 869 bool intel_crtc_active(struct drm_crtc *crtc)
 870 {
 871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 872
 873         /* Be paranoid as we can arrive here with only partial
 874          * state retrieved from the hardware during setup.
 875          *
 876          * We can ditch the adjusted_mode.crtc_clock check as soon
 877          * as Haswell has gained clock readout/fastboot support.
 878          *
 879          * We can ditch the crtc->primary->fb check as soon as we can
 880          * properly reconstruct framebuffers.
 881          */
 882         return intel_crtc->active && crtc->primary->fb &&
 883                 intel_crtc->config.adjusted_mode.crtc_clock;
 884 }
 885
 886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 887                                              enum pipe pipe)
 888 {
 889         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 891
 892         return intel_crtc->config.cpu_transcoder;
 893 }
 894
 895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 896 {
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 899
 900         frame = I915_READ(frame_reg);
 901
 902         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 903                 WARN(1, "vblank wait timed out\n");
 904 }
 905
 906 /**
 907  * intel_wait_for_vblank - wait for vblank on a given pipe
 908  * @dev: drm device
 909  * @pipe: pipe to wait for
 910  *
 911  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 912  * mode setting code.
 913  */
 914 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 915 {
 916         struct drm_i915_private *dev_priv = dev->dev_private;
 917         int pipestat_reg = PIPESTAT(pipe);
 918
 919         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 920                 g4x_wait_for_vblank(dev, pipe);
 921                 return;
 922         }
 923
 924         /* Clear existing vblank status. Note this will clear any other
 925          * sticky status fields as well.
 926          *
 927          * This races with i915_driver_irq_handler() with the result
 928          * that either function could miss a vblank event.  Here it is not
 929          * fatal, as we will either wait upon the next vblank interrupt or
 930          * timeout.  Generally speaking intel_wait_for_vblank() is only
 931          * called during modeset at which time the GPU should be idle and
 932          * should *not* be performing page flips and thus not waiting on
 933          * vblanks...
 934          * Currently, the result of us stealing a vblank from the irq
 935          * handler is that a single frame will be skipped during swapbuffers.
 936          */
 937         I915_WRITE(pipestat_reg,
 938                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 939
 940         /* Wait for vblank interrupt bit to set */
 941         if (wait_for(I915_READ(pipestat_reg) &
 942                      PIPE_VBLANK_INTERRUPT_STATUS,
 943                      50))
 944                 DRM_DEBUG_KMS("vblank wait timed out\n");
 945 }
 946
 947 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 948 {
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950         u32 reg = PIPEDSL(pipe);
 951         u32 line1, line2;
 952         u32 line_mask;
 953
 954         if (IS_GEN2(dev))
 955                 line_mask = DSL_LINEMASK_GEN2;
 956         else
 957                 line_mask = DSL_LINEMASK_GEN3;
 958
 959         line1 = I915_READ(reg) & line_mask;
 960         mdelay(5);
 961         line2 = I915_READ(reg) & line_mask;
 962
 963         return line1 == line2;
 964 }
 965
 966 /*
 967  * intel_wait_for_pipe_off - wait for pipe to turn off
 968  * @dev: drm device
 969  * @pipe: pipe to wait for
 970  *
 971  * After disabling a pipe, we can't wait for vblank in the usual way,
 972  * spinning on the vblank interrupt status bit, since we won't actually
 973  * see an interrupt when the pipe is disabled.
 974  *
 975  * On Gen4 and above:
 976  *   wait for the pipe register state bit to turn off
 977  *
 978  * Otherwise:
 979  *   wait for the display line value to settle (it usually
 980  *   ends up stopping at the start of the next frame).
 981  *
 982  */
 983 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 984 {
 985         struct drm_i915_private *dev_priv = dev->dev_private;
 986         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 987                                                                       pipe);
 988
 989         if (INTEL_INFO(dev)->gen >= 4) {
 990                 int reg = PIPECONF(cpu_transcoder);
 991
 992                 /* Wait for the Pipe State to go off */
 993                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 994                              100))
 995                         WARN(1, "pipe_off wait timed out\n");
 996         } else {
 997                 /* Wait for the display line to settle */
 998                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 999                         WARN(1, "pipe_off wait timed out\n");
1000         }
1001 }
1002
1003 /*
1004  * ibx_digital_port_connected - is the specified port connected?
1005  * @dev_priv: i915 private structure
1006  * @port: the port to test
1007  *
1008  * Returns true if @port is connected, false otherwise.
1009  */
1010 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011                                 struct intel_digital_port *port)
1012 {
1013         u32 bit;
1014
1015         if (HAS_PCH_IBX(dev_priv->dev)) {
1016                 switch (port->port) {
1017                 case PORT_B:
1018                         bit = SDE_PORTB_HOTPLUG;
1019                         break;
1020                 case PORT_C:
1021                         bit = SDE_PORTC_HOTPLUG;
1022                         break;
1023                 case PORT_D:
1024                         bit = SDE_PORTD_HOTPLUG;
1025                         break;
1026                 default:
1027                         return true;
1028                 }
1029         } else {
1030                 switch (port->port) {
1031                 case PORT_B:
1032                         bit = SDE_PORTB_HOTPLUG_CPT;
1033                         break;
1034                 case PORT_C:
1035                         bit = SDE_PORTC_HOTPLUG_CPT;
1036                         break;
1037                 case PORT_D:
1038                         bit = SDE_PORTD_HOTPLUG_CPT;
1039                         break;
1040                 default:
1041                         return true;
1042                 }
1043         }
1044
1045         return I915_READ(SDEISR) & bit;
1046 }
1047
1048 static const char *state_string(bool enabled)
1049 {
1050         return enabled ? "on" : "off";
1051 }
1052
1053 /* Only for pre-ILK configs */
1054 void assert_pll(struct drm_i915_private *dev_priv,
1055                 enum pipe pipe, bool state)
1056 {
1057         int reg;
1058         u32 val;
1059         bool cur_state;
1060
1061         reg = DPLL(pipe);
1062         val = I915_READ(reg);
1063         cur_state = !!(val & DPLL_VCO_ENABLE);
1064         WARN(cur_state != state,
1065              "PLL state assertion failure (expected %s, current %s)\n",
1066              state_string(state), state_string(cur_state));
1067 }
1068
1069 /* XXX: the dsi pll is shared between MIPI DSI ports */
1070 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1071 {
1072         u32 val;
1073         bool cur_state;
1074
1075         mutex_lock(&dev_priv->dpio_lock);
1076         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1077         mutex_unlock(&dev_priv->dpio_lock);
1078
1079         cur_state = val & DSI_PLL_VCO_EN;
1080         WARN(cur_state != state,
1081              "DSI PLL state assertion failure (expected %s, current %s)\n",
1082              state_string(state), state_string(cur_state));
1083 }
1084 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1085 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086
1087 struct intel_shared_dpll *
1088 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1089 {
1090         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091
1092         if (crtc->config.shared_dpll < 0)
1093                 return NULL;
1094
1095         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1096 }
1097
1098 /* For ILK+ */
1099 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1100                         struct intel_shared_dpll *pll,
1101                         bool state)
1102 {
1103         bool cur_state;
1104         struct intel_dpll_hw_state hw_state;
1105
1106         if (WARN (!pll,
1107                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1108                 return;
1109
1110         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1111         WARN(cur_state != state,
1112              "%s assertion failure (expected %s, current %s)\n",
1113              pll->name, state_string(state), state_string(cur_state));
1114 }
1115
1116 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117                           enum pipe pipe, bool state)
1118 {
1119         int reg;
1120         u32 val;
1121         bool cur_state;
1122         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123                                                                       pipe);
1124
1125         if (HAS_DDI(dev_priv->dev)) {
1126                 /* DDI does not have a specific FDI_TX register */
1127                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1128                 val = I915_READ(reg);
1129                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130         } else {
1131                 reg = FDI_TX_CTL(pipe);
1132                 val = I915_READ(reg);
1133                 cur_state = !!(val & FDI_TX_ENABLE);
1134         }
1135         WARN(cur_state != state,
1136              "FDI TX state assertion failure (expected %s, current %s)\n",
1137              state_string(state), state_string(cur_state));
1138 }
1139 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143                           enum pipe pipe, bool state)
1144 {
1145         int reg;
1146         u32 val;
1147         bool cur_state;
1148
1149         reg = FDI_RX_CTL(pipe);
1150         val = I915_READ(reg);
1151         cur_state = !!(val & FDI_RX_ENABLE);
1152         WARN(cur_state != state,
1153              "FDI RX state assertion failure (expected %s, current %s)\n",
1154              state_string(state), state_string(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160                                       enum pipe pipe)
1161 {
1162         int reg;
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv->dev))
1171                 return;
1172
1173         reg = FDI_TX_CTL(pipe);
1174         val = I915_READ(reg);
1175         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 }
1177
1178 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179                        enum pipe pipe, bool state)
1180 {
1181         int reg;
1182         u32 val;
1183         bool cur_state;
1184
1185         reg = FDI_RX_CTL(pipe);
1186         val = I915_READ(reg);
1187         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1188         WARN(cur_state != state,
1189              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1190              state_string(state), state_string(cur_state));
1191 }
1192
1193 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194                                   enum pipe pipe)
1195 {
1196         int pp_reg, lvds_reg;
1197         u32 val;
1198         enum pipe panel_pipe = PIPE_A;
1199         bool locked = true;
1200
1201         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1202                 pp_reg = PCH_PP_CONTROL;
1203                 lvds_reg = PCH_LVDS;
1204         } else {
1205                 pp_reg = PP_CONTROL;
1206                 lvds_reg = LVDS;
1207         }
1208
1209         val = I915_READ(pp_reg);
1210         if (!(val & PANEL_POWER_ON) ||
1211             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212                 locked = false;
1213
1214         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215                 panel_pipe = PIPE_B;
1216
1217         WARN(panel_pipe == pipe && locked,
1218              "panel assertion failure, pipe %c regs locked\n",
1219              pipe_name(pipe));
1220 }
1221
1222 static void assert_cursor(struct drm_i915_private *dev_priv,
1223                           enum pipe pipe, bool state)
1224 {
1225         struct drm_device *dev = dev_priv->dev;
1226         bool cur_state;
1227
1228         if (IS_845G(dev) || IS_I865G(dev))
1229                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1230         else
1231                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1232
1233         WARN(cur_state != state,
1234              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1235              pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1238 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239
1240 void assert_pipe(struct drm_i915_private *dev_priv,
1241                  enum pipe pipe, bool state)
1242 {
1243         int reg;
1244         u32 val;
1245         bool cur_state;
1246         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247                                                                       pipe);
1248
1249         /* if we need the pipe A quirk it must be always on */
1250         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1251                 state = true;
1252
1253         if (!intel_display_power_enabled(dev_priv,
1254                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1255                 cur_state = false;
1256         } else {
1257                 reg = PIPECONF(cpu_transcoder);
1258                 val = I915_READ(reg);
1259                 cur_state = !!(val & PIPECONF_ENABLE);
1260         }
1261
1262         WARN(cur_state != state,
1263              "pipe %c assertion failure (expected %s, current %s)\n",
1264              pipe_name(pipe), state_string(state), state_string(cur_state));
1265 }
1266
1267 static void assert_plane(struct drm_i915_private *dev_priv,
1268                          enum plane plane, bool state)
1269 {
1270         int reg;
1271         u32 val;
1272         bool cur_state;
1273
1274         reg = DSPCNTR(plane);
1275         val = I915_READ(reg);
1276         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1277         WARN(cur_state != state,
1278              "plane %c assertion failure (expected %s, current %s)\n",
1279              plane_name(plane), state_string(state), state_string(cur_state));
1280 }
1281
1282 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1283 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284
1285 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1286                                    enum pipe pipe)
1287 {
1288         struct drm_device *dev = dev_priv->dev;
1289         int reg, i;
1290         u32 val;
1291         int cur_pipe;
1292
1293         /* Primary planes are fixed to pipes on gen4+ */
1294         if (INTEL_INFO(dev)->gen >= 4) {
1295                 reg = DSPCNTR(pipe);
1296                 val = I915_READ(reg);
1297                 WARN(val & DISPLAY_PLANE_ENABLE,
1298                      "plane %c assertion failure, should be disabled but not\n",
1299                      plane_name(pipe));
1300                 return;
1301         }
1302
1303         /* Need to check both planes against the pipe */
1304         for_each_pipe(i) {
1305                 reg = DSPCNTR(i);
1306                 val = I915_READ(reg);
1307                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1308                         DISPPLANE_SEL_PIPE_SHIFT;
1309                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1310                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1311                      plane_name(i), pipe_name(pipe));
1312         }
1313 }
1314
1315 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1316                                     enum pipe pipe)
1317 {
1318         struct drm_device *dev = dev_priv->dev;
1319         int reg, sprite;
1320         u32 val;
1321
1322         if (IS_VALLEYVIEW(dev)) {
1323                 for_each_sprite(pipe, sprite) {
1324                         reg = SPCNTR(pipe, sprite);
1325                         val = I915_READ(reg);
1326                         WARN(val & SP_ENABLE,
1327                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328                              sprite_name(pipe, sprite), pipe_name(pipe));
1329                 }
1330         } else if (INTEL_INFO(dev)->gen >= 7) {
1331                 reg = SPRCTL(pipe);
1332                 val = I915_READ(reg);
1333                 WARN(val & SPRITE_ENABLE,
1334                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1335                      plane_name(pipe), pipe_name(pipe));
1336         } else if (INTEL_INFO(dev)->gen >= 5) {
1337                 reg = DVSCNTR(pipe);
1338                 val = I915_READ(reg);
1339                 WARN(val & DVS_ENABLE,
1340                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341                      plane_name(pipe), pipe_name(pipe));
1342         }
1343 }
1344
1345 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1346 {
1347         u32 val;
1348         bool enabled;
1349
1350         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1351
1352         val = I915_READ(PCH_DREF_CONTROL);
1353         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1354                             DREF_SUPERSPREAD_SOURCE_MASK));
1355         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1356 }
1357
1358 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359                                            enum pipe pipe)
1360 {
1361         int reg;
1362         u32 val;
1363         bool enabled;
1364
1365         reg = PCH_TRANSCONF(pipe);
1366         val = I915_READ(reg);
1367         enabled = !!(val & TRANS_ENABLE);
1368         WARN(enabled,
1369              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1370              pipe_name(pipe));
1371 }
1372
1373 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1374                             enum pipe pipe, u32 port_sel, u32 val)
1375 {
1376         if ((val & DP_PORT_EN) == 0)
1377                 return false;
1378
1379         if (HAS_PCH_CPT(dev_priv->dev)) {
1380                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1381                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1382                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383                         return false;
1384         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1385                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386                         return false;
1387         } else {
1388                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389                         return false;
1390         }
1391         return true;
1392 }
1393
1394 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395                               enum pipe pipe, u32 val)
1396 {
1397         if ((val & SDVO_ENABLE) == 0)
1398                 return false;
1399
1400         if (HAS_PCH_CPT(dev_priv->dev)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1402                         return false;
1403         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1404                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405                         return false;
1406         } else {
1407                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1408                         return false;
1409         }
1410         return true;
1411 }
1412
1413 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414                               enum pipe pipe, u32 val)
1415 {
1416         if ((val & LVDS_PORT_EN) == 0)
1417                 return false;
1418
1419         if (HAS_PCH_CPT(dev_priv->dev)) {
1420                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421                         return false;
1422         } else {
1423                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424                         return false;
1425         }
1426         return true;
1427 }
1428
1429 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430                               enum pipe pipe, u32 val)
1431 {
1432         if ((val & ADPA_DAC_ENABLE) == 0)
1433                 return false;
1434         if (HAS_PCH_CPT(dev_priv->dev)) {
1435                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436                         return false;
1437         } else {
1438                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439                         return false;
1440         }
1441         return true;
1442 }
1443
1444 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1445                                    enum pipe pipe, int reg, u32 port_sel)
1446 {
1447         u32 val = I915_READ(reg);
1448         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1449              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1450              reg, pipe_name(pipe));
1451
1452         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1453              && (val & DP_PIPEB_SELECT),
1454              "IBX PCH dp port still using transcoder B\n");
1455 }
1456
1457 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1458                                      enum pipe pipe, int reg)
1459 {
1460         u32 val = I915_READ(reg);
1461         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1462              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1463              reg, pipe_name(pipe));
1464
1465         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1466              && (val & SDVO_PIPE_B_SELECT),
1467              "IBX PCH hdmi port still using transcoder B\n");
1468 }
1469
1470 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1471                                       enum pipe pipe)
1472 {
1473         int reg;
1474         u32 val;
1475
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1479
1480         reg = PCH_ADPA;
1481         val = I915_READ(reg);
1482         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1483              "PCH VGA enabled on transcoder %c, should be disabled\n",
1484              pipe_name(pipe));
1485
1486         reg = PCH_LVDS;
1487         val = I915_READ(reg);
1488         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1489              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1490              pipe_name(pipe));
1491
1492         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1493         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1494         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1495 }
1496
1497 static void intel_init_dpio(struct drm_device *dev)
1498 {
1499         struct drm_i915_private *dev_priv = dev->dev_private;
1500
1501         if (!IS_VALLEYVIEW(dev))
1502                 return;
1503
1504         /*
1505          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1506          * CHV x1 PHY (DP/HDMI D)
1507          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1508          */
1509         if (IS_CHERRYVIEW(dev)) {
1510                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1511                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1512         } else {
1513                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1514         }
1515 }
1516
1517 static void vlv_enable_pll(struct intel_crtc *crtc)
1518 {
1519         struct drm_device *dev = crtc->base.dev;
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         int reg = DPLL(crtc->pipe);
1522         u32 dpll = crtc->config.dpll_hw_state.dpll;
1523
1524         assert_pipe_disabled(dev_priv, crtc->pipe);
1525
1526         /* No really, not for ILK+ */
1527         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1528
1529         /* PLL is protected by panel, make sure we can write it */
1530         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1531                 assert_panel_unlocked(dev_priv, crtc->pipe);
1532
1533         I915_WRITE(reg, dpll);
1534         POSTING_READ(reg);
1535         udelay(150);
1536
1537         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1538                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1539
1540         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1541         POSTING_READ(DPLL_MD(crtc->pipe));
1542
1543         /* We do this three times for luck */
1544         I915_WRITE(reg, dpll);
1545         POSTING_READ(reg);
1546         udelay(150); /* wait for warmup */
1547         I915_WRITE(reg, dpll);
1548         POSTING_READ(reg);
1549         udelay(150); /* wait for warmup */
1550         I915_WRITE(reg, dpll);
1551         POSTING_READ(reg);
1552         udelay(150); /* wait for warmup */
1553 }
1554
1555 static void chv_enable_pll(struct intel_crtc *crtc)
1556 {
1557         struct drm_device *dev = crtc->base.dev;
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         int pipe = crtc->pipe;
1560         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1561         u32 tmp;
1562
1563         assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1566
1567         mutex_lock(&dev_priv->dpio_lock);
1568
1569         /* Enable back the 10bit clock to display controller */
1570         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1571         tmp |= DPIO_DCLKP_EN;
1572         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1573
1574         /*
1575          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1576          */
1577         udelay(1);
1578
1579         /* Enable PLL */
1580         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1581
1582         /* Check PLL is locked */
1583         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1584                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1585
1586         /* not sure when this should be written */
1587         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1588         POSTING_READ(DPLL_MD(pipe));
1589
1590         mutex_unlock(&dev_priv->dpio_lock);
1591 }
1592
1593 static void i9xx_enable_pll(struct intel_crtc *crtc)
1594 {
1595         struct drm_device *dev = crtc->base.dev;
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         int reg = DPLL(crtc->pipe);
1598         u32 dpll = crtc->config.dpll_hw_state.dpll;
1599
1600         assert_pipe_disabled(dev_priv, crtc->pipe);
1601
1602         /* No really, not for ILK+ */
1603         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1604
1605         /* PLL is protected by panel, make sure we can write it */
1606         if (IS_MOBILE(dev) && !IS_I830(dev))
1607                 assert_panel_unlocked(dev_priv, crtc->pipe);
1608
1609         I915_WRITE(reg, dpll);
1610
1611         /* Wait for the clocks to stabilize. */
1612         POSTING_READ(reg);
1613         udelay(150);
1614
1615         if (INTEL_INFO(dev)->gen >= 4) {
1616                 I915_WRITE(DPLL_MD(crtc->pipe),
1617                            crtc->config.dpll_hw_state.dpll_md);
1618         } else {
1619                 /* The pixel multiplier can only be updated once the
1620                  * DPLL is enabled and the clocks are stable.
1621                  *
1622                  * So write it again.
1623                  */
1624                 I915_WRITE(reg, dpll);
1625         }
1626
1627         /* We do this three times for luck */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634         I915_WRITE(reg, dpll);
1635         POSTING_READ(reg);
1636         udelay(150); /* wait for warmup */
1637 }
1638
1639 /**
1640  * i9xx_disable_pll - disable a PLL
1641  * @dev_priv: i915 private structure
1642  * @pipe: pipe PLL to disable
1643  *
1644  * Disable the PLL for @pipe, making sure the pipe is off first.
1645  *
1646  * Note!  This is for pre-ILK only.
1647  */
1648 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1649 {
1650         /* Don't disable pipe A or pipe A PLLs if needed */
1651         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1652                 return;
1653
1654         /* Make sure the pipe isn't still relying on us */
1655         assert_pipe_disabled(dev_priv, pipe);
1656
1657         I915_WRITE(DPLL(pipe), 0);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         u32 val = 0;
1664
1665         /* Make sure the pipe isn't still relying on us */
1666         assert_pipe_disabled(dev_priv, pipe);
1667
1668         /*
1669          * Leave integrated clock source and reference clock enabled for pipe B.
1670          * The latter is needed for VGA hotplug / manual detection.
1671          */
1672         if (pipe == PIPE_B)
1673                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677 }
1678
1679 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1680 {
1681         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1682         u32 val;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         /* Set PLL en = 0 */
1688         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1689         if (pipe != PIPE_A)
1690                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1691         I915_WRITE(DPLL(pipe), val);
1692         POSTING_READ(DPLL(pipe));
1693
1694         mutex_lock(&dev_priv->dpio_lock);
1695
1696         /* Disable 10bit clock to display controller */
1697         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1698         val &= ~DPIO_DCLKP_EN;
1699         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1700
1701         /* disable left/right clock distribution */
1702         if (pipe != PIPE_B) {
1703                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1704                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1705                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1706         } else {
1707                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1708                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1709                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1710         }
1711
1712         mutex_unlock(&dev_priv->dpio_lock);
1713 }
1714
1715 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1716                 struct intel_digital_port *dport)
1717 {
1718         u32 port_mask;
1719         int dpll_reg;
1720
1721         switch (dport->port) {
1722         case PORT_B:
1723                 port_mask = DPLL_PORTB_READY_MASK;
1724                 dpll_reg = DPLL(0);
1725                 break;
1726         case PORT_C:
1727                 port_mask = DPLL_PORTC_READY_MASK;
1728                 dpll_reg = DPLL(0);
1729                 break;
1730         case PORT_D:
1731                 port_mask = DPLL_PORTD_READY_MASK;
1732                 dpll_reg = DPIO_PHY_STATUS;
1733                 break;
1734         default:
1735                 BUG();
1736         }
1737
1738         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1739                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1740                      port_name(dport->port), I915_READ(dpll_reg));
1741 }
1742
1743 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1744 {
1745         struct drm_device *dev = crtc->base.dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1748
1749         if (WARN_ON(pll == NULL))
1750                 return;
1751
1752         WARN_ON(!pll->refcount);
1753         if (pll->active == 0) {
1754                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755                 WARN_ON(pll->on);
1756                 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758                 pll->mode_set(dev_priv, pll);
1759         }
1760 }
1761
1762 /**
1763  * intel_enable_shared_dpll - enable PCH PLL
1764  * @dev_priv: i915 private structure
1765  * @pipe: pipe PLL to enable
1766  *
1767  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768  * drives the transcoder clock.
1769  */
1770 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1771 {
1772         struct drm_device *dev = crtc->base.dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776         if (WARN_ON(pll == NULL))
1777                 return;
1778
1779         if (WARN_ON(pll->refcount == 0))
1780                 return;
1781
1782         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1783                       pll->name, pll->active, pll->on,
1784                       crtc->base.base.id);
1785
1786         if (pll->active++) {
1787                 WARN_ON(!pll->on);
1788                 assert_shared_dpll_enabled(dev_priv, pll);
1789                 return;
1790         }
1791         WARN_ON(pll->on);
1792
1793         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1794
1795         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1796         pll->enable(dev_priv, pll);
1797         pll->on = true;
1798 }
1799
1800 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         /* PCH only available on ILK+ */
1807         BUG_ON(INTEL_INFO(dev)->gen < 5);
1808         if (WARN_ON(pll == NULL))
1809                return;
1810
1811         if (WARN_ON(pll->refcount == 0))
1812                 return;
1813
1814         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815                       pll->name, pll->active, pll->on,
1816                       crtc->base.base.id);
1817
1818         if (WARN_ON(pll->active == 0)) {
1819                 assert_shared_dpll_disabled(dev_priv, pll);
1820                 return;
1821         }
1822
1823         assert_shared_dpll_enabled(dev_priv, pll);
1824         WARN_ON(!pll->on);
1825         if (--pll->active)
1826                 return;
1827
1828         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1829         pll->disable(dev_priv, pll);
1830         pll->on = false;
1831
1832         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1833 }
1834
1835 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1836                                            enum pipe pipe)
1837 {
1838         struct drm_device *dev = dev_priv->dev;
1839         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1841         uint32_t reg, val, pipeconf_val;
1842
1843         /* PCH only available on ILK+ */
1844         BUG_ON(INTEL_INFO(dev)->gen < 5);
1845
1846         /* Make sure PCH DPLL is enabled */
1847         assert_shared_dpll_enabled(dev_priv,
1848                                    intel_crtc_to_shared_dpll(intel_crtc));
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, pipe);
1852         assert_fdi_rx_enabled(dev_priv, pipe);
1853
1854         if (HAS_PCH_CPT(dev)) {
1855                 /* Workaround: Set the timing override bit before enabling the
1856                  * pch transcoder. */
1857                 reg = TRANS_CHICKEN2(pipe);
1858                 val = I915_READ(reg);
1859                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1860                 I915_WRITE(reg, val);
1861         }
1862
1863         reg = PCH_TRANSCONF(pipe);
1864         val = I915_READ(reg);
1865         pipeconf_val = I915_READ(PIPECONF(pipe));
1866
1867         if (HAS_PCH_IBX(dev_priv->dev)) {
1868                 /*
1869                  * make the BPC in transcoder be consistent with
1870                  * that in pipeconf reg.
1871                  */
1872                 val &= ~PIPECONF_BPC_MASK;
1873                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1874         }
1875
1876         val &= ~TRANS_INTERLACE_MASK;
1877         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1878                 if (HAS_PCH_IBX(dev_priv->dev) &&
1879                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1880                         val |= TRANS_LEGACY_INTERLACED_ILK;
1881                 else
1882                         val |= TRANS_INTERLACED;
1883         else
1884                 val |= TRANS_PROGRESSIVE;
1885
1886         I915_WRITE(reg, val | TRANS_ENABLE);
1887         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1888                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1889 }
1890
1891 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1892                                       enum transcoder cpu_transcoder)
1893 {
1894         u32 val, pipeconf_val;
1895
1896         /* PCH only available on ILK+ */
1897         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1898
1899         /* FDI must be feeding us bits for PCH ports */
1900         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1901         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1902
1903         /* Workaround: set timing override bit. */
1904         val = I915_READ(_TRANSA_CHICKEN2);
1905         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1906         I915_WRITE(_TRANSA_CHICKEN2, val);
1907
1908         val = TRANS_ENABLE;
1909         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1910
1911         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1912             PIPECONF_INTERLACED_ILK)
1913                 val |= TRANS_INTERLACED;
1914         else
1915                 val |= TRANS_PROGRESSIVE;
1916
1917         I915_WRITE(LPT_TRANSCONF, val);
1918         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1919                 DRM_ERROR("Failed to enable PCH transcoder\n");
1920 }
1921
1922 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1923                                             enum pipe pipe)
1924 {
1925         struct drm_device *dev = dev_priv->dev;
1926         uint32_t reg, val;
1927
1928         /* FDI relies on the transcoder */
1929         assert_fdi_tx_disabled(dev_priv, pipe);
1930         assert_fdi_rx_disabled(dev_priv, pipe);
1931
1932         /* Ports must be off as well */
1933         assert_pch_ports_disabled(dev_priv, pipe);
1934
1935         reg = PCH_TRANSCONF(pipe);
1936         val = I915_READ(reg);
1937         val &= ~TRANS_ENABLE;
1938         I915_WRITE(reg, val);
1939         /* wait for PCH transcoder off, transcoder state */
1940         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1941                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1942
1943         if (!HAS_PCH_IBX(dev)) {
1944                 /* Workaround: Clear the timing override chicken bit again. */
1945                 reg = TRANS_CHICKEN2(pipe);
1946                 val = I915_READ(reg);
1947                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1948                 I915_WRITE(reg, val);
1949         }
1950 }
1951
1952 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1953 {
1954         u32 val;
1955
1956         val = I915_READ(LPT_TRANSCONF);
1957         val &= ~TRANS_ENABLE;
1958         I915_WRITE(LPT_TRANSCONF, val);
1959         /* wait for PCH transcoder off, transcoder state */
1960         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1961                 DRM_ERROR("Failed to disable PCH transcoder\n");
1962
1963         /* Workaround: clear timing override bit. */
1964         val = I915_READ(_TRANSA_CHICKEN2);
1965         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1966         I915_WRITE(_TRANSA_CHICKEN2, val);
1967 }
1968
1969 /**
1970  * intel_enable_pipe - enable a pipe, asserting requirements
1971  * @crtc: crtc responsible for the pipe
1972  *
1973  * Enable @crtc's pipe, making sure that various hardware specific requirements
1974  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1975  */
1976 static void intel_enable_pipe(struct intel_crtc *crtc)
1977 {
1978         struct drm_device *dev = crtc->base.dev;
1979         struct drm_i915_private *dev_priv = dev->dev_private;
1980         enum pipe pipe = crtc->pipe;
1981         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1982                                                                       pipe);
1983         enum pipe pch_transcoder;
1984         int reg;
1985         u32 val;
1986
1987         assert_planes_disabled(dev_priv, pipe);
1988         assert_cursor_disabled(dev_priv, pipe);
1989         assert_sprites_disabled(dev_priv, pipe);
1990
1991         if (HAS_PCH_LPT(dev_priv->dev))
1992                 pch_transcoder = TRANSCODER_A;
1993         else
1994                 pch_transcoder = pipe;
1995
1996         /*
1997          * A pipe without a PLL won't actually be able to drive bits from
1998          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1999          * need the check.
2000          */
2001         if (!HAS_PCH_SPLIT(dev_priv->dev))
2002                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2003                         assert_dsi_pll_enabled(dev_priv);
2004                 else
2005                         assert_pll_enabled(dev_priv, pipe);
2006         else {
2007                 if (crtc->config.has_pch_encoder) {
2008                         /* if driving the PCH, we need FDI enabled */
2009                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2010                         assert_fdi_tx_pll_enabled(dev_priv,
2011                                                   (enum pipe) cpu_transcoder);
2012                 }
2013                 /* FIXME: assert CPU port conditions for SNB+ */
2014         }
2015
2016         reg = PIPECONF(cpu_transcoder);
2017         val = I915_READ(reg);
2018         if (val & PIPECONF_ENABLE) {
2019                 WARN_ON(!(pipe == PIPE_A &&
2020                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2021                 return;
2022         }
2023
2024         I915_WRITE(reg, val | PIPECONF_ENABLE);
2025         POSTING_READ(reg);
2026 }
2027
2028 /**
2029  * intel_disable_pipe - disable a pipe, asserting requirements
2030  * @dev_priv: i915 private structure
2031  * @pipe: pipe to disable
2032  *
2033  * Disable @pipe, making sure that various hardware specific requirements
2034  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2035  *
2036  * @pipe should be %PIPE_A or %PIPE_B.
2037  *
2038  * Will wait until the pipe has shut down before returning.
2039  */
2040 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2041                                enum pipe pipe)
2042 {
2043         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2044                                                                       pipe);
2045         int reg;
2046         u32 val;
2047
2048         /*
2049          * Make sure planes won't keep trying to pump pixels to us,
2050          * or we might hang the display.
2051          */
2052         assert_planes_disabled(dev_priv, pipe);
2053         assert_cursor_disabled(dev_priv, pipe);
2054         assert_sprites_disabled(dev_priv, pipe);
2055
2056         /* Don't disable pipe A or pipe A PLLs if needed */
2057         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2058                 return;
2059
2060         reg = PIPECONF(cpu_transcoder);
2061         val = I915_READ(reg);
2062         if ((val & PIPECONF_ENABLE) == 0)
2063                 return;
2064
2065         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2066         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2067 }
2068
2069 /*
2070  * Plane regs are double buffered, going from enabled->disabled needs a
2071  * trigger in order to latch.  The display address reg provides this.
2072  */
2073 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2074                                enum plane plane)
2075 {
2076         struct drm_device *dev = dev_priv->dev;
2077         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2078
2079         I915_WRITE(reg, I915_READ(reg));
2080         POSTING_READ(reg);
2081 }
2082
2083 /**
2084  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2085  * @plane:  plane to be enabled
2086  * @crtc: crtc for the plane
2087  *
2088  * Enable @plane on @crtc, making sure that the pipe is running first.
2089  */
2090 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2091                                           struct drm_crtc *crtc)
2092 {
2093         struct drm_device *dev = plane->dev;
2094         struct drm_i915_private *dev_priv = dev->dev_private;
2095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2096
2097         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2098         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2099
2100         if (intel_crtc->primary_enabled)
2101                 return;
2102
2103         intel_crtc->primary_enabled = true;
2104
2105         dev_priv->display.update_primary_plane(crtc, plane->fb,
2106                                                crtc->x, crtc->y);
2107
2108         /*
2109          * BDW signals flip done immediately if the plane
2110          * is disabled, even if the plane enable is already
2111          * armed to occur at the next vblank :(
2112          */
2113         if (IS_BROADWELL(dev))
2114                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2115 }
2116
2117 /**
2118  * intel_disable_primary_hw_plane - disable the primary hardware plane
2119  * @plane: plane to be disabled
2120  * @crtc: crtc for the plane
2121  *
2122  * Disable @plane on @crtc, making sure that the pipe is running first.
2123  */
2124 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2125                                            struct drm_crtc *crtc)
2126 {
2127         struct drm_device *dev = plane->dev;
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130
2131         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2132
2133         if (!intel_crtc->primary_enabled)
2134                 return;
2135
2136         intel_crtc->primary_enabled = false;
2137
2138         dev_priv->display.update_primary_plane(crtc, plane->fb,
2139                                                crtc->x, crtc->y);
2140 }
2141
2142 static bool need_vtd_wa(struct drm_device *dev)
2143 {
2144 #ifdef CONFIG_INTEL_IOMMU
2145         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146                 return true;
2147 #endif
2148         return false;
2149 }
2150
2151 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2152 {
2153         int tile_height;
2154
2155         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2156         return ALIGN(height, tile_height);
2157 }
2158
2159 int
2160 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2161                            struct drm_i915_gem_object *obj,
2162                            struct intel_engine_cs *pipelined)
2163 {
2164         struct drm_i915_private *dev_priv = dev->dev_private;
2165         u32 alignment;
2166         int ret;
2167
2168         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2169
2170         switch (obj->tiling_mode) {
2171         case I915_TILING_NONE:
2172                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2173                         alignment = 128 * 1024;
2174                 else if (INTEL_INFO(dev)->gen >= 4)
2175                         alignment = 4 * 1024;
2176                 else
2177                         alignment = 64 * 1024;
2178                 break;
2179         case I915_TILING_X:
2180                 /* pin() will align the object as required by fence */
2181                 alignment = 0;
2182                 break;
2183         case I915_TILING_Y:
2184                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2185                 return -EINVAL;
2186         default:
2187                 BUG();
2188         }
2189
2190         /* Note that the w/a also requires 64 PTE of padding following the
2191          * bo. We currently fill all unused PTE with the shadow page and so
2192          * we should always have valid PTE following the scanout preventing
2193          * the VT-d warning.
2194          */
2195         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2196                 alignment = 256 * 1024;
2197
2198         dev_priv->mm.interruptible = false;
2199         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2200         if (ret)
2201                 goto err_interruptible;
2202
2203         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2204          * fence, whereas 965+ only requires a fence if using
2205          * framebuffer compression.  For simplicity, we always install
2206          * a fence as the cost is not that onerous.
2207          */
2208         ret = i915_gem_object_get_fence(obj);
2209         if (ret)
2210                 goto err_unpin;
2211
2212         i915_gem_object_pin_fence(obj);
2213
2214         dev_priv->mm.interruptible = true;
2215         return 0;
2216
2217 err_unpin:
2218         i915_gem_object_unpin_from_display_plane(obj);
2219 err_interruptible:
2220         dev_priv->mm.interruptible = true;
2221         return ret;
2222 }
2223
2224 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2225 {
2226         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2227
2228         i915_gem_object_unpin_fence(obj);
2229         i915_gem_object_unpin_from_display_plane(obj);
2230 }
2231
2232 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2233  * is assumed to be a power-of-two. */
2234 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2235                                              unsigned int tiling_mode,
2236                                              unsigned int cpp,
2237                                              unsigned int pitch)
2238 {
2239         if (tiling_mode != I915_TILING_NONE) {
2240                 unsigned int tile_rows, tiles;
2241
2242                 tile_rows = *y / 8;
2243                 *y %= 8;
2244
2245                 tiles = *x / (512/cpp);
2246                 *x %= 512/cpp;
2247
2248                 return tile_rows * pitch * 8 + tiles * 4096;
2249         } else {
2250                 unsigned int offset;
2251
2252                 offset = *y * pitch + *x * cpp;
2253                 *y = 0;
2254                 *x = (offset & 4095) / cpp;
2255                 return offset & -4096;
2256         }
2257 }
2258
2259 int intel_format_to_fourcc(int format)
2260 {
2261         switch (format) {
2262         case DISPPLANE_8BPP:
2263                 return DRM_FORMAT_C8;
2264         case DISPPLANE_BGRX555:
2265                 return DRM_FORMAT_XRGB1555;
2266         case DISPPLANE_BGRX565:
2267                 return DRM_FORMAT_RGB565;
2268         default:
2269         case DISPPLANE_BGRX888:
2270                 return DRM_FORMAT_XRGB8888;
2271         case DISPPLANE_RGBX888:
2272                 return DRM_FORMAT_XBGR8888;
2273         case DISPPLANE_BGRX101010:
2274                 return DRM_FORMAT_XRGB2101010;
2275         case DISPPLANE_RGBX101010:
2276                 return DRM_FORMAT_XBGR2101010;
2277         }
2278 }
2279
2280 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2281                                   struct intel_plane_config *plane_config)
2282 {
2283         struct drm_device *dev = crtc->base.dev;
2284         struct drm_i915_gem_object *obj = NULL;
2285         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2286         u32 base = plane_config->base;
2287
2288         if (plane_config->size == 0)
2289                 return false;
2290
2291         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2292                                                              plane_config->size);
2293         if (!obj)
2294                 return false;
2295
2296         if (plane_config->tiled) {
2297                 obj->tiling_mode = I915_TILING_X;
2298                 obj->stride = crtc->base.primary->fb->pitches[0];
2299         }
2300
2301         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2302         mode_cmd.width = crtc->base.primary->fb->width;
2303         mode_cmd.height = crtc->base.primary->fb->height;
2304         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2305
2306         mutex_lock(&dev->struct_mutex);
2307
2308         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2309                                    &mode_cmd, obj)) {
2310                 DRM_DEBUG_KMS("intel fb init failed\n");
2311                 goto out_unref_obj;
2312         }
2313
2314         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2315         mutex_unlock(&dev->struct_mutex);
2316
2317         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2318         return true;
2319
2320 out_unref_obj:
2321         drm_gem_object_unreference(&obj->base);
2322         mutex_unlock(&dev->struct_mutex);
2323         return false;
2324 }
2325
2326 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2327                                  struct intel_plane_config *plane_config)
2328 {
2329         struct drm_device *dev = intel_crtc->base.dev;
2330         struct drm_crtc *c;
2331         struct intel_crtc *i;
2332         struct drm_i915_gem_object *obj;
2333
2334         if (!intel_crtc->base.primary->fb)
2335                 return;
2336
2337         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2338                 return;
2339
2340         kfree(intel_crtc->base.primary->fb);
2341         intel_crtc->base.primary->fb = NULL;
2342
2343         /*
2344          * Failed to alloc the obj, check to see if we should share
2345          * an fb with another CRTC instead
2346          */
2347         for_each_crtc(dev, c) {
2348                 i = to_intel_crtc(c);
2349
2350                 if (c == &intel_crtc->base)
2351                         continue;
2352
2353                 if (!i->active)
2354                         continue;
2355
2356                 obj = intel_fb_obj(c->primary->fb);
2357                 if (obj == NULL)
2358                         continue;
2359
2360                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2361                         drm_framebuffer_reference(c->primary->fb);
2362                         intel_crtc->base.primary->fb = c->primary->fb;
2363                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2364                         break;
2365                 }
2366         }
2367 }
2368
2369 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2370                                       struct drm_framebuffer *fb,
2371                                       int x, int y)
2372 {
2373         struct drm_device *dev = crtc->dev;
2374         struct drm_i915_private *dev_priv = dev->dev_private;
2375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2377         int plane = intel_crtc->plane;
2378         unsigned long linear_offset;
2379         u32 dspcntr;
2380         u32 reg = DSPCNTR(plane);
2381
2382         if (!intel_crtc->primary_enabled) {
2383                 I915_WRITE(reg, 0);
2384                 if (INTEL_INFO(dev)->gen >= 4)
2385                         I915_WRITE(DSPSURF(plane), 0);
2386                 else
2387                         I915_WRITE(DSPADDR(plane), 0);
2388                 POSTING_READ(reg);
2389                 return;
2390         }
2391
2392         dspcntr = DISPPLANE_GAMMA_ENABLE;
2393
2394         dspcntr |= DISPLAY_PLANE_ENABLE;
2395
2396         if (INTEL_INFO(dev)->gen < 4) {
2397                 if (intel_crtc->pipe == PIPE_B)
2398                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2399
2400                 /* pipesrc and dspsize control the size that is scaled from,
2401                  * which should always be the user's requested size.
2402                  */
2403                 I915_WRITE(DSPSIZE(plane),
2404                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2405                            (intel_crtc->config.pipe_src_w - 1));
2406                 I915_WRITE(DSPPOS(plane), 0);
2407         }
2408
2409         switch (fb->pixel_format) {
2410         case DRM_FORMAT_C8:
2411                 dspcntr |= DISPPLANE_8BPP;
2412                 break;
2413         case DRM_FORMAT_XRGB1555:
2414         case DRM_FORMAT_ARGB1555:
2415                 dspcntr |= DISPPLANE_BGRX555;
2416                 break;
2417         case DRM_FORMAT_RGB565:
2418                 dspcntr |= DISPPLANE_BGRX565;
2419                 break;
2420         case DRM_FORMAT_XRGB8888:
2421         case DRM_FORMAT_ARGB8888:
2422                 dspcntr |= DISPPLANE_BGRX888;
2423                 break;
2424         case DRM_FORMAT_XBGR8888:
2425         case DRM_FORMAT_ABGR8888:
2426                 dspcntr |= DISPPLANE_RGBX888;
2427                 break;
2428         case DRM_FORMAT_XRGB2101010:
2429         case DRM_FORMAT_ARGB2101010:
2430                 dspcntr |= DISPPLANE_BGRX101010;
2431                 break;
2432         case DRM_FORMAT_XBGR2101010:
2433         case DRM_FORMAT_ABGR2101010:
2434                 dspcntr |= DISPPLANE_RGBX101010;
2435                 break;
2436         default:
2437                 BUG();
2438         }
2439
2440         if (INTEL_INFO(dev)->gen >= 4 &&
2441             obj->tiling_mode != I915_TILING_NONE)
2442                 dspcntr |= DISPPLANE_TILED;
2443
2444         if (IS_G4X(dev))
2445                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2446
2447         I915_WRITE(reg, dspcntr);
2448
2449         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2450
2451         if (INTEL_INFO(dev)->gen >= 4) {
2452                 intel_crtc->dspaddr_offset =
2453                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2454                                                        fb->bits_per_pixel / 8,
2455                                                        fb->pitches[0]);
2456                 linear_offset -= intel_crtc->dspaddr_offset;
2457         } else {
2458                 intel_crtc->dspaddr_offset = linear_offset;
2459         }
2460
2461         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2462                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2463                       fb->pitches[0]);
2464         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2465         if (INTEL_INFO(dev)->gen >= 4) {
2466                 I915_WRITE(DSPSURF(plane),
2467                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2468                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2469                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2470         } else
2471                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2472         POSTING_READ(reg);
2473 }
2474
2475 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2476                                           struct drm_framebuffer *fb,
2477                                           int x, int y)
2478 {
2479         struct drm_device *dev = crtc->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2483         int plane = intel_crtc->plane;
2484         unsigned long linear_offset;
2485         u32 dspcntr;
2486         u32 reg = DSPCNTR(plane);
2487
2488         if (!intel_crtc->primary_enabled) {
2489                 I915_WRITE(reg, 0);
2490                 I915_WRITE(DSPSURF(plane), 0);
2491                 POSTING_READ(reg);
2492                 return;
2493         }
2494
2495         dspcntr = DISPPLANE_GAMMA_ENABLE;
2496
2497         dspcntr |= DISPLAY_PLANE_ENABLE;
2498
2499         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2500                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2501
2502         switch (fb->pixel_format) {
2503         case DRM_FORMAT_C8:
2504                 dspcntr |= DISPPLANE_8BPP;
2505                 break;
2506         case DRM_FORMAT_RGB565:
2507                 dspcntr |= DISPPLANE_BGRX565;
2508                 break;
2509         case DRM_FORMAT_XRGB8888:
2510         case DRM_FORMAT_ARGB8888:
2511                 dspcntr |= DISPPLANE_BGRX888;
2512                 break;
2513         case DRM_FORMAT_XBGR8888:
2514         case DRM_FORMAT_ABGR8888:
2515                 dspcntr |= DISPPLANE_RGBX888;
2516                 break;
2517         case DRM_FORMAT_XRGB2101010:
2518         case DRM_FORMAT_ARGB2101010:
2519                 dspcntr |= DISPPLANE_BGRX101010;
2520                 break;
2521         case DRM_FORMAT_XBGR2101010:
2522         case DRM_FORMAT_ABGR2101010:
2523                 dspcntr |= DISPPLANE_RGBX101010;
2524                 break;
2525         default:
2526                 BUG();
2527         }
2528
2529         if (obj->tiling_mode != I915_TILING_NONE)
2530                 dspcntr |= DISPPLANE_TILED;
2531
2532         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2533                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2534
2535         I915_WRITE(reg, dspcntr);
2536
2537         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2538         intel_crtc->dspaddr_offset =
2539                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2540                                                fb->bits_per_pixel / 8,
2541                                                fb->pitches[0]);
2542         linear_offset -= intel_crtc->dspaddr_offset;
2543
2544         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2545                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2546                       fb->pitches[0]);
2547         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2548         I915_WRITE(DSPSURF(plane),
2549                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2550         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2551                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2552         } else {
2553                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2554                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2555         }
2556         POSTING_READ(reg);
2557 }
2558
2559 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2560 static int
2561 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2562                            int x, int y, enum mode_set_atomic state)
2563 {
2564         struct drm_device *dev = crtc->dev;
2565         struct drm_i915_private *dev_priv = dev->dev_private;
2566
2567         if (dev_priv->display.disable_fbc)
2568                 dev_priv->display.disable_fbc(dev);
2569         intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2570
2571         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2572
2573         return 0;
2574 }
2575
2576 void intel_display_handle_reset(struct drm_device *dev)
2577 {
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579         struct drm_crtc *crtc;
2580
2581         /*
2582          * Flips in the rings have been nuked by the reset,
2583          * so complete all pending flips so that user space
2584          * will get its events and not get stuck.
2585          *
2586          * Also update the base address of all primary
2587          * planes to the the last fb to make sure we're
2588          * showing the correct fb after a reset.
2589          *
2590          * Need to make two loops over the crtcs so that we
2591          * don't try to grab a crtc mutex before the
2592          * pending_flip_queue really got woken up.
2593          */
2594
2595         for_each_crtc(dev, crtc) {
2596                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597                 enum plane plane = intel_crtc->plane;
2598
2599                 intel_prepare_page_flip(dev, plane);
2600                 intel_finish_page_flip_plane(dev, plane);
2601         }
2602
2603         for_each_crtc(dev, crtc) {
2604                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605
2606                 drm_modeset_lock(&crtc->mutex, NULL);
2607                 /*
2608                  * FIXME: Once we have proper support for primary planes (and
2609                  * disabling them without disabling the entire crtc) allow again
2610                  * a NULL crtc->primary->fb.
2611                  */
2612                 if (intel_crtc->active && crtc->primary->fb)
2613                         dev_priv->display.update_primary_plane(crtc,
2614                                                                crtc->primary->fb,
2615                                                                crtc->x,
2616                                                                crtc->y);
2617                 drm_modeset_unlock(&crtc->mutex);
2618         }
2619 }
2620
2621 static int
2622 intel_finish_fb(struct drm_framebuffer *old_fb)
2623 {
2624         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2625         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2626         bool was_interruptible = dev_priv->mm.interruptible;
2627         int ret;
2628
2629         /* Big Hammer, we also need to ensure that any pending
2630          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2631          * current scanout is retired before unpinning the old
2632          * framebuffer.
2633          *
2634          * This should only fail upon a hung GPU, in which case we
2635          * can safely continue.
2636          */
2637         dev_priv->mm.interruptible = false;
2638         ret = i915_gem_object_finish_gpu(obj);
2639         dev_priv->mm.interruptible = was_interruptible;
2640
2641         return ret;
2642 }
2643
2644 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2645 {
2646         struct drm_device *dev = crtc->dev;
2647         struct drm_i915_private *dev_priv = dev->dev_private;
2648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2649         unsigned long flags;
2650         bool pending;
2651
2652         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2653             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2654                 return false;
2655
2656         spin_lock_irqsave(&dev->event_lock, flags);
2657         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2658         spin_unlock_irqrestore(&dev->event_lock, flags);
2659
2660         return pending;
2661 }
2662
2663 static int
2664 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2665                     struct drm_framebuffer *fb)
2666 {
2667         struct drm_device *dev = crtc->dev;
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670         enum pipe pipe = intel_crtc->pipe;
2671         struct drm_framebuffer *old_fb = crtc->primary->fb;
2672         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2673         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2674         int ret;
2675
2676         if (intel_crtc_has_pending_flip(crtc)) {
2677                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2678                 return -EBUSY;
2679         }
2680
2681         /* no fb bound */
2682         if (!fb) {
2683                 DRM_ERROR("No FB bound\n");
2684                 return 0;
2685         }
2686
2687         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2688                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2689                           plane_name(intel_crtc->plane),
2690                           INTEL_INFO(dev)->num_pipes);
2691                 return -EINVAL;
2692         }
2693
2694         mutex_lock(&dev->struct_mutex);
2695         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2696         if (ret == 0)
2697                 i915_gem_track_fb(old_obj, obj,
2698                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2699         mutex_unlock(&dev->struct_mutex);
2700         if (ret != 0) {
2701                 DRM_ERROR("pin & fence failed\n");
2702                 return ret;
2703         }
2704
2705         /*
2706          * Update pipe size and adjust fitter if needed: the reason for this is
2707          * that in compute_mode_changes we check the native mode (not the pfit
2708          * mode) to see if we can flip rather than do a full mode set. In the
2709          * fastboot case, we'll flip, but if we don't update the pipesrc and
2710          * pfit state, we'll end up with a big fb scanned out into the wrong
2711          * sized surface.
2712          *
2713          * To fix this properly, we need to hoist the checks up into
2714          * compute_mode_changes (or above), check the actual pfit state and
2715          * whether the platform allows pfit disable with pipe active, and only
2716          * then update the pipesrc and pfit state, even on the flip path.
2717          */
2718         if (i915.fastboot) {
2719                 const struct drm_display_mode *adjusted_mode =
2720                         &intel_crtc->config.adjusted_mode;
2721
2722                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2723                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2724                            (adjusted_mode->crtc_vdisplay - 1));
2725                 if (!intel_crtc->config.pch_pfit.enabled &&
2726                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2727                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2728                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2729                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2730                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2731                 }
2732                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2733                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2734         }
2735
2736         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2737
2738         if (intel_crtc->active)
2739                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2740
2741         crtc->primary->fb = fb;
2742         crtc->x = x;
2743         crtc->y = y;
2744
2745         if (old_fb) {
2746                 if (intel_crtc->active && old_fb != fb)
2747                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2748                 mutex_lock(&dev->struct_mutex);
2749                 intel_unpin_fb_obj(old_obj);
2750                 mutex_unlock(&dev->struct_mutex);
2751         }
2752
2753         mutex_lock(&dev->struct_mutex);
2754         intel_update_fbc(dev);
2755         mutex_unlock(&dev->struct_mutex);
2756
2757         return 0;
2758 }
2759
2760 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2761 {
2762         struct drm_device *dev = crtc->dev;
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765         int pipe = intel_crtc->pipe;
2766         u32 reg, temp;
2767
2768         /* enable normal train */
2769         reg = FDI_TX_CTL(pipe);
2770         temp = I915_READ(reg);
2771         if (IS_IVYBRIDGE(dev)) {
2772                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2773                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2774         } else {
2775                 temp &= ~FDI_LINK_TRAIN_NONE;
2776                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2777         }
2778         I915_WRITE(reg, temp);
2779
2780         reg = FDI_RX_CTL(pipe);
2781         temp = I915_READ(reg);
2782         if (HAS_PCH_CPT(dev)) {
2783                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2784                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2785         } else {
2786                 temp &= ~FDI_LINK_TRAIN_NONE;
2787                 temp |= FDI_LINK_TRAIN_NONE;
2788         }
2789         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2790
2791         /* wait one idle pattern time */
2792         POSTING_READ(reg);
2793         udelay(1000);
2794
2795         /* IVB wants error correction enabled */
2796         if (IS_IVYBRIDGE(dev))
2797                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2798                            FDI_FE_ERRC_ENABLE);
2799 }
2800
2801 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2802 {
2803         return crtc->base.enabled && crtc->active &&
2804                 crtc->config.has_pch_encoder;
2805 }
2806
2807 static void ivb_modeset_global_resources(struct drm_device *dev)
2808 {
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         struct intel_crtc *pipe_B_crtc =
2811                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2812         struct intel_crtc *pipe_C_crtc =
2813                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2814         uint32_t temp;
2815
2816         /*
2817          * When everything is off disable fdi C so that we could enable fdi B
2818          * with all lanes. Note that we don't care about enabled pipes without
2819          * an enabled pch encoder.
2820          */
2821         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2822             !pipe_has_enabled_pch(pipe_C_crtc)) {
2823                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2824                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2825
2826                 temp = I915_READ(SOUTH_CHICKEN1);
2827                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2828                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2829                 I915_WRITE(SOUTH_CHICKEN1, temp);
2830         }
2831 }
2832
2833 /* The FDI link training functions for ILK/Ibexpeak. */
2834 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839         int pipe = intel_crtc->pipe;
2840         u32 reg, temp, tries;
2841
2842         /* FDI needs bits from pipe first */
2843         assert_pipe_enabled(dev_priv, pipe);
2844
2845         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2846            for train result */
2847         reg = FDI_RX_IMR(pipe);
2848         temp = I915_READ(reg);
2849         temp &= ~FDI_RX_SYMBOL_LOCK;
2850         temp &= ~FDI_RX_BIT_LOCK;
2851         I915_WRITE(reg, temp);
2852         I915_READ(reg);
2853         udelay(150);
2854
2855         /* enable CPU FDI TX and PCH FDI RX */
2856         reg = FDI_TX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2859         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2860         temp &= ~FDI_LINK_TRAIN_NONE;
2861         temp |= FDI_LINK_TRAIN_PATTERN_1;
2862         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2863
2864         reg = FDI_RX_CTL(pipe);
2865         temp = I915_READ(reg);
2866         temp &= ~FDI_LINK_TRAIN_NONE;
2867         temp |= FDI_LINK_TRAIN_PATTERN_1;
2868         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2869
2870         POSTING_READ(reg);
2871         udelay(150);
2872
2873         /* Ironlake workaround, enable clock pointer after FDI enable*/
2874         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2875         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2876                    FDI_RX_PHASE_SYNC_POINTER_EN);
2877
2878         reg = FDI_RX_IIR(pipe);
2879         for (tries = 0; tries < 5; tries++) {
2880                 temp = I915_READ(reg);
2881                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2882
2883                 if ((temp & FDI_RX_BIT_LOCK)) {
2884                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2885                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2886                         break;
2887                 }
2888         }
2889         if (tries == 5)
2890                 DRM_ERROR("FDI train 1 fail!\n");
2891
2892         /* Train 2 */
2893         reg = FDI_TX_CTL(pipe);
2894         temp = I915_READ(reg);
2895         temp &= ~FDI_LINK_TRAIN_NONE;
2896         temp |= FDI_LINK_TRAIN_PATTERN_2;
2897         I915_WRITE(reg, temp);
2898
2899         reg = FDI_RX_CTL(pipe);
2900         temp = I915_READ(reg);
2901         temp &= ~FDI_LINK_TRAIN_NONE;
2902         temp |= FDI_LINK_TRAIN_PATTERN_2;
2903         I915_WRITE(reg, temp);
2904
2905         POSTING_READ(reg);
2906         udelay(150);
2907
2908         reg = FDI_RX_IIR(pipe);
2909         for (tries = 0; tries < 5; tries++) {
2910                 temp = I915_READ(reg);
2911                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2912
2913                 if (temp & FDI_RX_SYMBOL_LOCK) {
2914                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2915                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2916                         break;
2917                 }
2918         }
2919         if (tries == 5)
2920                 DRM_ERROR("FDI train 2 fail!\n");
2921
2922         DRM_DEBUG_KMS("FDI train done\n");
2923
2924 }
2925
2926 static const int snb_b_fdi_train_param[] = {
2927         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2928         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2929         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2930         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2931 };
2932
2933 /* The FDI link training functions for SNB/Cougarpoint. */
2934 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2935 {
2936         struct drm_device *dev = crtc->dev;
2937         struct drm_i915_private *dev_priv = dev->dev_private;
2938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2939         int pipe = intel_crtc->pipe;
2940         u32 reg, temp, i, retry;
2941
2942         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2943            for train result */
2944         reg = FDI_RX_IMR(pipe);
2945         temp = I915_READ(reg);
2946         temp &= ~FDI_RX_SYMBOL_LOCK;
2947         temp &= ~FDI_RX_BIT_LOCK;
2948         I915_WRITE(reg, temp);
2949
2950         POSTING_READ(reg);
2951         udelay(150);
2952
2953         /* enable CPU FDI TX and PCH FDI RX */
2954         reg = FDI_TX_CTL(pipe);
2955         temp = I915_READ(reg);
2956         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2957         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2958         temp &= ~FDI_LINK_TRAIN_NONE;
2959         temp |= FDI_LINK_TRAIN_PATTERN_1;
2960         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2961         /* SNB-B */
2962         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2963         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2964
2965         I915_WRITE(FDI_RX_MISC(pipe),
2966                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2967
2968         reg = FDI_RX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         if (HAS_PCH_CPT(dev)) {
2971                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2972                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2973         } else {
2974                 temp &= ~FDI_LINK_TRAIN_NONE;
2975                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2976         }
2977         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2978
2979         POSTING_READ(reg);
2980         udelay(150);
2981
2982         for (i = 0; i < 4; i++) {
2983                 reg = FDI_TX_CTL(pipe);
2984                 temp = I915_READ(reg);
2985                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2986                 temp |= snb_b_fdi_train_param[i];
2987                 I915_WRITE(reg, temp);
2988
2989                 POSTING_READ(reg);
2990                 udelay(500);
2991
2992                 for (retry = 0; retry < 5; retry++) {
2993                         reg = FDI_RX_IIR(pipe);
2994                         temp = I915_READ(reg);
2995                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2996                         if (temp & FDI_RX_BIT_LOCK) {
2997                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2998                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2999                                 break;
3000                         }
3001                         udelay(50);
3002                 }
3003                 if (retry < 5)
3004                         break;
3005         }
3006         if (i == 4)
3007                 DRM_ERROR("FDI train 1 fail!\n");
3008
3009         /* Train 2 */
3010         reg = FDI_TX_CTL(pipe);
3011         temp = I915_READ(reg);
3012         temp &= ~FDI_LINK_TRAIN_NONE;
3013         temp |= FDI_LINK_TRAIN_PATTERN_2;
3014         if (IS_GEN6(dev)) {
3015                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3016                 /* SNB-B */
3017                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3018         }
3019         I915_WRITE(reg, temp);
3020
3021         reg = FDI_RX_CTL(pipe);
3022         temp = I915_READ(reg);
3023         if (HAS_PCH_CPT(dev)) {
3024                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3025                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3026         } else {
3027                 temp &= ~FDI_LINK_TRAIN_NONE;
3028                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3029         }
3030         I915_WRITE(reg, temp);
3031
3032         POSTING_READ(reg);
3033         udelay(150);
3034
3035         for (i = 0; i < 4; i++) {
3036                 reg = FDI_TX_CTL(pipe);
3037                 temp = I915_READ(reg);
3038                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3039                 temp |= snb_b_fdi_train_param[i];
3040                 I915_WRITE(reg, temp);
3041
3042                 POSTING_READ(reg);
3043                 udelay(500);
3044
3045                 for (retry = 0; retry < 5; retry++) {
3046                         reg = FDI_RX_IIR(pipe);
3047                         temp = I915_READ(reg);
3048                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3049                         if (temp & FDI_RX_SYMBOL_LOCK) {
3050                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3051                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3052                                 break;
3053                         }
3054                         udelay(50);
3055                 }
3056                 if (retry < 5)
3057                         break;
3058         }
3059         if (i == 4)
3060                 DRM_ERROR("FDI train 2 fail!\n");
3061
3062         DRM_DEBUG_KMS("FDI train done.\n");
3063 }
3064
3065 /* Manual link training for Ivy Bridge A0 parts */
3066 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3067 {
3068         struct drm_device *dev = crtc->dev;
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071         int pipe = intel_crtc->pipe;
3072         u32 reg, temp, i, j;
3073
3074         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3075            for train result */
3076         reg = FDI_RX_IMR(pipe);
3077         temp = I915_READ(reg);
3078         temp &= ~FDI_RX_SYMBOL_LOCK;
3079         temp &= ~FDI_RX_BIT_LOCK;
3080         I915_WRITE(reg, temp);
3081
3082         POSTING_READ(reg);
3083         udelay(150);
3084
3085         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3086                       I915_READ(FDI_RX_IIR(pipe)));
3087
3088         /* Try each vswing and preemphasis setting twice before moving on */
3089         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3090                 /* disable first in case we need to retry */
3091                 reg = FDI_TX_CTL(pipe);
3092                 temp = I915_READ(reg);
3093                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3094                 temp &= ~FDI_TX_ENABLE;
3095                 I915_WRITE(reg, temp);
3096
3097                 reg = FDI_RX_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~FDI_LINK_TRAIN_AUTO;
3100                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3101                 temp &= ~FDI_RX_ENABLE;
3102                 I915_WRITE(reg, temp);
3103
3104                 /* enable CPU FDI TX and PCH FDI RX */
3105                 reg = FDI_TX_CTL(pipe);
3106                 temp = I915_READ(reg);
3107                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3108                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3109                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3110                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3111                 temp |= snb_b_fdi_train_param[j/2];
3112                 temp |= FDI_COMPOSITE_SYNC;
3113                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3114
3115                 I915_WRITE(FDI_RX_MISC(pipe),
3116                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3117
3118                 reg = FDI_RX_CTL(pipe);
3119                 temp = I915_READ(reg);
3120                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3121                 temp |= FDI_COMPOSITE_SYNC;
3122                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3123
3124                 POSTING_READ(reg);
3125                 udelay(1); /* should be 0.5us */
3126
3127                 for (i = 0; i < 4; i++) {
3128                         reg = FDI_RX_IIR(pipe);
3129                         temp = I915_READ(reg);
3130                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3131
3132                         if (temp & FDI_RX_BIT_LOCK ||
3133                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3134                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3135                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3136                                               i);
3137                                 break;
3138                         }
3139                         udelay(1); /* should be 0.5us */
3140                 }
3141                 if (i == 4) {
3142                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3143                         continue;
3144                 }
3145
3146                 /* Train 2 */
3147                 reg = FDI_TX_CTL(pipe);
3148                 temp = I915_READ(reg);
3149                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3150                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3151                 I915_WRITE(reg, temp);
3152
3153                 reg = FDI_RX_CTL(pipe);
3154                 temp = I915_READ(reg);
3155                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3156                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3157                 I915_WRITE(reg, temp);
3158
3159                 POSTING_READ(reg);
3160                 udelay(2); /* should be 1.5us */
3161
3162                 for (i = 0; i < 4; i++) {
3163                         reg = FDI_RX_IIR(pipe);
3164                         temp = I915_READ(reg);
3165                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3166
3167                         if (temp & FDI_RX_SYMBOL_LOCK ||
3168                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3169                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3170                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3171                                               i);
3172                                 goto train_done;
3173                         }
3174                         udelay(2); /* should be 1.5us */
3175                 }
3176                 if (i == 4)
3177                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3178         }
3179
3180 train_done:
3181         DRM_DEBUG_KMS("FDI train done.\n");
3182 }
3183
3184 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3185 {
3186         struct drm_device *dev = intel_crtc->base.dev;
3187         struct drm_i915_private *dev_priv = dev->dev_private;
3188         int pipe = intel_crtc->pipe;
3189         u32 reg, temp;
3190
3191
3192         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3193         reg = FDI_RX_CTL(pipe);
3194         temp = I915_READ(reg);
3195         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3196         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3197         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3198         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3199
3200         POSTING_READ(reg);
3201         udelay(200);
3202
3203         /* Switch from Rawclk to PCDclk */
3204         temp = I915_READ(reg);
3205         I915_WRITE(reg, temp | FDI_PCDCLK);
3206
3207         POSTING_READ(reg);
3208         udelay(200);
3209
3210         /* Enable CPU FDI TX PLL, always on for Ironlake */
3211         reg = FDI_TX_CTL(pipe);
3212         temp = I915_READ(reg);
3213         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3214                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3215
3216                 POSTING_READ(reg);
3217                 udelay(100);
3218         }
3219 }
3220
3221 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3222 {
3223         struct drm_device *dev = intel_crtc->base.dev;
3224         struct drm_i915_private *dev_priv = dev->dev_private;
3225         int pipe = intel_crtc->pipe;
3226         u32 reg, temp;
3227
3228         /* Switch from PCDclk to Rawclk */
3229         reg = FDI_RX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3232
3233         /* Disable CPU FDI TX PLL */
3234         reg = FDI_TX_CTL(pipe);
3235         temp = I915_READ(reg);
3236         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3237
3238         POSTING_READ(reg);
3239         udelay(100);
3240
3241         reg = FDI_RX_CTL(pipe);
3242         temp = I915_READ(reg);
3243         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3244
3245         /* Wait for the clocks to turn off. */
3246         POSTING_READ(reg);
3247         udelay(100);
3248 }
3249
3250 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3251 {
3252         struct drm_device *dev = crtc->dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255         int pipe = intel_crtc->pipe;
3256         u32 reg, temp;
3257
3258         /* disable CPU FDI tx and PCH FDI rx */
3259         reg = FDI_TX_CTL(pipe);
3260         temp = I915_READ(reg);
3261         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3262         POSTING_READ(reg);
3263
3264         reg = FDI_RX_CTL(pipe);
3265         temp = I915_READ(reg);
3266         temp &= ~(0x7 << 16);
3267         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3268         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3269
3270         POSTING_READ(reg);
3271         udelay(100);
3272
3273         /* Ironlake workaround, disable clock pointer after downing FDI */
3274         if (HAS_PCH_IBX(dev))
3275                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3276
3277         /* still set train pattern 1 */
3278         reg = FDI_TX_CTL(pipe);
3279         temp = I915_READ(reg);
3280         temp &= ~FDI_LINK_TRAIN_NONE;
3281         temp |= FDI_LINK_TRAIN_PATTERN_1;
3282         I915_WRITE(reg, temp);
3283
3284         reg = FDI_RX_CTL(pipe);
3285         temp = I915_READ(reg);
3286         if (HAS_PCH_CPT(dev)) {
3287                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3288                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3289         } else {
3290                 temp &= ~FDI_LINK_TRAIN_NONE;
3291                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3292         }
3293         /* BPC in FDI rx is consistent with that in PIPECONF */
3294         temp &= ~(0x07 << 16);
3295         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3296         I915_WRITE(reg, temp);
3297
3298         POSTING_READ(reg);
3299         udelay(100);
3300 }
3301
3302 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3303 {
3304         struct intel_crtc *crtc;
3305
3306         /* Note that we don't need to be called with mode_config.lock here
3307          * as our list of CRTC objects is static for the lifetime of the
3308          * device and so cannot disappear as we iterate. Similarly, we can
3309          * happily treat the predicates as racy, atomic checks as userspace
3310          * cannot claim and pin a new fb without at least acquring the
3311          * struct_mutex and so serialising with us.
3312          */
3313         for_each_intel_crtc(dev, crtc) {
3314                 if (atomic_read(&crtc->unpin_work_count) == 0)
3315                         continue;
3316
3317                 if (crtc->unpin_work)
3318                         intel_wait_for_vblank(dev, crtc->pipe);
3319
3320                 return true;
3321         }
3322
3323         return false;
3324 }
3325
3326 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3327 {
3328         struct drm_device *dev = crtc->dev;
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330
3331         if (crtc->primary->fb == NULL)
3332                 return;
3333
3334         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3335
3336         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3337                                    !intel_crtc_has_pending_flip(crtc),
3338                                    60*HZ) == 0);
3339
3340         mutex_lock(&dev->struct_mutex);
3341         intel_finish_fb(crtc->primary->fb);
3342         mutex_unlock(&dev->struct_mutex);
3343 }
3344
3345 /* Program iCLKIP clock to the desired frequency */
3346 static void lpt_program_iclkip(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3351         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3352         u32 temp;
3353
3354         mutex_lock(&dev_priv->dpio_lock);
3355
3356         /* It is necessary to ungate the pixclk gate prior to programming
3357          * the divisors, and gate it back when it is done.
3358          */
3359         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3360
3361         /* Disable SSCCTL */
3362         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3363                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3364                                 SBI_SSCCTL_DISABLE,
3365                         SBI_ICLK);
3366
3367         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3368         if (clock == 20000) {
3369                 auxdiv = 1;
3370                 divsel = 0x41;
3371                 phaseinc = 0x20;
3372         } else {
3373                 /* The iCLK virtual clock root frequency is in MHz,
3374                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3375                  * divisors, it is necessary to divide one by another, so we
3376                  * convert the virtual clock precision to KHz here for higher
3377                  * precision.
3378                  */
3379                 u32 iclk_virtual_root_freq = 172800 * 1000;
3380                 u32 iclk_pi_range = 64;
3381                 u32 desired_divisor, msb_divisor_value, pi_value;
3382
3383                 desired_divisor = (iclk_virtual_root_freq / clock);
3384                 msb_divisor_value = desired_divisor / iclk_pi_range;
3385                 pi_value = desired_divisor % iclk_pi_range;
3386
3387                 auxdiv = 0;
3388                 divsel = msb_divisor_value - 2;
3389                 phaseinc = pi_value;
3390         }
3391
3392         /* This should not happen with any sane values */
3393         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3394                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3395         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3396                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3397
3398         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3399                         clock,
3400                         auxdiv,
3401                         divsel,
3402                         phasedir,
3403                         phaseinc);
3404
3405         /* Program SSCDIVINTPHASE6 */
3406         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3407         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3408         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3409         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3410         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3411         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3412         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3413         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3414
3415         /* Program SSCAUXDIV */
3416         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3417         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3418         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3419         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3420
3421         /* Enable modulator and associated divider */
3422         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3423         temp &= ~SBI_SSCCTL_DISABLE;
3424         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3425
3426         /* Wait for initialization time */
3427         udelay(24);
3428
3429         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3430
3431         mutex_unlock(&dev_priv->dpio_lock);
3432 }
3433
3434 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3435                                                 enum pipe pch_transcoder)
3436 {
3437         struct drm_device *dev = crtc->base.dev;
3438         struct drm_i915_private *dev_priv = dev->dev_private;
3439         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3440
3441         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3442                    I915_READ(HTOTAL(cpu_transcoder)));
3443         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3444                    I915_READ(HBLANK(cpu_transcoder)));
3445         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3446                    I915_READ(HSYNC(cpu_transcoder)));
3447
3448         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3449                    I915_READ(VTOTAL(cpu_transcoder)));
3450         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3451                    I915_READ(VBLANK(cpu_transcoder)));
3452         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3453                    I915_READ(VSYNC(cpu_transcoder)));
3454         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3455                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3456 }
3457
3458 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3459 {
3460         struct drm_i915_private *dev_priv = dev->dev_private;
3461         uint32_t temp;
3462
3463         temp = I915_READ(SOUTH_CHICKEN1);
3464         if (temp & FDI_BC_BIFURCATION_SELECT)
3465                 return;
3466
3467         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3468         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3469
3470         temp |= FDI_BC_BIFURCATION_SELECT;
3471         DRM_DEBUG_KMS("enabling fdi C rx\n");
3472         I915_WRITE(SOUTH_CHICKEN1, temp);
3473         POSTING_READ(SOUTH_CHICKEN1);
3474 }
3475
3476 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3477 {
3478         struct drm_device *dev = intel_crtc->base.dev;
3479         struct drm_i915_private *dev_priv = dev->dev_private;
3480
3481         switch (intel_crtc->pipe) {
3482         case PIPE_A:
3483                 break;
3484         case PIPE_B:
3485                 if (intel_crtc->config.fdi_lanes > 2)
3486                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3487                 else
3488                         cpt_enable_fdi_bc_bifurcation(dev);
3489
3490                 break;
3491         case PIPE_C:
3492                 cpt_enable_fdi_bc_bifurcation(dev);
3493
3494                 break;
3495         default:
3496                 BUG();
3497         }
3498 }
3499
3500 /*
3501  * Enable PCH resources required for PCH ports:
3502  *   - PCH PLLs
3503  *   - FDI training & RX/TX
3504  *   - update transcoder timings
3505  *   - DP transcoding bits
3506  *   - transcoder
3507  */
3508 static void ironlake_pch_enable(struct drm_crtc *crtc)
3509 {
3510         struct drm_device *dev = crtc->dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513         int pipe = intel_crtc->pipe;
3514         u32 reg, temp;
3515
3516         assert_pch_transcoder_disabled(dev_priv, pipe);
3517
3518         if (IS_IVYBRIDGE(dev))
3519                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3520
3521         /* Write the TU size bits before fdi link training, so that error
3522          * detection works. */
3523         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3524                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3525
3526         /* For PCH output, training FDI link */
3527         dev_priv->display.fdi_link_train(crtc);
3528
3529         /* We need to program the right clock selection before writing the pixel
3530          * mutliplier into the DPLL. */
3531         if (HAS_PCH_CPT(dev)) {
3532                 u32 sel;
3533
3534                 temp = I915_READ(PCH_DPLL_SEL);
3535                 temp |= TRANS_DPLL_ENABLE(pipe);
3536                 sel = TRANS_DPLLB_SEL(pipe);
3537                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3538                         temp |= sel;
3539                 else
3540                         temp &= ~sel;
3541                 I915_WRITE(PCH_DPLL_SEL, temp);
3542         }
3543
3544         /* XXX: pch pll's can be enabled any time before we enable the PCH
3545          * transcoder, and we actually should do this to not upset any PCH
3546          * transcoder that already use the clock when we share it.
3547          *
3548          * Note that enable_shared_dpll tries to do the right thing, but
3549          * get_shared_dpll unconditionally resets the pll - we need that to have
3550          * the right LVDS enable sequence. */
3551         intel_enable_shared_dpll(intel_crtc);
3552
3553         /* set transcoder timing, panel must allow it */
3554         assert_panel_unlocked(dev_priv, pipe);
3555         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3556
3557         intel_fdi_normal_train(crtc);
3558
3559         /* For PCH DP, enable TRANS_DP_CTL */
3560         if (HAS_PCH_CPT(dev) &&
3561             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3562              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3563                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3564                 reg = TRANS_DP_CTL(pipe);
3565                 temp = I915_READ(reg);
3566                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3567                           TRANS_DP_SYNC_MASK |
3568                           TRANS_DP_BPC_MASK);
3569                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3570                          TRANS_DP_ENH_FRAMING);
3571                 temp |= bpc << 9; /* same format but at 11:9 */
3572
3573                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3574                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3575                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3576                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3577
3578                 switch (intel_trans_dp_port_sel(crtc)) {
3579                 case PCH_DP_B:
3580                         temp |= TRANS_DP_PORT_SEL_B;
3581                         break;
3582                 case PCH_DP_C:
3583                         temp |= TRANS_DP_PORT_SEL_C;
3584                         break;
3585                 case PCH_DP_D:
3586                         temp |= TRANS_DP_PORT_SEL_D;
3587                         break;
3588                 default:
3589                         BUG();
3590                 }
3591
3592                 I915_WRITE(reg, temp);
3593         }
3594
3595         ironlake_enable_pch_transcoder(dev_priv, pipe);
3596 }
3597
3598 static void lpt_pch_enable(struct drm_crtc *crtc)
3599 {
3600         struct drm_device *dev = crtc->dev;
3601         struct drm_i915_private *dev_priv = dev->dev_private;
3602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3604
3605         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3606
3607         lpt_program_iclkip(crtc);
3608
3609         /* Set transcoder timing. */
3610         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3611
3612         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3613 }
3614
3615 void intel_put_shared_dpll(struct intel_crtc *crtc)
3616 {
3617         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3618
3619         if (pll == NULL)
3620                 return;
3621
3622         if (pll->refcount == 0) {
3623                 WARN(1, "bad %s refcount\n", pll->name);
3624                 return;
3625         }
3626
3627         if (--pll->refcount == 0) {
3628                 WARN_ON(pll->on);
3629                 WARN_ON(pll->active);
3630         }
3631
3632         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3633 }
3634
3635 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3636 {
3637         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3638         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3639         enum intel_dpll_id i;
3640
3641         if (pll) {
3642                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3643                               crtc->base.base.id, pll->name);
3644                 intel_put_shared_dpll(crtc);
3645         }
3646
3647         if (HAS_PCH_IBX(dev_priv->dev)) {
3648                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3649                 i = (enum intel_dpll_id) crtc->pipe;
3650                 pll = &dev_priv->shared_dplls[i];
3651
3652                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3653                               crtc->base.base.id, pll->name);
3654
3655                 WARN_ON(pll->refcount);
3656
3657                 goto found;
3658         }
3659
3660         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3661                 pll = &dev_priv->shared_dplls[i];
3662
3663                 /* Only want to check enabled timings first */
3664                 if (pll->refcount == 0)
3665                         continue;
3666
3667                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3668                            sizeof(pll->hw_state)) == 0) {
3669                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3670                                       crtc->base.base.id,
3671                                       pll->name, pll->refcount, pll->active);
3672
3673                         goto found;
3674                 }
3675         }
3676
3677         /* Ok no matching timings, maybe there's a free one? */
3678         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3679                 pll = &dev_priv->shared_dplls[i];
3680                 if (pll->refcount == 0) {
3681                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3682                                       crtc->base.base.id, pll->name);
3683                         goto found;
3684                 }
3685         }
3686
3687         return NULL;
3688
3689 found:
3690         if (pll->refcount == 0)
3691                 pll->hw_state = crtc->config.dpll_hw_state;
3692
3693         crtc->config.shared_dpll = i;
3694         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3695                          pipe_name(crtc->pipe));
3696
3697         pll->refcount++;
3698
3699         return pll;
3700 }
3701
3702 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3703 {
3704         struct drm_i915_private *dev_priv = dev->dev_private;
3705         int dslreg = PIPEDSL(pipe);
3706         u32 temp;
3707
3708         temp = I915_READ(dslreg);
3709         udelay(500);
3710         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3711                 if (wait_for(I915_READ(dslreg) != temp, 5))
3712                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3713         }
3714 }
3715
3716 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->base.dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         int pipe = crtc->pipe;
3721
3722         if (crtc->config.pch_pfit.enabled) {
3723                 /* Force use of hard-coded filter coefficients
3724                  * as some pre-programmed values are broken,
3725                  * e.g. x201.
3726                  */
3727                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3728                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3729                                                  PF_PIPE_SEL_IVB(pipe));
3730                 else
3731                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3732                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3733                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3734         }
3735 }
3736
3737 static void intel_enable_planes(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3741         struct drm_plane *plane;
3742         struct intel_plane *intel_plane;
3743
3744         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3745                 intel_plane = to_intel_plane(plane);
3746                 if (intel_plane->pipe == pipe)
3747                         intel_plane_restore(&intel_plane->base);
3748         }
3749 }
3750
3751 static void intel_disable_planes(struct drm_crtc *crtc)
3752 {
3753         struct drm_device *dev = crtc->dev;
3754         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3755         struct drm_plane *plane;
3756         struct intel_plane *intel_plane;
3757
3758         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3759                 intel_plane = to_intel_plane(plane);
3760                 if (intel_plane->pipe == pipe)
3761                         intel_plane_disable(&intel_plane->base);
3762         }
3763 }
3764
3765 void hsw_enable_ips(struct intel_crtc *crtc)
3766 {
3767         struct drm_device *dev = crtc->base.dev;
3768         struct drm_i915_private *dev_priv = dev->dev_private;
3769
3770         if (!crtc->config.ips_enabled)
3771                 return;
3772
3773         /* We can only enable IPS after we enable a plane and wait for a vblank */
3774         intel_wait_for_vblank(dev, crtc->pipe);
3775
3776         assert_plane_enabled(dev_priv, crtc->plane);
3777         if (IS_BROADWELL(dev)) {
3778                 mutex_lock(&dev_priv->rps.hw_lock);
3779                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3780                 mutex_unlock(&dev_priv->rps.hw_lock);
3781                 /* Quoting Art Runyan: "its not safe to expect any particular
3782                  * value in IPS_CTL bit 31 after enabling IPS through the
3783                  * mailbox." Moreover, the mailbox may return a bogus state,
3784                  * so we need to just enable it and continue on.
3785                  */
3786         } else {
3787                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3788                 /* The bit only becomes 1 in the next vblank, so this wait here
3789                  * is essentially intel_wait_for_vblank. If we don't have this
3790                  * and don't wait for vblanks until the end of crtc_enable, then
3791                  * the HW state readout code will complain that the expected
3792                  * IPS_CTL value is not the one we read. */
3793                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3794                         DRM_ERROR("Timed out waiting for IPS enable\n");
3795         }
3796 }
3797
3798 void hsw_disable_ips(struct intel_crtc *crtc)
3799 {
3800         struct drm_device *dev = crtc->base.dev;
3801         struct drm_i915_private *dev_priv = dev->dev_private;
3802
3803         if (!crtc->config.ips_enabled)
3804                 return;
3805
3806         assert_plane_enabled(dev_priv, crtc->plane);
3807         if (IS_BROADWELL(dev)) {
3808                 mutex_lock(&dev_priv->rps.hw_lock);
3809                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3810                 mutex_unlock(&dev_priv->rps.hw_lock);
3811                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3812                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3813                         DRM_ERROR("Timed out waiting for IPS disable\n");
3814         } else {
3815                 I915_WRITE(IPS_CTL, 0);
3816                 POSTING_READ(IPS_CTL);
3817         }
3818
3819         /* We need to wait for a vblank before we can disable the plane. */
3820         intel_wait_for_vblank(dev, crtc->pipe);
3821 }
3822
3823 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3824 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829         enum pipe pipe = intel_crtc->pipe;
3830         int palreg = PALETTE(pipe);
3831         int i;
3832         bool reenable_ips = false;
3833
3834         /* The clocks have to be on to load the palette. */
3835         if (!crtc->enabled || !intel_crtc->active)
3836                 return;
3837
3838         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3839                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3840                         assert_dsi_pll_enabled(dev_priv);
3841                 else
3842                         assert_pll_enabled(dev_priv, pipe);
3843         }
3844
3845         /* use legacy palette for Ironlake */
3846         if (!HAS_GMCH_DISPLAY(dev))
3847                 palreg = LGC_PALETTE(pipe);
3848
3849         /* Workaround : Do not read or write the pipe palette/gamma data while
3850          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3851          */
3852         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3853             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3854              GAMMA_MODE_MODE_SPLIT)) {
3855                 hsw_disable_ips(intel_crtc);
3856                 reenable_ips = true;
3857         }
3858
3859         for (i = 0; i < 256; i++) {
3860                 I915_WRITE(palreg + 4 * i,
3861                            (intel_crtc->lut_r[i] << 16) |
3862                            (intel_crtc->lut_g[i] << 8) |
3863                            intel_crtc->lut_b[i]);
3864         }
3865
3866         if (reenable_ips)
3867                 hsw_enable_ips(intel_crtc);
3868 }
3869
3870 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3871 {
3872         if (!enable && intel_crtc->overlay) {
3873                 struct drm_device *dev = intel_crtc->base.dev;
3874                 struct drm_i915_private *dev_priv = dev->dev_private;
3875
3876                 mutex_lock(&dev->struct_mutex);
3877                 dev_priv->mm.interruptible = false;
3878                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3879                 dev_priv->mm.interruptible = true;
3880                 mutex_unlock(&dev->struct_mutex);
3881         }
3882
3883         /* Let userspace switch the overlay on again. In most cases userspace
3884          * has to recompute where to put it anyway.
3885          */
3886 }
3887
3888 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892         int pipe = intel_crtc->pipe;
3893
3894         drm_vblank_on(dev, pipe);
3895
3896         intel_enable_primary_hw_plane(crtc->primary, crtc);
3897         intel_enable_planes(crtc);
3898         intel_crtc_update_cursor(crtc, true);
3899         intel_crtc_dpms_overlay(intel_crtc, true);
3900
3901         hsw_enable_ips(intel_crtc);
3902
3903         mutex_lock(&dev->struct_mutex);
3904         intel_update_fbc(dev);
3905         mutex_unlock(&dev->struct_mutex);
3906
3907         /*
3908          * FIXME: Once we grow proper nuclear flip support out of this we need
3909          * to compute the mask of flip planes precisely. For the time being
3910          * consider this a flip from a NULL plane.
3911          */
3912         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3913 }
3914
3915 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3916 {
3917         struct drm_device *dev = crtc->dev;
3918         struct drm_i915_private *dev_priv = dev->dev_private;
3919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920         int pipe = intel_crtc->pipe;
3921         int plane = intel_crtc->plane;
3922
3923         intel_crtc_wait_for_pending_flips(crtc);
3924
3925         if (dev_priv->fbc.plane == plane)
3926                 intel_disable_fbc(dev);
3927
3928         hsw_disable_ips(intel_crtc);
3929
3930         intel_crtc_dpms_overlay(intel_crtc, false);
3931         intel_crtc_update_cursor(crtc, false);
3932         intel_disable_planes(crtc);
3933         intel_disable_primary_hw_plane(crtc->primary, crtc);
3934
3935         /*
3936          * FIXME: Once we grow proper nuclear flip support out of this we need
3937          * to compute the mask of flip planes precisely. For the time being
3938          * consider this a flip to a NULL plane.
3939          */
3940         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3941
3942         drm_vblank_off(dev, pipe);
3943 }
3944
3945 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3946 {
3947         struct drm_device *dev = crtc->dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950         struct intel_encoder *encoder;
3951         int pipe = intel_crtc->pipe;
3952
3953         WARN_ON(!crtc->enabled);
3954
3955         if (intel_crtc->active)
3956                 return;
3957
3958         if (intel_crtc->config.has_pch_encoder)
3959                 intel_prepare_shared_dpll(intel_crtc);
3960
3961         if (intel_crtc->config.has_dp_encoder)
3962                 intel_dp_set_m_n(intel_crtc);
3963
3964         intel_set_pipe_timings(intel_crtc);
3965
3966         if (intel_crtc->config.has_pch_encoder) {
3967                 intel_cpu_transcoder_set_m_n(intel_crtc,
3968                                      &intel_crtc->config.fdi_m_n, NULL);
3969         }
3970
3971         ironlake_set_pipeconf(crtc);
3972
3973         intel_crtc->active = true;
3974
3975         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3976         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3977
3978         for_each_encoder_on_crtc(dev, crtc, encoder)
3979                 if (encoder->pre_enable)
3980                         encoder->pre_enable(encoder);
3981
3982         if (intel_crtc->config.has_pch_encoder) {
3983                 /* Note: FDI PLL enabling _must_ be done before we enable the
3984                  * cpu pipes, hence this is separate from all the other fdi/pch
3985                  * enabling. */
3986                 ironlake_fdi_pll_enable(intel_crtc);
3987         } else {
3988                 assert_fdi_tx_disabled(dev_priv, pipe);
3989                 assert_fdi_rx_disabled(dev_priv, pipe);
3990         }
3991
3992         ironlake_pfit_enable(intel_crtc);
3993
3994         /*
3995          * On ILK+ LUT must be loaded before the pipe is running but with
3996          * clocks enabled
3997          */
3998         intel_crtc_load_lut(crtc);
3999
4000         intel_update_watermarks(crtc);
4001         intel_enable_pipe(intel_crtc);
4002
4003         if (intel_crtc->config.has_pch_encoder)
4004                 ironlake_pch_enable(crtc);
4005
4006         for_each_encoder_on_crtc(dev, crtc, encoder)
4007                 encoder->enable(encoder);
4008
4009         if (HAS_PCH_CPT(dev))
4010                 cpt_verify_modeset(dev, intel_crtc->pipe);
4011
4012         intel_crtc_enable_planes(crtc);
4013 }
4014
4015 /* IPS only exists on ULT machines and is tied to pipe A. */
4016 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4017 {
4018         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4019 }
4020
4021 /*
4022  * This implements the workaround described in the "notes" section of the mode
4023  * set sequence documentation. When going from no pipes or single pipe to
4024  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4025  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4026  */
4027 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4028 {
4029         struct drm_device *dev = crtc->base.dev;
4030         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4031
4032         /* We want to get the other_active_crtc only if there's only 1 other
4033          * active crtc. */
4034         for_each_intel_crtc(dev, crtc_it) {
4035                 if (!crtc_it->active || crtc_it == crtc)
4036                         continue;
4037
4038                 if (other_active_crtc)
4039                         return;
4040
4041                 other_active_crtc = crtc_it;
4042         }
4043         if (!other_active_crtc)
4044                 return;
4045
4046         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4047         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4048 }
4049
4050 static void haswell_crtc_enable(struct drm_crtc *crtc)
4051 {
4052         struct drm_device *dev = crtc->dev;
4053         struct drm_i915_private *dev_priv = dev->dev_private;
4054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4055         struct intel_encoder *encoder;
4056         int pipe = intel_crtc->pipe;
4057
4058         WARN_ON(!crtc->enabled);
4059
4060         if (intel_crtc->active)
4061                 return;
4062
4063         if (intel_crtc_to_shared_dpll(intel_crtc))
4064                 intel_enable_shared_dpll(intel_crtc);
4065
4066         if (intel_crtc->config.has_dp_encoder)
4067                 intel_dp_set_m_n(intel_crtc);
4068
4069         intel_set_pipe_timings(intel_crtc);
4070
4071         if (intel_crtc->config.has_pch_encoder) {
4072                 intel_cpu_transcoder_set_m_n(intel_crtc,
4073                                      &intel_crtc->config.fdi_m_n, NULL);
4074         }
4075
4076         haswell_set_pipeconf(crtc);
4077
4078         intel_set_pipe_csc(crtc);
4079
4080         intel_crtc->active = true;
4081
4082         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4083         for_each_encoder_on_crtc(dev, crtc, encoder)
4084                 if (encoder->pre_enable)
4085                         encoder->pre_enable(encoder);
4086
4087         if (intel_crtc->config.has_pch_encoder) {
4088                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4089                 dev_priv->display.fdi_link_train(crtc);
4090         }
4091
4092         intel_ddi_enable_pipe_clock(intel_crtc);
4093
4094         ironlake_pfit_enable(intel_crtc);
4095
4096         /*
4097          * On ILK+ LUT must be loaded before the pipe is running but with
4098          * clocks enabled
4099          */
4100         intel_crtc_load_lut(crtc);
4101
4102         intel_ddi_set_pipe_settings(crtc);
4103         intel_ddi_enable_transcoder_func(crtc);
4104
4105         intel_update_watermarks(crtc);
4106         intel_enable_pipe(intel_crtc);
4107
4108         if (intel_crtc->config.has_pch_encoder)
4109                 lpt_pch_enable(crtc);
4110
4111         if (intel_crtc->config.dp_encoder_is_mst)
4112                 intel_ddi_set_vc_payload_alloc(crtc, true);
4113
4114         for_each_encoder_on_crtc(dev, crtc, encoder) {
4115                 encoder->enable(encoder);
4116                 intel_opregion_notify_encoder(encoder, true);
4117         }
4118
4119         /* If we change the relative order between pipe/planes enabling, we need
4120          * to change the workaround. */
4121         haswell_mode_set_planes_workaround(intel_crtc);
4122         intel_crtc_enable_planes(crtc);
4123 }
4124
4125 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4126 {
4127         struct drm_device *dev = crtc->base.dev;
4128         struct drm_i915_private *dev_priv = dev->dev_private;
4129         int pipe = crtc->pipe;
4130
4131         /* To avoid upsetting the power well on haswell only disable the pfit if
4132          * it's in use. The hw state code will make sure we get this right. */
4133         if (crtc->config.pch_pfit.enabled) {
4134                 I915_WRITE(PF_CTL(pipe), 0);
4135                 I915_WRITE(PF_WIN_POS(pipe), 0);
4136                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4137         }
4138 }
4139
4140 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         struct intel_encoder *encoder;
4146         int pipe = intel_crtc->pipe;
4147         u32 reg, temp;
4148
4149         if (!intel_crtc->active)
4150                 return;
4151
4152         intel_crtc_disable_planes(crtc);
4153
4154         for_each_encoder_on_crtc(dev, crtc, encoder)
4155                 encoder->disable(encoder);
4156
4157         if (intel_crtc->config.has_pch_encoder)
4158                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4159
4160         intel_disable_pipe(dev_priv, pipe);
4161
4162         if (intel_crtc->config.dp_encoder_is_mst)
4163                 intel_ddi_set_vc_payload_alloc(crtc, false);
4164
4165         ironlake_pfit_disable(intel_crtc);
4166
4167         for_each_encoder_on_crtc(dev, crtc, encoder)
4168                 if (encoder->post_disable)
4169                         encoder->post_disable(encoder);
4170
4171         if (intel_crtc->config.has_pch_encoder) {
4172                 ironlake_fdi_disable(crtc);
4173
4174                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4175                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4176
4177                 if (HAS_PCH_CPT(dev)) {
4178                         /* disable TRANS_DP_CTL */
4179                         reg = TRANS_DP_CTL(pipe);
4180                         temp = I915_READ(reg);
4181                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4182                                   TRANS_DP_PORT_SEL_MASK);
4183                         temp |= TRANS_DP_PORT_SEL_NONE;
4184                         I915_WRITE(reg, temp);
4185
4186                         /* disable DPLL_SEL */
4187                         temp = I915_READ(PCH_DPLL_SEL);
4188                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4189                         I915_WRITE(PCH_DPLL_SEL, temp);
4190                 }
4191
4192                 /* disable PCH DPLL */
4193                 intel_disable_shared_dpll(intel_crtc);
4194
4195                 ironlake_fdi_pll_disable(intel_crtc);
4196         }
4197
4198         intel_crtc->active = false;
4199         intel_update_watermarks(crtc);
4200
4201         mutex_lock(&dev->struct_mutex);
4202         intel_update_fbc(dev);
4203         mutex_unlock(&dev->struct_mutex);
4204 }
4205
4206 static void haswell_crtc_disable(struct drm_crtc *crtc)
4207 {
4208         struct drm_device *dev = crtc->dev;
4209         struct drm_i915_private *dev_priv = dev->dev_private;
4210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211         struct intel_encoder *encoder;
4212         int pipe = intel_crtc->pipe;
4213         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4214
4215         if (!intel_crtc->active)
4216                 return;
4217
4218         intel_crtc_disable_planes(crtc);
4219
4220         for_each_encoder_on_crtc(dev, crtc, encoder) {
4221                 intel_opregion_notify_encoder(encoder, false);
4222                 encoder->disable(encoder);
4223         }
4224
4225         if (intel_crtc->config.has_pch_encoder)
4226                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4227         intel_disable_pipe(dev_priv, pipe);
4228
4229         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4230
4231         ironlake_pfit_disable(intel_crtc);
4232
4233         intel_ddi_disable_pipe_clock(intel_crtc);
4234
4235         if (intel_crtc->config.has_pch_encoder) {
4236                 lpt_disable_pch_transcoder(dev_priv);
4237                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4238                 intel_ddi_fdi_disable(crtc);
4239         }
4240
4241         for_each_encoder_on_crtc(dev, crtc, encoder)
4242                 if (encoder->post_disable)
4243                         encoder->post_disable(encoder);
4244
4245         intel_crtc->active = false;
4246         intel_update_watermarks(crtc);
4247
4248         mutex_lock(&dev->struct_mutex);
4249         intel_update_fbc(dev);
4250         mutex_unlock(&dev->struct_mutex);
4251
4252         if (intel_crtc_to_shared_dpll(intel_crtc))
4253                 intel_disable_shared_dpll(intel_crtc);
4254 }
4255
4256 static void ironlake_crtc_off(struct drm_crtc *crtc)
4257 {
4258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259         intel_put_shared_dpll(intel_crtc);
4260 }
4261
4262
4263 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4264 {
4265         struct drm_device *dev = crtc->base.dev;
4266         struct drm_i915_private *dev_priv = dev->dev_private;
4267         struct intel_crtc_config *pipe_config = &crtc->config;
4268
4269         if (!crtc->config.gmch_pfit.control)
4270                 return;
4271
4272         /*
4273          * The panel fitter should only be adjusted whilst the pipe is disabled,
4274          * according to register description and PRM.
4275          */
4276         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4277         assert_pipe_disabled(dev_priv, crtc->pipe);
4278
4279         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4280         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4281
4282         /* Border color in case we don't scale up to the full screen. Black by
4283          * default, change to something else for debugging. */
4284         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4285 }
4286
4287 static enum intel_display_power_domain port_to_power_domain(enum port port)
4288 {
4289         switch (port) {
4290         case PORT_A:
4291                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4292         case PORT_B:
4293                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4294         case PORT_C:
4295                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4296         case PORT_D:
4297                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4298         default:
4299                 WARN_ON_ONCE(1);
4300                 return POWER_DOMAIN_PORT_OTHER;
4301         }
4302 }
4303
4304 #define for_each_power_domain(domain, mask)                             \
4305         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4306                 if ((1 << (domain)) & (mask))
4307
4308 enum intel_display_power_domain
4309 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4310 {
4311         struct drm_device *dev = intel_encoder->base.dev;
4312         struct intel_digital_port *intel_dig_port;
4313
4314         switch (intel_encoder->type) {
4315         case INTEL_OUTPUT_UNKNOWN:
4316                 /* Only DDI platforms should ever use this output type */
4317                 WARN_ON_ONCE(!HAS_DDI(dev));
4318         case INTEL_OUTPUT_DISPLAYPORT:
4319         case INTEL_OUTPUT_HDMI:
4320         case INTEL_OUTPUT_EDP:
4321                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4322                 return port_to_power_domain(intel_dig_port->port);
4323         case INTEL_OUTPUT_DP_MST:
4324                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4325                 return port_to_power_domain(intel_dig_port->port);
4326         case INTEL_OUTPUT_ANALOG:
4327                 return POWER_DOMAIN_PORT_CRT;
4328         case INTEL_OUTPUT_DSI:
4329                 return POWER_DOMAIN_PORT_DSI;
4330         default:
4331                 return POWER_DOMAIN_PORT_OTHER;
4332         }
4333 }
4334
4335 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4336 {
4337         struct drm_device *dev = crtc->dev;
4338         struct intel_encoder *intel_encoder;
4339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4340         enum pipe pipe = intel_crtc->pipe;
4341         unsigned long mask;
4342         enum transcoder transcoder;
4343
4344         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4345
4346         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4347         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4348         if (intel_crtc->config.pch_pfit.enabled ||
4349             intel_crtc->config.pch_pfit.force_thru)
4350                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4351
4352         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4353                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4354
4355         return mask;
4356 }
4357
4358 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4359                                   bool enable)
4360 {
4361         if (dev_priv->power_domains.init_power_on == enable)
4362                 return;
4363
4364         if (enable)
4365                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4366         else
4367                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4368
4369         dev_priv->power_domains.init_power_on = enable;
4370 }
4371
4372 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4373 {
4374         struct drm_i915_private *dev_priv = dev->dev_private;
4375         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4376         struct intel_crtc *crtc;
4377
4378         /*
4379          * First get all needed power domains, then put all unneeded, to avoid
4380          * any unnecessary toggling of the power wells.
4381          */
4382         for_each_intel_crtc(dev, crtc) {
4383                 enum intel_display_power_domain domain;
4384
4385                 if (!crtc->base.enabled)
4386                         continue;
4387
4388                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4389
4390                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4391                         intel_display_power_get(dev_priv, domain);
4392         }
4393
4394         for_each_intel_crtc(dev, crtc) {
4395                 enum intel_display_power_domain domain;
4396
4397                 for_each_power_domain(domain, crtc->enabled_power_domains)
4398                         intel_display_power_put(dev_priv, domain);
4399
4400                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4401         }
4402
4403         intel_display_set_init_power(dev_priv, false);
4404 }
4405
4406 /* returns HPLL frequency in kHz */
4407 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4408 {
4409         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4410
4411         /* Obtain SKU information */
4412         mutex_lock(&dev_priv->dpio_lock);
4413         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4414                 CCK_FUSE_HPLL_FREQ_MASK;
4415         mutex_unlock(&dev_priv->dpio_lock);
4416
4417         return vco_freq[hpll_freq] * 1000;
4418 }
4419
4420 static void vlv_update_cdclk(struct drm_device *dev)
4421 {
4422         struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4425         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4426                          dev_priv->vlv_cdclk_freq);
4427
4428         /*
4429          * Program the gmbus_freq based on the cdclk frequency.
4430          * BSpec erroneously claims we should aim for 4MHz, but
4431          * in fact 1MHz is the correct frequency.
4432          */
4433         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4434 }
4435
4436 /* Adjust CDclk dividers to allow high res or save power if possible */
4437 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4438 {
4439         struct drm_i915_private *dev_priv = dev->dev_private;
4440         u32 val, cmd;
4441
4442         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4443
4444         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4445                 cmd = 2;
4446         else if (cdclk == 266667)
4447                 cmd = 1;
4448         else
4449                 cmd = 0;
4450
4451         mutex_lock(&dev_priv->rps.hw_lock);
4452         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4453         val &= ~DSPFREQGUAR_MASK;
4454         val |= (cmd << DSPFREQGUAR_SHIFT);
4455         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4456         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4457                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4458                      50)) {
4459                 DRM_ERROR("timed out waiting for CDclk change\n");
4460         }
4461         mutex_unlock(&dev_priv->rps.hw_lock);
4462
4463         if (cdclk == 400000) {
4464                 u32 divider, vco;
4465
4466                 vco = valleyview_get_vco(dev_priv);
4467                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4468
4469                 mutex_lock(&dev_priv->dpio_lock);
4470                 /* adjust cdclk divider */
4471                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4472                 val &= ~DISPLAY_FREQUENCY_VALUES;
4473                 val |= divider;
4474                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4475
4476                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4477                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4478                              50))
4479                         DRM_ERROR("timed out waiting for CDclk change\n");
4480                 mutex_unlock(&dev_priv->dpio_lock);
4481         }
4482
4483         mutex_lock(&dev_priv->dpio_lock);
4484         /* adjust self-refresh exit latency value */
4485         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4486         val &= ~0x7f;
4487
4488         /*
4489          * For high bandwidth configs, we set a higher latency in the bunit
4490          * so that the core display fetch happens in time to avoid underruns.
4491          */
4492         if (cdclk == 400000)
4493                 val |= 4500 / 250; /* 4.5 usec */
4494         else
4495                 val |= 3000 / 250; /* 3.0 usec */
4496         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4497         mutex_unlock(&dev_priv->dpio_lock);
4498
4499         vlv_update_cdclk(dev);
4500 }
4501
4502 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4503 {
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505         u32 val, cmd;
4506
4507         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4508
4509         switch (cdclk) {
4510         case 400000:
4511                 cmd = 3;
4512                 break;
4513         case 333333:
4514         case 320000:
4515                 cmd = 2;
4516                 break;
4517         case 266667:
4518                 cmd = 1;
4519                 break;
4520         case 200000:
4521                 cmd = 0;
4522                 break;
4523         default:
4524                 WARN_ON(1);
4525                 return;
4526         }
4527
4528         mutex_lock(&dev_priv->rps.hw_lock);
4529         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4530         val &= ~DSPFREQGUAR_MASK_CHV;
4531         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4532         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4533         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4534                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4535                      50)) {
4536                 DRM_ERROR("timed out waiting for CDclk change\n");
4537         }
4538         mutex_unlock(&dev_priv->rps.hw_lock);
4539
4540         vlv_update_cdclk(dev);
4541 }
4542
4543 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4544                                  int max_pixclk)
4545 {
4546         int vco = valleyview_get_vco(dev_priv);
4547         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4548
4549         /* FIXME: Punit isn't quite ready yet */
4550         if (IS_CHERRYVIEW(dev_priv->dev))
4551                 return 400000;
4552
4553         /*
4554          * Really only a few cases to deal with, as only 4 CDclks are supported:
4555          *   200MHz
4556          *   267MHz
4557          *   320/333MHz (depends on HPLL freq)
4558          *   400MHz
4559          * So we check to see whether we're above 90% of the lower bin and
4560          * adjust if needed.
4561          *
4562          * We seem to get an unstable or solid color picture at 200MHz.
4563          * Not sure what's wrong. For now use 200MHz only when all pipes
4564          * are off.
4565          */
4566         if (max_pixclk > freq_320*9/10)
4567                 return 400000;
4568         else if (max_pixclk > 266667*9/10)
4569                 return freq_320;
4570         else if (max_pixclk > 0)
4571                 return 266667;
4572         else
4573                 return 200000;
4574 }
4575
4576 /* compute the max pixel clock for new configuration */
4577 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4578 {
4579         struct drm_device *dev = dev_priv->dev;
4580         struct intel_crtc *intel_crtc;
4581         int max_pixclk = 0;
4582
4583         for_each_intel_crtc(dev, intel_crtc) {
4584                 if (intel_crtc->new_enabled)
4585                         max_pixclk = max(max_pixclk,
4586                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4587         }
4588
4589         return max_pixclk;
4590 }
4591
4592 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4593                                             unsigned *prepare_pipes)
4594 {
4595         struct drm_i915_private *dev_priv = dev->dev_private;
4596         struct intel_crtc *intel_crtc;
4597         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4598
4599         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4600             dev_priv->vlv_cdclk_freq)
4601                 return;
4602
4603         /* disable/enable all currently active pipes while we change cdclk */
4604         for_each_intel_crtc(dev, intel_crtc)
4605                 if (intel_crtc->base.enabled)
4606                         *prepare_pipes |= (1 << intel_crtc->pipe);
4607 }
4608
4609 static void valleyview_modeset_global_resources(struct drm_device *dev)
4610 {
4611         struct drm_i915_private *dev_priv = dev->dev_private;
4612         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4613         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4614
4615         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4616                 if (IS_CHERRYVIEW(dev))
4617                         cherryview_set_cdclk(dev, req_cdclk);
4618                 else
4619                         valleyview_set_cdclk(dev, req_cdclk);
4620         }
4621
4622         modeset_update_crtc_power_domains(dev);
4623 }
4624
4625 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4626 {
4627         struct drm_device *dev = crtc->dev;
4628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629         struct intel_encoder *encoder;
4630         int pipe = intel_crtc->pipe;
4631         bool is_dsi;
4632
4633         WARN_ON(!crtc->enabled);
4634
4635         if (intel_crtc->active)
4636                 return;
4637
4638         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4639
4640         if (!is_dsi) {
4641                 if (IS_CHERRYVIEW(dev))
4642                         chv_prepare_pll(intel_crtc);
4643                 else
4644                         vlv_prepare_pll(intel_crtc);
4645         }
4646
4647         if (intel_crtc->config.has_dp_encoder)
4648                 intel_dp_set_m_n(intel_crtc);
4649
4650         intel_set_pipe_timings(intel_crtc);
4651
4652         i9xx_set_pipeconf(intel_crtc);
4653
4654         intel_crtc->active = true;
4655
4656         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4657
4658         for_each_encoder_on_crtc(dev, crtc, encoder)
4659                 if (encoder->pre_pll_enable)
4660                         encoder->pre_pll_enable(encoder);
4661
4662         if (!is_dsi) {
4663                 if (IS_CHERRYVIEW(dev))
4664                         chv_enable_pll(intel_crtc);
4665                 else
4666                         vlv_enable_pll(intel_crtc);
4667         }
4668
4669         for_each_encoder_on_crtc(dev, crtc, encoder)
4670                 if (encoder->pre_enable)
4671                         encoder->pre_enable(encoder);
4672
4673         i9xx_pfit_enable(intel_crtc);
4674
4675         intel_crtc_load_lut(crtc);
4676
4677         intel_update_watermarks(crtc);
4678         intel_enable_pipe(intel_crtc);
4679
4680         for_each_encoder_on_crtc(dev, crtc, encoder)
4681                 encoder->enable(encoder);
4682
4683         intel_crtc_enable_planes(crtc);
4684
4685         /* Underruns don't raise interrupts, so check manually. */
4686         i9xx_check_fifo_underruns(dev);
4687 }
4688
4689 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4690 {
4691         struct drm_device *dev = crtc->base.dev;
4692         struct drm_i915_private *dev_priv = dev->dev_private;
4693
4694         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4695         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4696 }
4697
4698 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702         struct intel_encoder *encoder;
4703         int pipe = intel_crtc->pipe;
4704
4705         WARN_ON(!crtc->enabled);
4706
4707         if (intel_crtc->active)
4708                 return;
4709
4710         i9xx_set_pll_dividers(intel_crtc);
4711
4712         if (intel_crtc->config.has_dp_encoder)
4713                 intel_dp_set_m_n(intel_crtc);
4714
4715         intel_set_pipe_timings(intel_crtc);
4716
4717         i9xx_set_pipeconf(intel_crtc);
4718
4719         intel_crtc->active = true;
4720
4721         if (!IS_GEN2(dev))
4722                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4723
4724         for_each_encoder_on_crtc(dev, crtc, encoder)
4725                 if (encoder->pre_enable)
4726                         encoder->pre_enable(encoder);
4727
4728         i9xx_enable_pll(intel_crtc);
4729
4730         i9xx_pfit_enable(intel_crtc);
4731
4732         intel_crtc_load_lut(crtc);
4733
4734         intel_update_watermarks(crtc);
4735         intel_enable_pipe(intel_crtc);
4736
4737         for_each_encoder_on_crtc(dev, crtc, encoder)
4738                 encoder->enable(encoder);
4739
4740         intel_crtc_enable_planes(crtc);
4741
4742         /*
4743          * Gen2 reports pipe underruns whenever all planes are disabled.
4744          * So don't enable underrun reporting before at least some planes
4745          * are enabled.
4746          * FIXME: Need to fix the logic to work when we turn off all planes
4747          * but leave the pipe running.
4748          */
4749         if (IS_GEN2(dev))
4750                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4751
4752         /* Underruns don't raise interrupts, so check manually. */
4753         i9xx_check_fifo_underruns(dev);
4754 }
4755
4756 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4757 {
4758         struct drm_device *dev = crtc->base.dev;
4759         struct drm_i915_private *dev_priv = dev->dev_private;
4760
4761         if (!crtc->config.gmch_pfit.control)
4762                 return;
4763
4764         assert_pipe_disabled(dev_priv, crtc->pipe);
4765
4766         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4767                          I915_READ(PFIT_CONTROL));
4768         I915_WRITE(PFIT_CONTROL, 0);
4769 }
4770
4771 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4772 {
4773         struct drm_device *dev = crtc->dev;
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4776         struct intel_encoder *encoder;
4777         int pipe = intel_crtc->pipe;
4778
4779         if (!intel_crtc->active)
4780                 return;
4781
4782         /*
4783          * Gen2 reports pipe underruns whenever all planes are disabled.
4784          * So diasble underrun reporting before all the planes get disabled.
4785          * FIXME: Need to fix the logic to work when we turn off all planes
4786          * but leave the pipe running.
4787          */
4788         if (IS_GEN2(dev))
4789                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4790
4791         /*
4792          * Vblank time updates from the shadow to live plane control register
4793          * are blocked if the memory self-refresh mode is active at that
4794          * moment. So to make sure the plane gets truly disabled, disable
4795          * first the self-refresh mode. The self-refresh enable bit in turn
4796          * will be checked/applied by the HW only at the next frame start
4797          * event which is after the vblank start event, so we need to have a
4798          * wait-for-vblank between disabling the plane and the pipe.
4799          */
4800         intel_set_memory_cxsr(dev_priv, false);
4801         intel_crtc_disable_planes(crtc);
4802
4803         for_each_encoder_on_crtc(dev, crtc, encoder)
4804                 encoder->disable(encoder);
4805
4806         /*
4807          * On gen2 planes are double buffered but the pipe isn't, so we must
4808          * wait for planes to fully turn off before disabling the pipe.
4809          * We also need to wait on all gmch platforms because of the
4810          * self-refresh mode constraint explained above.
4811          */
4812         intel_wait_for_vblank(dev, pipe);
4813
4814         intel_disable_pipe(dev_priv, pipe);
4815
4816         i9xx_pfit_disable(intel_crtc);
4817
4818         for_each_encoder_on_crtc(dev, crtc, encoder)
4819                 if (encoder->post_disable)
4820                         encoder->post_disable(encoder);
4821
4822         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4823                 if (IS_CHERRYVIEW(dev))
4824                         chv_disable_pll(dev_priv, pipe);
4825                 else if (IS_VALLEYVIEW(dev))
4826                         vlv_disable_pll(dev_priv, pipe);
4827                 else
4828                         i9xx_disable_pll(dev_priv, pipe);
4829         }
4830
4831         if (!IS_GEN2(dev))
4832                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4833
4834         intel_crtc->active = false;
4835         intel_update_watermarks(crtc);
4836
4837         mutex_lock(&dev->struct_mutex);
4838         intel_update_fbc(dev);
4839         mutex_unlock(&dev->struct_mutex);
4840 }
4841
4842 static void i9xx_crtc_off(struct drm_crtc *crtc)
4843 {
4844 }
4845
4846 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4847                                     bool enabled)
4848 {
4849         struct drm_device *dev = crtc->dev;
4850         struct drm_i915_master_private *master_priv;
4851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4852         int pipe = intel_crtc->pipe;
4853
4854         if (!dev->primary->master)
4855                 return;
4856
4857         master_priv = dev->primary->master->driver_priv;
4858         if (!master_priv->sarea_priv)
4859                 return;
4860
4861         switch (pipe) {
4862         case 0:
4863                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4864                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4865                 break;
4866         case 1:
4867                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4868                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4869                 break;
4870         default:
4871                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4872                 break;
4873         }
4874 }
4875
4876 /* Master function to enable/disable CRTC and corresponding power wells */
4877 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4878 {
4879         struct drm_device *dev = crtc->dev;
4880         struct drm_i915_private *dev_priv = dev->dev_private;
4881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882         enum intel_display_power_domain domain;
4883         unsigned long domains;
4884
4885         if (enable) {
4886                 if (!intel_crtc->active) {
4887                         domains = get_crtc_power_domains(crtc);
4888                         for_each_power_domain(domain, domains)
4889                                 intel_display_power_get(dev_priv, domain);
4890                         intel_crtc->enabled_power_domains = domains;
4891
4892                         dev_priv->display.crtc_enable(crtc);
4893                 }
4894         } else {
4895                 if (intel_crtc->active) {
4896                         dev_priv->display.crtc_disable(crtc);
4897
4898                         domains = intel_crtc->enabled_power_domains;
4899                         for_each_power_domain(domain, domains)
4900                                 intel_display_power_put(dev_priv, domain);
4901                         intel_crtc->enabled_power_domains = 0;
4902                 }
4903         }
4904 }
4905
4906 /**
4907  * Sets the power management mode of the pipe and plane.
4908  */
4909 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4910 {
4911         struct drm_device *dev = crtc->dev;
4912         struct intel_encoder *intel_encoder;
4913         bool enable = false;
4914
4915         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4916                 enable |= intel_encoder->connectors_active;
4917
4918         intel_crtc_control(crtc, enable);
4919
4920         intel_crtc_update_sarea(crtc, enable);
4921 }
4922
4923 static void intel_crtc_disable(struct drm_crtc *crtc)
4924 {
4925         struct drm_device *dev = crtc->dev;
4926         struct drm_connector *connector;
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4929         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4930
4931         /* crtc should still be enabled when we disable it. */
4932         WARN_ON(!crtc->enabled);
4933
4934         dev_priv->display.crtc_disable(crtc);
4935         intel_crtc_update_sarea(crtc, false);
4936         dev_priv->display.off(crtc);
4937
4938         if (crtc->primary->fb) {
4939                 mutex_lock(&dev->struct_mutex);
4940                 intel_unpin_fb_obj(old_obj);
4941                 i915_gem_track_fb(old_obj, NULL,
4942                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
4943                 mutex_unlock(&dev->struct_mutex);
4944                 crtc->primary->fb = NULL;
4945         }
4946
4947         /* Update computed state. */
4948         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4949                 if (!connector->encoder || !connector->encoder->crtc)
4950                         continue;
4951
4952                 if (connector->encoder->crtc != crtc)
4953                         continue;
4954
4955                 connector->dpms = DRM_MODE_DPMS_OFF;
4956                 to_intel_encoder(connector->encoder)->connectors_active = false;
4957         }
4958 }
4959
4960 void intel_encoder_destroy(struct drm_encoder *encoder)
4961 {
4962         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4963
4964         drm_encoder_cleanup(encoder);
4965         kfree(intel_encoder);
4966 }
4967
4968 /* Simple dpms helper for encoders with just one connector, no cloning and only
4969  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4970  * state of the entire output pipe. */
4971 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4972 {
4973         if (mode == DRM_MODE_DPMS_ON) {
4974                 encoder->connectors_active = true;
4975
4976                 intel_crtc_update_dpms(encoder->base.crtc);
4977         } else {
4978                 encoder->connectors_active = false;
4979
4980                 intel_crtc_update_dpms(encoder->base.crtc);
4981         }
4982 }
4983
4984 /* Cross check the actual hw state with our own modeset state tracking (and it's
4985  * internal consistency). */
4986 static void intel_connector_check_state(struct intel_connector *connector)
4987 {
4988         if (connector->get_hw_state(connector)) {
4989                 struct intel_encoder *encoder = connector->encoder;
4990                 struct drm_crtc *crtc;
4991                 bool encoder_enabled;
4992                 enum pipe pipe;
4993
4994                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4995                               connector->base.base.id,
4996                               connector->base.name);
4997
4998                 /* there is no real hw state for MST connectors */
4999                 if (connector->mst_port)
5000                         return;
5001
5002                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5003                      "wrong connector dpms state\n");
5004                 WARN(connector->base.encoder != &encoder->base,
5005                      "active connector not linked to encoder\n");
5006
5007                 if (encoder) {
5008                         WARN(!encoder->connectors_active,
5009                              "encoder->connectors_active not set\n");
5010
5011                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5012                         WARN(!encoder_enabled, "encoder not enabled\n");
5013                         if (WARN_ON(!encoder->base.crtc))
5014                                 return;
5015
5016                         crtc = encoder->base.crtc;
5017
5018                         WARN(!crtc->enabled, "crtc not enabled\n");
5019                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5020                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5021                              "encoder active on the wrong pipe\n");
5022                 }
5023         }
5024 }
5025
5026 /* Even simpler default implementation, if there's really no special case to
5027  * consider. */
5028 void intel_connector_dpms(struct drm_connector *connector, int mode)
5029 {
5030         /* All the simple cases only support two dpms states. */
5031         if (mode != DRM_MODE_DPMS_ON)
5032                 mode = DRM_MODE_DPMS_OFF;
5033
5034         if (mode == connector->dpms)
5035                 return;
5036
5037         connector->dpms = mode;
5038
5039         /* Only need to change hw state when actually enabled */
5040         if (connector->encoder)
5041                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5042
5043         intel_modeset_check_state(connector->dev);
5044 }
5045
5046 /* Simple connector->get_hw_state implementation for encoders that support only
5047  * one connector and no cloning and hence the encoder state determines the state
5048  * of the connector. */
5049 bool intel_connector_get_hw_state(struct intel_connector *connector)
5050 {
5051         enum pipe pipe = 0;
5052         struct intel_encoder *encoder = connector->encoder;
5053
5054         return encoder->get_hw_state(encoder, &pipe);
5055 }
5056
5057 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5058                                      struct intel_crtc_config *pipe_config)
5059 {
5060         struct drm_i915_private *dev_priv = dev->dev_private;
5061         struct intel_crtc *pipe_B_crtc =
5062                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5063
5064         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5065                       pipe_name(pipe), pipe_config->fdi_lanes);
5066         if (pipe_config->fdi_lanes > 4) {
5067                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5068                               pipe_name(pipe), pipe_config->fdi_lanes);
5069                 return false;
5070         }
5071
5072         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5073                 if (pipe_config->fdi_lanes > 2) {
5074                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5075                                       pipe_config->fdi_lanes);
5076                         return false;
5077                 } else {
5078                         return true;
5079                 }
5080         }
5081
5082         if (INTEL_INFO(dev)->num_pipes == 2)
5083                 return true;
5084
5085         /* Ivybridge 3 pipe is really complicated */
5086         switch (pipe) {
5087         case PIPE_A:
5088                 return true;
5089         case PIPE_B:
5090                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5091                     pipe_config->fdi_lanes > 2) {
5092                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5093                                       pipe_name(pipe), pipe_config->fdi_lanes);
5094                         return false;
5095                 }
5096                 return true;
5097         case PIPE_C:
5098                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5099                     pipe_B_crtc->config.fdi_lanes <= 2) {
5100                         if (pipe_config->fdi_lanes > 2) {
5101                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5102                                               pipe_name(pipe), pipe_config->fdi_lanes);
5103                                 return false;
5104                         }
5105                 } else {
5106                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5107                         return false;
5108                 }
5109                 return true;
5110         default:
5111                 BUG();
5112         }
5113 }
5114
5115 #define RETRY 1
5116 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5117                                        struct intel_crtc_config *pipe_config)
5118 {
5119         struct drm_device *dev = intel_crtc->base.dev;
5120         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5121         int lane, link_bw, fdi_dotclock;
5122         bool setup_ok, needs_recompute = false;
5123
5124 retry:
5125         /* FDI is a binary signal running at ~2.7GHz, encoding
5126          * each output octet as 10 bits. The actual frequency
5127          * is stored as a divider into a 100MHz clock, and the
5128          * mode pixel clock is stored in units of 1KHz.
5129          * Hence the bw of each lane in terms of the mode signal
5130          * is:
5131          */
5132         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5133
5134         fdi_dotclock = adjusted_mode->crtc_clock;
5135
5136         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5137                                            pipe_config->pipe_bpp);
5138
5139         pipe_config->fdi_lanes = lane;
5140
5141         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5142                                link_bw, &pipe_config->fdi_m_n);
5143
5144         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5145                                             intel_crtc->pipe, pipe_config);
5146         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5147                 pipe_config->pipe_bpp -= 2*3;
5148                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5149                               pipe_config->pipe_bpp);
5150                 needs_recompute = true;
5151                 pipe_config->bw_constrained = true;
5152
5153                 goto retry;
5154         }
5155
5156         if (needs_recompute)
5157                 return RETRY;
5158
5159         return setup_ok ? 0 : -EINVAL;
5160 }
5161
5162 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5163                                    struct intel_crtc_config *pipe_config)
5164 {
5165         pipe_config->ips_enabled = i915.enable_ips &&
5166                                    hsw_crtc_supports_ips(crtc) &&
5167                                    pipe_config->pipe_bpp <= 24;
5168 }
5169
5170 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5171                                      struct intel_crtc_config *pipe_config)
5172 {
5173         struct drm_device *dev = crtc->base.dev;
5174         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5175
5176         /* FIXME should check pixel clock limits on all platforms */
5177         if (INTEL_INFO(dev)->gen < 4) {
5178                 struct drm_i915_private *dev_priv = dev->dev_private;
5179                 int clock_limit =
5180                         dev_priv->display.get_display_clock_speed(dev);
5181
5182                 /*
5183                  * Enable pixel doubling when the dot clock
5184                  * is > 90% of the (display) core speed.
5185                  *
5186                  * GDG double wide on either pipe,
5187                  * otherwise pipe A only.
5188                  */
5189                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5190                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5191                         clock_limit *= 2;
5192                         pipe_config->double_wide = true;
5193                 }
5194
5195                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5196                         return -EINVAL;
5197         }
5198
5199         /*
5200          * Pipe horizontal size must be even in:
5201          * - DVO ganged mode
5202          * - LVDS dual channel mode
5203          * - Double wide pipe
5204          */
5205         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5206              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5207                 pipe_config->pipe_src_w &= ~1;
5208
5209         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5210          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5211          */
5212         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5213                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5214                 return -EINVAL;
5215
5216         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5217                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5218         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5219                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5220                  * for lvds. */
5221                 pipe_config->pipe_bpp = 8*3;
5222         }
5223
5224         if (HAS_IPS(dev))
5225                 hsw_compute_ips_config(crtc, pipe_config);
5226
5227         /*
5228          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5229          * old clock survives for now.
5230          */
5231         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5232                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5233
5234         if (pipe_config->has_pch_encoder)
5235                 return ironlake_fdi_compute_config(crtc, pipe_config);
5236
5237         return 0;
5238 }
5239
5240 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5241 {
5242         struct drm_i915_private *dev_priv = dev->dev_private;
5243         int vco = valleyview_get_vco(dev_priv);
5244         u32 val;
5245         int divider;
5246
5247         /* FIXME: Punit isn't quite ready yet */
5248         if (IS_CHERRYVIEW(dev))
5249                 return 400000;
5250
5251         mutex_lock(&dev_priv->dpio_lock);
5252         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5253         mutex_unlock(&dev_priv->dpio_lock);
5254
5255         divider = val & DISPLAY_FREQUENCY_VALUES;
5256
5257         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5258              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5259              "cdclk change in progress\n");
5260
5261         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5262 }
5263
5264 static int i945_get_display_clock_speed(struct drm_device *dev)
5265 {
5266         return 400000;
5267 }
5268
5269 static int i915_get_display_clock_speed(struct drm_device *dev)
5270 {
5271         return 333000;
5272 }
5273
5274 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5275 {
5276         return 200000;
5277 }
5278
5279 static int pnv_get_display_clock_speed(struct drm_device *dev)
5280 {
5281         u16 gcfgc = 0;
5282
5283         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5284
5285         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5286         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5287                 return 267000;
5288         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5289                 return 333000;
5290         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5291                 return 444000;
5292         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5293                 return 200000;
5294         default:
5295                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5296         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5297                 return 133000;
5298         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5299                 return 167000;
5300         }
5301 }
5302
5303 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5304 {
5305         u16 gcfgc = 0;
5306
5307         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5308
5309         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5310                 return 133000;
5311         else {
5312                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5313                 case GC_DISPLAY_CLOCK_333_MHZ:
5314                         return 333000;
5315                 default:
5316                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5317                         return 190000;
5318                 }
5319         }
5320 }
5321
5322 static int i865_get_display_clock_speed(struct drm_device *dev)
5323 {
5324         return 266000;
5325 }
5326
5327 static int i855_get_display_clock_speed(struct drm_device *dev)
5328 {
5329         u16 hpllcc = 0;
5330         /* Assume that the hardware is in the high speed state.  This
5331          * should be the default.
5332          */
5333         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5334         case GC_CLOCK_133_200:
5335         case GC_CLOCK_100_200:
5336                 return 200000;
5337         case GC_CLOCK_166_250:
5338                 return 250000;
5339         case GC_CLOCK_100_133:
5340                 return 133000;
5341         }
5342
5343         /* Shouldn't happen */
5344         return 0;
5345 }
5346
5347 static int i830_get_display_clock_speed(struct drm_device *dev)
5348 {
5349         return 133000;
5350 }
5351
5352 static void
5353 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5354 {
5355         while (*num > DATA_LINK_M_N_MASK ||
5356                *den > DATA_LINK_M_N_MASK) {
5357                 *num >>= 1;
5358                 *den >>= 1;
5359         }
5360 }
5361
5362 static void compute_m_n(unsigned int m, unsigned int n,
5363                         uint32_t *ret_m, uint32_t *ret_n)
5364 {
5365         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5366         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5367         intel_reduce_m_n_ratio(ret_m, ret_n);
5368 }
5369
5370 void
5371 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5372                        int pixel_clock, int link_clock,
5373                        struct intel_link_m_n *m_n)
5374 {
5375         m_n->tu = 64;
5376
5377         compute_m_n(bits_per_pixel * pixel_clock,
5378                     link_clock * nlanes * 8,
5379                     &m_n->gmch_m, &m_n->gmch_n);
5380
5381         compute_m_n(pixel_clock, link_clock,
5382                     &m_n->link_m, &m_n->link_n);
5383 }
5384
5385 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5386 {
5387         if (i915.panel_use_ssc >= 0)
5388                 return i915.panel_use_ssc != 0;
5389         return dev_priv->vbt.lvds_use_ssc
5390                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5391 }
5392
5393 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5394 {
5395         struct drm_device *dev = crtc->dev;
5396         struct drm_i915_private *dev_priv = dev->dev_private;
5397         int refclk;
5398
5399         if (IS_VALLEYVIEW(dev)) {
5400                 refclk = 100000;
5401         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5402             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5403                 refclk = dev_priv->vbt.lvds_ssc_freq;
5404                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5405         } else if (!IS_GEN2(dev)) {
5406                 refclk = 96000;
5407         } else {
5408                 refclk = 48000;
5409         }
5410
5411         return refclk;
5412 }
5413
5414 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5415 {
5416         return (1 << dpll->n) << 16 | dpll->m2;
5417 }
5418
5419 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5420 {
5421         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5422 }
5423
5424 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5425                                      intel_clock_t *reduced_clock)
5426 {
5427         struct drm_device *dev = crtc->base.dev;
5428         u32 fp, fp2 = 0;
5429
5430         if (IS_PINEVIEW(dev)) {
5431                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5432                 if (reduced_clock)
5433                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5434         } else {
5435                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5436                 if (reduced_clock)
5437                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5438         }
5439
5440         crtc->config.dpll_hw_state.fp0 = fp;
5441
5442         crtc->lowfreq_avail = false;
5443         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5444             reduced_clock && i915.powersave) {
5445                 crtc->config.dpll_hw_state.fp1 = fp2;
5446                 crtc->lowfreq_avail = true;
5447         } else {
5448                 crtc->config.dpll_hw_state.fp1 = fp;
5449         }
5450 }
5451
5452 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5453                 pipe)
5454 {
5455         u32 reg_val;
5456
5457         /*
5458          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5459          * and set it to a reasonable value instead.
5460          */
5461         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5462         reg_val &= 0xffffff00;
5463         reg_val |= 0x00000030;
5464         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5465
5466         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5467         reg_val &= 0x8cffffff;
5468         reg_val = 0x8c000000;
5469         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5470
5471         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5472         reg_val &= 0xffffff00;
5473         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5474
5475         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5476         reg_val &= 0x00ffffff;
5477         reg_val |= 0xb0000000;
5478         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5479 }
5480
5481 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5482                                          struct intel_link_m_n *m_n)
5483 {
5484         struct drm_device *dev = crtc->base.dev;
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486         int pipe = crtc->pipe;
5487
5488         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5489         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5490         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5491         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5492 }
5493
5494 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5495                                          struct intel_link_m_n *m_n,
5496                                          struct intel_link_m_n *m2_n2)
5497 {
5498         struct drm_device *dev = crtc->base.dev;
5499         struct drm_i915_private *dev_priv = dev->dev_private;
5500         int pipe = crtc->pipe;
5501         enum transcoder transcoder = crtc->config.cpu_transcoder;
5502
5503         if (INTEL_INFO(dev)->gen >= 5) {
5504                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5505                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5506                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5507                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5508                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5509                  * for gen < 8) and if DRRS is supported (to make sure the
5510                  * registers are not unnecessarily accessed).
5511                  */
5512                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5513                         crtc->config.has_drrs) {
5514                         I915_WRITE(PIPE_DATA_M2(transcoder),
5515                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5516                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5517                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5518                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5519                 }
5520         } else {
5521                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5522                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5523                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5524                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5525         }
5526 }
5527
5528 void intel_dp_set_m_n(struct intel_crtc *crtc)
5529 {
5530         if (crtc->config.has_pch_encoder)
5531                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5532         else
5533                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5534                                                    &crtc->config.dp_m2_n2);
5535 }
5536
5537 static void vlv_update_pll(struct intel_crtc *crtc)
5538 {
5539         u32 dpll, dpll_md;
5540
5541         /*
5542          * Enable DPIO clock input. We should never disable the reference
5543          * clock for pipe B, since VGA hotplug / manual detection depends
5544          * on it.
5545          */
5546         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5547                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5548         /* We should never disable this, set it here for state tracking */
5549         if (crtc->pipe == PIPE_B)
5550                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5551         dpll |= DPLL_VCO_ENABLE;
5552         crtc->config.dpll_hw_state.dpll = dpll;
5553
5554         dpll_md = (crtc->config.pixel_multiplier - 1)
5555                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5556         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5557 }
5558
5559 static void vlv_prepare_pll(struct intel_crtc *crtc)
5560 {
5561         struct drm_device *dev = crtc->base.dev;
5562         struct drm_i915_private *dev_priv = dev->dev_private;
5563         int pipe = crtc->pipe;
5564         u32 mdiv;
5565         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5566         u32 coreclk, reg_val;
5567
5568         mutex_lock(&dev_priv->dpio_lock);
5569
5570         bestn = crtc->config.dpll.n;
5571         bestm1 = crtc->config.dpll.m1;
5572         bestm2 = crtc->config.dpll.m2;
5573         bestp1 = crtc->config.dpll.p1;
5574         bestp2 = crtc->config.dpll.p2;
5575
5576         /* See eDP HDMI DPIO driver vbios notes doc */
5577
5578         /* PLL B needs special handling */
5579         if (pipe == PIPE_B)
5580                 vlv_pllb_recal_opamp(dev_priv, pipe);
5581
5582         /* Set up Tx target for periodic Rcomp update */
5583         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5584
5585         /* Disable target IRef on PLL */
5586         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5587         reg_val &= 0x00ffffff;
5588         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5589
5590         /* Disable fast lock */
5591         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5592
5593         /* Set idtafcrecal before PLL is enabled */
5594         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5595         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5596         mdiv |= ((bestn << DPIO_N_SHIFT));
5597         mdiv |= (1 << DPIO_K_SHIFT);
5598
5599         /*
5600          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5601          * but we don't support that).
5602          * Note: don't use the DAC post divider as it seems unstable.
5603          */
5604         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5605         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5606
5607         mdiv |= DPIO_ENABLE_CALIBRATION;
5608         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5609
5610         /* Set HBR and RBR LPF coefficients */
5611         if (crtc->config.port_clock == 162000 ||
5612             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5613             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5614                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5615                                  0x009f0003);
5616         else
5617                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5618                                  0x00d0000f);
5619
5620         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5621             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5622                 /* Use SSC source */
5623                 if (pipe == PIPE_A)
5624                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5625                                          0x0df40000);
5626                 else
5627                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5628                                          0x0df70000);
5629         } else { /* HDMI or VGA */
5630                 /* Use bend source */
5631                 if (pipe == PIPE_A)
5632                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5633                                          0x0df70000);
5634                 else
5635                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5636                                          0x0df40000);
5637         }
5638
5639         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5640         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5641         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5642             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5643                 coreclk |= 0x01000000;
5644         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5645
5646         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5647         mutex_unlock(&dev_priv->dpio_lock);
5648 }
5649
5650 static void chv_update_pll(struct intel_crtc *crtc)
5651 {
5652         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5653                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5654                 DPLL_VCO_ENABLE;
5655         if (crtc->pipe != PIPE_A)
5656                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5657
5658         crtc->config.dpll_hw_state.dpll_md =
5659                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5660 }
5661
5662 static void chv_prepare_pll(struct intel_crtc *crtc)
5663 {
5664         struct drm_device *dev = crtc->base.dev;
5665         struct drm_i915_private *dev_priv = dev->dev_private;
5666         int pipe = crtc->pipe;
5667         int dpll_reg = DPLL(crtc->pipe);
5668         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5669         u32 loopfilter, intcoeff;
5670         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5671         int refclk;
5672
5673         bestn = crtc->config.dpll.n;
5674         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5675         bestm1 = crtc->config.dpll.m1;
5676         bestm2 = crtc->config.dpll.m2 >> 22;
5677         bestp1 = crtc->config.dpll.p1;
5678         bestp2 = crtc->config.dpll.p2;
5679
5680         /*
5681          * Enable Refclk and SSC
5682          */
5683         I915_WRITE(dpll_reg,
5684                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5685
5686         mutex_lock(&dev_priv->dpio_lock);
5687
5688         /* p1 and p2 divider */
5689         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5690                         5 << DPIO_CHV_S1_DIV_SHIFT |
5691                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5692                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5693                         1 << DPIO_CHV_K_DIV_SHIFT);
5694
5695         /* Feedback post-divider - m2 */
5696         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5697
5698         /* Feedback refclk divider - n and m1 */
5699         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5700                         DPIO_CHV_M1_DIV_BY_2 |
5701                         1 << DPIO_CHV_N_DIV_SHIFT);
5702
5703         /* M2 fraction division */
5704         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5705
5706         /* M2 fraction division enable */
5707         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5708                        DPIO_CHV_FRAC_DIV_EN |
5709                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5710
5711         /* Loop filter */
5712         refclk = i9xx_get_refclk(&crtc->base, 0);
5713         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5714                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5715         if (refclk == 100000)
5716                 intcoeff = 11;
5717         else if (refclk == 38400)
5718                 intcoeff = 10;
5719         else
5720                 intcoeff = 9;
5721         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5722         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5723
5724         /* AFC Recal */
5725         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5726                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5727                         DPIO_AFC_RECAL);
5728
5729         mutex_unlock(&dev_priv->dpio_lock);
5730 }
5731
5732 static void i9xx_update_pll(struct intel_crtc *crtc,
5733                             intel_clock_t *reduced_clock,
5734                             int num_connectors)
5735 {
5736         struct drm_device *dev = crtc->base.dev;
5737         struct drm_i915_private *dev_priv = dev->dev_private;
5738         u32 dpll;
5739         bool is_sdvo;
5740         struct dpll *clock = &crtc->config.dpll;
5741
5742         i9xx_update_pll_dividers(crtc, reduced_clock);
5743
5744         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5745                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5746
5747         dpll = DPLL_VGA_MODE_DIS;
5748
5749         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5750                 dpll |= DPLLB_MODE_LVDS;
5751         else
5752                 dpll |= DPLLB_MODE_DAC_SERIAL;
5753
5754         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5755                 dpll |= (crtc->config.pixel_multiplier - 1)
5756                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5757         }
5758
5759         if (is_sdvo)
5760                 dpll |= DPLL_SDVO_HIGH_SPEED;
5761
5762         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5763                 dpll |= DPLL_SDVO_HIGH_SPEED;
5764
5765         /* compute bitmask from p1 value */
5766         if (IS_PINEVIEW(dev))
5767                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5768         else {
5769                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5770                 if (IS_G4X(dev) && reduced_clock)
5771                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5772         }
5773         switch (clock->p2) {
5774         case 5:
5775                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5776                 break;
5777         case 7:
5778                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5779                 break;
5780         case 10:
5781                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5782                 break;
5783         case 14:
5784                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5785                 break;
5786         }
5787         if (INTEL_INFO(dev)->gen >= 4)
5788                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5789
5790         if (crtc->config.sdvo_tv_clock)
5791                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5792         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5793                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5794                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5795         else
5796                 dpll |= PLL_REF_INPUT_DREFCLK;
5797
5798         dpll |= DPLL_VCO_ENABLE;
5799         crtc->config.dpll_hw_state.dpll = dpll;
5800
5801         if (INTEL_INFO(dev)->gen >= 4) {
5802                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5803                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5804                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5805         }
5806 }
5807
5808 static void i8xx_update_pll(struct intel_crtc *crtc,
5809                             intel_clock_t *reduced_clock,
5810                             int num_connectors)
5811 {
5812         struct drm_device *dev = crtc->base.dev;
5813         struct drm_i915_private *dev_priv = dev->dev_private;
5814         u32 dpll;
5815         struct dpll *clock = &crtc->config.dpll;
5816
5817         i9xx_update_pll_dividers(crtc, reduced_clock);
5818
5819         dpll = DPLL_VGA_MODE_DIS;
5820
5821         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5822                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5823         } else {
5824                 if (clock->p1 == 2)
5825                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5826                 else
5827                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5828                 if (clock->p2 == 4)
5829                         dpll |= PLL_P2_DIVIDE_BY_4;
5830         }
5831
5832         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5833                 dpll |= DPLL_DVO_2X_MODE;
5834
5835         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5836                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5837                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5838         else
5839                 dpll |= PLL_REF_INPUT_DREFCLK;
5840
5841         dpll |= DPLL_VCO_ENABLE;
5842         crtc->config.dpll_hw_state.dpll = dpll;
5843 }
5844
5845 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5846 {
5847         struct drm_device *dev = intel_crtc->base.dev;
5848         struct drm_i915_private *dev_priv = dev->dev_private;
5849         enum pipe pipe = intel_crtc->pipe;
5850         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5851         struct drm_display_mode *adjusted_mode =
5852                 &intel_crtc->config.adjusted_mode;
5853         uint32_t crtc_vtotal, crtc_vblank_end;
5854         int vsyncshift = 0;
5855
5856         /* We need to be careful not to changed the adjusted mode, for otherwise
5857          * the hw state checker will get angry at the mismatch. */
5858         crtc_vtotal = adjusted_mode->crtc_vtotal;
5859         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5860
5861         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5862                 /* the chip adds 2 halflines automatically */
5863                 crtc_vtotal -= 1;
5864                 crtc_vblank_end -= 1;
5865
5866                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5867                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5868                 else
5869                         vsyncshift = adjusted_mode->crtc_hsync_start -
5870                                 adjusted_mode->crtc_htotal / 2;
5871                 if (vsyncshift < 0)
5872                         vsyncshift += adjusted_mode->crtc_htotal;
5873         }
5874
5875         if (INTEL_INFO(dev)->gen > 3)
5876                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5877
5878         I915_WRITE(HTOTAL(cpu_transcoder),
5879                    (adjusted_mode->crtc_hdisplay - 1) |
5880                    ((adjusted_mode->crtc_htotal - 1) << 16));
5881         I915_WRITE(HBLANK(cpu_transcoder),
5882                    (adjusted_mode->crtc_hblank_start - 1) |
5883                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5884         I915_WRITE(HSYNC(cpu_transcoder),
5885                    (adjusted_mode->crtc_hsync_start - 1) |
5886                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5887
5888         I915_WRITE(VTOTAL(cpu_transcoder),
5889                    (adjusted_mode->crtc_vdisplay - 1) |
5890                    ((crtc_vtotal - 1) << 16));
5891         I915_WRITE(VBLANK(cpu_transcoder),
5892                    (adjusted_mode->crtc_vblank_start - 1) |
5893                    ((crtc_vblank_end - 1) << 16));
5894         I915_WRITE(VSYNC(cpu_transcoder),
5895                    (adjusted_mode->crtc_vsync_start - 1) |
5896                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5897
5898         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5899          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5900          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5901          * bits. */
5902         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5903             (pipe == PIPE_B || pipe == PIPE_C))
5904                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5905
5906         /* pipesrc controls the size that is scaled from, which should
5907          * always be the user's requested size.
5908          */
5909         I915_WRITE(PIPESRC(pipe),
5910                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5911                    (intel_crtc->config.pipe_src_h - 1));
5912 }
5913
5914 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5915                                    struct intel_crtc_config *pipe_config)
5916 {
5917         struct drm_device *dev = crtc->base.dev;
5918         struct drm_i915_private *dev_priv = dev->dev_private;
5919         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5920         uint32_t tmp;
5921
5922         tmp = I915_READ(HTOTAL(cpu_transcoder));
5923         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5924         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5925         tmp = I915_READ(HBLANK(cpu_transcoder));
5926         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5927         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5928         tmp = I915_READ(HSYNC(cpu_transcoder));
5929         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5930         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5931
5932         tmp = I915_READ(VTOTAL(cpu_transcoder));
5933         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5934         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5935         tmp = I915_READ(VBLANK(cpu_transcoder));
5936         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5937         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5938         tmp = I915_READ(VSYNC(cpu_transcoder));
5939         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5940         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5941
5942         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5943                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5944                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5945                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5946         }
5947
5948         tmp = I915_READ(PIPESRC(crtc->pipe));
5949         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5950         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5951
5952         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5953         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5954 }
5955
5956 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5957                                  struct intel_crtc_config *pipe_config)
5958 {
5959         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5960         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5961         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5962         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5963
5964         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5965         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5966         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5967         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5968
5969         mode->flags = pipe_config->adjusted_mode.flags;
5970
5971         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5972         mode->flags |= pipe_config->adjusted_mode.flags;
5973 }
5974
5975 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5976 {
5977         struct drm_device *dev = intel_crtc->base.dev;
5978         struct drm_i915_private *dev_priv = dev->dev_private;
5979         uint32_t pipeconf;
5980
5981         pipeconf = 0;
5982
5983         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5984             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5985                 pipeconf |= PIPECONF_ENABLE;
5986
5987         if (intel_crtc->config.double_wide)
5988                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5989
5990         /* only g4x and later have fancy bpc/dither controls */
5991         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5992                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5993                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5994                         pipeconf |= PIPECONF_DITHER_EN |
5995                                     PIPECONF_DITHER_TYPE_SP;
5996
5997                 switch (intel_crtc->config.pipe_bpp) {
5998                 case 18:
5999                         pipeconf |= PIPECONF_6BPC;
6000                         break;
6001                 case 24:
6002                         pipeconf |= PIPECONF_8BPC;
6003                         break;
6004                 case 30:
6005                         pipeconf |= PIPECONF_10BPC;
6006                         break;
6007                 default:
6008                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6009                         BUG();
6010                 }
6011         }
6012
6013         if (HAS_PIPE_CXSR(dev)) {
6014                 if (intel_crtc->lowfreq_avail) {
6015                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6016                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6017                 } else {
6018                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6019                 }
6020         }
6021
6022         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6023                 if (INTEL_INFO(dev)->gen < 4 ||
6024                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6025                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6026                 else
6027                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6028         } else
6029                 pipeconf |= PIPECONF_PROGRESSIVE;
6030
6031         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6032                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6033
6034         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6035         POSTING_READ(PIPECONF(intel_crtc->pipe));
6036 }
6037
6038 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6039                               int x, int y,
6040                               struct drm_framebuffer *fb)
6041 {
6042         struct drm_device *dev = crtc->dev;
6043         struct drm_i915_private *dev_priv = dev->dev_private;
6044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045         int refclk, num_connectors = 0;
6046         intel_clock_t clock, reduced_clock;
6047         bool ok, has_reduced_clock = false;
6048         bool is_lvds = false, is_dsi = false;
6049         struct intel_encoder *encoder;
6050         const intel_limit_t *limit;
6051
6052         for_each_encoder_on_crtc(dev, crtc, encoder) {
6053                 switch (encoder->type) {
6054                 case INTEL_OUTPUT_LVDS:
6055                         is_lvds = true;
6056                         break;
6057                 case INTEL_OUTPUT_DSI:
6058                         is_dsi = true;
6059                         break;
6060                 }
6061
6062                 num_connectors++;
6063         }
6064
6065         if (is_dsi)
6066                 return 0;
6067
6068         if (!intel_crtc->config.clock_set) {
6069                 refclk = i9xx_get_refclk(crtc, num_connectors);
6070
6071                 /*
6072                  * Returns a set of divisors for the desired target clock with
6073                  * the given refclk, or FALSE.  The returned values represent
6074                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6075                  * 2) / p1 / p2.
6076                  */
6077                 limit = intel_limit(crtc, refclk);
6078                 ok = dev_priv->display.find_dpll(limit, crtc,
6079                                                  intel_crtc->config.port_clock,
6080                                                  refclk, NULL, &clock);
6081                 if (!ok) {
6082                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6083                         return -EINVAL;
6084                 }
6085
6086                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6087                         /*
6088                          * Ensure we match the reduced clock's P to the target
6089                          * clock.  If the clocks don't match, we can't switch
6090                          * the display clock by using the FP0/FP1. In such case
6091                          * we will disable the LVDS downclock feature.
6092                          */
6093                         has_reduced_clock =
6094                                 dev_priv->display.find_dpll(limit, crtc,
6095                                                             dev_priv->lvds_downclock,
6096                                                             refclk, &clock,
6097                                                             &reduced_clock);
6098                 }
6099                 /* Compat-code for transition, will disappear. */
6100                 intel_crtc->config.dpll.n = clock.n;
6101                 intel_crtc->config.dpll.m1 = clock.m1;
6102                 intel_crtc->config.dpll.m2 = clock.m2;
6103                 intel_crtc->config.dpll.p1 = clock.p1;
6104                 intel_crtc->config.dpll.p2 = clock.p2;
6105         }
6106
6107         if (IS_GEN2(dev)) {
6108                 i8xx_update_pll(intel_crtc,
6109                                 has_reduced_clock ? &reduced_clock : NULL,
6110                                 num_connectors);
6111         } else if (IS_CHERRYVIEW(dev)) {
6112                 chv_update_pll(intel_crtc);
6113         } else if (IS_VALLEYVIEW(dev)) {
6114                 vlv_update_pll(intel_crtc);
6115         } else {
6116                 i9xx_update_pll(intel_crtc,
6117                                 has_reduced_clock ? &reduced_clock : NULL,
6118                                 num_connectors);
6119         }
6120
6121         return 0;
6122 }
6123
6124 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6125                                  struct intel_crtc_config *pipe_config)
6126 {
6127         struct drm_device *dev = crtc->base.dev;
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129         uint32_t tmp;
6130
6131         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6132                 return;
6133
6134         tmp = I915_READ(PFIT_CONTROL);
6135         if (!(tmp & PFIT_ENABLE))
6136                 return;
6137
6138         /* Check whether the pfit is attached to our pipe. */
6139         if (INTEL_INFO(dev)->gen < 4) {
6140                 if (crtc->pipe != PIPE_B)
6141                         return;
6142         } else {
6143                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6144                         return;
6145         }
6146
6147         pipe_config->gmch_pfit.control = tmp;
6148         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6149         if (INTEL_INFO(dev)->gen < 5)
6150                 pipe_config->gmch_pfit.lvds_border_bits =
6151                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6152 }
6153
6154 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6155                                struct intel_crtc_config *pipe_config)
6156 {
6157         struct drm_device *dev = crtc->base.dev;
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159         int pipe = pipe_config->cpu_transcoder;
6160         intel_clock_t clock;
6161         u32 mdiv;
6162         int refclk = 100000;
6163
6164         /* In case of MIPI DPLL will not even be used */
6165         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6166                 return;
6167
6168         mutex_lock(&dev_priv->dpio_lock);
6169         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6170         mutex_unlock(&dev_priv->dpio_lock);
6171
6172         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6173         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6174         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6175         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6176         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6177
6178         vlv_clock(refclk, &clock);
6179
6180         /* clock.dot is the fast clock */
6181         pipe_config->port_clock = clock.dot / 5;
6182 }
6183
6184 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6185                                   struct intel_plane_config *plane_config)
6186 {
6187         struct drm_device *dev = crtc->base.dev;
6188         struct drm_i915_private *dev_priv = dev->dev_private;
6189         u32 val, base, offset;
6190         int pipe = crtc->pipe, plane = crtc->plane;
6191         int fourcc, pixel_format;
6192         int aligned_height;
6193
6194         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6195         if (!crtc->base.primary->fb) {
6196                 DRM_DEBUG_KMS("failed to alloc fb\n");
6197                 return;
6198         }
6199
6200         val = I915_READ(DSPCNTR(plane));
6201
6202         if (INTEL_INFO(dev)->gen >= 4)
6203                 if (val & DISPPLANE_TILED)
6204                         plane_config->tiled = true;
6205
6206         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6207         fourcc = intel_format_to_fourcc(pixel_format);
6208         crtc->base.primary->fb->pixel_format = fourcc;
6209         crtc->base.primary->fb->bits_per_pixel =
6210                 drm_format_plane_cpp(fourcc, 0) * 8;
6211
6212         if (INTEL_INFO(dev)->gen >= 4) {
6213                 if (plane_config->tiled)
6214                         offset = I915_READ(DSPTILEOFF(plane));
6215                 else
6216                         offset = I915_READ(DSPLINOFF(plane));
6217                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6218         } else {
6219                 base = I915_READ(DSPADDR(plane));
6220         }
6221         plane_config->base = base;
6222
6223         val = I915_READ(PIPESRC(pipe));
6224         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6225         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6226
6227         val = I915_READ(DSPSTRIDE(pipe));
6228         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6229
6230         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6231                                             plane_config->tiled);
6232
6233         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6234                                         aligned_height);
6235
6236         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6237                       pipe, plane, crtc->base.primary->fb->width,
6238                       crtc->base.primary->fb->height,
6239                       crtc->base.primary->fb->bits_per_pixel, base,
6240                       crtc->base.primary->fb->pitches[0],
6241                       plane_config->size);
6242
6243 }
6244
6245 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6246                                struct intel_crtc_config *pipe_config)
6247 {
6248         struct drm_device *dev = crtc->base.dev;
6249         struct drm_i915_private *dev_priv = dev->dev_private;
6250         int pipe = pipe_config->cpu_transcoder;
6251         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6252         intel_clock_t clock;
6253         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6254         int refclk = 100000;
6255
6256         mutex_lock(&dev_priv->dpio_lock);
6257         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6258         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6259         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6260         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6261         mutex_unlock(&dev_priv->dpio_lock);
6262
6263         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6264         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6265         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6266         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6267         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6268
6269         chv_clock(refclk, &clock);
6270
6271         /* clock.dot is the fast clock */
6272         pipe_config->port_clock = clock.dot / 5;
6273 }
6274
6275 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6276                                  struct intel_crtc_config *pipe_config)
6277 {
6278         struct drm_device *dev = crtc->base.dev;
6279         struct drm_i915_private *dev_priv = dev->dev_private;
6280         uint32_t tmp;
6281
6282         if (!intel_display_power_enabled(dev_priv,
6283                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6284                 return false;
6285
6286         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6287         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6288
6289         tmp = I915_READ(PIPECONF(crtc->pipe));
6290         if (!(tmp & PIPECONF_ENABLE))
6291                 return false;
6292
6293         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6294                 switch (tmp & PIPECONF_BPC_MASK) {
6295                 case PIPECONF_6BPC:
6296                         pipe_config->pipe_bpp = 18;
6297                         break;
6298                 case PIPECONF_8BPC:
6299                         pipe_config->pipe_bpp = 24;
6300                         break;
6301                 case PIPECONF_10BPC:
6302                         pipe_config->pipe_bpp = 30;
6303                         break;
6304                 default:
6305                         break;
6306                 }
6307         }
6308
6309         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6310                 pipe_config->limited_color_range = true;
6311
6312         if (INTEL_INFO(dev)->gen < 4)
6313                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6314
6315         intel_get_pipe_timings(crtc, pipe_config);
6316
6317         i9xx_get_pfit_config(crtc, pipe_config);
6318
6319         if (INTEL_INFO(dev)->gen >= 4) {
6320                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6321                 pipe_config->pixel_multiplier =
6322                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6323                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6324                 pipe_config->dpll_hw_state.dpll_md = tmp;
6325         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6326                 tmp = I915_READ(DPLL(crtc->pipe));
6327                 pipe_config->pixel_multiplier =
6328                         ((tmp & SDVO_MULTIPLIER_MASK)
6329                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6330         } else {
6331                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6332                  * port and will be fixed up in the encoder->get_config
6333                  * function. */
6334                 pipe_config->pixel_multiplier = 1;
6335         }
6336         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6337         if (!IS_VALLEYVIEW(dev)) {
6338                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6339                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6340         } else {
6341                 /* Mask out read-only status bits. */
6342                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6343                                                      DPLL_PORTC_READY_MASK |
6344                                                      DPLL_PORTB_READY_MASK);
6345         }
6346
6347         if (IS_CHERRYVIEW(dev))
6348                 chv_crtc_clock_get(crtc, pipe_config);
6349         else if (IS_VALLEYVIEW(dev))
6350                 vlv_crtc_clock_get(crtc, pipe_config);
6351         else
6352                 i9xx_crtc_clock_get(crtc, pipe_config);
6353
6354         return true;
6355 }
6356
6357 static void ironlake_init_pch_refclk(struct drm_device *dev)
6358 {
6359         struct drm_i915_private *dev_priv = dev->dev_private;
6360         struct intel_encoder *encoder;
6361         u32 val, final;
6362         bool has_lvds = false;
6363         bool has_cpu_edp = false;
6364         bool has_panel = false;
6365         bool has_ck505 = false;
6366         bool can_ssc = false;
6367
6368         /* We need to take the global config into account */
6369         for_each_intel_encoder(dev, encoder) {
6370                 switch (encoder->type) {
6371                 case INTEL_OUTPUT_LVDS:
6372                         has_panel = true;
6373                         has_lvds = true;
6374                         break;
6375                 case INTEL_OUTPUT_EDP:
6376                         has_panel = true;
6377                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6378                                 has_cpu_edp = true;
6379                         break;
6380                 }
6381         }
6382
6383         if (HAS_PCH_IBX(dev)) {
6384                 has_ck505 = dev_priv->vbt.display_clock_mode;
6385                 can_ssc = has_ck505;
6386         } else {
6387                 has_ck505 = false;
6388                 can_ssc = true;
6389         }
6390
6391         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6392                       has_panel, has_lvds, has_ck505);
6393
6394         /* Ironlake: try to setup display ref clock before DPLL
6395          * enabling. This is only under driver's control after
6396          * PCH B stepping, previous chipset stepping should be
6397          * ignoring this setting.
6398          */
6399         val = I915_READ(PCH_DREF_CONTROL);
6400
6401         /* As we must carefully and slowly disable/enable each source in turn,
6402          * compute the final state we want first and check if we need to
6403          * make any changes at all.
6404          */
6405         final = val;
6406         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6407         if (has_ck505)
6408                 final |= DREF_NONSPREAD_CK505_ENABLE;
6409         else
6410                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6411
6412         final &= ~DREF_SSC_SOURCE_MASK;
6413         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6414         final &= ~DREF_SSC1_ENABLE;
6415
6416         if (has_panel) {
6417                 final |= DREF_SSC_SOURCE_ENABLE;
6418
6419                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6420                         final |= DREF_SSC1_ENABLE;
6421
6422                 if (has_cpu_edp) {
6423                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6424                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6425                         else
6426                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6427                 } else
6428                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6429         } else {
6430                 final |= DREF_SSC_SOURCE_DISABLE;
6431                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6432         }
6433
6434         if (final == val)
6435                 return;
6436
6437         /* Always enable nonspread source */
6438         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6439
6440         if (has_ck505)
6441                 val |= DREF_NONSPREAD_CK505_ENABLE;
6442         else
6443                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6444
6445         if (has_panel) {
6446                 val &= ~DREF_SSC_SOURCE_MASK;
6447                 val |= DREF_SSC_SOURCE_ENABLE;
6448
6449                 /* SSC must be turned on before enabling the CPU output  */
6450                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6451                         DRM_DEBUG_KMS("Using SSC on panel\n");
6452                         val |= DREF_SSC1_ENABLE;
6453                 } else
6454                         val &= ~DREF_SSC1_ENABLE;
6455
6456                 /* Get SSC going before enabling the outputs */
6457                 I915_WRITE(PCH_DREF_CONTROL, val);
6458                 POSTING_READ(PCH_DREF_CONTROL);
6459                 udelay(200);
6460
6461                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6462
6463                 /* Enable CPU source on CPU attached eDP */
6464                 if (has_cpu_edp) {
6465                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6466                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6467                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6468                         } else
6469                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6470                 } else
6471                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6472
6473                 I915_WRITE(PCH_DREF_CONTROL, val);
6474                 POSTING_READ(PCH_DREF_CONTROL);
6475                 udelay(200);
6476         } else {
6477                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6478
6479                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6480
6481                 /* Turn off CPU output */
6482                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6483
6484                 I915_WRITE(PCH_DREF_CONTROL, val);
6485                 POSTING_READ(PCH_DREF_CONTROL);
6486                 udelay(200);
6487
6488                 /* Turn off the SSC source */
6489                 val &= ~DREF_SSC_SOURCE_MASK;
6490                 val |= DREF_SSC_SOURCE_DISABLE;
6491
6492                 /* Turn off SSC1 */
6493                 val &= ~DREF_SSC1_ENABLE;
6494
6495                 I915_WRITE(PCH_DREF_CONTROL, val);
6496                 POSTING_READ(PCH_DREF_CONTROL);
6497                 udelay(200);
6498         }
6499
6500         BUG_ON(val != final);
6501 }
6502
6503 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6504 {
6505         uint32_t tmp;
6506
6507         tmp = I915_READ(SOUTH_CHICKEN2);
6508         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6509         I915_WRITE(SOUTH_CHICKEN2, tmp);
6510
6511         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6512                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6513                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6514
6515         tmp = I915_READ(SOUTH_CHICKEN2);
6516         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6517         I915_WRITE(SOUTH_CHICKEN2, tmp);
6518
6519         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6520                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6521                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6522 }
6523
6524 /* WaMPhyProgramming:hsw */
6525 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6526 {
6527         uint32_t tmp;
6528
6529         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6530         tmp &= ~(0xFF << 24);
6531         tmp |= (0x12 << 24);
6532         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6533
6534         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6535         tmp |= (1 << 11);
6536         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6537
6538         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6539         tmp |= (1 << 11);
6540         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6541
6542         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6543         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6544         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6545
6546         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6547         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6548         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6549
6550         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6551         tmp &= ~(7 << 13);
6552         tmp |= (5 << 13);
6553         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6554
6555         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6556         tmp &= ~(7 << 13);
6557         tmp |= (5 << 13);
6558         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6559
6560         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6561         tmp &= ~0xFF;
6562         tmp |= 0x1C;
6563         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6564
6565         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6566         tmp &= ~0xFF;
6567         tmp |= 0x1C;
6568         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6569
6570         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6571         tmp &= ~(0xFF << 16);
6572         tmp |= (0x1C << 16);
6573         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6574
6575         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6576         tmp &= ~(0xFF << 16);
6577         tmp |= (0x1C << 16);
6578         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6579
6580         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6581         tmp |= (1 << 27);
6582         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6583
6584         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6585         tmp |= (1 << 27);
6586         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6587
6588         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6589         tmp &= ~(0xF << 28);
6590         tmp |= (4 << 28);
6591         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6592
6593         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6594         tmp &= ~(0xF << 28);
6595         tmp |= (4 << 28);
6596         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6597 }
6598
6599 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6600  * Programming" based on the parameters passed:
6601  * - Sequence to enable CLKOUT_DP
6602  * - Sequence to enable CLKOUT_DP without spread
6603  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6604  */
6605 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6606                                  bool with_fdi)
6607 {
6608         struct drm_i915_private *dev_priv = dev->dev_private;
6609         uint32_t reg, tmp;
6610
6611         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6612                 with_spread = true;
6613         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6614                  with_fdi, "LP PCH doesn't have FDI\n"))
6615                 with_fdi = false;
6616
6617         mutex_lock(&dev_priv->dpio_lock);
6618
6619         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6620         tmp &= ~SBI_SSCCTL_DISABLE;
6621         tmp |= SBI_SSCCTL_PATHALT;
6622         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6623
6624         udelay(24);
6625
6626         if (with_spread) {
6627                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6628                 tmp &= ~SBI_SSCCTL_PATHALT;
6629                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6630
6631                 if (with_fdi) {
6632                         lpt_reset_fdi_mphy(dev_priv);
6633                         lpt_program_fdi_mphy(dev_priv);
6634                 }
6635         }
6636
6637         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6638                SBI_GEN0 : SBI_DBUFF0;
6639         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6640         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6641         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6642
6643         mutex_unlock(&dev_priv->dpio_lock);
6644 }
6645
6646 /* Sequence to disable CLKOUT_DP */
6647 static void lpt_disable_clkout_dp(struct drm_device *dev)
6648 {
6649         struct drm_i915_private *dev_priv = dev->dev_private;
6650         uint32_t reg, tmp;
6651
6652         mutex_lock(&dev_priv->dpio_lock);
6653
6654         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6655                SBI_GEN0 : SBI_DBUFF0;
6656         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6657         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6658         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6659
6660         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6661         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6662                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6663                         tmp |= SBI_SSCCTL_PATHALT;
6664                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6665                         udelay(32);
6666                 }
6667                 tmp |= SBI_SSCCTL_DISABLE;
6668                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6669         }
6670
6671         mutex_unlock(&dev_priv->dpio_lock);
6672 }
6673
6674 static void lpt_init_pch_refclk(struct drm_device *dev)
6675 {
6676         struct intel_encoder *encoder;
6677         bool has_vga = false;
6678
6679         for_each_intel_encoder(dev, encoder) {
6680                 switch (encoder->type) {
6681                 case INTEL_OUTPUT_ANALOG:
6682                         has_vga = true;
6683                         break;
6684                 }
6685         }
6686
6687         if (has_vga)
6688                 lpt_enable_clkout_dp(dev, true, true);
6689         else
6690                 lpt_disable_clkout_dp(dev);
6691 }
6692
6693 /*
6694  * Initialize reference clocks when the driver loads
6695  */
6696 void intel_init_pch_refclk(struct drm_device *dev)
6697 {
6698         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6699                 ironlake_init_pch_refclk(dev);
6700         else if (HAS_PCH_LPT(dev))
6701                 lpt_init_pch_refclk(dev);
6702 }
6703
6704 static int ironlake_get_refclk(struct drm_crtc *crtc)
6705 {
6706         struct drm_device *dev = crtc->dev;
6707         struct drm_i915_private *dev_priv = dev->dev_private;
6708         struct intel_encoder *encoder;
6709         int num_connectors = 0;
6710         bool is_lvds = false;
6711
6712         for_each_encoder_on_crtc(dev, crtc, encoder) {
6713                 switch (encoder->type) {
6714                 case INTEL_OUTPUT_LVDS:
6715                         is_lvds = true;
6716                         break;
6717                 }
6718                 num_connectors++;
6719         }
6720
6721         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6722                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6723                               dev_priv->vbt.lvds_ssc_freq);
6724                 return dev_priv->vbt.lvds_ssc_freq;
6725         }
6726
6727         return 120000;
6728 }
6729
6730 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6731 {
6732         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6734         int pipe = intel_crtc->pipe;
6735         uint32_t val;
6736
6737         val = 0;
6738
6739         switch (intel_crtc->config.pipe_bpp) {
6740         case 18:
6741                 val |= PIPECONF_6BPC;
6742                 break;
6743         case 24:
6744                 val |= PIPECONF_8BPC;
6745                 break;
6746         case 30:
6747                 val |= PIPECONF_10BPC;
6748                 break;
6749         case 36:
6750                 val |= PIPECONF_12BPC;
6751                 break;
6752         default:
6753                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6754                 BUG();
6755         }
6756
6757         if (intel_crtc->config.dither)
6758                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6759
6760         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6761                 val |= PIPECONF_INTERLACED_ILK;
6762         else
6763                 val |= PIPECONF_PROGRESSIVE;
6764
6765         if (intel_crtc->config.limited_color_range)
6766                 val |= PIPECONF_COLOR_RANGE_SELECT;
6767
6768         I915_WRITE(PIPECONF(pipe), val);
6769         POSTING_READ(PIPECONF(pipe));
6770 }
6771
6772 /*
6773  * Set up the pipe CSC unit.
6774  *
6775  * Currently only full range RGB to limited range RGB conversion
6776  * is supported, but eventually this should handle various
6777  * RGB<->YCbCr scenarios as well.
6778  */
6779 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6780 {
6781         struct drm_device *dev = crtc->dev;
6782         struct drm_i915_private *dev_priv = dev->dev_private;
6783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784         int pipe = intel_crtc->pipe;
6785         uint16_t coeff = 0x7800; /* 1.0 */
6786
6787         /*
6788          * TODO: Check what kind of values actually come out of the pipe
6789          * with these coeff/postoff values and adjust to get the best
6790          * accuracy. Perhaps we even need to take the bpc value into
6791          * consideration.
6792          */
6793
6794         if (intel_crtc->config.limited_color_range)
6795                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6796
6797         /*
6798          * GY/GU and RY/RU should be the other way around according
6799          * to BSpec, but reality doesn't agree. Just set them up in
6800          * a way that results in the correct picture.
6801          */
6802         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6803         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6804
6805         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6806         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6807
6808         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6809         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6810
6811         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6812         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6813         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6814
6815         if (INTEL_INFO(dev)->gen > 6) {
6816                 uint16_t postoff = 0;
6817
6818                 if (intel_crtc->config.limited_color_range)
6819                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6820
6821                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6822                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6823                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6824
6825                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6826         } else {
6827                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6828
6829                 if (intel_crtc->config.limited_color_range)
6830                         mode |= CSC_BLACK_SCREEN_OFFSET;
6831
6832                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6833         }
6834 }
6835
6836 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6837 {
6838         struct drm_device *dev = crtc->dev;
6839         struct drm_i915_private *dev_priv = dev->dev_private;
6840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6841         enum pipe pipe = intel_crtc->pipe;
6842         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6843         uint32_t val;
6844
6845         val = 0;
6846
6847         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6848                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6849
6850         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6851                 val |= PIPECONF_INTERLACED_ILK;
6852         else
6853                 val |= PIPECONF_PROGRESSIVE;
6854
6855         I915_WRITE(PIPECONF(cpu_transcoder), val);
6856         POSTING_READ(PIPECONF(cpu_transcoder));
6857
6858         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6859         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6860
6861         if (IS_BROADWELL(dev)) {
6862                 val = 0;
6863
6864                 switch (intel_crtc->config.pipe_bpp) {
6865                 case 18:
6866                         val |= PIPEMISC_DITHER_6_BPC;
6867                         break;
6868                 case 24:
6869                         val |= PIPEMISC_DITHER_8_BPC;
6870                         break;
6871                 case 30:
6872                         val |= PIPEMISC_DITHER_10_BPC;
6873                         break;
6874                 case 36:
6875                         val |= PIPEMISC_DITHER_12_BPC;
6876                         break;
6877                 default:
6878                         /* Case prevented by pipe_config_set_bpp. */
6879                         BUG();
6880                 }
6881
6882                 if (intel_crtc->config.dither)
6883                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6884
6885                 I915_WRITE(PIPEMISC(pipe), val);
6886         }
6887 }
6888
6889 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6890                                     intel_clock_t *clock,
6891                                     bool *has_reduced_clock,
6892                                     intel_clock_t *reduced_clock)
6893 {
6894         struct drm_device *dev = crtc->dev;
6895         struct drm_i915_private *dev_priv = dev->dev_private;
6896         struct intel_encoder *intel_encoder;
6897         int refclk;
6898         const intel_limit_t *limit;
6899         bool ret, is_lvds = false;
6900
6901         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6902                 switch (intel_encoder->type) {
6903                 case INTEL_OUTPUT_LVDS:
6904                         is_lvds = true;
6905                         break;
6906                 }
6907         }
6908
6909         refclk = ironlake_get_refclk(crtc);
6910
6911         /*
6912          * Returns a set of divisors for the desired target clock with the given
6913          * refclk, or FALSE.  The returned values represent the clock equation:
6914          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6915          */
6916         limit = intel_limit(crtc, refclk);
6917         ret = dev_priv->display.find_dpll(limit, crtc,
6918                                           to_intel_crtc(crtc)->config.port_clock,
6919                                           refclk, NULL, clock);
6920         if (!ret)
6921                 return false;
6922
6923         if (is_lvds && dev_priv->lvds_downclock_avail) {
6924                 /*
6925                  * Ensure we match the reduced clock's P to the target clock.
6926                  * If the clocks don't match, we can't switch the display clock
6927                  * by using the FP0/FP1. In such case we will disable the LVDS
6928                  * downclock feature.
6929                 */
6930                 *has_reduced_clock =
6931                         dev_priv->display.find_dpll(limit, crtc,
6932                                                     dev_priv->lvds_downclock,
6933                                                     refclk, clock,
6934                                                     reduced_clock);
6935         }
6936
6937         return true;
6938 }
6939
6940 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6941 {
6942         /*
6943          * Account for spread spectrum to avoid
6944          * oversubscribing the link. Max center spread
6945          * is 2.5%; use 5% for safety's sake.
6946          */
6947         u32 bps = target_clock * bpp * 21 / 20;
6948         return DIV_ROUND_UP(bps, link_bw * 8);
6949 }
6950
6951 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6952 {
6953         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6954 }
6955
6956 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6957                                       u32 *fp,
6958                                       intel_clock_t *reduced_clock, u32 *fp2)
6959 {
6960         struct drm_crtc *crtc = &intel_crtc->base;
6961         struct drm_device *dev = crtc->dev;
6962         struct drm_i915_private *dev_priv = dev->dev_private;
6963         struct intel_encoder *intel_encoder;
6964         uint32_t dpll;
6965         int factor, num_connectors = 0;
6966         bool is_lvds = false, is_sdvo = false;
6967
6968         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6969                 switch (intel_encoder->type) {
6970                 case INTEL_OUTPUT_LVDS:
6971                         is_lvds = true;
6972                         break;
6973                 case INTEL_OUTPUT_SDVO:
6974                 case INTEL_OUTPUT_HDMI:
6975                         is_sdvo = true;
6976                         break;
6977                 }
6978
6979                 num_connectors++;
6980         }
6981
6982         /* Enable autotuning of the PLL clock (if permissible) */
6983         factor = 21;
6984         if (is_lvds) {
6985                 if ((intel_panel_use_ssc(dev_priv) &&
6986                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6987                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6988                         factor = 25;
6989         } else if (intel_crtc->config.sdvo_tv_clock)
6990                 factor = 20;
6991
6992         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6993                 *fp |= FP_CB_TUNE;
6994
6995         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6996                 *fp2 |= FP_CB_TUNE;
6997
6998         dpll = 0;
6999
7000         if (is_lvds)
7001                 dpll |= DPLLB_MODE_LVDS;
7002         else
7003                 dpll |= DPLLB_MODE_DAC_SERIAL;
7004
7005         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7006                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7007
7008         if (is_sdvo)
7009                 dpll |= DPLL_SDVO_HIGH_SPEED;
7010         if (intel_crtc->config.has_dp_encoder)
7011                 dpll |= DPLL_SDVO_HIGH_SPEED;
7012
7013         /* compute bitmask from p1 value */
7014         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7015         /* also FPA1 */
7016         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7017
7018         switch (intel_crtc->config.dpll.p2) {
7019         case 5:
7020                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7021                 break;
7022         case 7:
7023                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7024                 break;
7025         case 10:
7026                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7027                 break;
7028         case 14:
7029                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7030                 break;
7031         }
7032
7033         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7034                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7035         else
7036                 dpll |= PLL_REF_INPUT_DREFCLK;
7037
7038         return dpll | DPLL_VCO_ENABLE;
7039 }
7040
7041 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7042                                   int x, int y,
7043                                   struct drm_framebuffer *fb)
7044 {
7045         struct drm_device *dev = crtc->dev;
7046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047         int num_connectors = 0;
7048         intel_clock_t clock, reduced_clock;
7049         u32 dpll = 0, fp = 0, fp2 = 0;
7050         bool ok, has_reduced_clock = false;
7051         bool is_lvds = false;
7052         struct intel_encoder *encoder;
7053         struct intel_shared_dpll *pll;
7054
7055         for_each_encoder_on_crtc(dev, crtc, encoder) {
7056                 switch (encoder->type) {
7057                 case INTEL_OUTPUT_LVDS:
7058                         is_lvds = true;
7059                         break;
7060                 }
7061
7062                 num_connectors++;
7063         }
7064
7065         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7066              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7067
7068         ok = ironlake_compute_clocks(crtc, &clock,
7069                                      &has_reduced_clock, &reduced_clock);
7070         if (!ok && !intel_crtc->config.clock_set) {
7071                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7072                 return -EINVAL;
7073         }
7074         /* Compat-code for transition, will disappear. */
7075         if (!intel_crtc->config.clock_set) {
7076                 intel_crtc->config.dpll.n = clock.n;
7077                 intel_crtc->config.dpll.m1 = clock.m1;
7078                 intel_crtc->config.dpll.m2 = clock.m2;
7079                 intel_crtc->config.dpll.p1 = clock.p1;
7080                 intel_crtc->config.dpll.p2 = clock.p2;
7081         }
7082
7083         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7084         if (intel_crtc->config.has_pch_encoder) {
7085                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7086                 if (has_reduced_clock)
7087                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7088
7089                 dpll = ironlake_compute_dpll(intel_crtc,
7090                                              &fp, &reduced_clock,
7091                                              has_reduced_clock ? &fp2 : NULL);
7092
7093                 intel_crtc->config.dpll_hw_state.dpll = dpll;
7094                 intel_crtc->config.dpll_hw_state.fp0 = fp;
7095                 if (has_reduced_clock)
7096                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
7097                 else
7098                         intel_crtc->config.dpll_hw_state.fp1 = fp;
7099
7100                 pll = intel_get_shared_dpll(intel_crtc);
7101                 if (pll == NULL) {
7102                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7103                                          pipe_name(intel_crtc->pipe));
7104                         return -EINVAL;
7105                 }
7106         } else
7107                 intel_put_shared_dpll(intel_crtc);
7108
7109         if (is_lvds && has_reduced_clock && i915.powersave)
7110                 intel_crtc->lowfreq_avail = true;
7111         else
7112                 intel_crtc->lowfreq_avail = false;
7113
7114         return 0;
7115 }
7116
7117 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7118                                          struct intel_link_m_n *m_n)
7119 {
7120         struct drm_device *dev = crtc->base.dev;
7121         struct drm_i915_private *dev_priv = dev->dev_private;
7122         enum pipe pipe = crtc->pipe;
7123
7124         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7125         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7126         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7127                 & ~TU_SIZE_MASK;
7128         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7129         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7130                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7131 }
7132
7133 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7134                                          enum transcoder transcoder,
7135                                          struct intel_link_m_n *m_n,
7136                                          struct intel_link_m_n *m2_n2)
7137 {
7138         struct drm_device *dev = crtc->base.dev;
7139         struct drm_i915_private *dev_priv = dev->dev_private;
7140         enum pipe pipe = crtc->pipe;
7141
7142         if (INTEL_INFO(dev)->gen >= 5) {
7143                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7144                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7145                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7146                         & ~TU_SIZE_MASK;
7147                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7148                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7149                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7150                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7151                  * gen < 8) and if DRRS is supported (to make sure the
7152                  * registers are not unnecessarily read).
7153                  */
7154                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7155                         crtc->config.has_drrs) {
7156                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7157                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7158                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7159                                         & ~TU_SIZE_MASK;
7160                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7161                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7162                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7163                 }
7164         } else {
7165                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7166                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7167                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7168                         & ~TU_SIZE_MASK;
7169                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7170                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7171                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7172         }
7173 }
7174
7175 void intel_dp_get_m_n(struct intel_crtc *crtc,
7176                       struct intel_crtc_config *pipe_config)
7177 {
7178         if (crtc->config.has_pch_encoder)
7179                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7180         else
7181                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7182                                              &pipe_config->dp_m_n,
7183                                              &pipe_config->dp_m2_n2);
7184 }
7185
7186 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7187                                         struct intel_crtc_config *pipe_config)
7188 {
7189         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7190                                      &pipe_config->fdi_m_n, NULL);
7191 }
7192
7193 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7194                                      struct intel_crtc_config *pipe_config)
7195 {
7196         struct drm_device *dev = crtc->base.dev;
7197         struct drm_i915_private *dev_priv = dev->dev_private;
7198         uint32_t tmp;
7199
7200         tmp = I915_READ(PF_CTL(crtc->pipe));
7201
7202         if (tmp & PF_ENABLE) {
7203                 pipe_config->pch_pfit.enabled = true;
7204                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7205                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7206
7207                 /* We currently do not free assignements of panel fitters on
7208                  * ivb/hsw (since we don't use the higher upscaling modes which
7209                  * differentiates them) so just WARN about this case for now. */
7210                 if (IS_GEN7(dev)) {
7211                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7212                                 PF_PIPE_SEL_IVB(crtc->pipe));
7213                 }
7214         }
7215 }
7216
7217 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7218                                       struct intel_plane_config *plane_config)
7219 {
7220         struct drm_device *dev = crtc->base.dev;
7221         struct drm_i915_private *dev_priv = dev->dev_private;
7222         u32 val, base, offset;
7223         int pipe = crtc->pipe, plane = crtc->plane;
7224         int fourcc, pixel_format;
7225         int aligned_height;
7226
7227         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7228         if (!crtc->base.primary->fb) {
7229                 DRM_DEBUG_KMS("failed to alloc fb\n");
7230                 return;
7231         }
7232
7233         val = I915_READ(DSPCNTR(plane));
7234
7235         if (INTEL_INFO(dev)->gen >= 4)
7236                 if (val & DISPPLANE_TILED)
7237                         plane_config->tiled = true;
7238
7239         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7240         fourcc = intel_format_to_fourcc(pixel_format);
7241         crtc->base.primary->fb->pixel_format = fourcc;
7242         crtc->base.primary->fb->bits_per_pixel =
7243                 drm_format_plane_cpp(fourcc, 0) * 8;
7244
7245         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7246         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7247                 offset = I915_READ(DSPOFFSET(plane));
7248         } else {
7249                 if (plane_config->tiled)
7250                         offset = I915_READ(DSPTILEOFF(plane));
7251                 else
7252                         offset = I915_READ(DSPLINOFF(plane));
7253         }
7254         plane_config->base = base;
7255
7256         val = I915_READ(PIPESRC(pipe));
7257         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7258         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7259
7260         val = I915_READ(DSPSTRIDE(pipe));
7261         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7262
7263         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7264                                             plane_config->tiled);
7265
7266         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7267                                         aligned_height);
7268
7269         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7270                       pipe, plane, crtc->base.primary->fb->width,
7271                       crtc->base.primary->fb->height,
7272                       crtc->base.primary->fb->bits_per_pixel, base,
7273                       crtc->base.primary->fb->pitches[0],
7274                       plane_config->size);
7275 }
7276
7277 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7278                                      struct intel_crtc_config *pipe_config)
7279 {
7280         struct drm_device *dev = crtc->base.dev;
7281         struct drm_i915_private *dev_priv = dev->dev_private;
7282         uint32_t tmp;
7283
7284         if (!intel_display_power_enabled(dev_priv,
7285                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7286                 return false;
7287
7288         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7289         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7290
7291         tmp = I915_READ(PIPECONF(crtc->pipe));
7292         if (!(tmp & PIPECONF_ENABLE))
7293                 return false;
7294
7295         switch (tmp & PIPECONF_BPC_MASK) {
7296         case PIPECONF_6BPC:
7297                 pipe_config->pipe_bpp = 18;
7298                 break;
7299         case PIPECONF_8BPC:
7300                 pipe_config->pipe_bpp = 24;
7301                 break;
7302         case PIPECONF_10BPC:
7303                 pipe_config->pipe_bpp = 30;
7304                 break;
7305         case PIPECONF_12BPC:
7306                 pipe_config->pipe_bpp = 36;
7307                 break;
7308         default:
7309                 break;
7310         }
7311
7312         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7313                 pipe_config->limited_color_range = true;
7314
7315         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7316                 struct intel_shared_dpll *pll;
7317
7318                 pipe_config->has_pch_encoder = true;
7319
7320                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7321                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7322                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7323
7324                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7325
7326                 if (HAS_PCH_IBX(dev_priv->dev)) {
7327                         pipe_config->shared_dpll =
7328                                 (enum intel_dpll_id) crtc->pipe;
7329                 } else {
7330                         tmp = I915_READ(PCH_DPLL_SEL);
7331                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7332                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7333                         else
7334                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7335                 }
7336
7337                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7338
7339                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7340                                            &pipe_config->dpll_hw_state));
7341
7342                 tmp = pipe_config->dpll_hw_state.dpll;
7343                 pipe_config->pixel_multiplier =
7344                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7345                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7346
7347                 ironlake_pch_clock_get(crtc, pipe_config);
7348         } else {
7349                 pipe_config->pixel_multiplier = 1;
7350         }
7351
7352         intel_get_pipe_timings(crtc, pipe_config);
7353
7354         ironlake_get_pfit_config(crtc, pipe_config);
7355
7356         return true;
7357 }
7358
7359 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7360 {
7361         struct drm_device *dev = dev_priv->dev;
7362         struct intel_crtc *crtc;
7363
7364         for_each_intel_crtc(dev, crtc)
7365                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7366                      pipe_name(crtc->pipe));
7367
7368         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7369         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7370         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7371         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7372         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7373         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7374              "CPU PWM1 enabled\n");
7375         if (IS_HASWELL(dev))
7376                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7377                      "CPU PWM2 enabled\n");
7378         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7379              "PCH PWM1 enabled\n");
7380         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7381              "Utility pin enabled\n");
7382         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7383
7384         /*
7385          * In theory we can still leave IRQs enabled, as long as only the HPD
7386          * interrupts remain enabled. We used to check for that, but since it's
7387          * gen-specific and since we only disable LCPLL after we fully disable
7388          * the interrupts, the check below should be enough.
7389          */
7390         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7391 }
7392
7393 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7394 {
7395         struct drm_device *dev = dev_priv->dev;
7396
7397         if (IS_HASWELL(dev))
7398                 return I915_READ(D_COMP_HSW);
7399         else
7400                 return I915_READ(D_COMP_BDW);
7401 }
7402
7403 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7404 {
7405         struct drm_device *dev = dev_priv->dev;
7406
7407         if (IS_HASWELL(dev)) {
7408                 mutex_lock(&dev_priv->rps.hw_lock);
7409                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7410                                             val))
7411                         DRM_ERROR("Failed to write to D_COMP\n");
7412                 mutex_unlock(&dev_priv->rps.hw_lock);
7413         } else {
7414                 I915_WRITE(D_COMP_BDW, val);
7415                 POSTING_READ(D_COMP_BDW);
7416         }
7417 }
7418
7419 /*
7420  * This function implements pieces of two sequences from BSpec:
7421  * - Sequence for display software to disable LCPLL
7422  * - Sequence for display software to allow package C8+
7423  * The steps implemented here are just the steps that actually touch the LCPLL
7424  * register. Callers should take care of disabling all the display engine
7425  * functions, doing the mode unset, fixing interrupts, etc.
7426  */
7427 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7428                               bool switch_to_fclk, bool allow_power_down)
7429 {
7430         uint32_t val;
7431
7432         assert_can_disable_lcpll(dev_priv);
7433
7434         val = I915_READ(LCPLL_CTL);
7435
7436         if (switch_to_fclk) {
7437                 val |= LCPLL_CD_SOURCE_FCLK;
7438                 I915_WRITE(LCPLL_CTL, val);
7439
7440                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7441                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7442                         DRM_ERROR("Switching to FCLK failed\n");
7443
7444                 val = I915_READ(LCPLL_CTL);
7445         }
7446
7447         val |= LCPLL_PLL_DISABLE;
7448         I915_WRITE(LCPLL_CTL, val);
7449         POSTING_READ(LCPLL_CTL);
7450
7451         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7452                 DRM_ERROR("LCPLL still locked\n");
7453
7454         val = hsw_read_dcomp(dev_priv);
7455         val |= D_COMP_COMP_DISABLE;
7456         hsw_write_dcomp(dev_priv, val);
7457         ndelay(100);
7458
7459         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7460                      1))
7461                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7462
7463         if (allow_power_down) {
7464                 val = I915_READ(LCPLL_CTL);
7465                 val |= LCPLL_POWER_DOWN_ALLOW;
7466                 I915_WRITE(LCPLL_CTL, val);
7467                 POSTING_READ(LCPLL_CTL);
7468         }
7469 }
7470
7471 /*
7472  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7473  * source.
7474  */
7475 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7476 {
7477         uint32_t val;
7478         unsigned long irqflags;
7479
7480         val = I915_READ(LCPLL_CTL);
7481
7482         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7483                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7484                 return;
7485
7486         /*
7487          * Make sure we're not on PC8 state before disabling PC8, otherwise
7488          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7489          *
7490          * The other problem is that hsw_restore_lcpll() is called as part of
7491          * the runtime PM resume sequence, so we can't just call
7492          * gen6_gt_force_wake_get() because that function calls
7493          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7494          * while we are on the resume sequence. So to solve this problem we have
7495          * to call special forcewake code that doesn't touch runtime PM and
7496          * doesn't enable the forcewake delayed work.
7497          */
7498         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7499         if (dev_priv->uncore.forcewake_count++ == 0)
7500                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7501         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7502
7503         if (val & LCPLL_POWER_DOWN_ALLOW) {
7504                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7505                 I915_WRITE(LCPLL_CTL, val);
7506                 POSTING_READ(LCPLL_CTL);
7507         }
7508
7509         val = hsw_read_dcomp(dev_priv);
7510         val |= D_COMP_COMP_FORCE;
7511         val &= ~D_COMP_COMP_DISABLE;
7512         hsw_write_dcomp(dev_priv, val);
7513
7514         val = I915_READ(LCPLL_CTL);
7515         val &= ~LCPLL_PLL_DISABLE;
7516         I915_WRITE(LCPLL_CTL, val);
7517
7518         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7519                 DRM_ERROR("LCPLL not locked yet\n");
7520
7521         if (val & LCPLL_CD_SOURCE_FCLK) {
7522                 val = I915_READ(LCPLL_CTL);
7523                 val &= ~LCPLL_CD_SOURCE_FCLK;
7524                 I915_WRITE(LCPLL_CTL, val);
7525
7526                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7527                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7528                         DRM_ERROR("Switching back to LCPLL failed\n");
7529         }
7530
7531         /* See the big comment above. */
7532         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7533         if (--dev_priv->uncore.forcewake_count == 0)
7534                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7535         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7536 }
7537
7538 /*
7539  * Package states C8 and deeper are really deep PC states that can only be
7540  * reached when all the devices on the system allow it, so even if the graphics
7541  * device allows PC8+, it doesn't mean the system will actually get to these
7542  * states. Our driver only allows PC8+ when going into runtime PM.
7543  *
7544  * The requirements for PC8+ are that all the outputs are disabled, the power
7545  * well is disabled and most interrupts are disabled, and these are also
7546  * requirements for runtime PM. When these conditions are met, we manually do
7547  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7548  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7549  * hang the machine.
7550  *
7551  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7552  * the state of some registers, so when we come back from PC8+ we need to
7553  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7554  * need to take care of the registers kept by RC6. Notice that this happens even
7555  * if we don't put the device in PCI D3 state (which is what currently happens
7556  * because of the runtime PM support).
7557  *
7558  * For more, read "Display Sequences for Package C8" on the hardware
7559  * documentation.
7560  */
7561 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7562 {
7563         struct drm_device *dev = dev_priv->dev;
7564         uint32_t val;
7565
7566         DRM_DEBUG_KMS("Enabling package C8+\n");
7567
7568         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7569                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7570                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7571                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7572         }
7573
7574         lpt_disable_clkout_dp(dev);
7575         hsw_disable_lcpll(dev_priv, true, true);
7576 }
7577
7578 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7579 {
7580         struct drm_device *dev = dev_priv->dev;
7581         uint32_t val;
7582
7583         DRM_DEBUG_KMS("Disabling package C8+\n");
7584
7585         hsw_restore_lcpll(dev_priv);
7586         lpt_init_pch_refclk(dev);
7587
7588         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7589                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7590                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7591                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7592         }
7593
7594         intel_prepare_ddi(dev);
7595 }
7596
7597 static void snb_modeset_global_resources(struct drm_device *dev)
7598 {
7599         modeset_update_crtc_power_domains(dev);
7600 }
7601
7602 static void haswell_modeset_global_resources(struct drm_device *dev)
7603 {
7604         modeset_update_crtc_power_domains(dev);
7605 }
7606
7607 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7608                                  int x, int y,
7609                                  struct drm_framebuffer *fb)
7610 {
7611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7612
7613         if (!intel_ddi_pll_select(intel_crtc))
7614                 return -EINVAL;
7615
7616         intel_crtc->lowfreq_avail = false;
7617
7618         return 0;
7619 }
7620
7621 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7622                                 enum port port,
7623                                 struct intel_crtc_config *pipe_config)
7624 {
7625         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7626
7627         switch (pipe_config->ddi_pll_sel) {
7628         case PORT_CLK_SEL_WRPLL1:
7629                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7630                 break;
7631         case PORT_CLK_SEL_WRPLL2:
7632                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7633                 break;
7634         }
7635 }
7636
7637 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7638                                        struct intel_crtc_config *pipe_config)
7639 {
7640         struct drm_device *dev = crtc->base.dev;
7641         struct drm_i915_private *dev_priv = dev->dev_private;
7642         struct intel_shared_dpll *pll;
7643         enum port port;
7644         uint32_t tmp;
7645
7646         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7647
7648         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7649
7650         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7651
7652         if (pipe_config->shared_dpll >= 0) {
7653                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7654
7655                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7656                                            &pipe_config->dpll_hw_state));
7657         }
7658
7659         /*
7660          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7661          * DDI E. So just check whether this pipe is wired to DDI E and whether
7662          * the PCH transcoder is on.
7663          */
7664         if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7665                 pipe_config->has_pch_encoder = true;
7666
7667                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7668                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7669                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7670
7671                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7672         }
7673 }
7674
7675 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7676                                     struct intel_crtc_config *pipe_config)
7677 {
7678         struct drm_device *dev = crtc->base.dev;
7679         struct drm_i915_private *dev_priv = dev->dev_private;
7680         enum intel_display_power_domain pfit_domain;
7681         uint32_t tmp;
7682
7683         if (!intel_display_power_enabled(dev_priv,
7684                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7685                 return false;
7686
7687         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7688         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7689
7690         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7691         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7692                 enum pipe trans_edp_pipe;
7693                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7694                 default:
7695                         WARN(1, "unknown pipe linked to edp transcoder\n");
7696                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7697                 case TRANS_DDI_EDP_INPUT_A_ON:
7698                         trans_edp_pipe = PIPE_A;
7699                         break;
7700                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7701                         trans_edp_pipe = PIPE_B;
7702                         break;
7703                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7704                         trans_edp_pipe = PIPE_C;
7705                         break;
7706                 }
7707
7708                 if (trans_edp_pipe == crtc->pipe)
7709                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7710         }
7711
7712         if (!intel_display_power_enabled(dev_priv,
7713                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7714                 return false;
7715
7716         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7717         if (!(tmp & PIPECONF_ENABLE))
7718                 return false;
7719
7720         haswell_get_ddi_port_state(crtc, pipe_config);
7721
7722         intel_get_pipe_timings(crtc, pipe_config);
7723
7724         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7725         if (intel_display_power_enabled(dev_priv, pfit_domain))
7726                 ironlake_get_pfit_config(crtc, pipe_config);
7727
7728         if (IS_HASWELL(dev))
7729                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7730                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7731
7732         pipe_config->pixel_multiplier = 1;
7733
7734         return true;
7735 }
7736
7737 static struct {
7738         int clock;
7739         u32 config;
7740 } hdmi_audio_clock[] = {
7741         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7742         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7743         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7744         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7745         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7746         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7747         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7748         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7749         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7750         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7751 };
7752
7753 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7754 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7755 {
7756         int i;
7757
7758         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7759                 if (mode->clock == hdmi_audio_clock[i].clock)
7760                         break;
7761         }
7762
7763         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7764                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7765                 i = 1;
7766         }
7767
7768         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7769                       hdmi_audio_clock[i].clock,
7770                       hdmi_audio_clock[i].config);
7771
7772         return hdmi_audio_clock[i].config;
7773 }
7774
7775 static bool intel_eld_uptodate(struct drm_connector *connector,
7776                                int reg_eldv, uint32_t bits_eldv,
7777                                int reg_elda, uint32_t bits_elda,
7778                                int reg_edid)
7779 {
7780         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7781         uint8_t *eld = connector->eld;
7782         uint32_t i;
7783
7784         i = I915_READ(reg_eldv);
7785         i &= bits_eldv;
7786
7787         if (!eld[0])
7788                 return !i;
7789
7790         if (!i)
7791                 return false;
7792
7793         i = I915_READ(reg_elda);
7794         i &= ~bits_elda;
7795         I915_WRITE(reg_elda, i);
7796
7797         for (i = 0; i < eld[2]; i++)
7798                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7799                         return false;
7800
7801         return true;
7802 }
7803
7804 static void g4x_write_eld(struct drm_connector *connector,
7805                           struct drm_crtc *crtc,
7806                           struct drm_display_mode *mode)
7807 {
7808         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7809         uint8_t *eld = connector->eld;
7810         uint32_t eldv;
7811         uint32_t len;
7812         uint32_t i;
7813
7814         i = I915_READ(G4X_AUD_VID_DID);
7815
7816         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7817                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7818         else
7819                 eldv = G4X_ELDV_DEVCTG;
7820
7821         if (intel_eld_uptodate(connector,
7822                                G4X_AUD_CNTL_ST, eldv,
7823                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7824                                G4X_HDMIW_HDMIEDID))
7825                 return;
7826
7827         i = I915_READ(G4X_AUD_CNTL_ST);
7828         i &= ~(eldv | G4X_ELD_ADDR);
7829         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7830         I915_WRITE(G4X_AUD_CNTL_ST, i);
7831
7832         if (!eld[0])
7833                 return;
7834
7835         len = min_t(uint8_t, eld[2], len);
7836         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7837         for (i = 0; i < len; i++)
7838                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7839
7840         i = I915_READ(G4X_AUD_CNTL_ST);
7841         i |= eldv;
7842         I915_WRITE(G4X_AUD_CNTL_ST, i);
7843 }
7844
7845 static void haswell_write_eld(struct drm_connector *connector,
7846                               struct drm_crtc *crtc,
7847                               struct drm_display_mode *mode)
7848 {
7849         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7850         uint8_t *eld = connector->eld;
7851         uint32_t eldv;
7852         uint32_t i;
7853         int len;
7854         int pipe = to_intel_crtc(crtc)->pipe;
7855         int tmp;
7856
7857         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7858         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7859         int aud_config = HSW_AUD_CFG(pipe);
7860         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7861
7862         /* Audio output enable */
7863         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7864         tmp = I915_READ(aud_cntrl_st2);
7865         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7866         I915_WRITE(aud_cntrl_st2, tmp);
7867         POSTING_READ(aud_cntrl_st2);
7868
7869         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7870
7871         /* Set ELD valid state */
7872         tmp = I915_READ(aud_cntrl_st2);
7873         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7874         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7875         I915_WRITE(aud_cntrl_st2, tmp);
7876         tmp = I915_READ(aud_cntrl_st2);
7877         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7878
7879         /* Enable HDMI mode */
7880         tmp = I915_READ(aud_config);
7881         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7882         /* clear N_programing_enable and N_value_index */
7883         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7884         I915_WRITE(aud_config, tmp);
7885
7886         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7887
7888         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7889
7890         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7891                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7892                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7893                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7894         } else {
7895                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7896         }
7897
7898         if (intel_eld_uptodate(connector,
7899                                aud_cntrl_st2, eldv,
7900                                aud_cntl_st, IBX_ELD_ADDRESS,
7901                                hdmiw_hdmiedid))
7902                 return;
7903
7904         i = I915_READ(aud_cntrl_st2);
7905         i &= ~eldv;
7906         I915_WRITE(aud_cntrl_st2, i);
7907
7908         if (!eld[0])
7909                 return;
7910
7911         i = I915_READ(aud_cntl_st);
7912         i &= ~IBX_ELD_ADDRESS;
7913         I915_WRITE(aud_cntl_st, i);
7914         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7915         DRM_DEBUG_DRIVER("port num:%d\n", i);
7916
7917         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7918         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7919         for (i = 0; i < len; i++)
7920                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7921
7922         i = I915_READ(aud_cntrl_st2);
7923         i |= eldv;
7924         I915_WRITE(aud_cntrl_st2, i);
7925
7926 }
7927
7928 static void ironlake_write_eld(struct drm_connector *connector,
7929                                struct drm_crtc *crtc,
7930                                struct drm_display_mode *mode)
7931 {
7932         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7933         uint8_t *eld = connector->eld;
7934         uint32_t eldv;
7935         uint32_t i;
7936         int len;
7937         int hdmiw_hdmiedid;
7938         int aud_config;
7939         int aud_cntl_st;
7940         int aud_cntrl_st2;
7941         int pipe = to_intel_crtc(crtc)->pipe;
7942
7943         if (HAS_PCH_IBX(connector->dev)) {
7944                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7945                 aud_config = IBX_AUD_CFG(pipe);
7946                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7947                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7948         } else if (IS_VALLEYVIEW(connector->dev)) {
7949                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7950                 aud_config = VLV_AUD_CFG(pipe);
7951                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7952                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7953         } else {
7954                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7955                 aud_config = CPT_AUD_CFG(pipe);
7956                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7957                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7958         }
7959
7960         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7961
7962         if (IS_VALLEYVIEW(connector->dev))  {
7963                 struct intel_encoder *intel_encoder;
7964                 struct intel_digital_port *intel_dig_port;
7965
7966                 intel_encoder = intel_attached_encoder(connector);
7967                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7968                 i = intel_dig_port->port;
7969         } else {
7970                 i = I915_READ(aud_cntl_st);
7971                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7972                 /* DIP_Port_Select, 0x1 = PortB */
7973         }
7974
7975         if (!i) {
7976                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7977                 /* operate blindly on all ports */
7978                 eldv = IBX_ELD_VALIDB;
7979                 eldv |= IBX_ELD_VALIDB << 4;
7980                 eldv |= IBX_ELD_VALIDB << 8;
7981         } else {
7982                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7983                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7984         }
7985
7986         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7987                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7988                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7989                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7990         } else {
7991                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7992         }
7993
7994         if (intel_eld_uptodate(connector,
7995                                aud_cntrl_st2, eldv,
7996                                aud_cntl_st, IBX_ELD_ADDRESS,
7997                                hdmiw_hdmiedid))
7998                 return;
7999
8000         i = I915_READ(aud_cntrl_st2);
8001         i &= ~eldv;
8002         I915_WRITE(aud_cntrl_st2, i);
8003
8004         if (!eld[0])
8005                 return;
8006
8007         i = I915_READ(aud_cntl_st);
8008         i &= ~IBX_ELD_ADDRESS;
8009         I915_WRITE(aud_cntl_st, i);
8010
8011         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8012         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8013         for (i = 0; i < len; i++)
8014                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8015
8016         i = I915_READ(aud_cntrl_st2);
8017         i |= eldv;
8018         I915_WRITE(aud_cntrl_st2, i);
8019 }
8020
8021 void intel_write_eld(struct drm_encoder *encoder,
8022                      struct drm_display_mode *mode)
8023 {
8024         struct drm_crtc *crtc = encoder->crtc;
8025         struct drm_connector *connector;
8026         struct drm_device *dev = encoder->dev;
8027         struct drm_i915_private *dev_priv = dev->dev_private;
8028
8029         connector = drm_select_eld(encoder, mode);
8030         if (!connector)
8031                 return;
8032
8033         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8034                          connector->base.id,
8035                          connector->name,
8036                          connector->encoder->base.id,
8037                          connector->encoder->name);
8038
8039         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8040
8041         if (dev_priv->display.write_eld)
8042                 dev_priv->display.write_eld(connector, crtc, mode);
8043 }
8044
8045 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8046 {
8047         struct drm_device *dev = crtc->dev;
8048         struct drm_i915_private *dev_priv = dev->dev_private;
8049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8050         uint32_t cntl = 0, size = 0;
8051
8052         if (base) {
8053                 unsigned int width = intel_crtc->cursor_width;
8054                 unsigned int height = intel_crtc->cursor_height;
8055                 unsigned int stride = roundup_pow_of_two(width) * 4;
8056
8057                 switch (stride) {
8058                 default:
8059                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8060                                   width, stride);
8061                         stride = 256;
8062                         /* fallthrough */
8063                 case 256:
8064                 case 512:
8065                 case 1024:
8066                 case 2048:
8067                         break;
8068                 }
8069
8070                 cntl |= CURSOR_ENABLE |
8071                         CURSOR_GAMMA_ENABLE |
8072                         CURSOR_FORMAT_ARGB |
8073                         CURSOR_STRIDE(stride);
8074
8075                 size = (height << 12) | width;
8076         }
8077
8078         if (intel_crtc->cursor_cntl != 0 &&
8079             (intel_crtc->cursor_base != base ||
8080              intel_crtc->cursor_size != size ||
8081              intel_crtc->cursor_cntl != cntl)) {
8082                 /* On these chipsets we can only modify the base/size/stride
8083                  * whilst the cursor is disabled.
8084                  */
8085                 I915_WRITE(_CURACNTR, 0);
8086                 POSTING_READ(_CURACNTR);
8087                 intel_crtc->cursor_cntl = 0;
8088         }
8089
8090         if (intel_crtc->cursor_base != base)
8091                 I915_WRITE(_CURABASE, base);
8092
8093         if (intel_crtc->cursor_size != size) {
8094                 I915_WRITE(CURSIZE, size);
8095                 intel_crtc->cursor_size = size;
8096         }
8097
8098         if (intel_crtc->cursor_cntl != cntl) {
8099                 I915_WRITE(_CURACNTR, cntl);
8100                 POSTING_READ(_CURACNTR);
8101                 intel_crtc->cursor_cntl = cntl;
8102         }
8103 }
8104
8105 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8106 {
8107         struct drm_device *dev = crtc->dev;
8108         struct drm_i915_private *dev_priv = dev->dev_private;
8109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8110         int pipe = intel_crtc->pipe;
8111         uint32_t cntl;
8112
8113         cntl = 0;
8114         if (base) {
8115                 cntl = MCURSOR_GAMMA_ENABLE;
8116                 switch (intel_crtc->cursor_width) {
8117                         case 64:
8118                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8119                                 break;
8120                         case 128:
8121                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8122                                 break;
8123                         case 256:
8124                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8125                                 break;
8126                         default:
8127                                 WARN_ON(1);
8128                                 return;
8129                 }
8130                 cntl |= pipe << 28; /* Connect to correct pipe */
8131         }
8132         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8133                 cntl |= CURSOR_PIPE_CSC_ENABLE;
8134
8135         if (intel_crtc->cursor_cntl != cntl) {
8136                 I915_WRITE(CURCNTR(pipe), cntl);
8137                 POSTING_READ(CURCNTR(pipe));
8138                 intel_crtc->cursor_cntl = cntl;
8139         }
8140
8141         /* and commit changes on next vblank */
8142         I915_WRITE(CURBASE(pipe), base);
8143         POSTING_READ(CURBASE(pipe));
8144 }
8145
8146 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8147 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8148                                      bool on)
8149 {
8150         struct drm_device *dev = crtc->dev;
8151         struct drm_i915_private *dev_priv = dev->dev_private;
8152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8153         int pipe = intel_crtc->pipe;
8154         int x = crtc->cursor_x;
8155         int y = crtc->cursor_y;
8156         u32 base = 0, pos = 0;
8157
8158         if (on)
8159                 base = intel_crtc->cursor_addr;
8160
8161         if (x >= intel_crtc->config.pipe_src_w)
8162                 base = 0;
8163
8164         if (y >= intel_crtc->config.pipe_src_h)
8165                 base = 0;
8166
8167         if (x < 0) {
8168                 if (x + intel_crtc->cursor_width <= 0)
8169                         base = 0;
8170
8171                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8172                 x = -x;
8173         }
8174         pos |= x << CURSOR_X_SHIFT;
8175
8176         if (y < 0) {
8177                 if (y + intel_crtc->cursor_height <= 0)
8178                         base = 0;
8179
8180                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8181                 y = -y;
8182         }
8183         pos |= y << CURSOR_Y_SHIFT;
8184
8185         if (base == 0 && intel_crtc->cursor_base == 0)
8186                 return;
8187
8188         I915_WRITE(CURPOS(pipe), pos);
8189
8190         if (IS_845G(dev) || IS_I865G(dev))
8191                 i845_update_cursor(crtc, base);
8192         else
8193                 i9xx_update_cursor(crtc, base);
8194         intel_crtc->cursor_base = base;
8195 }
8196
8197 static bool cursor_size_ok(struct drm_device *dev,
8198                            uint32_t width, uint32_t height)
8199 {
8200         if (width == 0 || height == 0)
8201                 return false;
8202
8203         /*
8204          * 845g/865g are special in that they are only limited by
8205          * the width of their cursors, the height is arbitrary up to
8206          * the precision of the register. Everything else requires
8207          * square cursors, limited to a few power-of-two sizes.
8208          */
8209         if (IS_845G(dev) || IS_I865G(dev)) {
8210                 if ((width & 63) != 0)
8211                         return false;
8212
8213                 if (width > (IS_845G(dev) ? 64 : 512))
8214                         return false;
8215
8216                 if (height > 1023)
8217                         return false;
8218         } else {
8219                 switch (width | height) {
8220                 case 256:
8221                 case 128:
8222                         if (IS_GEN2(dev))
8223                                 return false;
8224                 case 64:
8225                         break;
8226                 default:
8227                         return false;
8228                 }
8229         }
8230
8231         return true;
8232 }
8233
8234 /*
8235  * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8236  *
8237  * Note that the object's reference will be consumed if the update fails.  If
8238  * the update succeeds, the reference of the old object (if any) will be
8239  * consumed.
8240  */
8241 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8242                                      struct drm_i915_gem_object *obj,
8243                                      uint32_t width, uint32_t height)
8244 {
8245         struct drm_device *dev = crtc->dev;
8246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8247         enum pipe pipe = intel_crtc->pipe;
8248         unsigned old_width, stride;
8249         uint32_t addr;
8250         int ret;
8251
8252         /* if we want to turn off the cursor ignore width and height */
8253         if (!obj) {
8254                 DRM_DEBUG_KMS("cursor off\n");
8255                 addr = 0;
8256                 obj = NULL;
8257                 mutex_lock(&dev->struct_mutex);
8258                 goto finish;
8259         }
8260
8261         /* Check for which cursor types we support */
8262         if (!cursor_size_ok(dev, width, height)) {
8263                 DRM_DEBUG("Cursor dimension not supported\n");
8264                 return -EINVAL;
8265         }
8266
8267         stride = roundup_pow_of_two(width) * 4;
8268         if (obj->base.size < stride * height) {
8269                 DRM_DEBUG_KMS("buffer is too small\n");
8270                 ret = -ENOMEM;
8271                 goto fail;
8272         }
8273
8274         /* we only need to pin inside GTT if cursor is non-phy */
8275         mutex_lock(&dev->struct_mutex);
8276         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8277                 unsigned alignment;
8278
8279                 if (obj->tiling_mode) {
8280                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8281                         ret = -EINVAL;
8282                         goto fail_locked;
8283                 }
8284
8285                 /* Note that the w/a also requires 2 PTE of padding following
8286                  * the bo. We currently fill all unused PTE with the shadow
8287                  * page and so we should always have valid PTE following the
8288                  * cursor preventing the VT-d warning.
8289                  */
8290                 alignment = 0;
8291                 if (need_vtd_wa(dev))
8292                         alignment = 64*1024;
8293
8294                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8295                 if (ret) {
8296                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8297                         goto fail_locked;
8298                 }
8299
8300                 ret = i915_gem_object_put_fence(obj);
8301                 if (ret) {
8302                         DRM_DEBUG_KMS("failed to release fence for cursor");
8303                         goto fail_unpin;
8304                 }
8305
8306                 addr = i915_gem_obj_ggtt_offset(obj);
8307         } else {
8308                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8309                 ret = i915_gem_object_attach_phys(obj, align);
8310                 if (ret) {
8311                         DRM_DEBUG_KMS("failed to attach phys object\n");
8312                         goto fail_locked;
8313                 }
8314                 addr = obj->phys_handle->busaddr;
8315         }
8316
8317  finish:
8318         if (intel_crtc->cursor_bo) {
8319                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8320                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8321         }
8322
8323         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8324                           INTEL_FRONTBUFFER_CURSOR(pipe));
8325         mutex_unlock(&dev->struct_mutex);
8326
8327         old_width = intel_crtc->cursor_width;
8328
8329         intel_crtc->cursor_addr = addr;
8330         intel_crtc->cursor_bo = obj;
8331         intel_crtc->cursor_width = width;
8332         intel_crtc->cursor_height = height;
8333
8334         if (intel_crtc->active) {
8335                 if (old_width != width)
8336                         intel_update_watermarks(crtc);
8337                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8338         }
8339
8340         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8341
8342         return 0;
8343 fail_unpin:
8344         i915_gem_object_unpin_from_display_plane(obj);
8345 fail_locked:
8346         mutex_unlock(&dev->struct_mutex);
8347 fail:
8348         drm_gem_object_unreference_unlocked(&obj->base);
8349         return ret;
8350 }
8351
8352 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8353                                  u16 *blue, uint32_t start, uint32_t size)
8354 {
8355         int end = (start + size > 256) ? 256 : start + size, i;
8356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8357
8358         for (i = start; i < end; i++) {
8359                 intel_crtc->lut_r[i] = red[i] >> 8;
8360                 intel_crtc->lut_g[i] = green[i] >> 8;
8361                 intel_crtc->lut_b[i] = blue[i] >> 8;
8362         }
8363
8364         intel_crtc_load_lut(crtc);
8365 }
8366
8367 /* VESA 640x480x72Hz mode to set on the pipe */
8368 static struct drm_display_mode load_detect_mode = {
8369         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8370                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8371 };
8372
8373 struct drm_framebuffer *
8374 __intel_framebuffer_create(struct drm_device *dev,
8375                            struct drm_mode_fb_cmd2 *mode_cmd,
8376                            struct drm_i915_gem_object *obj)
8377 {
8378         struct intel_framebuffer *intel_fb;
8379         int ret;
8380
8381         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8382         if (!intel_fb) {
8383                 drm_gem_object_unreference_unlocked(&obj->base);
8384                 return ERR_PTR(-ENOMEM);
8385         }
8386
8387         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8388         if (ret)
8389                 goto err;
8390
8391         return &intel_fb->base;
8392 err:
8393         drm_gem_object_unreference_unlocked(&obj->base);
8394         kfree(intel_fb);
8395
8396         return ERR_PTR(ret);
8397 }
8398
8399 static struct drm_framebuffer *
8400 intel_framebuffer_create(struct drm_device *dev,
8401                          struct drm_mode_fb_cmd2 *mode_cmd,
8402                          struct drm_i915_gem_object *obj)
8403 {
8404         struct drm_framebuffer *fb;
8405         int ret;
8406
8407         ret = i915_mutex_lock_interruptible(dev);
8408         if (ret)
8409                 return ERR_PTR(ret);
8410         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8411         mutex_unlock(&dev->struct_mutex);
8412
8413         return fb;
8414 }
8415
8416 static u32
8417 intel_framebuffer_pitch_for_width(int width, int bpp)
8418 {
8419         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8420         return ALIGN(pitch, 64);
8421 }
8422
8423 static u32
8424 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8425 {
8426         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8427         return PAGE_ALIGN(pitch * mode->vdisplay);
8428 }
8429
8430 static struct drm_framebuffer *
8431 intel_framebuffer_create_for_mode(struct drm_device *dev,
8432                                   struct drm_display_mode *mode,
8433                                   int depth, int bpp)
8434 {
8435         struct drm_i915_gem_object *obj;
8436         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8437
8438         obj = i915_gem_alloc_object(dev,
8439                                     intel_framebuffer_size_for_mode(mode, bpp));
8440         if (obj == NULL)
8441                 return ERR_PTR(-ENOMEM);
8442
8443         mode_cmd.width = mode->hdisplay;
8444         mode_cmd.height = mode->vdisplay;
8445         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8446                                                                 bpp);
8447         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8448
8449         return intel_framebuffer_create(dev, &mode_cmd, obj);
8450 }
8451
8452 static struct drm_framebuffer *
8453 mode_fits_in_fbdev(struct drm_device *dev,
8454                    struct drm_display_mode *mode)
8455 {
8456 #ifdef CONFIG_DRM_I915_FBDEV
8457         struct drm_i915_private *dev_priv = dev->dev_private;
8458         struct drm_i915_gem_object *obj;
8459         struct drm_framebuffer *fb;
8460
8461         if (!dev_priv->fbdev)
8462                 return NULL;
8463
8464         if (!dev_priv->fbdev->fb)
8465                 return NULL;
8466
8467         obj = dev_priv->fbdev->fb->obj;
8468         BUG_ON(!obj);
8469
8470         fb = &dev_priv->fbdev->fb->base;
8471         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8472                                                                fb->bits_per_pixel))
8473                 return NULL;
8474
8475         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8476                 return NULL;
8477
8478         return fb;
8479 #else
8480         return NULL;
8481 #endif
8482 }
8483
8484 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8485                                 struct drm_display_mode *mode,
8486                                 struct intel_load_detect_pipe *old,
8487                                 struct drm_modeset_acquire_ctx *ctx)
8488 {
8489         struct intel_crtc *intel_crtc;
8490         struct intel_encoder *intel_encoder =
8491                 intel_attached_encoder(connector);
8492         struct drm_crtc *possible_crtc;
8493         struct drm_encoder *encoder = &intel_encoder->base;
8494         struct drm_crtc *crtc = NULL;
8495         struct drm_device *dev = encoder->dev;
8496         struct drm_framebuffer *fb;
8497         struct drm_mode_config *config = &dev->mode_config;
8498         int ret, i = -1;
8499
8500         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8501                       connector->base.id, connector->name,
8502                       encoder->base.id, encoder->name);
8503
8504 retry:
8505         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8506         if (ret)
8507                 goto fail_unlock;
8508
8509         /*
8510          * Algorithm gets a little messy:
8511          *
8512          *   - if the connector already has an assigned crtc, use it (but make
8513          *     sure it's on first)
8514          *
8515          *   - try to find the first unused crtc that can drive this connector,
8516          *     and use that if we find one
8517          */
8518
8519         /* See if we already have a CRTC for this connector */
8520         if (encoder->crtc) {
8521                 crtc = encoder->crtc;
8522
8523                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8524                 if (ret)
8525                         goto fail_unlock;
8526
8527                 old->dpms_mode = connector->dpms;
8528                 old->load_detect_temp = false;
8529
8530                 /* Make sure the crtc and connector are running */
8531                 if (connector->dpms != DRM_MODE_DPMS_ON)
8532                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8533
8534                 return true;
8535         }
8536
8537         /* Find an unused one (if possible) */
8538         for_each_crtc(dev, possible_crtc) {
8539                 i++;
8540                 if (!(encoder->possible_crtcs & (1 << i)))
8541                         continue;
8542                 if (possible_crtc->enabled)
8543                         continue;
8544                 /* This can occur when applying the pipe A quirk on resume. */
8545                 if (to_intel_crtc(possible_crtc)->new_enabled)
8546                         continue;
8547
8548                 crtc = possible_crtc;
8549                 break;
8550         }
8551
8552         /*
8553          * If we didn't find an unused CRTC, don't use any.
8554          */
8555         if (!crtc) {
8556                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8557                 goto fail_unlock;
8558         }
8559
8560         ret = drm_modeset_lock(&crtc->mutex, ctx);
8561         if (ret)
8562                 goto fail_unlock;
8563         intel_encoder->new_crtc = to_intel_crtc(crtc);
8564         to_intel_connector(connector)->new_encoder = intel_encoder;
8565
8566         intel_crtc = to_intel_crtc(crtc);
8567         intel_crtc->new_enabled = true;
8568         intel_crtc->new_config = &intel_crtc->config;
8569         old->dpms_mode = connector->dpms;
8570         old->load_detect_temp = true;
8571         old->release_fb = NULL;
8572
8573         if (!mode)
8574                 mode = &load_detect_mode;
8575
8576         /* We need a framebuffer large enough to accommodate all accesses
8577          * that the plane may generate whilst we perform load detection.
8578          * We can not rely on the fbcon either being present (we get called
8579          * during its initialisation to detect all boot displays, or it may
8580          * not even exist) or that it is large enough to satisfy the
8581          * requested mode.
8582          */
8583         fb = mode_fits_in_fbdev(dev, mode);
8584         if (fb == NULL) {
8585                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8586                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8587                 old->release_fb = fb;
8588         } else
8589                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8590         if (IS_ERR(fb)) {
8591                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8592                 goto fail;
8593         }
8594
8595         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8596                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8597                 if (old->release_fb)
8598                         old->release_fb->funcs->destroy(old->release_fb);
8599                 goto fail;
8600         }
8601
8602         /* let the connector get through one full cycle before testing */
8603         intel_wait_for_vblank(dev, intel_crtc->pipe);
8604         return true;
8605
8606  fail:
8607         intel_crtc->new_enabled = crtc->enabled;
8608         if (intel_crtc->new_enabled)
8609                 intel_crtc->new_config = &intel_crtc->config;
8610         else
8611                 intel_crtc->new_config = NULL;
8612 fail_unlock:
8613         if (ret == -EDEADLK) {
8614                 drm_modeset_backoff(ctx);
8615                 goto retry;
8616         }
8617
8618         return false;
8619 }
8620
8621 void intel_release_load_detect_pipe(struct drm_connector *connector,
8622                                     struct intel_load_detect_pipe *old)
8623 {
8624         struct intel_encoder *intel_encoder =
8625                 intel_attached_encoder(connector);
8626         struct drm_encoder *encoder = &intel_encoder->base;
8627         struct drm_crtc *crtc = encoder->crtc;
8628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629
8630         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8631                       connector->base.id, connector->name,
8632                       encoder->base.id, encoder->name);
8633
8634         if (old->load_detect_temp) {
8635                 to_intel_connector(connector)->new_encoder = NULL;
8636                 intel_encoder->new_crtc = NULL;
8637                 intel_crtc->new_enabled = false;
8638                 intel_crtc->new_config = NULL;
8639                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8640
8641                 if (old->release_fb) {
8642                         drm_framebuffer_unregister_private(old->release_fb);
8643                         drm_framebuffer_unreference(old->release_fb);
8644                 }
8645
8646                 return;
8647         }
8648
8649         /* Switch crtc and encoder back off if necessary */
8650         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8651                 connector->funcs->dpms(connector, old->dpms_mode);
8652 }
8653
8654 static int i9xx_pll_refclk(struct drm_device *dev,
8655                            const struct intel_crtc_config *pipe_config)
8656 {
8657         struct drm_i915_private *dev_priv = dev->dev_private;
8658         u32 dpll = pipe_config->dpll_hw_state.dpll;
8659
8660         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8661                 return dev_priv->vbt.lvds_ssc_freq;
8662         else if (HAS_PCH_SPLIT(dev))
8663                 return 120000;
8664         else if (!IS_GEN2(dev))
8665                 return 96000;
8666         else
8667                 return 48000;
8668 }
8669
8670 /* Returns the clock of the currently programmed mode of the given pipe. */
8671 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8672                                 struct intel_crtc_config *pipe_config)
8673 {
8674         struct drm_device *dev = crtc->base.dev;
8675         struct drm_i915_private *dev_priv = dev->dev_private;
8676         int pipe = pipe_config->cpu_transcoder;
8677         u32 dpll = pipe_config->dpll_hw_state.dpll;
8678         u32 fp;
8679         intel_clock_t clock;
8680         int refclk = i9xx_pll_refclk(dev, pipe_config);
8681
8682         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8683                 fp = pipe_config->dpll_hw_state.fp0;
8684         else
8685                 fp = pipe_config->dpll_hw_state.fp1;
8686
8687         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8688         if (IS_PINEVIEW(dev)) {
8689                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8690                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8691         } else {
8692                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8693                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8694         }
8695
8696         if (!IS_GEN2(dev)) {
8697                 if (IS_PINEVIEW(dev))
8698                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8699                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8700                 else
8701                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8702                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8703
8704                 switch (dpll & DPLL_MODE_MASK) {
8705                 case DPLLB_MODE_DAC_SERIAL:
8706                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8707                                 5 : 10;
8708                         break;
8709                 case DPLLB_MODE_LVDS:
8710                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8711                                 7 : 14;
8712                         break;
8713                 default:
8714                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8715                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8716                         return;
8717                 }
8718
8719                 if (IS_PINEVIEW(dev))
8720                         pineview_clock(refclk, &clock);
8721                 else
8722                         i9xx_clock(refclk, &clock);
8723         } else {
8724                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8725                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8726
8727                 if (is_lvds) {
8728                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8729                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8730
8731                         if (lvds & LVDS_CLKB_POWER_UP)
8732                                 clock.p2 = 7;
8733                         else
8734                                 clock.p2 = 14;
8735                 } else {
8736                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8737                                 clock.p1 = 2;
8738                         else {
8739                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8740                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8741                         }
8742                         if (dpll & PLL_P2_DIVIDE_BY_4)
8743                                 clock.p2 = 4;
8744                         else
8745                                 clock.p2 = 2;
8746                 }
8747
8748                 i9xx_clock(refclk, &clock);
8749         }
8750
8751         /*
8752          * This value includes pixel_multiplier. We will use
8753          * port_clock to compute adjusted_mode.crtc_clock in the
8754          * encoder's get_config() function.
8755          */
8756         pipe_config->port_clock = clock.dot;
8757 }
8758
8759 int intel_dotclock_calculate(int link_freq,
8760                              const struct intel_link_m_n *m_n)
8761 {
8762         /*
8763          * The calculation for the data clock is:
8764          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8765          * But we want to avoid losing precison if possible, so:
8766          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8767          *
8768          * and the link clock is simpler:
8769          * link_clock = (m * link_clock) / n
8770          */
8771
8772         if (!m_n->link_n)
8773                 return 0;
8774
8775         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8776 }
8777
8778 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8779                                    struct intel_crtc_config *pipe_config)
8780 {
8781         struct drm_device *dev = crtc->base.dev;
8782
8783         /* read out port_clock from the DPLL */
8784         i9xx_crtc_clock_get(crtc, pipe_config);
8785
8786         /*
8787          * This value does not include pixel_multiplier.
8788          * We will check that port_clock and adjusted_mode.crtc_clock
8789          * agree once we know their relationship in the encoder's
8790          * get_config() function.
8791          */
8792         pipe_config->adjusted_mode.crtc_clock =
8793                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8794                                          &pipe_config->fdi_m_n);
8795 }
8796
8797 /** Returns the currently programmed mode of the given pipe. */
8798 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8799                                              struct drm_crtc *crtc)
8800 {
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8803         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8804         struct drm_display_mode *mode;
8805         struct intel_crtc_config pipe_config;
8806         int htot = I915_READ(HTOTAL(cpu_transcoder));
8807         int hsync = I915_READ(HSYNC(cpu_transcoder));
8808         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8809         int vsync = I915_READ(VSYNC(cpu_transcoder));
8810         enum pipe pipe = intel_crtc->pipe;
8811
8812         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8813         if (!mode)
8814                 return NULL;
8815
8816         /*
8817          * Construct a pipe_config sufficient for getting the clock info
8818          * back out of crtc_clock_get.
8819          *
8820          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8821          * to use a real value here instead.
8822          */
8823         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8824         pipe_config.pixel_multiplier = 1;
8825         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8826         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8827         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8828         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8829
8830         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8831         mode->hdisplay = (htot & 0xffff) + 1;
8832         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8833         mode->hsync_start = (hsync & 0xffff) + 1;
8834         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8835         mode->vdisplay = (vtot & 0xffff) + 1;
8836         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8837         mode->vsync_start = (vsync & 0xffff) + 1;
8838         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8839
8840         drm_mode_set_name(mode);
8841
8842         return mode;
8843 }
8844
8845 static void intel_increase_pllclock(struct drm_device *dev,
8846                                     enum pipe pipe)
8847 {
8848         struct drm_i915_private *dev_priv = dev->dev_private;
8849         int dpll_reg = DPLL(pipe);
8850         int dpll;
8851
8852         if (!HAS_GMCH_DISPLAY(dev))
8853                 return;
8854
8855         if (!dev_priv->lvds_downclock_avail)
8856                 return;
8857
8858         dpll = I915_READ(dpll_reg);
8859         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8860                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8861
8862                 assert_panel_unlocked(dev_priv, pipe);
8863
8864                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8865                 I915_WRITE(dpll_reg, dpll);
8866                 intel_wait_for_vblank(dev, pipe);
8867
8868                 dpll = I915_READ(dpll_reg);
8869                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8870                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8871         }
8872 }
8873
8874 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8875 {
8876         struct drm_device *dev = crtc->dev;
8877         struct drm_i915_private *dev_priv = dev->dev_private;
8878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8879
8880         if (!HAS_GMCH_DISPLAY(dev))
8881                 return;
8882
8883         if (!dev_priv->lvds_downclock_avail)
8884                 return;
8885
8886         /*
8887          * Since this is called by a timer, we should never get here in
8888          * the manual case.
8889          */
8890         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8891                 int pipe = intel_crtc->pipe;
8892                 int dpll_reg = DPLL(pipe);
8893                 int dpll;
8894
8895                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8896
8897                 assert_panel_unlocked(dev_priv, pipe);
8898
8899                 dpll = I915_READ(dpll_reg);
8900                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8901                 I915_WRITE(dpll_reg, dpll);
8902                 intel_wait_for_vblank(dev, pipe);
8903                 dpll = I915_READ(dpll_reg);
8904                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8905                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8906         }
8907
8908 }
8909
8910 void intel_mark_busy(struct drm_device *dev)
8911 {
8912         struct drm_i915_private *dev_priv = dev->dev_private;
8913
8914         if (dev_priv->mm.busy)
8915                 return;
8916
8917         intel_runtime_pm_get(dev_priv);
8918         i915_update_gfx_val(dev_priv);
8919         dev_priv->mm.busy = true;
8920 }
8921
8922 void intel_mark_idle(struct drm_device *dev)
8923 {
8924         struct drm_i915_private *dev_priv = dev->dev_private;
8925         struct drm_crtc *crtc;
8926
8927         if (!dev_priv->mm.busy)
8928                 return;
8929
8930         dev_priv->mm.busy = false;
8931
8932         if (!i915.powersave)
8933                 goto out;
8934
8935         for_each_crtc(dev, crtc) {
8936                 if (!crtc->primary->fb)
8937                         continue;
8938
8939                 intel_decrease_pllclock(crtc);
8940         }
8941
8942         if (INTEL_INFO(dev)->gen >= 6)
8943                 gen6_rps_idle(dev->dev_private);
8944
8945 out:
8946         intel_runtime_pm_put(dev_priv);
8947 }
8948
8949
8950 /**
8951  * intel_mark_fb_busy - mark given planes as busy
8952  * @dev: DRM device
8953  * @frontbuffer_bits: bits for the affected planes
8954  * @ring: optional ring for asynchronous commands
8955  *
8956  * This function gets called every time the screen contents change. It can be
8957  * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8958  */
8959 static void intel_mark_fb_busy(struct drm_device *dev,
8960                                unsigned frontbuffer_bits,
8961                                struct intel_engine_cs *ring)
8962 {
8963         enum pipe pipe;
8964
8965         if (!i915.powersave)
8966                 return;
8967
8968         for_each_pipe(pipe) {
8969                 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8970                         continue;
8971
8972                 intel_increase_pllclock(dev, pipe);
8973                 if (ring && intel_fbc_enabled(dev))
8974                         ring->fbc_dirty = true;
8975         }
8976 }
8977
8978 /**
8979  * intel_fb_obj_invalidate - invalidate frontbuffer object
8980  * @obj: GEM object to invalidate
8981  * @ring: set for asynchronous rendering
8982  *
8983  * This function gets called every time rendering on the given object starts and
8984  * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8985  * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8986  * until the rendering completes or a flip on this frontbuffer plane is
8987  * scheduled.
8988  */
8989 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8990                              struct intel_engine_cs *ring)
8991 {
8992         struct drm_device *dev = obj->base.dev;
8993         struct drm_i915_private *dev_priv = dev->dev_private;
8994
8995         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8996
8997         if (!obj->frontbuffer_bits)
8998                 return;
8999
9000         if (ring) {
9001                 mutex_lock(&dev_priv->fb_tracking.lock);
9002                 dev_priv->fb_tracking.busy_bits
9003                         |= obj->frontbuffer_bits;
9004                 dev_priv->fb_tracking.flip_bits
9005                         &= ~obj->frontbuffer_bits;
9006                 mutex_unlock(&dev_priv->fb_tracking.lock);
9007         }
9008
9009         intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9010
9011         intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9012 }
9013
9014 /**
9015  * intel_frontbuffer_flush - flush frontbuffer
9016  * @dev: DRM device
9017  * @frontbuffer_bits: frontbuffer plane tracking bits
9018  *
9019  * This function gets called every time rendering on the given planes has
9020  * completed and frontbuffer caching can be started again. Flushes will get
9021  * delayed if they're blocked by some oustanding asynchronous rendering.
9022  *
9023  * Can be called without any locks held.
9024  */
9025 void intel_frontbuffer_flush(struct drm_device *dev,
9026                              unsigned frontbuffer_bits)
9027 {
9028         struct drm_i915_private *dev_priv = dev->dev_private;
9029
9030         /* Delay flushing when rings are still busy.*/
9031         mutex_lock(&dev_priv->fb_tracking.lock);
9032         frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9033         mutex_unlock(&dev_priv->fb_tracking.lock);
9034
9035         intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9036
9037         intel_edp_psr_flush(dev, frontbuffer_bits);
9038 }
9039
9040 /**
9041  * intel_fb_obj_flush - flush frontbuffer object
9042  * @obj: GEM object to flush
9043  * @retire: set when retiring asynchronous rendering
9044  *
9045  * This function gets called every time rendering on the given object has
9046  * completed and frontbuffer caching can be started again. If @retire is true
9047  * then any delayed flushes will be unblocked.
9048  */
9049 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9050                         bool retire)
9051 {
9052         struct drm_device *dev = obj->base.dev;
9053         struct drm_i915_private *dev_priv = dev->dev_private;
9054         unsigned frontbuffer_bits;
9055
9056         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9057
9058         if (!obj->frontbuffer_bits)
9059                 return;
9060
9061         frontbuffer_bits = obj->frontbuffer_bits;
9062
9063         if (retire) {
9064                 mutex_lock(&dev_priv->fb_tracking.lock);
9065                 /* Filter out new bits since rendering started. */
9066                 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9067
9068                 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9069                 mutex_unlock(&dev_priv->fb_tracking.lock);
9070         }
9071
9072         intel_frontbuffer_flush(dev, frontbuffer_bits);
9073 }
9074
9075 /**
9076  * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9077  * @dev: DRM device
9078  * @frontbuffer_bits: frontbuffer plane tracking bits
9079  *
9080  * This function gets called after scheduling a flip on @obj. The actual
9081  * frontbuffer flushing will be delayed until completion is signalled with
9082  * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9083  * flush will be cancelled.
9084  *
9085  * Can be called without any locks held.
9086  */
9087 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9088                                     unsigned frontbuffer_bits)
9089 {
9090         struct drm_i915_private *dev_priv = dev->dev_private;
9091
9092         mutex_lock(&dev_priv->fb_tracking.lock);
9093         dev_priv->fb_tracking.flip_bits
9094                 |= frontbuffer_bits;
9095         mutex_unlock(&dev_priv->fb_tracking.lock);
9096 }
9097
9098 /**
9099  * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9100  * @dev: DRM device
9101  * @frontbuffer_bits: frontbuffer plane tracking bits
9102  *
9103  * This function gets called after the flip has been latched and will complete
9104  * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9105  *
9106  * Can be called without any locks held.
9107  */
9108 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9109                                      unsigned frontbuffer_bits)
9110 {
9111         struct drm_i915_private *dev_priv = dev->dev_private;
9112
9113         mutex_lock(&dev_priv->fb_tracking.lock);
9114         /* Mask any cancelled flips. */
9115         frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9116         dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9117         mutex_unlock(&dev_priv->fb_tracking.lock);
9118
9119         intel_frontbuffer_flush(dev, frontbuffer_bits);
9120 }
9121
9122 static void intel_crtc_destroy(struct drm_crtc *crtc)
9123 {
9124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9125         struct drm_device *dev = crtc->dev;
9126         struct intel_unpin_work *work;
9127         unsigned long flags;
9128
9129         spin_lock_irqsave(&dev->event_lock, flags);
9130         work = intel_crtc->unpin_work;
9131         intel_crtc->unpin_work = NULL;
9132         spin_unlock_irqrestore(&dev->event_lock, flags);
9133
9134         if (work) {
9135                 cancel_work_sync(&work->work);
9136                 kfree(work);
9137         }
9138
9139         drm_crtc_cleanup(crtc);
9140
9141         kfree(intel_crtc);
9142 }
9143
9144 static void intel_unpin_work_fn(struct work_struct *__work)
9145 {
9146         struct intel_unpin_work *work =
9147                 container_of(__work, struct intel_unpin_work, work);
9148         struct drm_device *dev = work->crtc->dev;
9149         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9150
9151         mutex_lock(&dev->struct_mutex);
9152         intel_unpin_fb_obj(work->old_fb_obj);
9153         drm_gem_object_unreference(&work->pending_flip_obj->base);
9154         drm_gem_object_unreference(&work->old_fb_obj->base);
9155
9156         intel_update_fbc(dev);
9157         mutex_unlock(&dev->struct_mutex);
9158
9159         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9160
9161         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9162         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9163
9164         kfree(work);
9165 }
9166
9167 static void do_intel_finish_page_flip(struct drm_device *dev,
9168                                       struct drm_crtc *crtc)
9169 {
9170         struct drm_i915_private *dev_priv = dev->dev_private;
9171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9172         struct intel_unpin_work *work;
9173         unsigned long flags;
9174
9175         /* Ignore early vblank irqs */
9176         if (intel_crtc == NULL)
9177                 return;
9178
9179         spin_lock_irqsave(&dev->event_lock, flags);
9180         work = intel_crtc->unpin_work;
9181
9182         /* Ensure we don't miss a work->pending update ... */
9183         smp_rmb();
9184
9185         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9186                 spin_unlock_irqrestore(&dev->event_lock, flags);
9187                 return;
9188         }
9189
9190         /* and that the unpin work is consistent wrt ->pending. */
9191         smp_rmb();
9192
9193         intel_crtc->unpin_work = NULL;
9194
9195         if (work->event)
9196                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9197
9198         drm_crtc_vblank_put(crtc);
9199
9200         spin_unlock_irqrestore(&dev->event_lock, flags);
9201
9202         wake_up_all(&dev_priv->pending_flip_queue);
9203
9204         queue_work(dev_priv->wq, &work->work);
9205
9206         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9207 }
9208
9209 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9210 {
9211         struct drm_i915_private *dev_priv = dev->dev_private;
9212         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9213
9214         do_intel_finish_page_flip(dev, crtc);
9215 }
9216
9217 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9218 {
9219         struct drm_i915_private *dev_priv = dev->dev_private;
9220         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9221
9222         do_intel_finish_page_flip(dev, crtc);
9223 }
9224
9225 /* Is 'a' after or equal to 'b'? */
9226 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9227 {
9228         return !((a - b) & 0x80000000);
9229 }
9230
9231 static bool page_flip_finished(struct intel_crtc *crtc)
9232 {
9233         struct drm_device *dev = crtc->base.dev;
9234         struct drm_i915_private *dev_priv = dev->dev_private;
9235
9236         /*
9237          * The relevant registers doen't exist on pre-ctg.
9238          * As the flip done interrupt doesn't trigger for mmio
9239          * flips on gmch platforms, a flip count check isn't
9240          * really needed there. But since ctg has the registers,
9241          * include it in the check anyway.
9242          */
9243         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9244                 return true;
9245
9246         /*
9247          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9248          * used the same base address. In that case the mmio flip might
9249          * have completed, but the CS hasn't even executed the flip yet.
9250          *
9251          * A flip count check isn't enough as the CS might have updated
9252          * the base address just after start of vblank, but before we
9253          * managed to process the interrupt. This means we'd complete the
9254          * CS flip too soon.
9255          *
9256          * Combining both checks should get us a good enough result. It may
9257          * still happen that the CS flip has been executed, but has not
9258          * yet actually completed. But in case the base address is the same
9259          * anyway, we don't really care.
9260          */
9261         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9262                 crtc->unpin_work->gtt_offset &&
9263                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9264                                     crtc->unpin_work->flip_count);
9265 }
9266
9267 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9268 {
9269         struct drm_i915_private *dev_priv = dev->dev_private;
9270         struct intel_crtc *intel_crtc =
9271                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9272         unsigned long flags;
9273
9274         /* NB: An MMIO update of the plane base pointer will also
9275          * generate a page-flip completion irq, i.e. every modeset
9276          * is also accompanied by a spurious intel_prepare_page_flip().
9277          */
9278         spin_lock_irqsave(&dev->event_lock, flags);
9279         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9280                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9281         spin_unlock_irqrestore(&dev->event_lock, flags);
9282 }
9283
9284 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9285 {
9286         /* Ensure that the work item is consistent when activating it ... */
9287         smp_wmb();
9288         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9289         /* and that it is marked active as soon as the irq could fire. */
9290         smp_wmb();
9291 }
9292
9293 static int intel_gen2_queue_flip(struct drm_device *dev,
9294                                  struct drm_crtc *crtc,
9295                                  struct drm_framebuffer *fb,
9296                                  struct drm_i915_gem_object *obj,
9297                                  struct intel_engine_cs *ring,
9298                                  uint32_t flags)
9299 {
9300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9301         u32 flip_mask;
9302         int ret;
9303
9304         ret = intel_ring_begin(ring, 6);
9305         if (ret)
9306                 return ret;
9307
9308         /* Can't queue multiple flips, so wait for the previous
9309          * one to finish before executing the next.
9310          */
9311         if (intel_crtc->plane)
9312                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9313         else
9314                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9315         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9316         intel_ring_emit(ring, MI_NOOP);
9317         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9318                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9319         intel_ring_emit(ring, fb->pitches[0]);
9320         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9321         intel_ring_emit(ring, 0); /* aux display base address, unused */
9322
9323         intel_mark_page_flip_active(intel_crtc);
9324         __intel_ring_advance(ring);
9325         return 0;
9326 }
9327
9328 static int intel_gen3_queue_flip(struct drm_device *dev,
9329                                  struct drm_crtc *crtc,
9330                                  struct drm_framebuffer *fb,
9331                                  struct drm_i915_gem_object *obj,
9332                                  struct intel_engine_cs *ring,
9333                                  uint32_t flags)
9334 {
9335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9336         u32 flip_mask;
9337         int ret;
9338
9339         ret = intel_ring_begin(ring, 6);
9340         if (ret)
9341                 return ret;
9342
9343         if (intel_crtc->plane)
9344                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9345         else
9346                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9347         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9348         intel_ring_emit(ring, MI_NOOP);
9349         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9350                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9351         intel_ring_emit(ring, fb->pitches[0]);
9352         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9353         intel_ring_emit(ring, MI_NOOP);
9354
9355         intel_mark_page_flip_active(intel_crtc);
9356         __intel_ring_advance(ring);
9357         return 0;
9358 }
9359
9360 static int intel_gen4_queue_flip(struct drm_device *dev,
9361                                  struct drm_crtc *crtc,
9362                                  struct drm_framebuffer *fb,
9363                                  struct drm_i915_gem_object *obj,
9364                                  struct intel_engine_cs *ring,
9365                                  uint32_t flags)
9366 {
9367         struct drm_i915_private *dev_priv = dev->dev_private;
9368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9369         uint32_t pf, pipesrc;
9370         int ret;
9371
9372         ret = intel_ring_begin(ring, 4);
9373         if (ret)
9374                 return ret;
9375
9376         /* i965+ uses the linear or tiled offsets from the
9377          * Display Registers (which do not change across a page-flip)
9378          * so we need only reprogram the base address.
9379          */
9380         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9381                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9382         intel_ring_emit(ring, fb->pitches[0]);
9383         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9384                         obj->tiling_mode);
9385
9386         /* XXX Enabling the panel-fitter across page-flip is so far
9387          * untested on non-native modes, so ignore it for now.
9388          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9389          */
9390         pf = 0;
9391         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9392         intel_ring_emit(ring, pf | pipesrc);
9393
9394         intel_mark_page_flip_active(intel_crtc);
9395         __intel_ring_advance(ring);
9396         return 0;
9397 }
9398
9399 static int intel_gen6_queue_flip(struct drm_device *dev,
9400                                  struct drm_crtc *crtc,
9401                                  struct drm_framebuffer *fb,
9402                                  struct drm_i915_gem_object *obj,
9403                                  struct intel_engine_cs *ring,
9404                                  uint32_t flags)
9405 {
9406         struct drm_i915_private *dev_priv = dev->dev_private;
9407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9408         uint32_t pf, pipesrc;
9409         int ret;
9410
9411         ret = intel_ring_begin(ring, 4);
9412         if (ret)
9413                 return ret;
9414
9415         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9416                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9417         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9418         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9419
9420         /* Contrary to the suggestions in the documentation,
9421          * "Enable Panel Fitter" does not seem to be required when page
9422          * flipping with a non-native mode, and worse causes a normal
9423          * modeset to fail.
9424          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9425          */
9426         pf = 0;
9427         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9428         intel_ring_emit(ring, pf | pipesrc);
9429
9430         intel_mark_page_flip_active(intel_crtc);
9431         __intel_ring_advance(ring);
9432         return 0;
9433 }
9434
9435 static int intel_gen7_queue_flip(struct drm_device *dev,
9436                                  struct drm_crtc *crtc,
9437                                  struct drm_framebuffer *fb,
9438                                  struct drm_i915_gem_object *obj,
9439                                  struct intel_engine_cs *ring,
9440                                  uint32_t flags)
9441 {
9442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9443         uint32_t plane_bit = 0;
9444         int len, ret;
9445
9446         switch (intel_crtc->plane) {
9447         case PLANE_A:
9448                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9449                 break;
9450         case PLANE_B:
9451                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9452                 break;
9453         case PLANE_C:
9454                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9455                 break;
9456         default:
9457                 WARN_ONCE(1, "unknown plane in flip command\n");
9458                 return -ENODEV;
9459         }
9460
9461         len = 4;
9462         if (ring->id == RCS) {
9463                 len += 6;
9464                 /*
9465                  * On Gen 8, SRM is now taking an extra dword to accommodate
9466                  * 48bits addresses, and we need a NOOP for the batch size to
9467                  * stay even.
9468                  */
9469                 if (IS_GEN8(dev))
9470                         len += 2;
9471         }
9472
9473         /*
9474          * BSpec MI_DISPLAY_FLIP for IVB:
9475          * "The full packet must be contained within the same cache line."
9476          *
9477          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9478          * cacheline, if we ever start emitting more commands before
9479          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9480          * then do the cacheline alignment, and finally emit the
9481          * MI_DISPLAY_FLIP.
9482          */
9483         ret = intel_ring_cacheline_align(ring);
9484         if (ret)
9485                 return ret;
9486
9487         ret = intel_ring_begin(ring, len);
9488         if (ret)
9489                 return ret;
9490
9491         /* Unmask the flip-done completion message. Note that the bspec says that
9492          * we should do this for both the BCS and RCS, and that we must not unmask
9493          * more than one flip event at any time (or ensure that one flip message
9494          * can be sent by waiting for flip-done prior to queueing new flips).
9495          * Experimentation says that BCS works despite DERRMR masking all
9496          * flip-done completion events and that unmasking all planes at once
9497          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9498          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9499          */
9500         if (ring->id == RCS) {
9501                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9502                 intel_ring_emit(ring, DERRMR);
9503                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9504                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9505                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9506                 if (IS_GEN8(dev))
9507                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9508                                               MI_SRM_LRM_GLOBAL_GTT);
9509                 else
9510                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9511                                               MI_SRM_LRM_GLOBAL_GTT);
9512                 intel_ring_emit(ring, DERRMR);
9513                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9514                 if (IS_GEN8(dev)) {
9515                         intel_ring_emit(ring, 0);
9516                         intel_ring_emit(ring, MI_NOOP);
9517                 }
9518         }
9519
9520         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9521         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9522         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9523         intel_ring_emit(ring, (MI_NOOP));
9524
9525         intel_mark_page_flip_active(intel_crtc);
9526         __intel_ring_advance(ring);
9527         return 0;
9528 }
9529
9530 static bool use_mmio_flip(struct intel_engine_cs *ring,
9531                           struct drm_i915_gem_object *obj)
9532 {
9533         /*
9534          * This is not being used for older platforms, because
9535          * non-availability of flip done interrupt forces us to use
9536          * CS flips. Older platforms derive flip done using some clever
9537          * tricks involving the flip_pending status bits and vblank irqs.
9538          * So using MMIO flips there would disrupt this mechanism.
9539          */
9540
9541         if (ring == NULL)
9542                 return true;
9543
9544         if (INTEL_INFO(ring->dev)->gen < 5)
9545                 return false;
9546
9547         if (i915.use_mmio_flip < 0)
9548                 return false;
9549         else if (i915.use_mmio_flip > 0)
9550                 return true;
9551         else if (i915.enable_execlists)
9552                 return true;
9553         else
9554                 return ring != obj->ring;
9555 }
9556
9557 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9558 {
9559         struct drm_device *dev = intel_crtc->base.dev;
9560         struct drm_i915_private *dev_priv = dev->dev_private;
9561         struct intel_framebuffer *intel_fb =
9562                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9563         struct drm_i915_gem_object *obj = intel_fb->obj;
9564         u32 dspcntr;
9565         u32 reg;
9566
9567         intel_mark_page_flip_active(intel_crtc);
9568
9569         reg = DSPCNTR(intel_crtc->plane);
9570         dspcntr = I915_READ(reg);
9571
9572         if (INTEL_INFO(dev)->gen >= 4) {
9573                 if (obj->tiling_mode != I915_TILING_NONE)
9574                         dspcntr |= DISPPLANE_TILED;
9575                 else
9576                         dspcntr &= ~DISPPLANE_TILED;
9577         }
9578         I915_WRITE(reg, dspcntr);
9579
9580         I915_WRITE(DSPSURF(intel_crtc->plane),
9581                    intel_crtc->unpin_work->gtt_offset);
9582         POSTING_READ(DSPSURF(intel_crtc->plane));
9583 }
9584
9585 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9586 {
9587         struct intel_engine_cs *ring;
9588         int ret;
9589
9590         lockdep_assert_held(&obj->base.dev->struct_mutex);
9591
9592         if (!obj->last_write_seqno)
9593                 return 0;
9594
9595         ring = obj->ring;
9596
9597         if (i915_seqno_passed(ring->get_seqno(ring, true),
9598                               obj->last_write_seqno))
9599                 return 0;
9600
9601         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9602         if (ret)
9603                 return ret;
9604
9605         if (WARN_ON(!ring->irq_get(ring)))
9606                 return 0;
9607
9608         return 1;
9609 }
9610
9611 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9612 {
9613         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9614         struct intel_crtc *intel_crtc;
9615         unsigned long irq_flags;
9616         u32 seqno;
9617
9618         seqno = ring->get_seqno(ring, false);
9619
9620         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9621         for_each_intel_crtc(ring->dev, intel_crtc) {
9622                 struct intel_mmio_flip *mmio_flip;
9623
9624                 mmio_flip = &intel_crtc->mmio_flip;
9625                 if (mmio_flip->seqno == 0)
9626                         continue;
9627
9628                 if (ring->id != mmio_flip->ring_id)
9629                         continue;
9630
9631                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9632                         intel_do_mmio_flip(intel_crtc);
9633                         mmio_flip->seqno = 0;
9634                         ring->irq_put(ring);
9635                 }
9636         }
9637         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9638 }
9639
9640 static int intel_queue_mmio_flip(struct drm_device *dev,
9641                                  struct drm_crtc *crtc,
9642                                  struct drm_framebuffer *fb,
9643                                  struct drm_i915_gem_object *obj,
9644                                  struct intel_engine_cs *ring,
9645                                  uint32_t flags)
9646 {
9647         struct drm_i915_private *dev_priv = dev->dev_private;
9648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9649         unsigned long irq_flags;
9650         int ret;
9651
9652         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9653                 return -EBUSY;
9654
9655         ret = intel_postpone_flip(obj);
9656         if (ret < 0)
9657                 return ret;
9658         if (ret == 0) {
9659                 intel_do_mmio_flip(intel_crtc);
9660                 return 0;
9661         }
9662
9663         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9664         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9665         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9666         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9667
9668         /*
9669          * Double check to catch cases where irq fired before
9670          * mmio flip data was ready
9671          */
9672         intel_notify_mmio_flip(obj->ring);
9673         return 0;
9674 }
9675
9676 static int intel_default_queue_flip(struct drm_device *dev,
9677                                     struct drm_crtc *crtc,
9678                                     struct drm_framebuffer *fb,
9679                                     struct drm_i915_gem_object *obj,
9680                                     struct intel_engine_cs *ring,
9681                                     uint32_t flags)
9682 {
9683         return -ENODEV;
9684 }
9685
9686 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9687                                 struct drm_framebuffer *fb,
9688                                 struct drm_pending_vblank_event *event,
9689                                 uint32_t page_flip_flags)
9690 {
9691         struct drm_device *dev = crtc->dev;
9692         struct drm_i915_private *dev_priv = dev->dev_private;
9693         struct drm_framebuffer *old_fb = crtc->primary->fb;
9694         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9696         enum pipe pipe = intel_crtc->pipe;
9697         struct intel_unpin_work *work;
9698         struct intel_engine_cs *ring;
9699         unsigned long flags;
9700         int ret;
9701
9702         /*
9703          * drm_mode_page_flip_ioctl() should already catch this, but double
9704          * check to be safe.  In the future we may enable pageflipping from
9705          * a disabled primary plane.
9706          */
9707         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9708                 return -EBUSY;
9709
9710         /* Can't change pixel format via MI display flips. */
9711         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9712                 return -EINVAL;
9713
9714         /*
9715          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9716          * Note that pitch changes could also affect these register.
9717          */
9718         if (INTEL_INFO(dev)->gen > 3 &&
9719             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9720              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9721                 return -EINVAL;
9722
9723         if (i915_terminally_wedged(&dev_priv->gpu_error))
9724                 goto out_hang;
9725
9726         work = kzalloc(sizeof(*work), GFP_KERNEL);
9727         if (work == NULL)
9728                 return -ENOMEM;
9729
9730         work->event = event;
9731         work->crtc = crtc;
9732         work->old_fb_obj = intel_fb_obj(old_fb);
9733         INIT_WORK(&work->work, intel_unpin_work_fn);
9734
9735         ret = drm_crtc_vblank_get(crtc);
9736         if (ret)
9737                 goto free_work;
9738
9739         /* We borrow the event spin lock for protecting unpin_work */
9740         spin_lock_irqsave(&dev->event_lock, flags);
9741         if (intel_crtc->unpin_work) {
9742                 spin_unlock_irqrestore(&dev->event_lock, flags);
9743                 kfree(work);
9744                 drm_crtc_vblank_put(crtc);
9745
9746                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9747                 return -EBUSY;
9748         }
9749         intel_crtc->unpin_work = work;
9750         spin_unlock_irqrestore(&dev->event_lock, flags);
9751
9752         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9753                 flush_workqueue(dev_priv->wq);
9754
9755         ret = i915_mutex_lock_interruptible(dev);
9756         if (ret)
9757                 goto cleanup;
9758
9759         /* Reference the objects for the scheduled work. */
9760         drm_gem_object_reference(&work->old_fb_obj->base);
9761         drm_gem_object_reference(&obj->base);
9762
9763         crtc->primary->fb = fb;
9764
9765         work->pending_flip_obj = obj;
9766
9767         work->enable_stall_check = true;
9768
9769         atomic_inc(&intel_crtc->unpin_work_count);
9770         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9771
9772         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9773                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9774
9775         if (IS_VALLEYVIEW(dev)) {
9776                 ring = &dev_priv->ring[BCS];
9777                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9778                         /* vlv: DISPLAY_FLIP fails to change tiling */
9779                         ring = NULL;
9780         } else if (IS_IVYBRIDGE(dev)) {
9781                 ring = &dev_priv->ring[BCS];
9782         } else if (INTEL_INFO(dev)->gen >= 7) {
9783                 ring = obj->ring;
9784                 if (ring == NULL || ring->id != RCS)
9785                         ring = &dev_priv->ring[BCS];
9786         } else {
9787                 ring = &dev_priv->ring[RCS];
9788         }
9789
9790         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9791         if (ret)
9792                 goto cleanup_pending;
9793
9794         work->gtt_offset =
9795                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9796
9797         if (use_mmio_flip(ring, obj))
9798                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9799                                             page_flip_flags);
9800         else
9801                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9802                                 page_flip_flags);
9803         if (ret)
9804                 goto cleanup_unpin;
9805
9806         i915_gem_track_fb(work->old_fb_obj, obj,
9807                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9808
9809         intel_disable_fbc(dev);
9810         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9811         mutex_unlock(&dev->struct_mutex);
9812
9813         trace_i915_flip_request(intel_crtc->plane, obj);
9814
9815         return 0;
9816
9817 cleanup_unpin:
9818         intel_unpin_fb_obj(obj);
9819 cleanup_pending:
9820         atomic_dec(&intel_crtc->unpin_work_count);
9821         crtc->primary->fb = old_fb;
9822         drm_gem_object_unreference(&work->old_fb_obj->base);
9823         drm_gem_object_unreference(&obj->base);
9824         mutex_unlock(&dev->struct_mutex);
9825
9826 cleanup:
9827         spin_lock_irqsave(&dev->event_lock, flags);
9828         intel_crtc->unpin_work = NULL;
9829         spin_unlock_irqrestore(&dev->event_lock, flags);
9830
9831         drm_crtc_vblank_put(crtc);
9832 free_work:
9833         kfree(work);
9834
9835         if (ret == -EIO) {
9836 out_hang:
9837                 intel_crtc_wait_for_pending_flips(crtc);
9838                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9839                 if (ret == 0 && event)
9840                         drm_send_vblank_event(dev, pipe, event);
9841         }
9842         return ret;
9843 }
9844
9845 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9846         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9847         .load_lut = intel_crtc_load_lut,
9848 };
9849
9850 /**
9851  * intel_modeset_update_staged_output_state
9852  *
9853  * Updates the staged output configuration state, e.g. after we've read out the
9854  * current hw state.
9855  */
9856 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9857 {
9858         struct intel_crtc *crtc;
9859         struct intel_encoder *encoder;
9860         struct intel_connector *connector;
9861
9862         list_for_each_entry(connector, &dev->mode_config.connector_list,
9863                             base.head) {
9864                 connector->new_encoder =
9865                         to_intel_encoder(connector->base.encoder);
9866         }
9867
9868         for_each_intel_encoder(dev, encoder) {
9869                 encoder->new_crtc =
9870                         to_intel_crtc(encoder->base.crtc);
9871         }
9872
9873         for_each_intel_crtc(dev, crtc) {
9874                 crtc->new_enabled = crtc->base.enabled;
9875
9876                 if (crtc->new_enabled)
9877                         crtc->new_config = &crtc->config;
9878                 else
9879                         crtc->new_config = NULL;
9880         }
9881 }
9882
9883 /**
9884  * intel_modeset_commit_output_state
9885  *
9886  * This function copies the stage display pipe configuration to the real one.
9887  */
9888 static void intel_modeset_commit_output_state(struct drm_device *dev)
9889 {
9890         struct intel_crtc *crtc;
9891         struct intel_encoder *encoder;
9892         struct intel_connector *connector;
9893
9894         list_for_each_entry(connector, &dev->mode_config.connector_list,
9895                             base.head) {
9896                 connector->base.encoder = &connector->new_encoder->base;
9897         }
9898
9899         for_each_intel_encoder(dev, encoder) {
9900                 encoder->base.crtc = &encoder->new_crtc->base;
9901         }
9902
9903         for_each_intel_crtc(dev, crtc) {
9904                 crtc->base.enabled = crtc->new_enabled;
9905         }
9906 }
9907
9908 static void
9909 connected_sink_compute_bpp(struct intel_connector *connector,
9910                            struct intel_crtc_config *pipe_config)
9911 {
9912         int bpp = pipe_config->pipe_bpp;
9913
9914         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9915                 connector->base.base.id,
9916                 connector->base.name);
9917
9918         /* Don't use an invalid EDID bpc value */
9919         if (connector->base.display_info.bpc &&
9920             connector->base.display_info.bpc * 3 < bpp) {
9921                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9922                               bpp, connector->base.display_info.bpc*3);
9923                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9924         }
9925
9926         /* Clamp bpp to 8 on screens without EDID 1.4 */
9927         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9928                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9929                               bpp);
9930                 pipe_config->pipe_bpp = 24;
9931         }
9932 }
9933
9934 static int
9935 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9936                           struct drm_framebuffer *fb,
9937                           struct intel_crtc_config *pipe_config)
9938 {
9939         struct drm_device *dev = crtc->base.dev;
9940         struct intel_connector *connector;
9941         int bpp;
9942
9943         switch (fb->pixel_format) {
9944         case DRM_FORMAT_C8:
9945                 bpp = 8*3; /* since we go through a colormap */
9946                 break;
9947         case DRM_FORMAT_XRGB1555:
9948         case DRM_FORMAT_ARGB1555:
9949                 /* checked in intel_framebuffer_init already */
9950                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9951                         return -EINVAL;
9952         case DRM_FORMAT_RGB565:
9953                 bpp = 6*3; /* min is 18bpp */
9954                 break;
9955         case DRM_FORMAT_XBGR8888:
9956         case DRM_FORMAT_ABGR8888:
9957                 /* checked in intel_framebuffer_init already */
9958                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9959                         return -EINVAL;
9960         case DRM_FORMAT_XRGB8888:
9961         case DRM_FORMAT_ARGB8888:
9962                 bpp = 8*3;
9963                 break;
9964         case DRM_FORMAT_XRGB2101010:
9965         case DRM_FORMAT_ARGB2101010:
9966         case DRM_FORMAT_XBGR2101010:
9967         case DRM_FORMAT_ABGR2101010:
9968                 /* checked in intel_framebuffer_init already */
9969                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9970                         return -EINVAL;
9971                 bpp = 10*3;
9972                 break;
9973         /* TODO: gen4+ supports 16 bpc floating point, too. */
9974         default:
9975                 DRM_DEBUG_KMS("unsupported depth\n");
9976                 return -EINVAL;
9977         }
9978
9979         pipe_config->pipe_bpp = bpp;
9980
9981         /* Clamp display bpp to EDID value */
9982         list_for_each_entry(connector, &dev->mode_config.connector_list,
9983                             base.head) {
9984                 if (!connector->new_encoder ||
9985                     connector->new_encoder->new_crtc != crtc)
9986                         continue;
9987
9988                 connected_sink_compute_bpp(connector, pipe_config);
9989         }
9990
9991         return bpp;
9992 }
9993
9994 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9995 {
9996         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9997                         "type: 0x%x flags: 0x%x\n",
9998                 mode->crtc_clock,
9999                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10000                 mode->crtc_hsync_end, mode->crtc_htotal,
10001                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10002                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10003 }
10004
10005 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10006                                    struct intel_crtc_config *pipe_config,
10007                                    const char *context)
10008 {
10009         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10010                       context, pipe_name(crtc->pipe));
10011
10012         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10013         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10014                       pipe_config->pipe_bpp, pipe_config->dither);
10015         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10016                       pipe_config->has_pch_encoder,
10017                       pipe_config->fdi_lanes,
10018                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10019                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10020                       pipe_config->fdi_m_n.tu);
10021         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10022                       pipe_config->has_dp_encoder,
10023                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10024                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10025                       pipe_config->dp_m_n.tu);
10026
10027         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10028                       pipe_config->has_dp_encoder,
10029                       pipe_config->dp_m2_n2.gmch_m,
10030                       pipe_config->dp_m2_n2.gmch_n,
10031                       pipe_config->dp_m2_n2.link_m,
10032                       pipe_config->dp_m2_n2.link_n,
10033                       pipe_config->dp_m2_n2.tu);
10034
10035         DRM_DEBUG_KMS("requested mode:\n");
10036         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10037         DRM_DEBUG_KMS("adjusted mode:\n");
10038         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10039         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10040         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10041         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10042                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10043         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10044                       pipe_config->gmch_pfit.control,
10045                       pipe_config->gmch_pfit.pgm_ratios,
10046                       pipe_config->gmch_pfit.lvds_border_bits);
10047         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10048                       pipe_config->pch_pfit.pos,
10049                       pipe_config->pch_pfit.size,
10050                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10051         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10052         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10053 }
10054
10055 static bool encoders_cloneable(const struct intel_encoder *a,
10056                                const struct intel_encoder *b)
10057 {
10058         /* masks could be asymmetric, so check both ways */
10059         return a == b || (a->cloneable & (1 << b->type) &&
10060                           b->cloneable & (1 << a->type));
10061 }
10062
10063 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10064                                          struct intel_encoder *encoder)
10065 {
10066         struct drm_device *dev = crtc->base.dev;
10067         struct intel_encoder *source_encoder;
10068
10069         for_each_intel_encoder(dev, source_encoder) {
10070                 if (source_encoder->new_crtc != crtc)
10071                         continue;
10072
10073                 if (!encoders_cloneable(encoder, source_encoder))
10074                         return false;
10075         }
10076
10077         return true;
10078 }
10079
10080 static bool check_encoder_cloning(struct intel_crtc *crtc)
10081 {
10082         struct drm_device *dev = crtc->base.dev;
10083         struct intel_encoder *encoder;
10084
10085         for_each_intel_encoder(dev, encoder) {
10086                 if (encoder->new_crtc != crtc)
10087                         continue;
10088
10089                 if (!check_single_encoder_cloning(crtc, encoder))
10090                         return false;
10091         }
10092
10093         return true;
10094 }
10095
10096 static struct intel_crtc_config *
10097 intel_modeset_pipe_config(struct drm_crtc *crtc,
10098                           struct drm_framebuffer *fb,
10099                           struct drm_display_mode *mode)
10100 {
10101         struct drm_device *dev = crtc->dev;
10102         struct intel_encoder *encoder;
10103         struct intel_crtc_config *pipe_config;
10104         int plane_bpp, ret = -EINVAL;
10105         bool retry = true;
10106
10107         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10108                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10109                 return ERR_PTR(-EINVAL);
10110         }
10111
10112         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10113         if (!pipe_config)
10114                 return ERR_PTR(-ENOMEM);
10115
10116         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10117         drm_mode_copy(&pipe_config->requested_mode, mode);
10118
10119         pipe_config->cpu_transcoder =
10120                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10121         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10122
10123         /*
10124          * Sanitize sync polarity flags based on requested ones. If neither
10125          * positive or negative polarity is requested, treat this as meaning
10126          * negative polarity.
10127          */
10128         if (!(pipe_config->adjusted_mode.flags &
10129               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10130                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10131
10132         if (!(pipe_config->adjusted_mode.flags &
10133               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10134                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10135
10136         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10137          * plane pixel format and any sink constraints into account. Returns the
10138          * source plane bpp so that dithering can be selected on mismatches
10139          * after encoders and crtc also have had their say. */
10140         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10141                                               fb, pipe_config);
10142         if (plane_bpp < 0)
10143                 goto fail;
10144
10145         /*
10146          * Determine the real pipe dimensions. Note that stereo modes can
10147          * increase the actual pipe size due to the frame doubling and
10148          * insertion of additional space for blanks between the frame. This
10149          * is stored in the crtc timings. We use the requested mode to do this
10150          * computation to clearly distinguish it from the adjusted mode, which
10151          * can be changed by the connectors in the below retry loop.
10152          */
10153         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10154         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10155         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10156
10157 encoder_retry:
10158         /* Ensure the port clock defaults are reset when retrying. */
10159         pipe_config->port_clock = 0;
10160         pipe_config->pixel_multiplier = 1;
10161
10162         /* Fill in default crtc timings, allow encoders to overwrite them. */
10163         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10164
10165         /* Pass our mode to the connectors and the CRTC to give them a chance to
10166          * adjust it according to limitations or connector properties, and also
10167          * a chance to reject the mode entirely.
10168          */
10169         for_each_intel_encoder(dev, encoder) {
10170
10171                 if (&encoder->new_crtc->base != crtc)
10172                         continue;
10173
10174                 if (!(encoder->compute_config(encoder, pipe_config))) {
10175                         DRM_DEBUG_KMS("Encoder config failure\n");
10176                         goto fail;
10177                 }
10178         }
10179
10180         /* Set default port clock if not overwritten by the encoder. Needs to be
10181          * done afterwards in case the encoder adjusts the mode. */
10182         if (!pipe_config->port_clock)
10183                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10184                         * pipe_config->pixel_multiplier;
10185
10186         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10187         if (ret < 0) {
10188                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10189                 goto fail;
10190         }
10191
10192         if (ret == RETRY) {
10193                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10194                         ret = -EINVAL;
10195                         goto fail;
10196                 }
10197
10198                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10199                 retry = false;
10200                 goto encoder_retry;
10201         }
10202
10203         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10204         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10205                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10206
10207         return pipe_config;
10208 fail:
10209         kfree(pipe_config);
10210         return ERR_PTR(ret);
10211 }
10212
10213 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10214  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10215 static void
10216 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10217                              unsigned *prepare_pipes, unsigned *disable_pipes)
10218 {
10219         struct intel_crtc *intel_crtc;
10220         struct drm_device *dev = crtc->dev;
10221         struct intel_encoder *encoder;
10222         struct intel_connector *connector;
10223         struct drm_crtc *tmp_crtc;
10224
10225         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10226
10227         /* Check which crtcs have changed outputs connected to them, these need
10228          * to be part of the prepare_pipes mask. We don't (yet) support global
10229          * modeset across multiple crtcs, so modeset_pipes will only have one
10230          * bit set at most. */
10231         list_for_each_entry(connector, &dev->mode_config.connector_list,
10232                             base.head) {
10233                 if (connector->base.encoder == &connector->new_encoder->base)
10234                         continue;
10235
10236                 if (connector->base.encoder) {
10237                         tmp_crtc = connector->base.encoder->crtc;
10238
10239                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10240                 }
10241
10242                 if (connector->new_encoder)
10243                         *prepare_pipes |=
10244                                 1 << connector->new_encoder->new_crtc->pipe;
10245         }
10246
10247         for_each_intel_encoder(dev, encoder) {
10248                 if (encoder->base.crtc == &encoder->new_crtc->base)
10249                         continue;
10250
10251                 if (encoder->base.crtc) {
10252                         tmp_crtc = encoder->base.crtc;
10253
10254                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10255                 }
10256
10257                 if (encoder->new_crtc)
10258                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10259         }
10260
10261         /* Check for pipes that will be enabled/disabled ... */
10262         for_each_intel_crtc(dev, intel_crtc) {
10263                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10264                         continue;
10265
10266                 if (!intel_crtc->new_enabled)
10267                         *disable_pipes |= 1 << intel_crtc->pipe;
10268                 else
10269                         *prepare_pipes |= 1 << intel_crtc->pipe;
10270         }
10271
10272
10273         /* set_mode is also used to update properties on life display pipes. */
10274         intel_crtc = to_intel_crtc(crtc);
10275         if (intel_crtc->new_enabled)
10276                 *prepare_pipes |= 1 << intel_crtc->pipe;
10277
10278         /*
10279          * For simplicity do a full modeset on any pipe where the output routing
10280          * changed. We could be more clever, but that would require us to be
10281          * more careful with calling the relevant encoder->mode_set functions.
10282          */
10283         if (*prepare_pipes)
10284                 *modeset_pipes = *prepare_pipes;
10285
10286         /* ... and mask these out. */
10287         *modeset_pipes &= ~(*disable_pipes);
10288         *prepare_pipes &= ~(*disable_pipes);
10289
10290         /*
10291          * HACK: We don't (yet) fully support global modesets. intel_set_config
10292          * obies this rule, but the modeset restore mode of
10293          * intel_modeset_setup_hw_state does not.
10294          */
10295         *modeset_pipes &= 1 << intel_crtc->pipe;
10296         *prepare_pipes &= 1 << intel_crtc->pipe;
10297
10298         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10299                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10300 }
10301
10302 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10303 {
10304         struct drm_encoder *encoder;
10305         struct drm_device *dev = crtc->dev;
10306
10307         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10308                 if (encoder->crtc == crtc)
10309                         return true;
10310
10311         return false;
10312 }
10313
10314 static void
10315 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10316 {
10317         struct intel_encoder *intel_encoder;
10318         struct intel_crtc *intel_crtc;
10319         struct drm_connector *connector;
10320
10321         for_each_intel_encoder(dev, intel_encoder) {
10322                 if (!intel_encoder->base.crtc)
10323                         continue;
10324
10325                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10326
10327                 if (prepare_pipes & (1 << intel_crtc->pipe))
10328                         intel_encoder->connectors_active = false;
10329         }
10330
10331         intel_modeset_commit_output_state(dev);
10332
10333         /* Double check state. */
10334         for_each_intel_crtc(dev, intel_crtc) {
10335                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10336                 WARN_ON(intel_crtc->new_config &&
10337                         intel_crtc->new_config != &intel_crtc->config);
10338                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10339         }
10340
10341         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10342                 if (!connector->encoder || !connector->encoder->crtc)
10343                         continue;
10344
10345                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10346
10347                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10348                         struct drm_property *dpms_property =
10349                                 dev->mode_config.dpms_property;
10350
10351                         connector->dpms = DRM_MODE_DPMS_ON;
10352                         drm_object_property_set_value(&connector->base,
10353                                                          dpms_property,
10354                                                          DRM_MODE_DPMS_ON);
10355
10356                         intel_encoder = to_intel_encoder(connector->encoder);
10357                         intel_encoder->connectors_active = true;
10358                 }
10359         }
10360
10361 }
10362
10363 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10364 {
10365         int diff;
10366
10367         if (clock1 == clock2)
10368                 return true;
10369
10370         if (!clock1 || !clock2)
10371                 return false;
10372
10373         diff = abs(clock1 - clock2);
10374
10375         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10376                 return true;
10377
10378         return false;
10379 }
10380
10381 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10382         list_for_each_entry((intel_crtc), \
10383                             &(dev)->mode_config.crtc_list, \
10384                             base.head) \
10385                 if (mask & (1 <<(intel_crtc)->pipe))
10386
10387 static bool
10388 intel_pipe_config_compare(struct drm_device *dev,
10389                           struct intel_crtc_config *current_config,
10390                           struct intel_crtc_config *pipe_config)
10391 {
10392 #define PIPE_CONF_CHECK_X(name) \
10393         if (current_config->name != pipe_config->name) { \
10394                 DRM_ERROR("mismatch in " #name " " \
10395                           "(expected 0x%08x, found 0x%08x)\n", \
10396                           current_config->name, \
10397                           pipe_config->name); \
10398                 return false; \
10399         }
10400
10401 #define PIPE_CONF_CHECK_I(name) \
10402         if (current_config->name != pipe_config->name) { \
10403                 DRM_ERROR("mismatch in " #name " " \
10404                           "(expected %i, found %i)\n", \
10405                           current_config->name, \
10406                           pipe_config->name); \
10407                 return false; \
10408         }
10409
10410 /* This is required for BDW+ where there is only one set of registers for
10411  * switching between high and low RR.
10412  * This macro can be used whenever a comparison has to be made between one
10413  * hw state and multiple sw state variables.
10414  */
10415 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10416         if ((current_config->name != pipe_config->name) && \
10417                 (current_config->alt_name != pipe_config->name)) { \
10418                         DRM_ERROR("mismatch in " #name " " \
10419                                   "(expected %i or %i, found %i)\n", \
10420                                   current_config->name, \
10421                                   current_config->alt_name, \
10422                                   pipe_config->name); \
10423                         return false; \
10424         }
10425
10426 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10427         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10428                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10429                           "(expected %i, found %i)\n", \
10430                           current_config->name & (mask), \
10431                           pipe_config->name & (mask)); \
10432                 return false; \
10433         }
10434
10435 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10436         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10437                 DRM_ERROR("mismatch in " #name " " \
10438                           "(expected %i, found %i)\n", \
10439                           current_config->name, \
10440                           pipe_config->name); \
10441                 return false; \
10442         }
10443
10444 #define PIPE_CONF_QUIRK(quirk)  \
10445         ((current_config->quirks | pipe_config->quirks) & (quirk))
10446
10447         PIPE_CONF_CHECK_I(cpu_transcoder);
10448
10449         PIPE_CONF_CHECK_I(has_pch_encoder);
10450         PIPE_CONF_CHECK_I(fdi_lanes);
10451         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10452         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10453         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10454         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10455         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10456
10457         PIPE_CONF_CHECK_I(has_dp_encoder);
10458
10459         if (INTEL_INFO(dev)->gen < 8) {
10460                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10461                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10462                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10463                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10464                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10465
10466                 if (current_config->has_drrs) {
10467                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10468                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10469                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10470                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10471                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10472                 }
10473         } else {
10474                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10475                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10476                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10477                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10478                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10479         }
10480
10481         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10482         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10483         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10484         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10485         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10486         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10487
10488         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10489         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10490         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10491         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10492         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10493         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10494
10495         PIPE_CONF_CHECK_I(pixel_multiplier);
10496         PIPE_CONF_CHECK_I(has_hdmi_sink);
10497         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10498             IS_VALLEYVIEW(dev))
10499                 PIPE_CONF_CHECK_I(limited_color_range);
10500
10501         PIPE_CONF_CHECK_I(has_audio);
10502
10503         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10504                               DRM_MODE_FLAG_INTERLACE);
10505
10506         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10507                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10508                                       DRM_MODE_FLAG_PHSYNC);
10509                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10510                                       DRM_MODE_FLAG_NHSYNC);
10511                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10512                                       DRM_MODE_FLAG_PVSYNC);
10513                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10514                                       DRM_MODE_FLAG_NVSYNC);
10515         }
10516
10517         PIPE_CONF_CHECK_I(pipe_src_w);
10518         PIPE_CONF_CHECK_I(pipe_src_h);
10519
10520         /*
10521          * FIXME: BIOS likes to set up a cloned config with lvds+external
10522          * screen. Since we don't yet re-compute the pipe config when moving
10523          * just the lvds port away to another pipe the sw tracking won't match.
10524          *
10525          * Proper atomic modesets with recomputed global state will fix this.
10526          * Until then just don't check gmch state for inherited modes.
10527          */
10528         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10529                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10530                 /* pfit ratios are autocomputed by the hw on gen4+ */
10531                 if (INTEL_INFO(dev)->gen < 4)
10532                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10533                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10534         }
10535
10536         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10537         if (current_config->pch_pfit.enabled) {
10538                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10539                 PIPE_CONF_CHECK_I(pch_pfit.size);
10540         }
10541
10542         /* BDW+ don't expose a synchronous way to read the state */
10543         if (IS_HASWELL(dev))
10544                 PIPE_CONF_CHECK_I(ips_enabled);
10545
10546         PIPE_CONF_CHECK_I(double_wide);
10547
10548         PIPE_CONF_CHECK_X(ddi_pll_sel);
10549
10550         PIPE_CONF_CHECK_I(shared_dpll);
10551         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10552         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10553         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10554         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10555         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10556
10557         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10558                 PIPE_CONF_CHECK_I(pipe_bpp);
10559
10560         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10561         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10562
10563 #undef PIPE_CONF_CHECK_X
10564 #undef PIPE_CONF_CHECK_I
10565 #undef PIPE_CONF_CHECK_I_ALT
10566 #undef PIPE_CONF_CHECK_FLAGS
10567 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10568 #undef PIPE_CONF_QUIRK
10569
10570         return true;
10571 }
10572
10573 static void
10574 check_connector_state(struct drm_device *dev)
10575 {
10576         struct intel_connector *connector;
10577
10578         list_for_each_entry(connector, &dev->mode_config.connector_list,
10579                             base.head) {
10580                 /* This also checks the encoder/connector hw state with the
10581                  * ->get_hw_state callbacks. */
10582                 intel_connector_check_state(connector);
10583
10584                 WARN(&connector->new_encoder->base != connector->base.encoder,
10585                      "connector's staged encoder doesn't match current encoder\n");
10586         }
10587 }
10588
10589 static void
10590 check_encoder_state(struct drm_device *dev)
10591 {
10592         struct intel_encoder *encoder;
10593         struct intel_connector *connector;
10594
10595         for_each_intel_encoder(dev, encoder) {
10596                 bool enabled = false;
10597                 bool active = false;
10598                 enum pipe pipe, tracked_pipe;
10599
10600                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10601                               encoder->base.base.id,
10602                               encoder->base.name);
10603
10604                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10605                      "encoder's stage crtc doesn't match current crtc\n");
10606                 WARN(encoder->connectors_active && !encoder->base.crtc,
10607                      "encoder's active_connectors set, but no crtc\n");
10608
10609                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10610                                     base.head) {
10611                         if (connector->base.encoder != &encoder->base)
10612                                 continue;
10613                         enabled = true;
10614                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10615                                 active = true;
10616                 }
10617                 /*
10618                  * for MST connectors if we unplug the connector is gone
10619                  * away but the encoder is still connected to a crtc
10620                  * until a modeset happens in response to the hotplug.
10621                  */
10622                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10623                         continue;
10624
10625                 WARN(!!encoder->base.crtc != enabled,
10626                      "encoder's enabled state mismatch "
10627                      "(expected %i, found %i)\n",
10628                      !!encoder->base.crtc, enabled);
10629                 WARN(active && !encoder->base.crtc,
10630                      "active encoder with no crtc\n");
10631
10632                 WARN(encoder->connectors_active != active,
10633                      "encoder's computed active state doesn't match tracked active state "
10634                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10635
10636                 active = encoder->get_hw_state(encoder, &pipe);
10637                 WARN(active != encoder->connectors_active,
10638                      "encoder's hw state doesn't match sw tracking "
10639                      "(expected %i, found %i)\n",
10640                      encoder->connectors_active, active);
10641
10642                 if (!encoder->base.crtc)
10643                         continue;
10644
10645                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10646                 WARN(active && pipe != tracked_pipe,
10647                      "active encoder's pipe doesn't match"
10648                      "(expected %i, found %i)\n",
10649                      tracked_pipe, pipe);
10650
10651         }
10652 }
10653
10654 static void
10655 check_crtc_state(struct drm_device *dev)
10656 {
10657         struct drm_i915_private *dev_priv = dev->dev_private;
10658         struct intel_crtc *crtc;
10659         struct intel_encoder *encoder;
10660         struct intel_crtc_config pipe_config;
10661
10662         for_each_intel_crtc(dev, crtc) {
10663                 bool enabled = false;
10664                 bool active = false;
10665
10666                 memset(&pipe_config, 0, sizeof(pipe_config));
10667
10668                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10669                               crtc->base.base.id);
10670
10671                 WARN(crtc->active && !crtc->base.enabled,
10672                      "active crtc, but not enabled in sw tracking\n");
10673
10674                 for_each_intel_encoder(dev, encoder) {
10675                         if (encoder->base.crtc != &crtc->base)
10676                                 continue;
10677                         enabled = true;
10678                         if (encoder->connectors_active)
10679                                 active = true;
10680                 }
10681
10682                 WARN(active != crtc->active,
10683                      "crtc's computed active state doesn't match tracked active state "
10684                      "(expected %i, found %i)\n", active, crtc->active);
10685                 WARN(enabled != crtc->base.enabled,
10686                      "crtc's computed enabled state doesn't match tracked enabled state "
10687                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10688
10689                 active = dev_priv->display.get_pipe_config(crtc,
10690                                                            &pipe_config);
10691
10692                 /* hw state is inconsistent with the pipe A quirk */
10693                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10694                         active = crtc->active;
10695
10696                 for_each_intel_encoder(dev, encoder) {
10697                         enum pipe pipe;
10698                         if (encoder->base.crtc != &crtc->base)
10699                                 continue;
10700                         if (encoder->get_hw_state(encoder, &pipe))
10701                                 encoder->get_config(encoder, &pipe_config);
10702                 }
10703
10704                 WARN(crtc->active != active,
10705                      "crtc active state doesn't match with hw state "
10706                      "(expected %i, found %i)\n", crtc->active, active);
10707
10708                 if (active &&
10709                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10710                         WARN(1, "pipe state doesn't match!\n");
10711                         intel_dump_pipe_config(crtc, &pipe_config,
10712                                                "[hw state]");
10713                         intel_dump_pipe_config(crtc, &crtc->config,
10714                                                "[sw state]");
10715                 }
10716         }
10717 }
10718
10719 static void
10720 check_shared_dpll_state(struct drm_device *dev)
10721 {
10722         struct drm_i915_private *dev_priv = dev->dev_private;
10723         struct intel_crtc *crtc;
10724         struct intel_dpll_hw_state dpll_hw_state;
10725         int i;
10726
10727         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10728                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10729                 int enabled_crtcs = 0, active_crtcs = 0;
10730                 bool active;
10731
10732                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10733
10734                 DRM_DEBUG_KMS("%s\n", pll->name);
10735
10736                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10737
10738                 WARN(pll->active > pll->refcount,
10739                      "more active pll users than references: %i vs %i\n",
10740                      pll->active, pll->refcount);
10741                 WARN(pll->active && !pll->on,
10742                      "pll in active use but not on in sw tracking\n");
10743                 WARN(pll->on && !pll->active,
10744                      "pll in on but not on in use in sw tracking\n");
10745                 WARN(pll->on != active,
10746                      "pll on state mismatch (expected %i, found %i)\n",
10747                      pll->on, active);
10748
10749                 for_each_intel_crtc(dev, crtc) {
10750                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10751                                 enabled_crtcs++;
10752                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10753                                 active_crtcs++;
10754                 }
10755                 WARN(pll->active != active_crtcs,
10756                      "pll active crtcs mismatch (expected %i, found %i)\n",
10757                      pll->active, active_crtcs);
10758                 WARN(pll->refcount != enabled_crtcs,
10759                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10760                      pll->refcount, enabled_crtcs);
10761
10762                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10763                                        sizeof(dpll_hw_state)),
10764                      "pll hw state mismatch\n");
10765         }
10766 }
10767
10768 void
10769 intel_modeset_check_state(struct drm_device *dev)
10770 {
10771         check_connector_state(dev);
10772         check_encoder_state(dev);
10773         check_crtc_state(dev);
10774         check_shared_dpll_state(dev);
10775 }
10776
10777 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10778                                      int dotclock)
10779 {
10780         /*
10781          * FDI already provided one idea for the dotclock.
10782          * Yell if the encoder disagrees.
10783          */
10784         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10785              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10786              pipe_config->adjusted_mode.crtc_clock, dotclock);
10787 }
10788
10789 static void update_scanline_offset(struct intel_crtc *crtc)
10790 {
10791         struct drm_device *dev = crtc->base.dev;
10792
10793         /*
10794          * The scanline counter increments at the leading edge of hsync.
10795          *
10796          * On most platforms it starts counting from vtotal-1 on the
10797          * first active line. That means the scanline counter value is
10798          * always one less than what we would expect. Ie. just after
10799          * start of vblank, which also occurs at start of hsync (on the
10800          * last active line), the scanline counter will read vblank_start-1.
10801          *
10802          * On gen2 the scanline counter starts counting from 1 instead
10803          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10804          * to keep the value positive), instead of adding one.
10805          *
10806          * On HSW+ the behaviour of the scanline counter depends on the output
10807          * type. For DP ports it behaves like most other platforms, but on HDMI
10808          * there's an extra 1 line difference. So we need to add two instead of
10809          * one to the value.
10810          */
10811         if (IS_GEN2(dev)) {
10812                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10813                 int vtotal;
10814
10815                 vtotal = mode->crtc_vtotal;
10816                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10817                         vtotal /= 2;
10818
10819                 crtc->scanline_offset = vtotal - 1;
10820         } else if (HAS_DDI(dev) &&
10821                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10822                 crtc->scanline_offset = 2;
10823         } else
10824                 crtc->scanline_offset = 1;
10825 }
10826
10827 static int __intel_set_mode(struct drm_crtc *crtc,
10828                             struct drm_display_mode *mode,
10829                             int x, int y, struct drm_framebuffer *fb)
10830 {
10831         struct drm_device *dev = crtc->dev;
10832         struct drm_i915_private *dev_priv = dev->dev_private;
10833         struct drm_display_mode *saved_mode;
10834         struct intel_crtc_config *pipe_config = NULL;
10835         struct intel_crtc *intel_crtc;
10836         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10837         int ret = 0;
10838
10839         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10840         if (!saved_mode)
10841                 return -ENOMEM;
10842
10843         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10844                                      &prepare_pipes, &disable_pipes);
10845
10846         *saved_mode = crtc->mode;
10847
10848         /* Hack: Because we don't (yet) support global modeset on multiple
10849          * crtcs, we don't keep track of the new mode for more than one crtc.
10850          * Hence simply check whether any bit is set in modeset_pipes in all the
10851          * pieces of code that are not yet converted to deal with mutliple crtcs
10852          * changing their mode at the same time. */
10853         if (modeset_pipes) {
10854                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10855                 if (IS_ERR(pipe_config)) {
10856                         ret = PTR_ERR(pipe_config);
10857                         pipe_config = NULL;
10858
10859                         goto out;
10860                 }
10861                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10862                                        "[modeset]");
10863                 to_intel_crtc(crtc)->new_config = pipe_config;
10864         }
10865
10866         /*
10867          * See if the config requires any additional preparation, e.g.
10868          * to adjust global state with pipes off.  We need to do this
10869          * here so we can get the modeset_pipe updated config for the new
10870          * mode set on this crtc.  For other crtcs we need to use the
10871          * adjusted_mode bits in the crtc directly.
10872          */
10873         if (IS_VALLEYVIEW(dev)) {
10874                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10875
10876                 /* may have added more to prepare_pipes than we should */
10877                 prepare_pipes &= ~disable_pipes;
10878         }
10879
10880         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10881                 intel_crtc_disable(&intel_crtc->base);
10882
10883         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10884                 if (intel_crtc->base.enabled)
10885                         dev_priv->display.crtc_disable(&intel_crtc->base);
10886         }
10887
10888         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10889          * to set it here already despite that we pass it down the callchain.
10890          */
10891         if (modeset_pipes) {
10892                 crtc->mode = *mode;
10893                 /* mode_set/enable/disable functions rely on a correct pipe
10894                  * config. */
10895                 to_intel_crtc(crtc)->config = *pipe_config;
10896                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10897
10898                 /*
10899                  * Calculate and store various constants which
10900                  * are later needed by vblank and swap-completion
10901                  * timestamping. They are derived from true hwmode.
10902                  */
10903                 drm_calc_timestamping_constants(crtc,
10904                                                 &pipe_config->adjusted_mode);
10905         }
10906
10907         /* Only after disabling all output pipelines that will be changed can we
10908          * update the the output configuration. */
10909         intel_modeset_update_state(dev, prepare_pipes);
10910
10911         if (dev_priv->display.modeset_global_resources)
10912                 dev_priv->display.modeset_global_resources(dev);
10913
10914         /* Set up the DPLL and any encoders state that needs to adjust or depend
10915          * on the DPLL.
10916          */
10917         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10918                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10919                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10920                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10921
10922                 mutex_lock(&dev->struct_mutex);
10923                 ret = intel_pin_and_fence_fb_obj(dev,
10924                                                  obj,
10925                                                  NULL);
10926                 if (ret != 0) {
10927                         DRM_ERROR("pin & fence failed\n");
10928                         mutex_unlock(&dev->struct_mutex);
10929                         goto done;
10930                 }
10931                 if (old_fb)
10932                         intel_unpin_fb_obj(old_obj);
10933                 i915_gem_track_fb(old_obj, obj,
10934                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10935                 mutex_unlock(&dev->struct_mutex);
10936
10937                 crtc->primary->fb = fb;
10938                 crtc->x = x;
10939                 crtc->y = y;
10940
10941                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10942                                                       x, y, fb);
10943                 if (ret)
10944                         goto done;
10945         }
10946
10947         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10948         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10949                 update_scanline_offset(intel_crtc);
10950
10951                 dev_priv->display.crtc_enable(&intel_crtc->base);
10952         }
10953
10954         /* FIXME: add subpixel order */
10955 done:
10956         if (ret && crtc->enabled)
10957                 crtc->mode = *saved_mode;
10958
10959 out:
10960         kfree(pipe_config);
10961         kfree(saved_mode);
10962         return ret;
10963 }
10964
10965 static int intel_set_mode(struct drm_crtc *crtc,
10966                           struct drm_display_mode *mode,
10967                           int x, int y, struct drm_framebuffer *fb)
10968 {
10969         int ret;
10970
10971         ret = __intel_set_mode(crtc, mode, x, y, fb);
10972
10973         if (ret == 0)
10974                 intel_modeset_check_state(crtc->dev);
10975
10976         return ret;
10977 }
10978
10979 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10980 {
10981         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10982 }
10983
10984 #undef for_each_intel_crtc_masked
10985
10986 static void intel_set_config_free(struct intel_set_config *config)
10987 {
10988         if (!config)
10989                 return;
10990
10991         kfree(config->save_connector_encoders);
10992         kfree(config->save_encoder_crtcs);
10993         kfree(config->save_crtc_enabled);
10994         kfree(config);
10995 }
10996
10997 static int intel_set_config_save_state(struct drm_device *dev,
10998                                        struct intel_set_config *config)
10999 {
11000         struct drm_crtc *crtc;
11001         struct drm_encoder *encoder;
11002         struct drm_connector *connector;
11003         int count;
11004
11005         config->save_crtc_enabled =
11006                 kcalloc(dev->mode_config.num_crtc,
11007                         sizeof(bool), GFP_KERNEL);
11008         if (!config->save_crtc_enabled)
11009                 return -ENOMEM;
11010
11011         config->save_encoder_crtcs =
11012                 kcalloc(dev->mode_config.num_encoder,
11013                         sizeof(struct drm_crtc *), GFP_KERNEL);
11014         if (!config->save_encoder_crtcs)
11015                 return -ENOMEM;
11016
11017         config->save_connector_encoders =
11018                 kcalloc(dev->mode_config.num_connector,
11019                         sizeof(struct drm_encoder *), GFP_KERNEL);
11020         if (!config->save_connector_encoders)
11021                 return -ENOMEM;
11022
11023         /* Copy data. Note that driver private data is not affected.
11024          * Should anything bad happen only the expected state is
11025          * restored, not the drivers personal bookkeeping.
11026          */
11027         count = 0;
11028         for_each_crtc(dev, crtc) {
11029                 config->save_crtc_enabled[count++] = crtc->enabled;
11030         }
11031
11032         count = 0;
11033         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11034                 config->save_encoder_crtcs[count++] = encoder->crtc;
11035         }
11036
11037         count = 0;
11038         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11039                 config->save_connector_encoders[count++] = connector->encoder;
11040         }
11041
11042         return 0;
11043 }
11044
11045 static void intel_set_config_restore_state(struct drm_device *dev,
11046                                            struct intel_set_config *config)
11047 {
11048         struct intel_crtc *crtc;
11049         struct intel_encoder *encoder;
11050         struct intel_connector *connector;
11051         int count;
11052
11053         count = 0;
11054         for_each_intel_crtc(dev, crtc) {
11055                 crtc->new_enabled = config->save_crtc_enabled[count++];
11056
11057                 if (crtc->new_enabled)
11058                         crtc->new_config = &crtc->config;
11059                 else
11060                         crtc->new_config = NULL;
11061         }
11062
11063         count = 0;
11064         for_each_intel_encoder(dev, encoder) {
11065                 encoder->new_crtc =
11066                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11067         }
11068
11069         count = 0;
11070         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11071                 connector->new_encoder =
11072                         to_intel_encoder(config->save_connector_encoders[count++]);
11073         }
11074 }
11075
11076 static bool
11077 is_crtc_connector_off(struct drm_mode_set *set)
11078 {
11079         int i;
11080
11081         if (set->num_connectors == 0)
11082                 return false;
11083
11084         if (WARN_ON(set->connectors == NULL))
11085                 return false;
11086
11087         for (i = 0; i < set->num_connectors; i++)
11088                 if (set->connectors[i]->encoder &&
11089                     set->connectors[i]->encoder->crtc == set->crtc &&
11090                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11091                         return true;
11092
11093         return false;
11094 }
11095
11096 static void
11097 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11098                                       struct intel_set_config *config)
11099 {
11100
11101         /* We should be able to check here if the fb has the same properties
11102          * and then just flip_or_move it */
11103         if (is_crtc_connector_off(set)) {
11104                 config->mode_changed = true;
11105         } else if (set->crtc->primary->fb != set->fb) {
11106                 /*
11107                  * If we have no fb, we can only flip as long as the crtc is
11108                  * active, otherwise we need a full mode set.  The crtc may
11109                  * be active if we've only disabled the primary plane, or
11110                  * in fastboot situations.
11111                  */
11112                 if (set->crtc->primary->fb == NULL) {
11113                         struct intel_crtc *intel_crtc =
11114                                 to_intel_crtc(set->crtc);
11115
11116                         if (intel_crtc->active) {
11117                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11118                                 config->fb_changed = true;
11119                         } else {
11120                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11121                                 config->mode_changed = true;
11122                         }
11123                 } else if (set->fb == NULL) {
11124                         config->mode_changed = true;
11125                 } else if (set->fb->pixel_format !=
11126                            set->crtc->primary->fb->pixel_format) {
11127                         config->mode_changed = true;
11128                 } else {
11129                         config->fb_changed = true;
11130                 }
11131         }
11132
11133         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11134                 config->fb_changed = true;
11135
11136         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11137                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11138                 drm_mode_debug_printmodeline(&set->crtc->mode);
11139                 drm_mode_debug_printmodeline(set->mode);
11140                 config->mode_changed = true;
11141         }
11142
11143         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11144                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11145 }
11146
11147 static int
11148 intel_modeset_stage_output_state(struct drm_device *dev,
11149                                  struct drm_mode_set *set,
11150                                  struct intel_set_config *config)
11151 {
11152         struct intel_connector *connector;
11153         struct intel_encoder *encoder;
11154         struct intel_crtc *crtc;
11155         int ro;
11156
11157         /* The upper layers ensure that we either disable a crtc or have a list
11158          * of connectors. For paranoia, double-check this. */
11159         WARN_ON(!set->fb && (set->num_connectors != 0));
11160         WARN_ON(set->fb && (set->num_connectors == 0));
11161
11162         list_for_each_entry(connector, &dev->mode_config.connector_list,
11163                             base.head) {
11164                 /* Otherwise traverse passed in connector list and get encoders
11165                  * for them. */
11166                 for (ro = 0; ro < set->num_connectors; ro++) {
11167                         if (set->connectors[ro] == &connector->base) {
11168                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11169                                 break;
11170                         }
11171                 }
11172
11173                 /* If we disable the crtc, disable all its connectors. Also, if
11174                  * the connector is on the changing crtc but not on the new
11175                  * connector list, disable it. */
11176                 if ((!set->fb || ro == set->num_connectors) &&
11177                     connector->base.encoder &&
11178                     connector->base.encoder->crtc == set->crtc) {
11179                         connector->new_encoder = NULL;
11180
11181                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11182                                 connector->base.base.id,
11183                                 connector->base.name);
11184                 }
11185
11186
11187                 if (&connector->new_encoder->base != connector->base.encoder) {
11188                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11189                         config->mode_changed = true;
11190                 }
11191         }
11192         /* connector->new_encoder is now updated for all connectors. */
11193
11194         /* Update crtc of enabled connectors. */
11195         list_for_each_entry(connector, &dev->mode_config.connector_list,
11196                             base.head) {
11197                 struct drm_crtc *new_crtc;
11198
11199                 if (!connector->new_encoder)
11200                         continue;
11201
11202                 new_crtc = connector->new_encoder->base.crtc;
11203
11204                 for (ro = 0; ro < set->num_connectors; ro++) {
11205                         if (set->connectors[ro] == &connector->base)
11206                                 new_crtc = set->crtc;
11207                 }
11208
11209                 /* Make sure the new CRTC will work with the encoder */
11210                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11211                                          new_crtc)) {
11212                         return -EINVAL;
11213                 }
11214                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11215
11216                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11217                         connector->base.base.id,
11218                         connector->base.name,
11219                         new_crtc->base.id);
11220         }
11221
11222         /* Check for any encoders that needs to be disabled. */
11223         for_each_intel_encoder(dev, encoder) {
11224                 int num_connectors = 0;
11225                 list_for_each_entry(connector,
11226                                     &dev->mode_config.connector_list,
11227                                     base.head) {
11228                         if (connector->new_encoder == encoder) {
11229                                 WARN_ON(!connector->new_encoder->new_crtc);
11230                                 num_connectors++;
11231                         }
11232                 }
11233
11234                 if (num_connectors == 0)
11235                         encoder->new_crtc = NULL;
11236                 else if (num_connectors > 1)
11237                         return -EINVAL;
11238
11239                 /* Only now check for crtc changes so we don't miss encoders
11240                  * that will be disabled. */
11241                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11242                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11243                         config->mode_changed = true;
11244                 }
11245         }
11246         /* Now we've also updated encoder->new_crtc for all encoders. */
11247         list_for_each_entry(connector, &dev->mode_config.connector_list,
11248                             base.head) {
11249                 if (connector->new_encoder)
11250                         if (connector->new_encoder != connector->encoder)
11251                                 connector->encoder = connector->new_encoder;
11252         }
11253         for_each_intel_crtc(dev, crtc) {
11254                 crtc->new_enabled = false;
11255
11256                 for_each_intel_encoder(dev, encoder) {
11257                         if (encoder->new_crtc == crtc) {
11258                                 crtc->new_enabled = true;
11259                                 break;
11260                         }
11261                 }
11262
11263                 if (crtc->new_enabled != crtc->base.enabled) {
11264                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11265                                       crtc->new_enabled ? "en" : "dis");
11266                         config->mode_changed = true;
11267                 }
11268
11269                 if (crtc->new_enabled)
11270                         crtc->new_config = &crtc->config;
11271                 else
11272                         crtc->new_config = NULL;
11273         }
11274
11275         return 0;
11276 }
11277
11278 static void disable_crtc_nofb(struct intel_crtc *crtc)
11279 {
11280         struct drm_device *dev = crtc->base.dev;
11281         struct intel_encoder *encoder;
11282         struct intel_connector *connector;
11283
11284         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11285                       pipe_name(crtc->pipe));
11286
11287         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11288                 if (connector->new_encoder &&
11289                     connector->new_encoder->new_crtc == crtc)
11290                         connector->new_encoder = NULL;
11291         }
11292
11293         for_each_intel_encoder(dev, encoder) {
11294                 if (encoder->new_crtc == crtc)
11295                         encoder->new_crtc = NULL;
11296         }
11297
11298         crtc->new_enabled = false;
11299         crtc->new_config = NULL;
11300 }
11301
11302 static int intel_crtc_set_config(struct drm_mode_set *set)
11303 {
11304         struct drm_device *dev;
11305         struct drm_mode_set save_set;
11306         struct intel_set_config *config;
11307         int ret;
11308
11309         BUG_ON(!set);
11310         BUG_ON(!set->crtc);
11311         BUG_ON(!set->crtc->helper_private);
11312
11313         /* Enforce sane interface api - has been abused by the fb helper. */
11314         BUG_ON(!set->mode && set->fb);
11315         BUG_ON(set->fb && set->num_connectors == 0);
11316
11317         if (set->fb) {
11318                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11319                                 set->crtc->base.id, set->fb->base.id,
11320                                 (int)set->num_connectors, set->x, set->y);
11321         } else {
11322                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11323         }
11324
11325         dev = set->crtc->dev;
11326
11327         ret = -ENOMEM;
11328         config = kzalloc(sizeof(*config), GFP_KERNEL);
11329         if (!config)
11330                 goto out_config;
11331
11332         ret = intel_set_config_save_state(dev, config);
11333         if (ret)
11334                 goto out_config;
11335
11336         save_set.crtc = set->crtc;
11337         save_set.mode = &set->crtc->mode;
11338         save_set.x = set->crtc->x;
11339         save_set.y = set->crtc->y;
11340         save_set.fb = set->crtc->primary->fb;
11341
11342         /* Compute whether we need a full modeset, only an fb base update or no
11343          * change at all. In the future we might also check whether only the
11344          * mode changed, e.g. for LVDS where we only change the panel fitter in
11345          * such cases. */
11346         intel_set_config_compute_mode_changes(set, config);
11347
11348         ret = intel_modeset_stage_output_state(dev, set, config);
11349         if (ret)
11350                 goto fail;
11351
11352         if (config->mode_changed) {
11353                 ret = intel_set_mode(set->crtc, set->mode,
11354                                      set->x, set->y, set->fb);
11355         } else if (config->fb_changed) {
11356                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11357
11358                 intel_crtc_wait_for_pending_flips(set->crtc);
11359
11360                 ret = intel_pipe_set_base(set->crtc,
11361                                           set->x, set->y, set->fb);
11362
11363                 /*
11364                  * We need to make sure the primary plane is re-enabled if it
11365                  * has previously been turned off.
11366                  */
11367                 if (!intel_crtc->primary_enabled && ret == 0) {
11368                         WARN_ON(!intel_crtc->active);
11369                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11370                 }
11371
11372                 /*
11373                  * In the fastboot case this may be our only check of the
11374                  * state after boot.  It would be better to only do it on
11375                  * the first update, but we don't have a nice way of doing that
11376                  * (and really, set_config isn't used much for high freq page
11377                  * flipping, so increasing its cost here shouldn't be a big
11378                  * deal).
11379                  */
11380                 if (i915.fastboot && ret == 0)
11381                         intel_modeset_check_state(set->crtc->dev);
11382         }
11383
11384         if (ret) {
11385                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11386                               set->crtc->base.id, ret);
11387 fail:
11388                 intel_set_config_restore_state(dev, config);
11389
11390                 /*
11391                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11392                  * force the pipe off to avoid oopsing in the modeset code
11393                  * due to fb==NULL. This should only happen during boot since
11394                  * we don't yet reconstruct the FB from the hardware state.
11395                  */
11396                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11397                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11398
11399                 /* Try to restore the config */
11400                 if (config->mode_changed &&
11401                     intel_set_mode(save_set.crtc, save_set.mode,
11402                                    save_set.x, save_set.y, save_set.fb))
11403                         DRM_ERROR("failed to restore config after modeset failure\n");
11404         }
11405
11406 out_config:
11407         intel_set_config_free(config);
11408         return ret;
11409 }
11410
11411 static const struct drm_crtc_funcs intel_crtc_funcs = {
11412         .gamma_set = intel_crtc_gamma_set,
11413         .set_config = intel_crtc_set_config,
11414         .destroy = intel_crtc_destroy,
11415         .page_flip = intel_crtc_page_flip,
11416 };
11417
11418 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11419                                       struct intel_shared_dpll *pll,
11420                                       struct intel_dpll_hw_state *hw_state)
11421 {
11422         uint32_t val;
11423
11424         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11425                 return false;
11426
11427         val = I915_READ(PCH_DPLL(pll->id));
11428         hw_state->dpll = val;
11429         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11430         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11431
11432         return val & DPLL_VCO_ENABLE;
11433 }
11434
11435 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11436                                   struct intel_shared_dpll *pll)
11437 {
11438         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11439         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11440 }
11441
11442 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11443                                 struct intel_shared_dpll *pll)
11444 {
11445         /* PCH refclock must be enabled first */
11446         ibx_assert_pch_refclk_enabled(dev_priv);
11447
11448         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11449
11450         /* Wait for the clocks to stabilize. */
11451         POSTING_READ(PCH_DPLL(pll->id));
11452         udelay(150);
11453
11454         /* The pixel multiplier can only be updated once the
11455          * DPLL is enabled and the clocks are stable.
11456          *
11457          * So write it again.
11458          */
11459         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11460         POSTING_READ(PCH_DPLL(pll->id));
11461         udelay(200);
11462 }
11463
11464 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11465                                  struct intel_shared_dpll *pll)
11466 {
11467         struct drm_device *dev = dev_priv->dev;
11468         struct intel_crtc *crtc;
11469
11470         /* Make sure no transcoder isn't still depending on us. */
11471         for_each_intel_crtc(dev, crtc) {
11472                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11473                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11474         }
11475
11476         I915_WRITE(PCH_DPLL(pll->id), 0);
11477         POSTING_READ(PCH_DPLL(pll->id));
11478         udelay(200);
11479 }
11480
11481 static char *ibx_pch_dpll_names[] = {
11482         "PCH DPLL A",
11483         "PCH DPLL B",
11484 };
11485
11486 static void ibx_pch_dpll_init(struct drm_device *dev)
11487 {
11488         struct drm_i915_private *dev_priv = dev->dev_private;
11489         int i;
11490
11491         dev_priv->num_shared_dpll = 2;
11492
11493         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11494                 dev_priv->shared_dplls[i].id = i;
11495                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11496                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11497                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11498                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11499                 dev_priv->shared_dplls[i].get_hw_state =
11500                         ibx_pch_dpll_get_hw_state;
11501         }
11502 }
11503
11504 static void intel_shared_dpll_init(struct drm_device *dev)
11505 {
11506         struct drm_i915_private *dev_priv = dev->dev_private;
11507
11508         if (HAS_DDI(dev))
11509                 intel_ddi_pll_init(dev);
11510         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11511                 ibx_pch_dpll_init(dev);
11512         else
11513                 dev_priv->num_shared_dpll = 0;
11514
11515         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11516 }
11517
11518 static int
11519 intel_primary_plane_disable(struct drm_plane *plane)
11520 {
11521         struct drm_device *dev = plane->dev;
11522         struct intel_crtc *intel_crtc;
11523
11524         if (!plane->fb)
11525                 return 0;
11526
11527         BUG_ON(!plane->crtc);
11528
11529         intel_crtc = to_intel_crtc(plane->crtc);
11530
11531         /*
11532          * Even though we checked plane->fb above, it's still possible that
11533          * the primary plane has been implicitly disabled because the crtc
11534          * coordinates given weren't visible, or because we detected
11535          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11536          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11537          * In either case, we need to unpin the FB and let the fb pointer get
11538          * updated, but otherwise we don't need to touch the hardware.
11539          */
11540         if (!intel_crtc->primary_enabled)
11541                 goto disable_unpin;
11542
11543         intel_crtc_wait_for_pending_flips(plane->crtc);
11544         intel_disable_primary_hw_plane(plane, plane->crtc);
11545
11546 disable_unpin:
11547         mutex_lock(&dev->struct_mutex);
11548         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11549                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11550         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11551         mutex_unlock(&dev->struct_mutex);
11552         plane->fb = NULL;
11553
11554         return 0;
11555 }
11556
11557 static int
11558 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11559                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11560                              unsigned int crtc_w, unsigned int crtc_h,
11561                              uint32_t src_x, uint32_t src_y,
11562                              uint32_t src_w, uint32_t src_h)
11563 {
11564         struct drm_device *dev = crtc->dev;
11565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11566         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11567         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11568         struct drm_rect dest = {
11569                 /* integer pixels */
11570                 .x1 = crtc_x,
11571                 .y1 = crtc_y,
11572                 .x2 = crtc_x + crtc_w,
11573                 .y2 = crtc_y + crtc_h,
11574         };
11575         struct drm_rect src = {
11576                 /* 16.16 fixed point */
11577                 .x1 = src_x,
11578                 .y1 = src_y,
11579                 .x2 = src_x + src_w,
11580                 .y2 = src_y + src_h,
11581         };
11582         const struct drm_rect clip = {
11583                 /* integer pixels */
11584                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11585                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11586         };
11587         bool visible;
11588         int ret;
11589
11590         ret = drm_plane_helper_check_update(plane, crtc, fb,
11591                                             &src, &dest, &clip,
11592                                             DRM_PLANE_HELPER_NO_SCALING,
11593                                             DRM_PLANE_HELPER_NO_SCALING,
11594                                             false, true, &visible);
11595
11596         if (ret)
11597                 return ret;
11598
11599         /*
11600          * If the CRTC isn't enabled, we're just pinning the framebuffer,
11601          * updating the fb pointer, and returning without touching the
11602          * hardware.  This allows us to later do a drmModeSetCrtc with fb=-1 to
11603          * turn on the display with all planes setup as desired.
11604          */
11605         if (!crtc->enabled) {
11606                 mutex_lock(&dev->struct_mutex);
11607
11608                 /*
11609                  * If we already called setplane while the crtc was disabled,
11610                  * we may have an fb pinned; unpin it.
11611                  */
11612                 if (plane->fb)
11613                         intel_unpin_fb_obj(old_obj);
11614
11615                 i915_gem_track_fb(old_obj, obj,
11616                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11617
11618                 /* Pin and return without programming hardware */
11619                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11620                 mutex_unlock(&dev->struct_mutex);
11621
11622                 return ret;
11623         }
11624
11625         intel_crtc_wait_for_pending_flips(crtc);
11626
11627         /*
11628          * If clipping results in a non-visible primary plane, we'll disable
11629          * the primary plane.  Note that this is a bit different than what
11630          * happens if userspace explicitly disables the plane by passing fb=0
11631          * because plane->fb still gets set and pinned.
11632          */
11633         if (!visible) {
11634                 mutex_lock(&dev->struct_mutex);
11635
11636                 /*
11637                  * Try to pin the new fb first so that we can bail out if we
11638                  * fail.
11639                  */
11640                 if (plane->fb != fb) {
11641                         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11642                         if (ret) {
11643                                 mutex_unlock(&dev->struct_mutex);
11644                                 return ret;
11645                         }
11646                 }
11647
11648                 i915_gem_track_fb(old_obj, obj,
11649                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11650
11651                 if (intel_crtc->primary_enabled)
11652                         intel_disable_primary_hw_plane(plane, crtc);
11653
11654
11655                 if (plane->fb != fb)
11656                         if (plane->fb)
11657                                 intel_unpin_fb_obj(old_obj);
11658
11659                 mutex_unlock(&dev->struct_mutex);
11660
11661                 return 0;
11662         }
11663
11664         ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11665         if (ret)
11666                 return ret;
11667
11668         if (!intel_crtc->primary_enabled)
11669                 intel_enable_primary_hw_plane(plane, crtc);
11670
11671         return 0;
11672 }
11673
11674 /* Common destruction function for both primary and cursor planes */
11675 static void intel_plane_destroy(struct drm_plane *plane)
11676 {
11677         struct intel_plane *intel_plane = to_intel_plane(plane);
11678         drm_plane_cleanup(plane);
11679         kfree(intel_plane);
11680 }
11681
11682 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11683         .update_plane = intel_primary_plane_setplane,
11684         .disable_plane = intel_primary_plane_disable,
11685         .destroy = intel_plane_destroy,
11686 };
11687
11688 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11689                                                     int pipe)
11690 {
11691         struct intel_plane *primary;
11692         const uint32_t *intel_primary_formats;
11693         int num_formats;
11694
11695         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11696         if (primary == NULL)
11697                 return NULL;
11698
11699         primary->can_scale = false;
11700         primary->max_downscale = 1;
11701         primary->pipe = pipe;
11702         primary->plane = pipe;
11703         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11704                 primary->plane = !pipe;
11705
11706         if (INTEL_INFO(dev)->gen <= 3) {
11707                 intel_primary_formats = intel_primary_formats_gen2;
11708                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11709         } else {
11710                 intel_primary_formats = intel_primary_formats_gen4;
11711                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11712         }
11713
11714         drm_universal_plane_init(dev, &primary->base, 0,
11715                                  &intel_primary_plane_funcs,
11716                                  intel_primary_formats, num_formats,
11717                                  DRM_PLANE_TYPE_PRIMARY);
11718         return &primary->base;
11719 }
11720
11721 static int
11722 intel_cursor_plane_disable(struct drm_plane *plane)
11723 {
11724         if (!plane->fb)
11725                 return 0;
11726
11727         BUG_ON(!plane->crtc);
11728
11729         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11730 }
11731
11732 static int
11733 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11734                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11735                           unsigned int crtc_w, unsigned int crtc_h,
11736                           uint32_t src_x, uint32_t src_y,
11737                           uint32_t src_w, uint32_t src_h)
11738 {
11739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11740         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11741         struct drm_i915_gem_object *obj = intel_fb->obj;
11742         struct drm_rect dest = {
11743                 /* integer pixels */
11744                 .x1 = crtc_x,
11745                 .y1 = crtc_y,
11746                 .x2 = crtc_x + crtc_w,
11747                 .y2 = crtc_y + crtc_h,
11748         };
11749         struct drm_rect src = {
11750                 /* 16.16 fixed point */
11751                 .x1 = src_x,
11752                 .y1 = src_y,
11753                 .x2 = src_x + src_w,
11754                 .y2 = src_y + src_h,
11755         };
11756         const struct drm_rect clip = {
11757                 /* integer pixels */
11758                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11759                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11760         };
11761         bool visible;
11762         int ret;
11763
11764         ret = drm_plane_helper_check_update(plane, crtc, fb,
11765                                             &src, &dest, &clip,
11766                                             DRM_PLANE_HELPER_NO_SCALING,
11767                                             DRM_PLANE_HELPER_NO_SCALING,
11768                                             true, true, &visible);
11769         if (ret)
11770                 return ret;
11771
11772         crtc->cursor_x = crtc_x;
11773         crtc->cursor_y = crtc_y;
11774         if (fb != crtc->cursor->fb) {
11775                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11776         } else {
11777                 intel_crtc_update_cursor(crtc, visible);
11778
11779                 intel_frontbuffer_flip(crtc->dev,
11780                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11781
11782                 return 0;
11783         }
11784 }
11785 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11786         .update_plane = intel_cursor_plane_update,
11787         .disable_plane = intel_cursor_plane_disable,
11788         .destroy = intel_plane_destroy,
11789 };
11790
11791 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11792                                                    int pipe)
11793 {
11794         struct intel_plane *cursor;
11795
11796         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11797         if (cursor == NULL)
11798                 return NULL;
11799
11800         cursor->can_scale = false;
11801         cursor->max_downscale = 1;
11802         cursor->pipe = pipe;
11803         cursor->plane = pipe;
11804
11805         drm_universal_plane_init(dev, &cursor->base, 0,
11806                                  &intel_cursor_plane_funcs,
11807                                  intel_cursor_formats,
11808                                  ARRAY_SIZE(intel_cursor_formats),
11809                                  DRM_PLANE_TYPE_CURSOR);
11810         return &cursor->base;
11811 }
11812
11813 static void intel_crtc_init(struct drm_device *dev, int pipe)
11814 {
11815         struct drm_i915_private *dev_priv = dev->dev_private;
11816         struct intel_crtc *intel_crtc;
11817         struct drm_plane *primary = NULL;
11818         struct drm_plane *cursor = NULL;
11819         int i, ret;
11820
11821         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11822         if (intel_crtc == NULL)
11823                 return;
11824
11825         primary = intel_primary_plane_create(dev, pipe);
11826         if (!primary)
11827                 goto fail;
11828
11829         cursor = intel_cursor_plane_create(dev, pipe);
11830         if (!cursor)
11831                 goto fail;
11832
11833         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11834                                         cursor, &intel_crtc_funcs);
11835         if (ret)
11836                 goto fail;
11837
11838         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11839         for (i = 0; i < 256; i++) {
11840                 intel_crtc->lut_r[i] = i;
11841                 intel_crtc->lut_g[i] = i;
11842                 intel_crtc->lut_b[i] = i;
11843         }
11844
11845         /*
11846          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11847          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11848          */
11849         intel_crtc->pipe = pipe;
11850         intel_crtc->plane = pipe;
11851         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11852                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11853                 intel_crtc->plane = !pipe;
11854         }
11855
11856         intel_crtc->cursor_base = ~0;
11857         intel_crtc->cursor_cntl = ~0;
11858         intel_crtc->cursor_size = ~0;
11859
11860         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11861                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11862         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11863         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11864
11865         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11866
11867         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11868         return;
11869
11870 fail:
11871         if (primary)
11872                 drm_plane_cleanup(primary);
11873         if (cursor)
11874                 drm_plane_cleanup(cursor);
11875         kfree(intel_crtc);
11876 }
11877
11878 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11879 {
11880         struct drm_encoder *encoder = connector->base.encoder;
11881         struct drm_device *dev = connector->base.dev;
11882
11883         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11884
11885         if (!encoder)
11886                 return INVALID_PIPE;
11887
11888         return to_intel_crtc(encoder->crtc)->pipe;
11889 }
11890
11891 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11892                                 struct drm_file *file)
11893 {
11894         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11895         struct drm_crtc *drmmode_crtc;
11896         struct intel_crtc *crtc;
11897
11898         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11899                 return -ENODEV;
11900
11901         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11902
11903         if (!drmmode_crtc) {
11904                 DRM_ERROR("no such CRTC id\n");
11905                 return -ENOENT;
11906         }
11907
11908         crtc = to_intel_crtc(drmmode_crtc);
11909         pipe_from_crtc_id->pipe = crtc->pipe;
11910
11911         return 0;
11912 }
11913
11914 static int intel_encoder_clones(struct intel_encoder *encoder)
11915 {
11916         struct drm_device *dev = encoder->base.dev;
11917         struct intel_encoder *source_encoder;
11918         int index_mask = 0;
11919         int entry = 0;
11920
11921         for_each_intel_encoder(dev, source_encoder) {
11922                 if (encoders_cloneable(encoder, source_encoder))
11923                         index_mask |= (1 << entry);
11924
11925                 entry++;
11926         }
11927
11928         return index_mask;
11929 }
11930
11931 static bool has_edp_a(struct drm_device *dev)
11932 {
11933         struct drm_i915_private *dev_priv = dev->dev_private;
11934
11935         if (!IS_MOBILE(dev))
11936                 return false;
11937
11938         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11939                 return false;
11940
11941         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11942                 return false;
11943
11944         return true;
11945 }
11946
11947 const char *intel_output_name(int output)
11948 {
11949         static const char *names[] = {
11950                 [INTEL_OUTPUT_UNUSED] = "Unused",
11951                 [INTEL_OUTPUT_ANALOG] = "Analog",
11952                 [INTEL_OUTPUT_DVO] = "DVO",
11953                 [INTEL_OUTPUT_SDVO] = "SDVO",
11954                 [INTEL_OUTPUT_LVDS] = "LVDS",
11955                 [INTEL_OUTPUT_TVOUT] = "TV",
11956                 [INTEL_OUTPUT_HDMI] = "HDMI",
11957                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11958                 [INTEL_OUTPUT_EDP] = "eDP",
11959                 [INTEL_OUTPUT_DSI] = "DSI",
11960                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11961         };
11962
11963         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11964                 return "Invalid";
11965
11966         return names[output];
11967 }
11968
11969 static bool intel_crt_present(struct drm_device *dev)
11970 {
11971         struct drm_i915_private *dev_priv = dev->dev_private;
11972
11973         if (IS_ULT(dev))
11974                 return false;
11975
11976         if (IS_CHERRYVIEW(dev))
11977                 return false;
11978
11979         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11980                 return false;
11981
11982         return true;
11983 }
11984
11985 static void intel_setup_outputs(struct drm_device *dev)
11986 {
11987         struct drm_i915_private *dev_priv = dev->dev_private;
11988         struct intel_encoder *encoder;
11989         bool dpd_is_edp = false;
11990
11991         intel_lvds_init(dev);
11992
11993         if (intel_crt_present(dev))
11994                 intel_crt_init(dev);
11995
11996         if (HAS_DDI(dev)) {
11997                 int found;
11998
11999                 /* Haswell uses DDI functions to detect digital outputs */
12000                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12001                 /* DDI A only supports eDP */
12002                 if (found)
12003                         intel_ddi_init(dev, PORT_A);
12004
12005                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12006                  * register */
12007                 found = I915_READ(SFUSE_STRAP);
12008
12009                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12010                         intel_ddi_init(dev, PORT_B);
12011                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12012                         intel_ddi_init(dev, PORT_C);
12013                 if (found & SFUSE_STRAP_DDID_DETECTED)
12014                         intel_ddi_init(dev, PORT_D);
12015         } else if (HAS_PCH_SPLIT(dev)) {
12016                 int found;
12017                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12018
12019                 if (has_edp_a(dev))
12020                         intel_dp_init(dev, DP_A, PORT_A);
12021
12022                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12023                         /* PCH SDVOB multiplex with HDMIB */
12024                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12025                         if (!found)
12026                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12027                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12028                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12029                 }
12030
12031                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12032                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12033
12034                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12035                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12036
12037                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12038                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12039
12040                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12041                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12042         } else if (IS_VALLEYVIEW(dev)) {
12043                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12044                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12045                                         PORT_B);
12046                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12047                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12048                 }
12049
12050                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12051                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12052                                         PORT_C);
12053                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12054                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12055                 }
12056
12057                 if (IS_CHERRYVIEW(dev)) {
12058                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12059                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12060                                                 PORT_D);
12061                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12062                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12063                         }
12064                 }
12065
12066                 intel_dsi_init(dev);
12067         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12068                 bool found = false;
12069
12070                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12071                         DRM_DEBUG_KMS("probing SDVOB\n");
12072                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12073                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12074                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12075                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12076                         }
12077
12078                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12079                                 intel_dp_init(dev, DP_B, PORT_B);
12080                 }
12081
12082                 /* Before G4X SDVOC doesn't have its own detect register */
12083
12084                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12085                         DRM_DEBUG_KMS("probing SDVOC\n");
12086                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12087                 }
12088
12089                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12090
12091                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12092                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12093                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12094                         }
12095                         if (SUPPORTS_INTEGRATED_DP(dev))
12096                                 intel_dp_init(dev, DP_C, PORT_C);
12097                 }
12098
12099                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12100                     (I915_READ(DP_D) & DP_DETECTED))
12101                         intel_dp_init(dev, DP_D, PORT_D);
12102         } else if (IS_GEN2(dev))
12103                 intel_dvo_init(dev);
12104
12105         if (SUPPORTS_TV(dev))
12106                 intel_tv_init(dev);
12107
12108         intel_edp_psr_init(dev);
12109
12110         for_each_intel_encoder(dev, encoder) {
12111                 encoder->base.possible_crtcs = encoder->crtc_mask;
12112                 encoder->base.possible_clones =
12113                         intel_encoder_clones(encoder);
12114         }
12115
12116         intel_init_pch_refclk(dev);
12117
12118         drm_helper_move_panel_connectors_to_head(dev);
12119 }
12120
12121 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12122 {
12123         struct drm_device *dev = fb->dev;
12124         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12125
12126         drm_framebuffer_cleanup(fb);
12127         mutex_lock(&dev->struct_mutex);
12128         WARN_ON(!intel_fb->obj->framebuffer_references--);
12129         drm_gem_object_unreference(&intel_fb->obj->base);
12130         mutex_unlock(&dev->struct_mutex);
12131         kfree(intel_fb);
12132 }
12133
12134 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12135                                                 struct drm_file *file,
12136                                                 unsigned int *handle)
12137 {
12138         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12139         struct drm_i915_gem_object *obj = intel_fb->obj;
12140
12141         return drm_gem_handle_create(file, &obj->base, handle);
12142 }
12143
12144 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12145         .destroy = intel_user_framebuffer_destroy,
12146         .create_handle = intel_user_framebuffer_create_handle,
12147 };
12148
12149 static int intel_framebuffer_init(struct drm_device *dev,
12150                                   struct intel_framebuffer *intel_fb,
12151                                   struct drm_mode_fb_cmd2 *mode_cmd,
12152                                   struct drm_i915_gem_object *obj)
12153 {
12154         int aligned_height;
12155         int pitch_limit;
12156         int ret;
12157
12158         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12159
12160         if (obj->tiling_mode == I915_TILING_Y) {
12161                 DRM_DEBUG("hardware does not support tiling Y\n");
12162                 return -EINVAL;
12163         }
12164
12165         if (mode_cmd->pitches[0] & 63) {
12166                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12167                           mode_cmd->pitches[0]);
12168                 return -EINVAL;
12169         }
12170
12171         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12172                 pitch_limit = 32*1024;
12173         } else if (INTEL_INFO(dev)->gen >= 4) {
12174                 if (obj->tiling_mode)
12175                         pitch_limit = 16*1024;
12176                 else
12177                         pitch_limit = 32*1024;
12178         } else if (INTEL_INFO(dev)->gen >= 3) {
12179                 if (obj->tiling_mode)
12180                         pitch_limit = 8*1024;
12181                 else
12182                         pitch_limit = 16*1024;
12183         } else
12184                 /* XXX DSPC is limited to 4k tiled */
12185                 pitch_limit = 8*1024;
12186
12187         if (mode_cmd->pitches[0] > pitch_limit) {
12188                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12189                           obj->tiling_mode ? "tiled" : "linear",
12190                           mode_cmd->pitches[0], pitch_limit);
12191                 return -EINVAL;
12192         }
12193
12194         if (obj->tiling_mode != I915_TILING_NONE &&
12195             mode_cmd->pitches[0] != obj->stride) {
12196                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12197                           mode_cmd->pitches[0], obj->stride);
12198                 return -EINVAL;
12199         }
12200
12201         /* Reject formats not supported by any plane early. */
12202         switch (mode_cmd->pixel_format) {
12203         case DRM_FORMAT_C8:
12204         case DRM_FORMAT_RGB565:
12205         case DRM_FORMAT_XRGB8888:
12206         case DRM_FORMAT_ARGB8888:
12207                 break;
12208         case DRM_FORMAT_XRGB1555:
12209         case DRM_FORMAT_ARGB1555:
12210                 if (INTEL_INFO(dev)->gen > 3) {
12211                         DRM_DEBUG("unsupported pixel format: %s\n",
12212                                   drm_get_format_name(mode_cmd->pixel_format));
12213                         return -EINVAL;
12214                 }
12215                 break;
12216         case DRM_FORMAT_XBGR8888:
12217         case DRM_FORMAT_ABGR8888:
12218         case DRM_FORMAT_XRGB2101010:
12219         case DRM_FORMAT_ARGB2101010:
12220         case DRM_FORMAT_XBGR2101010:
12221         case DRM_FORMAT_ABGR2101010:
12222                 if (INTEL_INFO(dev)->gen < 4) {
12223                         DRM_DEBUG("unsupported pixel format: %s\n",
12224                                   drm_get_format_name(mode_cmd->pixel_format));
12225                         return -EINVAL;
12226                 }
12227                 break;
12228         case DRM_FORMAT_YUYV:
12229         case DRM_FORMAT_UYVY:
12230         case DRM_FORMAT_YVYU:
12231         case DRM_FORMAT_VYUY:
12232                 if (INTEL_INFO(dev)->gen < 5) {
12233                         DRM_DEBUG("unsupported pixel format: %s\n",
12234                                   drm_get_format_name(mode_cmd->pixel_format));
12235                         return -EINVAL;
12236                 }
12237                 break;
12238         default:
12239                 DRM_DEBUG("unsupported pixel format: %s\n",
12240                           drm_get_format_name(mode_cmd->pixel_format));
12241                 return -EINVAL;
12242         }
12243
12244         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12245         if (mode_cmd->offsets[0] != 0)
12246                 return -EINVAL;
12247
12248         aligned_height = intel_align_height(dev, mode_cmd->height,
12249                                             obj->tiling_mode);
12250         /* FIXME drm helper for size checks (especially planar formats)? */
12251         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12252                 return -EINVAL;
12253
12254         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12255         intel_fb->obj = obj;
12256         intel_fb->obj->framebuffer_references++;
12257
12258         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12259         if (ret) {
12260                 DRM_ERROR("framebuffer init failed %d\n", ret);
12261                 return ret;
12262         }
12263
12264         return 0;
12265 }
12266
12267 static struct drm_framebuffer *
12268 intel_user_framebuffer_create(struct drm_device *dev,
12269                               struct drm_file *filp,
12270                               struct drm_mode_fb_cmd2 *mode_cmd)
12271 {
12272         struct drm_i915_gem_object *obj;
12273
12274         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12275                                                 mode_cmd->handles[0]));
12276         if (&obj->base == NULL)
12277                 return ERR_PTR(-ENOENT);
12278
12279         return intel_framebuffer_create(dev, mode_cmd, obj);
12280 }
12281
12282 #ifndef CONFIG_DRM_I915_FBDEV
12283 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12284 {
12285 }
12286 #endif
12287
12288 static const struct drm_mode_config_funcs intel_mode_funcs = {
12289         .fb_create = intel_user_framebuffer_create,
12290         .output_poll_changed = intel_fbdev_output_poll_changed,
12291 };
12292
12293 /* Set up chip specific display functions */
12294 static void intel_init_display(struct drm_device *dev)
12295 {
12296         struct drm_i915_private *dev_priv = dev->dev_private;
12297
12298         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12299                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12300         else if (IS_CHERRYVIEW(dev))
12301                 dev_priv->display.find_dpll = chv_find_best_dpll;
12302         else if (IS_VALLEYVIEW(dev))
12303                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12304         else if (IS_PINEVIEW(dev))
12305                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12306         else
12307                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12308
12309         if (HAS_DDI(dev)) {
12310                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12311                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12312                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12313                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12314                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12315                 dev_priv->display.off = ironlake_crtc_off;
12316                 dev_priv->display.update_primary_plane =
12317                         ironlake_update_primary_plane;
12318         } else if (HAS_PCH_SPLIT(dev)) {
12319                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12320                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12321                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12322                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12323                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12324                 dev_priv->display.off = ironlake_crtc_off;
12325                 dev_priv->display.update_primary_plane =
12326                         ironlake_update_primary_plane;
12327         } else if (IS_VALLEYVIEW(dev)) {
12328                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12329                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12330                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12331                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12332                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12333                 dev_priv->display.off = i9xx_crtc_off;
12334                 dev_priv->display.update_primary_plane =
12335                         i9xx_update_primary_plane;
12336         } else {
12337                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12338                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12339                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12340                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12341                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12342                 dev_priv->display.off = i9xx_crtc_off;
12343                 dev_priv->display.update_primary_plane =
12344                         i9xx_update_primary_plane;
12345         }
12346
12347         /* Returns the core display clock speed */
12348         if (IS_VALLEYVIEW(dev))
12349                 dev_priv->display.get_display_clock_speed =
12350                         valleyview_get_display_clock_speed;
12351         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12352                 dev_priv->display.get_display_clock_speed =
12353                         i945_get_display_clock_speed;
12354         else if (IS_I915G(dev))
12355                 dev_priv->display.get_display_clock_speed =
12356                         i915_get_display_clock_speed;
12357         else if (IS_I945GM(dev) || IS_845G(dev))
12358                 dev_priv->display.get_display_clock_speed =
12359                         i9xx_misc_get_display_clock_speed;
12360         else if (IS_PINEVIEW(dev))
12361                 dev_priv->display.get_display_clock_speed =
12362                         pnv_get_display_clock_speed;
12363         else if (IS_I915GM(dev))
12364                 dev_priv->display.get_display_clock_speed =
12365                         i915gm_get_display_clock_speed;
12366         else if (IS_I865G(dev))
12367                 dev_priv->display.get_display_clock_speed =
12368                         i865_get_display_clock_speed;
12369         else if (IS_I85X(dev))
12370                 dev_priv->display.get_display_clock_speed =
12371                         i855_get_display_clock_speed;
12372         else /* 852, 830 */
12373                 dev_priv->display.get_display_clock_speed =
12374                         i830_get_display_clock_speed;
12375
12376         if (IS_G4X(dev)) {
12377                 dev_priv->display.write_eld = g4x_write_eld;
12378         } else if (IS_GEN5(dev)) {
12379                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12380                 dev_priv->display.write_eld = ironlake_write_eld;
12381         } else if (IS_GEN6(dev)) {
12382                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12383                 dev_priv->display.write_eld = ironlake_write_eld;
12384                 dev_priv->display.modeset_global_resources =
12385                         snb_modeset_global_resources;
12386         } else if (IS_IVYBRIDGE(dev)) {
12387                 /* FIXME: detect B0+ stepping and use auto training */
12388                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12389                 dev_priv->display.write_eld = ironlake_write_eld;
12390                 dev_priv->display.modeset_global_resources =
12391                         ivb_modeset_global_resources;
12392         } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12393                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12394                 dev_priv->display.write_eld = haswell_write_eld;
12395                 dev_priv->display.modeset_global_resources =
12396                         haswell_modeset_global_resources;
12397         } else if (IS_VALLEYVIEW(dev)) {
12398                 dev_priv->display.modeset_global_resources =
12399                         valleyview_modeset_global_resources;
12400                 dev_priv->display.write_eld = ironlake_write_eld;
12401         }
12402
12403         /* Default just returns -ENODEV to indicate unsupported */
12404         dev_priv->display.queue_flip = intel_default_queue_flip;
12405
12406         switch (INTEL_INFO(dev)->gen) {
12407         case 2:
12408                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12409                 break;
12410
12411         case 3:
12412                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12413                 break;
12414
12415         case 4:
12416         case 5:
12417                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12418                 break;
12419
12420         case 6:
12421                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12422                 break;
12423         case 7:
12424         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12425                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12426                 break;
12427         }
12428
12429         intel_panel_init_backlight_funcs(dev);
12430 }
12431
12432 /*
12433  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12434  * resume, or other times.  This quirk makes sure that's the case for
12435  * affected systems.
12436  */
12437 static void quirk_pipea_force(struct drm_device *dev)
12438 {
12439         struct drm_i915_private *dev_priv = dev->dev_private;
12440
12441         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12442         DRM_INFO("applying pipe a force quirk\n");
12443 }
12444
12445 /*
12446  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12447  */
12448 static void quirk_ssc_force_disable(struct drm_device *dev)
12449 {
12450         struct drm_i915_private *dev_priv = dev->dev_private;
12451         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12452         DRM_INFO("applying lvds SSC disable quirk\n");
12453 }
12454
12455 /*
12456  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12457  * brightness value
12458  */
12459 static void quirk_invert_brightness(struct drm_device *dev)
12460 {
12461         struct drm_i915_private *dev_priv = dev->dev_private;
12462         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12463         DRM_INFO("applying inverted panel brightness quirk\n");
12464 }
12465
12466 /* Some VBT's incorrectly indicate no backlight is present */
12467 static void quirk_backlight_present(struct drm_device *dev)
12468 {
12469         struct drm_i915_private *dev_priv = dev->dev_private;
12470         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12471         DRM_INFO("applying backlight present quirk\n");
12472 }
12473
12474 struct intel_quirk {
12475         int device;
12476         int subsystem_vendor;
12477         int subsystem_device;
12478         void (*hook)(struct drm_device *dev);
12479 };
12480
12481 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12482 struct intel_dmi_quirk {
12483         void (*hook)(struct drm_device *dev);
12484         const struct dmi_system_id (*dmi_id_list)[];
12485 };
12486
12487 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12488 {
12489         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12490         return 1;
12491 }
12492
12493 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12494         {
12495                 .dmi_id_list = &(const struct dmi_system_id[]) {
12496                         {
12497                                 .callback = intel_dmi_reverse_brightness,
12498                                 .ident = "NCR Corporation",
12499                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12500                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12501                                 },
12502                         },
12503                         { }  /* terminating entry */
12504                 },
12505                 .hook = quirk_invert_brightness,
12506         },
12507 };
12508
12509 static struct intel_quirk intel_quirks[] = {
12510         /* HP Mini needs pipe A force quirk (LP: #322104) */
12511         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12512
12513         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12514         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12515
12516         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12517         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12518
12519         /* Lenovo U160 cannot use SSC on LVDS */
12520         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12521
12522         /* Sony Vaio Y cannot use SSC on LVDS */
12523         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12524
12525         /* Acer Aspire 5734Z must invert backlight brightness */
12526         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12527
12528         /* Acer/eMachines G725 */
12529         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12530
12531         /* Acer/eMachines e725 */
12532         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12533
12534         /* Acer/Packard Bell NCL20 */
12535         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12536
12537         /* Acer Aspire 4736Z */
12538         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12539
12540         /* Acer Aspire 5336 */
12541         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12542
12543         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12544         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12545
12546         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12547         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12548
12549         /* HP Chromebook 14 (Celeron 2955U) */
12550         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12551 };
12552
12553 static void intel_init_quirks(struct drm_device *dev)
12554 {
12555         struct pci_dev *d = dev->pdev;
12556         int i;
12557
12558         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12559                 struct intel_quirk *q = &intel_quirks[i];
12560
12561                 if (d->device == q->device &&
12562                     (d->subsystem_vendor == q->subsystem_vendor ||
12563                      q->subsystem_vendor == PCI_ANY_ID) &&
12564                     (d->subsystem_device == q->subsystem_device ||
12565                      q->subsystem_device == PCI_ANY_ID))
12566                         q->hook(dev);
12567         }
12568         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12569                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12570                         intel_dmi_quirks[i].hook(dev);
12571         }
12572 }
12573
12574 /* Disable the VGA plane that we never use */
12575 static void i915_disable_vga(struct drm_device *dev)
12576 {
12577         struct drm_i915_private *dev_priv = dev->dev_private;
12578         u8 sr1;
12579         u32 vga_reg = i915_vgacntrl_reg(dev);
12580
12581         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12582         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12583         outb(SR01, VGA_SR_INDEX);
12584         sr1 = inb(VGA_SR_DATA);
12585         outb(sr1 | 1<<5, VGA_SR_DATA);
12586         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12587         udelay(300);
12588
12589         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12590         POSTING_READ(vga_reg);
12591 }
12592
12593 void intel_modeset_init_hw(struct drm_device *dev)
12594 {
12595         intel_prepare_ddi(dev);
12596
12597         if (IS_VALLEYVIEW(dev))
12598                 vlv_update_cdclk(dev);
12599
12600         intel_init_clock_gating(dev);
12601
12602         intel_enable_gt_powersave(dev);
12603 }
12604
12605 void intel_modeset_suspend_hw(struct drm_device *dev)
12606 {
12607         intel_suspend_hw(dev);
12608 }
12609
12610 void intel_modeset_init(struct drm_device *dev)
12611 {
12612         struct drm_i915_private *dev_priv = dev->dev_private;
12613         int sprite, ret;
12614         enum pipe pipe;
12615         struct intel_crtc *crtc;
12616
12617         drm_mode_config_init(dev);
12618
12619         dev->mode_config.min_width = 0;
12620         dev->mode_config.min_height = 0;
12621
12622         dev->mode_config.preferred_depth = 24;
12623         dev->mode_config.prefer_shadow = 1;
12624
12625         dev->mode_config.funcs = &intel_mode_funcs;
12626
12627         intel_init_quirks(dev);
12628
12629         intel_init_pm(dev);
12630
12631         if (INTEL_INFO(dev)->num_pipes == 0)
12632                 return;
12633
12634         intel_init_display(dev);
12635
12636         if (IS_GEN2(dev)) {
12637                 dev->mode_config.max_width = 2048;
12638                 dev->mode_config.max_height = 2048;
12639         } else if (IS_GEN3(dev)) {
12640                 dev->mode_config.max_width = 4096;
12641                 dev->mode_config.max_height = 4096;
12642         } else {
12643                 dev->mode_config.max_width = 8192;
12644                 dev->mode_config.max_height = 8192;
12645         }
12646
12647         if (IS_845G(dev) || IS_I865G(dev)) {
12648                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12649                 dev->mode_config.cursor_height = 1023;
12650         } else if (IS_GEN2(dev)) {
12651                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12652                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12653         } else {
12654                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12655                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12656         }
12657
12658         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12659
12660         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12661                       INTEL_INFO(dev)->num_pipes,
12662                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12663
12664         for_each_pipe(pipe) {
12665                 intel_crtc_init(dev, pipe);
12666                 for_each_sprite(pipe, sprite) {
12667                         ret = intel_plane_init(dev, pipe, sprite);
12668                         if (ret)
12669                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12670                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12671                 }
12672         }
12673
12674         intel_init_dpio(dev);
12675
12676         intel_shared_dpll_init(dev);
12677
12678         /* Just disable it once at startup */
12679         i915_disable_vga(dev);
12680         intel_setup_outputs(dev);
12681
12682         /* Just in case the BIOS is doing something questionable. */
12683         intel_disable_fbc(dev);
12684
12685         drm_modeset_lock_all(dev);
12686         intel_modeset_setup_hw_state(dev, false);
12687         drm_modeset_unlock_all(dev);
12688
12689         for_each_intel_crtc(dev, crtc) {
12690                 if (!crtc->active)
12691                         continue;
12692
12693                 /*
12694                  * Note that reserving the BIOS fb up front prevents us
12695                  * from stuffing other stolen allocations like the ring
12696                  * on top.  This prevents some ugliness at boot time, and
12697                  * can even allow for smooth boot transitions if the BIOS
12698                  * fb is large enough for the active pipe configuration.
12699                  */
12700                 if (dev_priv->display.get_plane_config) {
12701                         dev_priv->display.get_plane_config(crtc,
12702                                                            &crtc->plane_config);
12703                         /*
12704                          * If the fb is shared between multiple heads, we'll
12705                          * just get the first one.
12706                          */
12707                         intel_find_plane_obj(crtc, &crtc->plane_config);
12708                 }
12709         }
12710 }
12711
12712 static void intel_enable_pipe_a(struct drm_device *dev)
12713 {
12714         struct intel_connector *connector;
12715         struct drm_connector *crt = NULL;
12716         struct intel_load_detect_pipe load_detect_temp;
12717         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12718
12719         /* We can't just switch on the pipe A, we need to set things up with a
12720          * proper mode and output configuration. As a gross hack, enable pipe A
12721          * by enabling the load detect pipe once. */
12722         list_for_each_entry(connector,
12723                             &dev->mode_config.connector_list,
12724                             base.head) {
12725                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12726                         crt = &connector->base;
12727                         break;
12728                 }
12729         }
12730
12731         if (!crt)
12732                 return;
12733
12734         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12735                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12736 }
12737
12738 static bool
12739 intel_check_plane_mapping(struct intel_crtc *crtc)
12740 {
12741         struct drm_device *dev = crtc->base.dev;
12742         struct drm_i915_private *dev_priv = dev->dev_private;
12743         u32 reg, val;
12744
12745         if (INTEL_INFO(dev)->num_pipes == 1)
12746                 return true;
12747
12748         reg = DSPCNTR(!crtc->plane);
12749         val = I915_READ(reg);
12750
12751         if ((val & DISPLAY_PLANE_ENABLE) &&
12752             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12753                 return false;
12754
12755         return true;
12756 }
12757
12758 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12759 {
12760         struct drm_device *dev = crtc->base.dev;
12761         struct drm_i915_private *dev_priv = dev->dev_private;
12762         u32 reg;
12763
12764         /* Clear any frame start delays used for debugging left by the BIOS */
12765         reg = PIPECONF(crtc->config.cpu_transcoder);
12766         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12767
12768         /* restore vblank interrupts to correct state */
12769         if (crtc->active)
12770                 drm_vblank_on(dev, crtc->pipe);
12771         else
12772                 drm_vblank_off(dev, crtc->pipe);
12773
12774         /* We need to sanitize the plane -> pipe mapping first because this will
12775          * disable the crtc (and hence change the state) if it is wrong. Note
12776          * that gen4+ has a fixed plane -> pipe mapping.  */
12777         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12778                 struct intel_connector *connector;
12779                 bool plane;
12780
12781                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12782                               crtc->base.base.id);
12783
12784                 /* Pipe has the wrong plane attached and the plane is active.
12785                  * Temporarily change the plane mapping and disable everything
12786                  * ...  */
12787                 plane = crtc->plane;
12788                 crtc->plane = !plane;
12789                 crtc->primary_enabled = true;
12790                 dev_priv->display.crtc_disable(&crtc->base);
12791                 crtc->plane = plane;
12792
12793                 /* ... and break all links. */
12794                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12795                                     base.head) {
12796                         if (connector->encoder->base.crtc != &crtc->base)
12797                                 continue;
12798
12799                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12800                         connector->base.encoder = NULL;
12801                 }
12802                 /* multiple connectors may have the same encoder:
12803                  *  handle them and break crtc link separately */
12804                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12805                                     base.head)
12806                         if (connector->encoder->base.crtc == &crtc->base) {
12807                                 connector->encoder->base.crtc = NULL;
12808                                 connector->encoder->connectors_active = false;
12809                         }
12810
12811                 WARN_ON(crtc->active);
12812                 crtc->base.enabled = false;
12813         }
12814
12815         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12816             crtc->pipe == PIPE_A && !crtc->active) {
12817                 /* BIOS forgot to enable pipe A, this mostly happens after
12818                  * resume. Force-enable the pipe to fix this, the update_dpms
12819                  * call below we restore the pipe to the right state, but leave
12820                  * the required bits on. */
12821                 intel_enable_pipe_a(dev);
12822         }
12823
12824         /* Adjust the state of the output pipe according to whether we
12825          * have active connectors/encoders. */
12826         intel_crtc_update_dpms(&crtc->base);
12827
12828         if (crtc->active != crtc->base.enabled) {
12829                 struct intel_encoder *encoder;
12830
12831                 /* This can happen either due to bugs in the get_hw_state
12832                  * functions or because the pipe is force-enabled due to the
12833                  * pipe A quirk. */
12834                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12835                               crtc->base.base.id,
12836                               crtc->base.enabled ? "enabled" : "disabled",
12837                               crtc->active ? "enabled" : "disabled");
12838
12839                 crtc->base.enabled = crtc->active;
12840
12841                 /* Because we only establish the connector -> encoder ->
12842                  * crtc links if something is active, this means the
12843                  * crtc is now deactivated. Break the links. connector
12844                  * -> encoder links are only establish when things are
12845                  *  actually up, hence no need to break them. */
12846                 WARN_ON(crtc->active);
12847
12848                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12849                         WARN_ON(encoder->connectors_active);
12850                         encoder->base.crtc = NULL;
12851                 }
12852         }
12853
12854         if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12855                 /*
12856                  * We start out with underrun reporting disabled to avoid races.
12857                  * For correct bookkeeping mark this on active crtcs.
12858                  *
12859                  * Also on gmch platforms we dont have any hardware bits to
12860                  * disable the underrun reporting. Which means we need to start
12861                  * out with underrun reporting disabled also on inactive pipes,
12862                  * since otherwise we'll complain about the garbage we read when
12863                  * e.g. coming up after runtime pm.
12864                  *
12865                  * No protection against concurrent access is required - at
12866                  * worst a fifo underrun happens which also sets this to false.
12867                  */
12868                 crtc->cpu_fifo_underrun_disabled = true;
12869                 crtc->pch_fifo_underrun_disabled = true;
12870
12871                 update_scanline_offset(crtc);
12872         }
12873 }
12874
12875 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12876 {
12877         struct intel_connector *connector;
12878         struct drm_device *dev = encoder->base.dev;
12879
12880         /* We need to check both for a crtc link (meaning that the
12881          * encoder is active and trying to read from a pipe) and the
12882          * pipe itself being active. */
12883         bool has_active_crtc = encoder->base.crtc &&
12884                 to_intel_crtc(encoder->base.crtc)->active;
12885
12886         if (encoder->connectors_active && !has_active_crtc) {
12887                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12888                               encoder->base.base.id,
12889                               encoder->base.name);
12890
12891                 /* Connector is active, but has no active pipe. This is
12892                  * fallout from our resume register restoring. Disable
12893                  * the encoder manually again. */
12894                 if (encoder->base.crtc) {
12895                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12896                                       encoder->base.base.id,
12897                                       encoder->base.name);
12898                         encoder->disable(encoder);
12899                         if (encoder->post_disable)
12900                                 encoder->post_disable(encoder);
12901                 }
12902                 encoder->base.crtc = NULL;
12903                 encoder->connectors_active = false;
12904
12905                 /* Inconsistent output/port/pipe state happens presumably due to
12906                  * a bug in one of the get_hw_state functions. Or someplace else
12907                  * in our code, like the register restore mess on resume. Clamp
12908                  * things to off as a safer default. */
12909                 list_for_each_entry(connector,
12910                                     &dev->mode_config.connector_list,
12911                                     base.head) {
12912                         if (connector->encoder != encoder)
12913                                 continue;
12914                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12915                         connector->base.encoder = NULL;
12916                 }
12917         }
12918         /* Enabled encoders without active connectors will be fixed in
12919          * the crtc fixup. */
12920 }
12921
12922 void i915_redisable_vga_power_on(struct drm_device *dev)
12923 {
12924         struct drm_i915_private *dev_priv = dev->dev_private;
12925         u32 vga_reg = i915_vgacntrl_reg(dev);
12926
12927         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12928                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12929                 i915_disable_vga(dev);
12930         }
12931 }
12932
12933 void i915_redisable_vga(struct drm_device *dev)
12934 {
12935         struct drm_i915_private *dev_priv = dev->dev_private;
12936
12937         /* This function can be called both from intel_modeset_setup_hw_state or
12938          * at a very early point in our resume sequence, where the power well
12939          * structures are not yet restored. Since this function is at a very
12940          * paranoid "someone might have enabled VGA while we were not looking"
12941          * level, just check if the power well is enabled instead of trying to
12942          * follow the "don't touch the power well if we don't need it" policy
12943          * the rest of the driver uses. */
12944         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12945                 return;
12946
12947         i915_redisable_vga_power_on(dev);
12948 }
12949
12950 static bool primary_get_hw_state(struct intel_crtc *crtc)
12951 {
12952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12953
12954         if (!crtc->active)
12955                 return false;
12956
12957         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12958 }
12959
12960 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12961 {
12962         struct drm_i915_private *dev_priv = dev->dev_private;
12963         enum pipe pipe;
12964         struct intel_crtc *crtc;
12965         struct intel_encoder *encoder;
12966         struct intel_connector *connector;
12967         int i;
12968
12969         for_each_intel_crtc(dev, crtc) {
12970                 memset(&crtc->config, 0, sizeof(crtc->config));
12971
12972                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12973
12974                 crtc->active = dev_priv->display.get_pipe_config(crtc,
12975                                                                  &crtc->config);
12976
12977                 crtc->base.enabled = crtc->active;
12978                 crtc->primary_enabled = primary_get_hw_state(crtc);
12979
12980                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12981                               crtc->base.base.id,
12982                               crtc->active ? "enabled" : "disabled");
12983         }
12984
12985         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12986                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12987
12988                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12989                 pll->active = 0;
12990                 for_each_intel_crtc(dev, crtc) {
12991                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12992                                 pll->active++;
12993                 }
12994                 pll->refcount = pll->active;
12995
12996                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12997                               pll->name, pll->refcount, pll->on);
12998
12999                 if (pll->refcount)
13000                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13001         }
13002
13003         for_each_intel_encoder(dev, encoder) {
13004                 pipe = 0;
13005
13006                 if (encoder->get_hw_state(encoder, &pipe)) {
13007                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13008                         encoder->base.crtc = &crtc->base;
13009                         encoder->get_config(encoder, &crtc->config);
13010                 } else {
13011                         encoder->base.crtc = NULL;
13012                 }
13013
13014                 encoder->connectors_active = false;
13015                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13016                               encoder->base.base.id,
13017                               encoder->base.name,
13018                               encoder->base.crtc ? "enabled" : "disabled",
13019                               pipe_name(pipe));
13020         }
13021
13022         list_for_each_entry(connector, &dev->mode_config.connector_list,
13023                             base.head) {
13024                 if (connector->get_hw_state(connector)) {
13025                         connector->base.dpms = DRM_MODE_DPMS_ON;
13026                         connector->encoder->connectors_active = true;
13027                         connector->base.encoder = &connector->encoder->base;
13028                 } else {
13029                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13030                         connector->base.encoder = NULL;
13031                 }
13032                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13033                               connector->base.base.id,
13034                               connector->base.name,
13035                               connector->base.encoder ? "enabled" : "disabled");
13036         }
13037 }
13038
13039 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13040  * and i915 state tracking structures. */
13041 void intel_modeset_setup_hw_state(struct drm_device *dev,
13042                                   bool force_restore)
13043 {
13044         struct drm_i915_private *dev_priv = dev->dev_private;
13045         enum pipe pipe;
13046         struct intel_crtc *crtc;
13047         struct intel_encoder *encoder;
13048         int i;
13049
13050         intel_modeset_readout_hw_state(dev);
13051
13052         /*
13053          * Now that we have the config, copy it to each CRTC struct
13054          * Note that this could go away if we move to using crtc_config
13055          * checking everywhere.
13056          */
13057         for_each_intel_crtc(dev, crtc) {
13058                 if (crtc->active && i915.fastboot) {
13059                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13060                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13061                                       crtc->base.base.id);
13062                         drm_mode_debug_printmodeline(&crtc->base.mode);
13063                 }
13064         }
13065
13066         /* HW state is read out, now we need to sanitize this mess. */
13067         for_each_intel_encoder(dev, encoder) {
13068                 intel_sanitize_encoder(encoder);
13069         }
13070
13071         for_each_pipe(pipe) {
13072                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13073                 intel_sanitize_crtc(crtc);
13074                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13075         }
13076
13077         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13078                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13079
13080                 if (!pll->on || pll->active)
13081                         continue;
13082
13083                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13084
13085                 pll->disable(dev_priv, pll);
13086                 pll->on = false;
13087         }
13088
13089         if (HAS_PCH_SPLIT(dev))
13090                 ilk_wm_get_hw_state(dev);
13091
13092         if (force_restore) {
13093                 i915_redisable_vga(dev);
13094
13095                 /*
13096                  * We need to use raw interfaces for restoring state to avoid
13097                  * checking (bogus) intermediate states.
13098                  */
13099                 for_each_pipe(pipe) {
13100                         struct drm_crtc *crtc =
13101                                 dev_priv->pipe_to_crtc_mapping[pipe];
13102
13103                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13104                                          crtc->primary->fb);
13105                 }
13106         } else {
13107                 intel_modeset_update_staged_output_state(dev);
13108         }
13109
13110         intel_modeset_check_state(dev);
13111 }
13112
13113 void intel_modeset_gem_init(struct drm_device *dev)
13114 {
13115         struct drm_crtc *c;
13116         struct drm_i915_gem_object *obj;
13117
13118         mutex_lock(&dev->struct_mutex);
13119         intel_init_gt_powersave(dev);
13120         mutex_unlock(&dev->struct_mutex);
13121
13122         intel_modeset_init_hw(dev);
13123
13124         intel_setup_overlay(dev);
13125
13126         /*
13127          * Make sure any fbs we allocated at startup are properly
13128          * pinned & fenced.  When we do the allocation it's too early
13129          * for this.
13130          */
13131         mutex_lock(&dev->struct_mutex);
13132         for_each_crtc(dev, c) {
13133                 obj = intel_fb_obj(c->primary->fb);
13134                 if (obj == NULL)
13135                         continue;
13136
13137                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13138                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13139                                   to_intel_crtc(c)->pipe);
13140                         drm_framebuffer_unreference(c->primary->fb);
13141                         c->primary->fb = NULL;
13142                 }
13143         }
13144         mutex_unlock(&dev->struct_mutex);
13145 }
13146
13147 void intel_connector_unregister(struct intel_connector *intel_connector)
13148 {
13149         struct drm_connector *connector = &intel_connector->base;
13150
13151         intel_panel_destroy_backlight(connector);
13152         drm_connector_unregister(connector);
13153 }
13154
13155 void intel_modeset_cleanup(struct drm_device *dev)
13156 {
13157         struct drm_i915_private *dev_priv = dev->dev_private;
13158         struct drm_connector *connector;
13159
13160         /*
13161          * Interrupts and polling as the first thing to avoid creating havoc.
13162          * Too much stuff here (turning of rps, connectors, ...) would
13163          * experience fancy races otherwise.
13164          */
13165         drm_irq_uninstall(dev);
13166         intel_hpd_cancel_work(dev_priv);
13167         dev_priv->pm._irqs_disabled = true;
13168
13169         /*
13170          * Due to the hpd irq storm handling the hotplug work can re-arm the
13171          * poll handlers. Hence disable polling after hpd handling is shut down.
13172          */
13173         drm_kms_helper_poll_fini(dev);
13174
13175         mutex_lock(&dev->struct_mutex);
13176
13177         intel_unregister_dsm_handler();
13178
13179         intel_disable_fbc(dev);
13180
13181         intel_disable_gt_powersave(dev);
13182
13183         ironlake_teardown_rc6(dev);
13184
13185         mutex_unlock(&dev->struct_mutex);
13186
13187         /* flush any delayed tasks or pending work */
13188         flush_scheduled_work();
13189
13190         /* destroy the backlight and sysfs files before encoders/connectors */
13191         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13192                 struct intel_connector *intel_connector;
13193
13194                 intel_connector = to_intel_connector(connector);
13195                 intel_connector->unregister(intel_connector);
13196         }
13197
13198         drm_mode_config_cleanup(dev);
13199
13200         intel_cleanup_overlay(dev);
13201
13202         mutex_lock(&dev->struct_mutex);
13203         intel_cleanup_gt_powersave(dev);
13204         mutex_unlock(&dev->struct_mutex);
13205 }
13206
13207 /*
13208  * Return which encoder is currently attached for connector.
13209  */
13210 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13211 {
13212         return &intel_attached_encoder(connector)->base;
13213 }
13214
13215 void intel_connector_attach_encoder(struct intel_connector *connector,
13216                                     struct intel_encoder *encoder)
13217 {
13218         connector->encoder = encoder;
13219         drm_mode_connector_attach_encoder(&connector->base,
13220                                           &encoder->base);
13221 }
13222
13223 /*
13224  * set vga decode state - true == enable VGA decode
13225  */
13226 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13227 {
13228         struct drm_i915_private *dev_priv = dev->dev_private;
13229         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13230         u16 gmch_ctrl;
13231
13232         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13233                 DRM_ERROR("failed to read control word\n");
13234                 return -EIO;
13235         }
13236
13237         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13238                 return 0;
13239
13240         if (state)
13241                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13242         else
13243                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13244
13245         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13246                 DRM_ERROR("failed to write control word\n");
13247                 return -EIO;
13248         }
13249
13250         return 0;
13251 }
13252
13253 struct intel_display_error_state {
13254
13255         u32 power_well_driver;
13256
13257         int num_transcoders;
13258
13259         struct intel_cursor_error_state {
13260                 u32 control;
13261                 u32 position;
13262                 u32 base;
13263                 u32 size;
13264         } cursor[I915_MAX_PIPES];
13265
13266         struct intel_pipe_error_state {
13267                 bool power_domain_on;
13268                 u32 source;
13269                 u32 stat;
13270         } pipe[I915_MAX_PIPES];
13271
13272         struct intel_plane_error_state {
13273                 u32 control;
13274                 u32 stride;
13275                 u32 size;
13276                 u32 pos;
13277                 u32 addr;
13278                 u32 surface;
13279                 u32 tile_offset;
13280         } plane[I915_MAX_PIPES];
13281
13282         struct intel_transcoder_error_state {
13283                 bool power_domain_on;
13284                 enum transcoder cpu_transcoder;
13285
13286                 u32 conf;
13287
13288                 u32 htotal;
13289                 u32 hblank;
13290                 u32 hsync;
13291                 u32 vtotal;
13292                 u32 vblank;
13293                 u32 vsync;
13294         } transcoder[4];
13295 };
13296
13297 struct intel_display_error_state *
13298 intel_display_capture_error_state(struct drm_device *dev)
13299 {
13300         struct drm_i915_private *dev_priv = dev->dev_private;
13301         struct intel_display_error_state *error;
13302         int transcoders[] = {
13303                 TRANSCODER_A,
13304                 TRANSCODER_B,
13305                 TRANSCODER_C,
13306                 TRANSCODER_EDP,
13307         };
13308         int i;
13309
13310         if (INTEL_INFO(dev)->num_pipes == 0)
13311                 return NULL;
13312
13313         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13314         if (error == NULL)
13315                 return NULL;
13316
13317         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13318                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13319
13320         for_each_pipe(i) {
13321                 error->pipe[i].power_domain_on =
13322                         intel_display_power_enabled_unlocked(dev_priv,
13323                                                            POWER_DOMAIN_PIPE(i));
13324                 if (!error->pipe[i].power_domain_on)
13325                         continue;
13326
13327                 error->cursor[i].control = I915_READ(CURCNTR(i));
13328                 error->cursor[i].position = I915_READ(CURPOS(i));
13329                 error->cursor[i].base = I915_READ(CURBASE(i));
13330
13331                 error->plane[i].control = I915_READ(DSPCNTR(i));
13332                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13333                 if (INTEL_INFO(dev)->gen <= 3) {
13334                         error->plane[i].size = I915_READ(DSPSIZE(i));
13335                         error->plane[i].pos = I915_READ(DSPPOS(i));
13336                 }
13337                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13338                         error->plane[i].addr = I915_READ(DSPADDR(i));
13339                 if (INTEL_INFO(dev)->gen >= 4) {
13340                         error->plane[i].surface = I915_READ(DSPSURF(i));
13341                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13342                 }
13343
13344                 error->pipe[i].source = I915_READ(PIPESRC(i));
13345
13346                 if (HAS_GMCH_DISPLAY(dev))
13347                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13348         }
13349
13350         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13351         if (HAS_DDI(dev_priv->dev))
13352                 error->num_transcoders++; /* Account for eDP. */
13353
13354         for (i = 0; i < error->num_transcoders; i++) {
13355                 enum transcoder cpu_transcoder = transcoders[i];
13356
13357                 error->transcoder[i].power_domain_on =
13358                         intel_display_power_enabled_unlocked(dev_priv,
13359                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13360                 if (!error->transcoder[i].power_domain_on)
13361                         continue;
13362
13363                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13364
13365                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13366                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13367                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13368                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13369                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13370                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13371                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13372         }
13373
13374         return error;
13375 }
13376
13377 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13378
13379 void
13380 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13381                                 struct drm_device *dev,
13382                                 struct intel_display_error_state *error)
13383 {
13384         int i;
13385
13386         if (!error)
13387                 return;
13388
13389         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13390         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13391                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13392                            error->power_well_driver);
13393         for_each_pipe(i) {
13394                 err_printf(m, "Pipe [%d]:\n", i);
13395                 err_printf(m, "  Power: %s\n",
13396                            error->pipe[i].power_domain_on ? "on" : "off");
13397                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13398                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13399
13400                 err_printf(m, "Plane [%d]:\n", i);
13401                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13402                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13403                 if (INTEL_INFO(dev)->gen <= 3) {
13404                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13405                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13406                 }
13407                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13408                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13409                 if (INTEL_INFO(dev)->gen >= 4) {
13410                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13411                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13412                 }
13413
13414                 err_printf(m, "Cursor [%d]:\n", i);
13415                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13416                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13417                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13418         }
13419
13420         for (i = 0; i < error->num_transcoders; i++) {
13421                 err_printf(m, "CPU transcoder: %c\n",
13422                            transcoder_name(error->transcoder[i].cpu_transcoder));
13423                 err_printf(m, "  Power: %s\n",
13424                            error->transcoder[i].power_domain_on ? "on" : "off");
13425                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13426                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13427                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13428                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13429                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13430                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13431                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13432         }
13433 }
13434
13435 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13436 {
13437         struct intel_crtc *crtc;
13438
13439         for_each_intel_crtc(dev, crtc) {
13440                 struct intel_unpin_work *work;
13441                 unsigned long irqflags;
13442
13443                 spin_lock_irqsave(&dev->event_lock, irqflags);
13444
13445                 work = crtc->unpin_work;
13446
13447                 if (work && work->event &&
13448                     work->event->base.file_priv == file) {
13449                         kfree(work->event);
13450                         work->event = NULL;
13451                 }
13452
13453                 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13454         }
13455 }