drivers/gpu/drm/display/drm_dp_helper.c

   1 /*
   2  * Copyright © 2009 Keith Packard
   3  *
   4  * Permission to use, copy, modify, distribute, and sell this software and its
   5  * documentation for any purpose is hereby granted without fee, provided that
   6  * the above copyright notice appear in all copies and that both that copyright
   7  * notice and this permission notice appear in supporting documentation, and
   8  * that the name of the copyright holders not be used in advertising or
   9  * publicity pertaining to distribution of the software without specific,
  10  * written prior permission.  The copyright holders make no representations
  11  * about the suitability of this software for any purpose.  It is provided "as
  12  * is" without express or implied warranty.
  13  *
  14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20  * OF THIS SOFTWARE.
  21  */
  22
  23 #include <linux/backlight.h>
  24 #include <linux/delay.h>
  25 #include <linux/errno.h>
  26 #include <linux/i2c.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/sched.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/dynamic_debug.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/display/drm_dp_mst_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include <drm/drm_print.h>
  39 #include <drm/drm_vblank.h>
  40 #include <drm/drm_panel.h>
  41
  42 #include "drm_dp_helper_internal.h"
  43
  44 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
  45                         "DRM_UT_CORE",
  46                         "DRM_UT_DRIVER",
  47                         "DRM_UT_KMS",
  48                         "DRM_UT_PRIME",
  49                         "DRM_UT_ATOMIC",
  50                         "DRM_UT_VBL",
  51                         "DRM_UT_STATE",
  52                         "DRM_UT_LEASE",
  53                         "DRM_UT_DP",
  54                         "DRM_UT_DRMRES");
  55
  56 struct dp_aux_backlight {
  57         struct backlight_device *base;
  58         struct drm_dp_aux *aux;
  59         struct drm_edp_backlight_info info;
  60         bool enabled;
  61 };
  62
  63 /**
  64  * DOC: dp helpers
  65  *
  66  * These functions contain some common logic and helpers at various abstraction
  67  * levels to deal with Display Port sink devices and related things like DP aux
  68  * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
  69  * blocks, ...
  70  */
  71
  72 /* Helpers for DP link training */
  73 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
  74 {
  75         return link_status[r - DP_LANE0_1_STATUS];
  76 }
  77
  78 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
  79                              int lane)
  80 {
  81         int i = DP_LANE0_1_STATUS + (lane >> 1);
  82         int s = (lane & 1) * 4;
  83         u8 l = dp_link_status(link_status, i);
  84
  85         return (l >> s) & 0xf;
  86 }
  87
  88 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  89                           int lane_count)
  90 {
  91         u8 lane_align;
  92         u8 lane_status;
  93         int lane;
  94
  95         lane_align = dp_link_status(link_status,
  96                                     DP_LANE_ALIGN_STATUS_UPDATED);
  97         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  98                 return false;
  99         for (lane = 0; lane < lane_count; lane++) {
 100                 lane_status = dp_get_lane_status(link_status, lane);
 101                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
 102                         return false;
 103         }
 104         return true;
 105 }
 106 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
 107
 108 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
 109                               int lane_count)
 110 {
 111         int lane;
 112         u8 lane_status;
 113
 114         for (lane = 0; lane < lane_count; lane++) {
 115                 lane_status = dp_get_lane_status(link_status, lane);
 116                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 117                         return false;
 118         }
 119         return true;
 120 }
 121 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
 122
 123 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
 124                                      int lane)
 125 {
 126         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 127         int s = ((lane & 1) ?
 128                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 129                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 130         u8 l = dp_link_status(link_status, i);
 131
 132         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 133 }
 134 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
 135
 136 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
 137                                           int lane)
 138 {
 139         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 140         int s = ((lane & 1) ?
 141                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 142                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 143         u8 l = dp_link_status(link_status, i);
 144
 145         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 146 }
 147 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 148
 149 /* DP 2.0 128b/132b */
 150 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
 151                                    int lane)
 152 {
 153         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 154         int s = ((lane & 1) ?
 155                  DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
 156                  DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
 157         u8 l = dp_link_status(link_status, i);
 158
 159         return (l >> s) & 0xf;
 160 }
 161 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
 162
 163 /* DP 2.0 errata for 128b/132b */
 164 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
 165                                           int lane_count)
 166 {
 167         u8 lane_align, lane_status;
 168         int lane;
 169
 170         lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
 171         if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
 172                 return false;
 173
 174         for (lane = 0; lane < lane_count; lane++) {
 175                 lane_status = dp_get_lane_status(link_status, lane);
 176                 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
 177                         return false;
 178         }
 179         return true;
 180 }
 181 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
 182
 183 /* DP 2.0 errata for 128b/132b */
 184 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
 185                                         int lane_count)
 186 {
 187         u8 lane_status;
 188         int lane;
 189
 190         for (lane = 0; lane < lane_count; lane++) {
 191                 lane_status = dp_get_lane_status(link_status, lane);
 192                 if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
 193                         return false;
 194         }
 195         return true;
 196 }
 197 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
 198
 199 /* DP 2.0 errata for 128b/132b */
 200 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
 201 {
 202         u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
 203
 204         return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
 205 }
 206 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
 207
 208 /* DP 2.0 errata for 128b/132b */
 209 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
 210 {
 211         u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
 212
 213         return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
 214 }
 215 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
 216
 217 /* DP 2.0 errata for 128b/132b */
 218 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
 219 {
 220         u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
 221
 222         return status & DP_128B132B_LT_FAILED;
 223 }
 224 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
 225
 226 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
 227 {
 228         if (rd_interval > 4)
 229                 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
 230                             aux->name, rd_interval);
 231
 232         if (rd_interval == 0)
 233                 return 100;
 234
 235         return rd_interval * 4 * USEC_PER_MSEC;
 236 }
 237
 238 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
 239 {
 240         if (rd_interval > 4)
 241                 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
 242                             aux->name, rd_interval);
 243
 244         if (rd_interval == 0)
 245                 return 400;
 246
 247         return rd_interval * 4 * USEC_PER_MSEC;
 248 }
 249
 250 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
 251 {
 252         switch (rd_interval) {
 253         default:
 254                 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
 255                             aux->name, rd_interval);
 256                 fallthrough;
 257         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
 258                 return 400;
 259         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
 260                 return 4000;
 261         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
 262                 return 8000;
 263         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
 264                 return 12000;
 265         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
 266                 return 16000;
 267         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
 268                 return 32000;
 269         case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
 270                 return 64000;
 271         }
 272 }
 273
 274 /*
 275  * The link training delays are different for:
 276  *
 277  *  - Clock recovery vs. channel equalization
 278  *  - DPRX vs. LTTPR
 279  *  - 128b/132b vs. 8b/10b
 280  *  - DPCD rev 1.3 vs. later
 281  *
 282  * Get the correct delay in us, reading DPCD if necessary.
 283  */
 284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 285                         enum drm_dp_phy dp_phy, bool uhbr, bool cr)
 286 {
 287         int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
 288         unsigned int offset;
 289         u8 rd_interval, mask;
 290
 291         if (dp_phy == DP_PHY_DPRX) {
 292                 if (uhbr) {
 293                         if (cr)
 294                                 return 100;
 295
 296                         offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
 297                         mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
 298                         parse = __128b132b_channel_eq_delay_us;
 299                 } else {
 300                         if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 301                                 return 100;
 302
 303                         offset = DP_TRAINING_AUX_RD_INTERVAL;
 304                         mask = DP_TRAINING_AUX_RD_MASK;
 305                         if (cr)
 306                                 parse = __8b10b_clock_recovery_delay_us;
 307                         else
 308                                 parse = __8b10b_channel_eq_delay_us;
 309                 }
 310         } else {
 311                 if (uhbr) {
 312                         offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
 313                         mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
 314                         parse = __128b132b_channel_eq_delay_us;
 315                 } else {
 316                         if (cr)
 317                                 return 100;
 318
 319                         offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
 320                         mask = DP_TRAINING_AUX_RD_MASK;
 321                         parse = __8b10b_channel_eq_delay_us;
 322                 }
 323         }
 324
 325         if (offset < DP_RECEIVER_CAP_SIZE) {
 326                 rd_interval = dpcd[offset];
 327         } else {
 328                 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
 329                         drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
 330                                     aux->name);
 331                         /* arbitrary default delay */
 332                         return 400;
 333                 }
 334         }
 335
 336         return parse(aux, rd_interval & mask);
 337 }
 338
 339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 340                                      enum drm_dp_phy dp_phy, bool uhbr)
 341 {
 342         return __read_delay(aux, dpcd, dp_phy, uhbr, true);
 343 }
 344 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
 345
 346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 347                                  enum drm_dp_phy dp_phy, bool uhbr)
 348 {
 349         return __read_delay(aux, dpcd, dp_phy, uhbr, false);
 350 }
 351 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
 352
 353 /* Per DP 2.0 Errata */
 354 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
 355 {
 356         int unit;
 357         u8 val;
 358
 359         if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) {
 360                 drm_err(aux->drm_dev, "%s: failed rd interval read\n",
 361                         aux->name);
 362                 /* default to max */
 363                 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
 364         }
 365
 366         unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
 367         val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
 368
 369         return (val + 1) * unit * 1000;
 370 }
 371 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
 372
 373 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
 374                                             const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 375 {
 376         u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 377                 DP_TRAINING_AUX_RD_MASK;
 378         int delay_us;
 379
 380         if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 381                 delay_us = 100;
 382         else
 383                 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
 384
 385         usleep_range(delay_us, delay_us * 2);
 386 }
 387 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 388
 389 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
 390                                                  u8 rd_interval)
 391 {
 392         int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
 393
 394         usleep_range(delay_us, delay_us * 2);
 395 }
 396
 397 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
 398                                         const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 399 {
 400         __drm_dp_link_train_channel_eq_delay(aux,
 401                                              dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 402                                              DP_TRAINING_AUX_RD_MASK);
 403 }
 404 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 405
 406 void drm_dp_lttpr_link_train_clock_recovery_delay(void)
 407 {
 408         usleep_range(100, 200);
 409 }
 410 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
 411
 412 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
 413 {
 414         return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
 415 }
 416
 417 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
 418                                               const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
 419 {
 420         u8 interval = dp_lttpr_phy_cap(phy_cap,
 421                                        DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
 422                       DP_TRAINING_AUX_RD_MASK;
 423
 424         __drm_dp_link_train_channel_eq_delay(aux, interval);
 425 }
 426 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
 427
 428 u8 drm_dp_link_rate_to_bw_code(int link_rate)
 429 {
 430         switch (link_rate) {
 431         case 1000000:
 432                 return DP_LINK_BW_10;
 433         case 1350000:
 434                 return DP_LINK_BW_13_5;
 435         case 2000000:
 436                 return DP_LINK_BW_20;
 437         default:
 438                 /* Spec says link_bw = link_rate / 0.27Gbps */
 439                 return link_rate / 27000;
 440         }
 441 }
 442 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
 443
 444 int drm_dp_bw_code_to_link_rate(u8 link_bw)
 445 {
 446         switch (link_bw) {
 447         case DP_LINK_BW_10:
 448                 return 1000000;
 449         case DP_LINK_BW_13_5:
 450                 return 1350000;
 451         case DP_LINK_BW_20:
 452                 return 2000000;
 453         default:
 454                 /* Spec says link_rate = link_bw * 0.27Gbps */
 455                 return link_bw * 27000;
 456         }
 457 }
 458 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
 459
 460 #define AUX_RETRY_INTERVAL 500 /* us */
 461
 462 static inline void
 463 drm_dp_dump_access(const struct drm_dp_aux *aux,
 464                    u8 request, uint offset, void *buffer, int ret)
 465 {
 466         const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
 467
 468         if (ret > 0)
 469                 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
 470                            aux->name, offset, arrow, ret, min(ret, 20), buffer);
 471         else
 472                 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
 473                            aux->name, offset, arrow, ret);
 474 }
 475
 476 /**
 477  * DOC: dp helpers
 478  *
 479  * The DisplayPort AUX channel is an abstraction to allow generic, driver-
 480  * independent access to AUX functionality. Drivers can take advantage of
 481  * this by filling in the fields of the drm_dp_aux structure.
 482  *
 483  * Transactions are described using a hardware-independent drm_dp_aux_msg
 484  * structure, which is passed into a driver's .transfer() implementation.
 485  * Both native and I2C-over-AUX transactions are supported.
 486  */
 487
 488 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
 489                               unsigned int offset, void *buffer, size_t size)
 490 {
 491         struct drm_dp_aux_msg msg;
 492         unsigned int retry, native_reply;
 493         int err = 0, ret = 0;
 494
 495         memset(&msg, 0, sizeof(msg));
 496         msg.address = offset;
 497         msg.request = request;
 498         msg.buffer = buffer;
 499         msg.size = size;
 500
 501         mutex_lock(&aux->hw_mutex);
 502
 503         /*
 504          * The specification doesn't give any recommendation on how often to
 505          * retry native transactions. We used to retry 7 times like for
 506          * aux i2c transactions but real world devices this wasn't
 507          * sufficient, bump to 32 which makes Dell 4k monitors happier.
 508          */
 509         for (retry = 0; retry < 32; retry++) {
 510                 if (ret != 0 && ret != -ETIMEDOUT) {
 511                         usleep_range(AUX_RETRY_INTERVAL,
 512                                      AUX_RETRY_INTERVAL + 100);
 513                 }
 514
 515                 ret = aux->transfer(aux, &msg);
 516                 if (ret >= 0) {
 517                         native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
 518                         if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
 519                                 if (ret == size)
 520                                         goto unlock;
 521
 522                                 ret = -EPROTO;
 523                         } else
 524                                 ret = -EIO;
 525                 }
 526
 527                 /*
 528                  * We want the error we return to be the error we received on
 529                  * the first transaction, since we may get a different error the
 530                  * next time we retry
 531                  */
 532                 if (!err)
 533                         err = ret;
 534         }
 535
 536         drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
 537                     aux->name, err);
 538         ret = err;
 539
 540 unlock:
 541         mutex_unlock(&aux->hw_mutex);
 542         return ret;
 543 }
 544
 545 /**
 546  * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
 547  * @aux: DisplayPort AUX channel (SST)
 548  * @offset: address of the register to probe
 549  *
 550  * Probe the provided DPCD address by reading 1 byte from it. The function can
 551  * be used to trigger some side-effect the read access has, like waking up the
 552  * sink, without the need for the read-out value.
 553  *
 554  * Returns 0 if the read access suceeded, or a negative error code on failure.
 555  */
 556 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
 557 {
 558         u8 buffer;
 559         int ret;
 560
 561         ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1);
 562         WARN_ON(ret == 0);
 563
 564         drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret);
 565
 566         return ret < 0 ? ret : 0;
 567 }
 568 EXPORT_SYMBOL(drm_dp_dpcd_probe);
 569
 570 /**
 571  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
 572  * @aux: DisplayPort AUX channel (SST or MST)
 573  * @offset: address of the (first) register to read
 574  * @buffer: buffer to store the register values
 575  * @size: number of bytes in @buffer
 576  *
 577  * Returns the number of bytes transferred on success, or a negative error
 578  * code on failure. -EIO is returned if the request was NAKed by the sink or
 579  * if the retry count was exceeded. If not all bytes were transferred, this
 580  * function returns -EPROTO. Errors from the underlying AUX channel transfer
 581  * function, with the exception of -EBUSY (which causes the transaction to
 582  * be retried), are propagated to the caller.
 583  */
 584 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
 585                          void *buffer, size_t size)
 586 {
 587         int ret;
 588
 589         /*
 590          * HP ZR24w corrupts the first DPCD access after entering power save
 591          * mode. Eg. on a read, the entire buffer will be filled with the same
 592          * byte. Do a throw away read to avoid corrupting anything we care
 593          * about. Afterwards things will work correctly until the monitor
 594          * gets woken up and subsequently re-enters power save mode.
 595          *
 596          * The user pressing any button on the monitor is enough to wake it
 597          * up, so there is no particularly good place to do the workaround.
 598          * We just have to do it before any DPCD access and hope that the
 599          * monitor doesn't power down exactly after the throw away read.
 600          */
 601         if (!aux->is_remote) {
 602                 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV);
 603                 if (ret < 0)
 604                         return ret;
 605         }
 606
 607         if (aux->is_remote)
 608                 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
 609         else
 610                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
 611                                          buffer, size);
 612
 613         drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
 614         return ret;
 615 }
 616 EXPORT_SYMBOL(drm_dp_dpcd_read);
 617
 618 /**
 619  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
 620  * @aux: DisplayPort AUX channel (SST or MST)
 621  * @offset: address of the (first) register to write
 622  * @buffer: buffer containing the values to write
 623  * @size: number of bytes in @buffer
 624  *
 625  * Returns the number of bytes transferred on success, or a negative error
 626  * code on failure. -EIO is returned if the request was NAKed by the sink or
 627  * if the retry count was exceeded. If not all bytes were transferred, this
 628  * function returns -EPROTO. Errors from the underlying AUX channel transfer
 629  * function, with the exception of -EBUSY (which causes the transaction to
 630  * be retried), are propagated to the caller.
 631  */
 632 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
 633                           void *buffer, size_t size)
 634 {
 635         int ret;
 636
 637         if (aux->is_remote)
 638                 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
 639         else
 640                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
 641                                          buffer, size);
 642
 643         drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
 644         return ret;
 645 }
 646 EXPORT_SYMBOL(drm_dp_dpcd_write);
 647
 648 /**
 649  * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
 650  * @aux: DisplayPort AUX channel
 651  * @status: buffer to store the link status in (must be at least 6 bytes)
 652  *
 653  * Returns the number of bytes transferred on success or a negative error
 654  * code on failure.
 655  */
 656 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 657                                  u8 status[DP_LINK_STATUS_SIZE])
 658 {
 659         return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
 660                                 DP_LINK_STATUS_SIZE);
 661 }
 662 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
 663
 664 /**
 665  * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
 666  * @aux: DisplayPort AUX channel
 667  * @dp_phy: the DP PHY to get the link status for
 668  * @link_status: buffer to return the status in
 669  *
 670  * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
 671  * layout of the returned @link_status matches the DPCD register layout of the
 672  * DPRX PHY link status.
 673  *
 674  * Returns 0 if the information was read successfully or a negative error code
 675  * on failure.
 676  */
 677 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
 678                                      enum drm_dp_phy dp_phy,
 679                                      u8 link_status[DP_LINK_STATUS_SIZE])
 680 {
 681         int ret;
 682
 683         if (dp_phy == DP_PHY_DPRX) {
 684                 ret = drm_dp_dpcd_read(aux,
 685                                        DP_LANE0_1_STATUS,
 686                                        link_status,
 687                                        DP_LINK_STATUS_SIZE);
 688
 689                 if (ret < 0)
 690                         return ret;
 691
 692                 WARN_ON(ret != DP_LINK_STATUS_SIZE);
 693
 694                 return 0;
 695         }
 696
 697         ret = drm_dp_dpcd_read(aux,
 698                                DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
 699                                link_status,
 700                                DP_LINK_STATUS_SIZE - 1);
 701
 702         if (ret < 0)
 703                 return ret;
 704
 705         WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
 706
 707         /* Convert the LTTPR to the sink PHY link status layout */
 708         memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
 709                 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
 710                 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
 711         link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
 712
 713         return 0;
 714 }
 715 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
 716
 717 static bool is_edid_digital_input_dp(const struct edid *edid)
 718 {
 719         return edid && edid->revision >= 4 &&
 720                 edid->input & DRM_EDID_INPUT_DIGITAL &&
 721                 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
 722 }
 723
 724 /**
 725  * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
 726  * @dpcd: DisplayPort configuration data
 727  * @port_cap: port capabilities
 728  * @type: port type to be checked. Can be:
 729  *        %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
 730  *        %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
 731  *        %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
 732  *
 733  * Caveat: Only works with DPCD 1.1+ port caps.
 734  *
 735  * Returns: whether the downstream facing port matches the type.
 736  */
 737 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 738                                const u8 port_cap[4], u8 type)
 739 {
 740         return drm_dp_is_branch(dpcd) &&
 741                 dpcd[DP_DPCD_REV] >= 0x11 &&
 742                 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
 743 }
 744 EXPORT_SYMBOL(drm_dp_downstream_is_type);
 745
 746 /**
 747  * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
 748  * @dpcd: DisplayPort configuration data
 749  * @port_cap: port capabilities
 750  * @edid: EDID
 751  *
 752  * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
 753  */
 754 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 755                                const u8 port_cap[4],
 756                                const struct edid *edid)
 757 {
 758         if (dpcd[DP_DPCD_REV] < 0x11) {
 759                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 760                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 761                         return true;
 762                 default:
 763                         return false;
 764                 }
 765         }
 766
 767         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 768         case DP_DS_PORT_TYPE_DP_DUALMODE:
 769                 if (is_edid_digital_input_dp(edid))
 770                         return false;
 771                 fallthrough;
 772         case DP_DS_PORT_TYPE_DVI:
 773         case DP_DS_PORT_TYPE_HDMI:
 774                 return true;
 775         default:
 776                 return false;
 777         }
 778 }
 779 EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
 780
 781 /**
 782  * drm_dp_send_real_edid_checksum() - send back real edid checksum value
 783  * @aux: DisplayPort AUX channel
 784  * @real_edid_checksum: real edid checksum for the last block
 785  *
 786  * Returns:
 787  * True on success
 788  */
 789 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
 790                                     u8 real_edid_checksum)
 791 {
 792         u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
 793
 794         if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
 795                              &auto_test_req, 1) < 1) {
 796                 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
 797                         aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
 798                 return false;
 799         }
 800         auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
 801
 802         if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
 803                 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
 804                         aux->name, DP_TEST_REQUEST);
 805                 return false;
 806         }
 807         link_edid_read &= DP_TEST_LINK_EDID_READ;
 808
 809         if (!auto_test_req || !link_edid_read) {
 810                 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
 811                             aux->name);
 812                 return false;
 813         }
 814
 815         if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
 816                               &auto_test_req, 1) < 1) {
 817                 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
 818                         aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
 819                 return false;
 820         }
 821
 822         /* send back checksum for the last edid extension block data */
 823         if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
 824                               &real_edid_checksum, 1) < 1) {
 825                 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
 826                         aux->name, DP_TEST_EDID_CHECKSUM);
 827                 return false;
 828         }
 829
 830         test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
 831         if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
 832                 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
 833                         aux->name, DP_TEST_RESPONSE);
 834                 return false;
 835         }
 836
 837         return true;
 838 }
 839 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
 840
 841 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 842 {
 843         u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
 844
 845         if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
 846                 port_count = 4;
 847
 848         return port_count;
 849 }
 850
 851 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
 852                                           u8 dpcd[DP_RECEIVER_CAP_SIZE])
 853 {
 854         u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
 855         int ret;
 856
 857         /*
 858          * Prior to DP1.3 the bit represented by
 859          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
 860          * If it is set DP_DPCD_REV at 0000h could be at a value less than
 861          * the true capability of the panel. The only way to check is to
 862          * then compare 0000h and 2200h.
 863          */
 864         if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 865               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
 866                 return 0;
 867
 868         ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
 869                                sizeof(dpcd_ext));
 870         if (ret < 0)
 871                 return ret;
 872         if (ret != sizeof(dpcd_ext))
 873                 return -EIO;
 874
 875         if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
 876                 drm_dbg_kms(aux->drm_dev,
 877                             "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
 878                             aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
 879                 return 0;
 880         }
 881
 882         if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
 883                 return 0;
 884
 885         drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
 886
 887         memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
 888
 889         return 0;
 890 }
 891
 892 /**
 893  * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
 894  * available
 895  * @aux: DisplayPort AUX channel
 896  * @dpcd: Buffer to store the resulting DPCD in
 897  *
 898  * Attempts to read the base DPCD caps for @aux. Additionally, this function
 899  * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
 900  * present.
 901  *
 902  * Returns: %0 if the DPCD was read successfully, negative error code
 903  * otherwise.
 904  */
 905 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
 906                           u8 dpcd[DP_RECEIVER_CAP_SIZE])
 907 {
 908         int ret;
 909
 910         ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
 911         if (ret < 0)
 912                 return ret;
 913         if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
 914                 return -EIO;
 915
 916         ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
 917         if (ret < 0)
 918                 return ret;
 919
 920         drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
 921
 922         return ret;
 923 }
 924 EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
 925
 926 /**
 927  * drm_dp_read_downstream_info() - read DPCD downstream port info if available
 928  * @aux: DisplayPort AUX channel
 929  * @dpcd: A cached copy of the port's DPCD
 930  * @downstream_ports: buffer to store the downstream port info in
 931  *
 932  * See also:
 933  * drm_dp_downstream_max_clock()
 934  * drm_dp_downstream_max_bpc()
 935  *
 936  * Returns: 0 if either the downstream port info was read successfully or
 937  * there was no downstream info to read, or a negative error code otherwise.
 938  */
 939 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
 940                                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 941                                 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
 942 {
 943         int ret;
 944         u8 len;
 945
 946         memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
 947
 948         /* No downstream info to read */
 949         if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
 950                 return 0;
 951
 952         /* Some branches advertise having 0 downstream ports, despite also advertising they have a
 953          * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
 954          * some branches do it we need to handle it regardless.
 955          */
 956         len = drm_dp_downstream_port_count(dpcd);
 957         if (!len)
 958                 return 0;
 959
 960         if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
 961                 len *= 4;
 962
 963         ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
 964         if (ret < 0)
 965                 return ret;
 966         if (ret != len)
 967                 return -EIO;
 968
 969         drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
 970
 971         return 0;
 972 }
 973 EXPORT_SYMBOL(drm_dp_read_downstream_info);
 974
 975 /**
 976  * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
 977  * @dpcd: DisplayPort configuration data
 978  * @port_cap: port capabilities
 979  *
 980  * Returns: Downstream facing port max dot clock in kHz on success,
 981  * or 0 if max clock not defined
 982  */
 983 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 984                                    const u8 port_cap[4])
 985 {
 986         if (!drm_dp_is_branch(dpcd))
 987                 return 0;
 988
 989         if (dpcd[DP_DPCD_REV] < 0x11)
 990                 return 0;
 991
 992         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 993         case DP_DS_PORT_TYPE_VGA:
 994                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 995                         return 0;
 996                 return port_cap[1] * 8000;
 997         default:
 998                 return 0;
 999         }
1000 }
1001 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1002
1003 /**
1004  * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1005  * @dpcd: DisplayPort configuration data
1006  * @port_cap: port capabilities
1007  * @edid: EDID
1008  *
1009  * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1010  * or 0 if max TMDS clock not defined
1011  */
1012 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1013                                      const u8 port_cap[4],
1014                                      const struct edid *edid)
1015 {
1016         if (!drm_dp_is_branch(dpcd))
1017                 return 0;
1018
1019         if (dpcd[DP_DPCD_REV] < 0x11) {
1020                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1021                 case DP_DWN_STRM_PORT_TYPE_TMDS:
1022                         return 165000;
1023                 default:
1024                         return 0;
1025                 }
1026         }
1027
1028         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1029         case DP_DS_PORT_TYPE_DP_DUALMODE:
1030                 if (is_edid_digital_input_dp(edid))
1031                         return 0;
1032                 /*
1033                  * It's left up to the driver to check the
1034                  * DP dual mode adapter's max TMDS clock.
1035                  *
1036                  * Unfortunately it looks like branch devices
1037                  * may not fordward that the DP dual mode i2c
1038                  * access so we just usually get i2c nak :(
1039                  */
1040                 fallthrough;
1041         case DP_DS_PORT_TYPE_HDMI:
1042                  /*
1043                   * We should perhaps assume 165 MHz when detailed cap
1044                   * info is not available. But looks like many typical
1045                   * branch devices fall into that category and so we'd
1046                   * probably end up with users complaining that they can't
1047                   * get high resolution modes with their favorite dongle.
1048                   *
1049                   * So let's limit to 300 MHz instead since DPCD 1.4
1050                   * HDMI 2.0 DFPs are required to have the detailed cap
1051                   * info. So it's more likely we're dealing with a HDMI 1.4
1052                   * compatible* device here.
1053                   */
1054                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1055                         return 300000;
1056                 return port_cap[1] * 2500;
1057         case DP_DS_PORT_TYPE_DVI:
1058                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1059                         return 165000;
1060                 /* FIXME what to do about DVI dual link? */
1061                 return port_cap[1] * 2500;
1062         default:
1063                 return 0;
1064         }
1065 }
1066 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1067
1068 /**
1069  * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1070  * @dpcd: DisplayPort configuration data
1071  * @port_cap: port capabilities
1072  * @edid: EDID
1073  *
1074  * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1075  * or 0 if max TMDS clock not defined
1076  */
1077 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1078                                      const u8 port_cap[4],
1079                                      const struct edid *edid)
1080 {
1081         if (!drm_dp_is_branch(dpcd))
1082                 return 0;
1083
1084         if (dpcd[DP_DPCD_REV] < 0x11) {
1085                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1086                 case DP_DWN_STRM_PORT_TYPE_TMDS:
1087                         return 25000;
1088                 default:
1089                         return 0;
1090                 }
1091         }
1092
1093         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1094         case DP_DS_PORT_TYPE_DP_DUALMODE:
1095                 if (is_edid_digital_input_dp(edid))
1096                         return 0;
1097                 fallthrough;
1098         case DP_DS_PORT_TYPE_DVI:
1099         case DP_DS_PORT_TYPE_HDMI:
1100                 /*
1101                  * Unclear whether the protocol converter could
1102                  * utilize pixel replication. Assume it won't.
1103                  */
1104                 return 25000;
1105         default:
1106                 return 0;
1107         }
1108 }
1109 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1110
1111 /**
1112  * drm_dp_downstream_max_bpc() - extract downstream facing port max
1113  *                               bits per component
1114  * @dpcd: DisplayPort configuration data
1115  * @port_cap: downstream facing port capabilities
1116  * @edid: EDID
1117  *
1118  * Returns: Max bpc on success or 0 if max bpc not defined
1119  */
1120 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1121                               const u8 port_cap[4],
1122                               const struct edid *edid)
1123 {
1124         if (!drm_dp_is_branch(dpcd))
1125                 return 0;
1126
1127         if (dpcd[DP_DPCD_REV] < 0x11) {
1128                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1129                 case DP_DWN_STRM_PORT_TYPE_DP:
1130                         return 0;
1131                 default:
1132                         return 8;
1133                 }
1134         }
1135
1136         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1137         case DP_DS_PORT_TYPE_DP:
1138                 return 0;
1139         case DP_DS_PORT_TYPE_DP_DUALMODE:
1140                 if (is_edid_digital_input_dp(edid))
1141                         return 0;
1142                 fallthrough;
1143         case DP_DS_PORT_TYPE_HDMI:
1144         case DP_DS_PORT_TYPE_DVI:
1145         case DP_DS_PORT_TYPE_VGA:
1146                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1147                         return 8;
1148
1149                 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1150                 case DP_DS_8BPC:
1151                         return 8;
1152                 case DP_DS_10BPC:
1153                         return 10;
1154                 case DP_DS_12BPC:
1155                         return 12;
1156                 case DP_DS_16BPC:
1157                         return 16;
1158                 default:
1159                         return 8;
1160                 }
1161                 break;
1162         default:
1163                 return 8;
1164         }
1165 }
1166 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1167
1168 /**
1169  * drm_dp_downstream_420_passthrough() - determine downstream facing port
1170  *                                       YCbCr 4:2:0 pass-through capability
1171  * @dpcd: DisplayPort configuration data
1172  * @port_cap: downstream facing port capabilities
1173  *
1174  * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1175  */
1176 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1177                                        const u8 port_cap[4])
1178 {
1179         if (!drm_dp_is_branch(dpcd))
1180                 return false;
1181
1182         if (dpcd[DP_DPCD_REV] < 0x13)
1183                 return false;
1184
1185         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1186         case DP_DS_PORT_TYPE_DP:
1187                 return true;
1188         case DP_DS_PORT_TYPE_HDMI:
1189                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1190                         return false;
1191
1192                 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1193         default:
1194                 return false;
1195         }
1196 }
1197 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1198
1199 /**
1200  * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1201  *                                             YCbCr 4:4:4->4:2:0 conversion capability
1202  * @dpcd: DisplayPort configuration data
1203  * @port_cap: downstream facing port capabilities
1204  *
1205  * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1206  */
1207 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1208                                              const u8 port_cap[4])
1209 {
1210         if (!drm_dp_is_branch(dpcd))
1211                 return false;
1212
1213         if (dpcd[DP_DPCD_REV] < 0x13)
1214                 return false;
1215
1216         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1217         case DP_DS_PORT_TYPE_HDMI:
1218                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1219                         return false;
1220
1221                 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1222         default:
1223                 return false;
1224         }
1225 }
1226 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1227
1228 /**
1229  * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1230  *                                               RGB->YCbCr conversion capability
1231  * @dpcd: DisplayPort configuration data
1232  * @port_cap: downstream facing port capabilities
1233  * @color_spc: Colorspace for which conversion cap is sought
1234  *
1235  * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1236  * colorspace.
1237  */
1238 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1239                                                const u8 port_cap[4],
1240                                                u8 color_spc)
1241 {
1242         if (!drm_dp_is_branch(dpcd))
1243                 return false;
1244
1245         if (dpcd[DP_DPCD_REV] < 0x13)
1246                 return false;
1247
1248         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1249         case DP_DS_PORT_TYPE_HDMI:
1250                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1251                         return false;
1252
1253                 return port_cap[3] & color_spc;
1254         default:
1255                 return false;
1256         }
1257 }
1258 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1259
1260 /**
1261  * drm_dp_downstream_mode() - return a mode for downstream facing port
1262  * @dev: DRM device
1263  * @dpcd: DisplayPort configuration data
1264  * @port_cap: port capabilities
1265  *
1266  * Provides a suitable mode for downstream facing ports without EDID.
1267  *
1268  * Returns: A new drm_display_mode on success or NULL on failure
1269  */
1270 struct drm_display_mode *
1271 drm_dp_downstream_mode(struct drm_device *dev,
1272                        const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1273                        const u8 port_cap[4])
1274
1275 {
1276         u8 vic;
1277
1278         if (!drm_dp_is_branch(dpcd))
1279                 return NULL;
1280
1281         if (dpcd[DP_DPCD_REV] < 0x11)
1282                 return NULL;
1283
1284         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1285         case DP_DS_PORT_TYPE_NON_EDID:
1286                 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1287                 case DP_DS_NON_EDID_720x480i_60:
1288                         vic = 6;
1289                         break;
1290                 case DP_DS_NON_EDID_720x480i_50:
1291                         vic = 21;
1292                         break;
1293                 case DP_DS_NON_EDID_1920x1080i_60:
1294                         vic = 5;
1295                         break;
1296                 case DP_DS_NON_EDID_1920x1080i_50:
1297                         vic = 20;
1298                         break;
1299                 case DP_DS_NON_EDID_1280x720_60:
1300                         vic = 4;
1301                         break;
1302                 case DP_DS_NON_EDID_1280x720_50:
1303                         vic = 19;
1304                         break;
1305                 default:
1306                         return NULL;
1307                 }
1308                 return drm_display_mode_from_cea_vic(dev, vic);
1309         default:
1310                 return NULL;
1311         }
1312 }
1313 EXPORT_SYMBOL(drm_dp_downstream_mode);
1314
1315 /**
1316  * drm_dp_downstream_id() - identify branch device
1317  * @aux: DisplayPort AUX channel
1318  * @id: DisplayPort branch device id
1319  *
1320  * Returns branch device id on success or NULL on failure
1321  */
1322 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1323 {
1324         return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1325 }
1326 EXPORT_SYMBOL(drm_dp_downstream_id);
1327
1328 /**
1329  * drm_dp_downstream_debug() - debug DP branch devices
1330  * @m: pointer for debugfs file
1331  * @dpcd: DisplayPort configuration data
1332  * @port_cap: port capabilities
1333  * @edid: EDID
1334  * @aux: DisplayPort AUX channel
1335  *
1336  */
1337 void drm_dp_downstream_debug(struct seq_file *m,
1338                              const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1339                              const u8 port_cap[4],
1340                              const struct edid *edid,
1341                              struct drm_dp_aux *aux)
1342 {
1343         bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1344                                  DP_DETAILED_CAP_INFO_AVAILABLE;
1345         int clk;
1346         int bpc;
1347         char id[7];
1348         int len;
1349         uint8_t rev[2];
1350         int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1351         bool branch_device = drm_dp_is_branch(dpcd);
1352
1353         seq_printf(m, "\tDP branch device present: %s\n",
1354                    str_yes_no(branch_device));
1355
1356         if (!branch_device)
1357                 return;
1358
1359         switch (type) {
1360         case DP_DS_PORT_TYPE_DP:
1361                 seq_puts(m, "\t\tType: DisplayPort\n");
1362                 break;
1363         case DP_DS_PORT_TYPE_VGA:
1364                 seq_puts(m, "\t\tType: VGA\n");
1365                 break;
1366         case DP_DS_PORT_TYPE_DVI:
1367                 seq_puts(m, "\t\tType: DVI\n");
1368                 break;
1369         case DP_DS_PORT_TYPE_HDMI:
1370                 seq_puts(m, "\t\tType: HDMI\n");
1371                 break;
1372         case DP_DS_PORT_TYPE_NON_EDID:
1373                 seq_puts(m, "\t\tType: others without EDID support\n");
1374                 break;
1375         case DP_DS_PORT_TYPE_DP_DUALMODE:
1376                 seq_puts(m, "\t\tType: DP++\n");
1377                 break;
1378         case DP_DS_PORT_TYPE_WIRELESS:
1379                 seq_puts(m, "\t\tType: Wireless\n");
1380                 break;
1381         default:
1382                 seq_puts(m, "\t\tType: N/A\n");
1383         }
1384
1385         memset(id, 0, sizeof(id));
1386         drm_dp_downstream_id(aux, id);
1387         seq_printf(m, "\t\tID: %s\n", id);
1388
1389         len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1390         if (len > 0)
1391                 seq_printf(m, "\t\tHW: %d.%d\n",
1392                            (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1393
1394         len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1395         if (len > 0)
1396                 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1397
1398         if (detailed_cap_info) {
1399                 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1400                 if (clk > 0)
1401                         seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1402
1403                 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
1404                 if (clk > 0)
1405                         seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1406
1407                 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
1408                 if (clk > 0)
1409                         seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1410
1411                 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
1412
1413                 if (bpc > 0)
1414                         seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1415         }
1416 }
1417 EXPORT_SYMBOL(drm_dp_downstream_debug);
1418
1419 /**
1420  * drm_dp_subconnector_type() - get DP branch device type
1421  * @dpcd: DisplayPort configuration data
1422  * @port_cap: port capabilities
1423  */
1424 enum drm_mode_subconnector
1425 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1426                          const u8 port_cap[4])
1427 {
1428         int type;
1429         if (!drm_dp_is_branch(dpcd))
1430                 return DRM_MODE_SUBCONNECTOR_Native;
1431         /* DP 1.0 approach */
1432         if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1433                 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1434                        DP_DWN_STRM_PORT_TYPE_MASK;
1435
1436                 switch (type) {
1437                 case DP_DWN_STRM_PORT_TYPE_TMDS:
1438                         /* Can be HDMI or DVI-D, DVI-D is a safer option */
1439                         return DRM_MODE_SUBCONNECTOR_DVID;
1440                 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1441                         /* Can be VGA or DVI-A, VGA is more popular */
1442                         return DRM_MODE_SUBCONNECTOR_VGA;
1443                 case DP_DWN_STRM_PORT_TYPE_DP:
1444                         return DRM_MODE_SUBCONNECTOR_DisplayPort;
1445                 case DP_DWN_STRM_PORT_TYPE_OTHER:
1446                 default:
1447                         return DRM_MODE_SUBCONNECTOR_Unknown;
1448                 }
1449         }
1450         type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1451
1452         switch (type) {
1453         case DP_DS_PORT_TYPE_DP:
1454         case DP_DS_PORT_TYPE_DP_DUALMODE:
1455                 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1456         case DP_DS_PORT_TYPE_VGA:
1457                 return DRM_MODE_SUBCONNECTOR_VGA;
1458         case DP_DS_PORT_TYPE_DVI:
1459                 return DRM_MODE_SUBCONNECTOR_DVID;
1460         case DP_DS_PORT_TYPE_HDMI:
1461                 return DRM_MODE_SUBCONNECTOR_HDMIA;
1462         case DP_DS_PORT_TYPE_WIRELESS:
1463                 return DRM_MODE_SUBCONNECTOR_Wireless;
1464         case DP_DS_PORT_TYPE_NON_EDID:
1465         default:
1466                 return DRM_MODE_SUBCONNECTOR_Unknown;
1467         }
1468 }
1469 EXPORT_SYMBOL(drm_dp_subconnector_type);
1470
1471 /**
1472  * drm_dp_set_subconnector_property - set subconnector for DP connector
1473  * @connector: connector to set property on
1474  * @status: connector status
1475  * @dpcd: DisplayPort configuration data
1476  * @port_cap: port capabilities
1477  *
1478  * Called by a driver on every detect event.
1479  */
1480 void drm_dp_set_subconnector_property(struct drm_connector *connector,
1481                                       enum drm_connector_status status,
1482                                       const u8 *dpcd,
1483                                       const u8 port_cap[4])
1484 {
1485         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1486
1487         if (status == connector_status_connected)
1488                 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1489         drm_object_property_set_value(&connector->base,
1490                         connector->dev->mode_config.dp_subconnector_property,
1491                         subconnector);
1492 }
1493 EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1494
1495 /**
1496  * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1497  * count
1498  * @connector: The DRM connector to check
1499  * @dpcd: A cached copy of the connector's DPCD RX capabilities
1500  * @desc: A cached copy of the connector's DP descriptor
1501  *
1502  * See also: drm_dp_read_sink_count()
1503  *
1504  * Returns: %True if the (e)DP connector has a valid sink count that should
1505  * be probed, %false otherwise.
1506  */
1507 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1508                                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1509                                 const struct drm_dp_desc *desc)
1510 {
1511         /* Some eDP panels don't set a valid value for the sink count */
1512         return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1513                 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1514                 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1515                 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1516 }
1517 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1518
1519 /**
1520  * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1521  * @aux: The DP AUX channel to use
1522  *
1523  * See also: drm_dp_read_sink_count_cap()
1524  *
1525  * Returns: The current sink count reported by @aux, or a negative error code
1526  * otherwise.
1527  */
1528 int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1529 {
1530         u8 count;
1531         int ret;
1532
1533         ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1534         if (ret < 0)
1535                 return ret;
1536         if (ret != 1)
1537                 return -EIO;
1538
1539         return DP_GET_SINK_COUNT(count);
1540 }
1541 EXPORT_SYMBOL(drm_dp_read_sink_count);
1542
1543 /*
1544  * I2C-over-AUX implementation
1545  */
1546
1547 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1548 {
1549         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1550                I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1551                I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1552                I2C_FUNC_10BIT_ADDR;
1553 }
1554
1555 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1556 {
1557         /*
1558          * In case of i2c defer or short i2c ack reply to a write,
1559          * we need to switch to WRITE_STATUS_UPDATE to drain the
1560          * rest of the message
1561          */
1562         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1563                 msg->request &= DP_AUX_I2C_MOT;
1564                 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1565         }
1566 }
1567
1568 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1569 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1570 #define AUX_STOP_LEN 4
1571 #define AUX_CMD_LEN 4
1572 #define AUX_ADDRESS_LEN 20
1573 #define AUX_REPLY_PAD_LEN 4
1574 #define AUX_LENGTH_LEN 8
1575
1576 /*
1577  * Calculate the duration of the AUX request/reply in usec. Gives the
1578  * "best" case estimate, ie. successful while as short as possible.
1579  */
1580 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1581 {
1582         int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1583                 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1584
1585         if ((msg->request & DP_AUX_I2C_READ) == 0)
1586                 len += msg->size * 8;
1587
1588         return len;
1589 }
1590
1591 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1592 {
1593         int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1594                 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1595
1596         /*
1597          * For read we expect what was asked. For writes there will
1598          * be 0 or 1 data bytes. Assume 0 for the "best" case.
1599          */
1600         if (msg->request & DP_AUX_I2C_READ)
1601                 len += msg->size * 8;
1602
1603         return len;
1604 }
1605
1606 #define I2C_START_LEN 1
1607 #define I2C_STOP_LEN 1
1608 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1609 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1610
1611 /*
1612  * Calculate the length of the i2c transfer in usec, assuming
1613  * the i2c bus speed is as specified. Gives the the "worst"
1614  * case estimate, ie. successful while as long as possible.
1615  * Doesn't account the "MOT" bit, and instead assumes each
1616  * message includes a START, ADDRESS and STOP. Neither does it
1617  * account for additional random variables such as clock stretching.
1618  */
1619 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1620                                    int i2c_speed_khz)
1621 {
1622         /* AUX bitrate is 1MHz, i2c bitrate as specified */
1623         return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1624                              msg->size * I2C_DATA_LEN +
1625                              I2C_STOP_LEN) * 1000, i2c_speed_khz);
1626 }
1627
1628 /*
1629  * Determine how many retries should be attempted to successfully transfer
1630  * the specified message, based on the estimated durations of the
1631  * i2c and AUX transfers.
1632  */
1633 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1634                               int i2c_speed_khz)
1635 {
1636         int aux_time_us = drm_dp_aux_req_duration(msg) +
1637                 drm_dp_aux_reply_duration(msg);
1638         int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1639
1640         return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1641 }
1642
1643 /*
1644  * FIXME currently assumes 10 kHz as some real world devices seem
1645  * to require it. We should query/set the speed via DPCD if supported.
1646  */
1647 static int dp_aux_i2c_speed_khz __read_mostly = 10;
1648 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1649 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1650                  "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1651
1652 /*
1653  * Transfer a single I2C-over-AUX message and handle various error conditions,
1654  * retrying the transaction as appropriate.  It is assumed that the
1655  * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1656  * reply field.
1657  *
1658  * Returns bytes transferred on success, or a negative error code on failure.
1659  */
1660 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1661 {
1662         unsigned int retry, defer_i2c;
1663         int ret;
1664         /*
1665          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1666          * is required to retry at least seven times upon receiving AUX_DEFER
1667          * before giving up the AUX transaction.
1668          *
1669          * We also try to account for the i2c bus speed.
1670          */
1671         int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1672
1673         for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1674                 ret = aux->transfer(aux, msg);
1675                 if (ret < 0) {
1676                         if (ret == -EBUSY)
1677                                 continue;
1678
1679                         /*
1680                          * While timeouts can be errors, they're usually normal
1681                          * behavior (for instance, when a driver tries to
1682                          * communicate with a non-existent DisplayPort device).
1683                          * Avoid spamming the kernel log with timeout errors.
1684                          */
1685                         if (ret == -ETIMEDOUT)
1686                                 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1687                                                         aux->name);
1688                         else
1689                                 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1690                                             aux->name, ret);
1691                         return ret;
1692                 }
1693
1694
1695                 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1696                 case DP_AUX_NATIVE_REPLY_ACK:
1697                         /*
1698                          * For I2C-over-AUX transactions this isn't enough, we
1699                          * need to check for the I2C ACK reply.
1700                          */
1701                         break;
1702
1703                 case DP_AUX_NATIVE_REPLY_NACK:
1704                         drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1705                                     aux->name, ret, msg->size);
1706                         return -EREMOTEIO;
1707
1708                 case DP_AUX_NATIVE_REPLY_DEFER:
1709                         drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1710                         /*
1711                          * We could check for I2C bit rate capabilities and if
1712                          * available adjust this interval. We could also be
1713                          * more careful with DP-to-legacy adapters where a
1714                          * long legacy cable may force very low I2C bit rates.
1715                          *
1716                          * For now just defer for long enough to hopefully be
1717                          * safe for all use-cases.
1718                          */
1719                         usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1720                         continue;
1721
1722                 default:
1723                         drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1724                                 aux->name, msg->reply);
1725                         return -EREMOTEIO;
1726                 }
1727
1728                 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1729                 case DP_AUX_I2C_REPLY_ACK:
1730                         /*
1731                          * Both native ACK and I2C ACK replies received. We
1732                          * can assume the transfer was successful.
1733                          */
1734                         if (ret != msg->size)
1735                                 drm_dp_i2c_msg_write_status_update(msg);
1736                         return ret;
1737
1738                 case DP_AUX_I2C_REPLY_NACK:
1739                         drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1740                                     aux->name, ret, msg->size);
1741                         aux->i2c_nack_count++;
1742                         return -EREMOTEIO;
1743
1744                 case DP_AUX_I2C_REPLY_DEFER:
1745                         drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1746                         /* DP Compliance Test 4.2.2.5 Requirement:
1747                          * Must have at least 7 retries for I2C defers on the
1748                          * transaction to pass this test
1749                          */
1750                         aux->i2c_defer_count++;
1751                         if (defer_i2c < 7)
1752                                 defer_i2c++;
1753                         usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1754                         drm_dp_i2c_msg_write_status_update(msg);
1755
1756                         continue;
1757
1758                 default:
1759                         drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1760                                 aux->name, msg->reply);
1761                         return -EREMOTEIO;
1762                 }
1763         }
1764
1765         drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1766         return -EREMOTEIO;
1767 }
1768
1769 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1770                                        const struct i2c_msg *i2c_msg)
1771 {
1772         msg->request = (i2c_msg->flags & I2C_M_RD) ?
1773                 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1774         if (!(i2c_msg->flags & I2C_M_STOP))
1775                 msg->request |= DP_AUX_I2C_MOT;
1776 }
1777
1778 /*
1779  * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1780  *
1781  * Returns an error code on failure, or a recommended transfer size on success.
1782  */
1783 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1784 {
1785         int err, ret = orig_msg->size;
1786         struct drm_dp_aux_msg msg = *orig_msg;
1787
1788         while (msg.size > 0) {
1789                 err = drm_dp_i2c_do_msg(aux, &msg);
1790                 if (err <= 0)
1791                         return err == 0 ? -EPROTO : err;
1792
1793                 if (err < msg.size && err < ret) {
1794                         drm_dbg_kms(aux->drm_dev,
1795                                     "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1796                                     aux->name, msg.size, err);
1797                         ret = err;
1798                 }
1799
1800                 msg.size -= err;
1801                 msg.buffer += err;
1802         }
1803
1804         return ret;
1805 }
1806
1807 /*
1808  * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1809  * packets to be as large as possible. If not, the I2C transactions never
1810  * succeed. Hence the default is maximum.
1811  */
1812 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1813 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1814 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1815                  "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1816
1817 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1818                            int num)
1819 {
1820         struct drm_dp_aux *aux = adapter->algo_data;
1821         unsigned int i, j;
1822         unsigned transfer_size;
1823         struct drm_dp_aux_msg msg;
1824         int err = 0;
1825
1826         dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1827
1828         memset(&msg, 0, sizeof(msg));
1829
1830         for (i = 0; i < num; i++) {
1831                 msg.address = msgs[i].addr;
1832                 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1833                 /* Send a bare address packet to start the transaction.
1834                  * Zero sized messages specify an address only (bare
1835                  * address) transaction.
1836                  */
1837                 msg.buffer = NULL;
1838                 msg.size = 0;
1839                 err = drm_dp_i2c_do_msg(aux, &msg);
1840
1841                 /*
1842                  * Reset msg.request in case in case it got
1843                  * changed into a WRITE_STATUS_UPDATE.
1844                  */
1845                 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1846
1847                 if (err < 0)
1848                         break;
1849                 /* We want each transaction to be as large as possible, but
1850                  * we'll go to smaller sizes if the hardware gives us a
1851                  * short reply.
1852                  */
1853                 transfer_size = dp_aux_i2c_transfer_size;
1854                 for (j = 0; j < msgs[i].len; j += msg.size) {
1855                         msg.buffer = msgs[i].buf + j;
1856                         msg.size = min(transfer_size, msgs[i].len - j);
1857
1858                         err = drm_dp_i2c_drain_msg(aux, &msg);
1859
1860                         /*
1861                          * Reset msg.request in case in case it got
1862                          * changed into a WRITE_STATUS_UPDATE.
1863                          */
1864                         drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1865
1866                         if (err < 0)
1867                                 break;
1868                         transfer_size = err;
1869                 }
1870                 if (err < 0)
1871                         break;
1872         }
1873         if (err >= 0)
1874                 err = num;
1875         /* Send a bare address packet to close out the transaction.
1876          * Zero sized messages specify an address only (bare
1877          * address) transaction.
1878          */
1879         msg.request &= ~DP_AUX_I2C_MOT;
1880         msg.buffer = NULL;
1881         msg.size = 0;
1882         (void)drm_dp_i2c_do_msg(aux, &msg);
1883
1884         return err;
1885 }
1886
1887 static const struct i2c_algorithm drm_dp_i2c_algo = {
1888         .functionality = drm_dp_i2c_functionality,
1889         .master_xfer = drm_dp_i2c_xfer,
1890 };
1891
1892 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1893 {
1894         return container_of(i2c, struct drm_dp_aux, ddc);
1895 }
1896
1897 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1898 {
1899         mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1900 }
1901
1902 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1903 {
1904         return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1905 }
1906
1907 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1908 {
1909         mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1910 }
1911
1912 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1913         .lock_bus = lock_bus,
1914         .trylock_bus = trylock_bus,
1915         .unlock_bus = unlock_bus,
1916 };
1917
1918 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1919 {
1920         u8 buf, count;
1921         int ret;
1922
1923         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1924         if (ret < 0)
1925                 return ret;
1926
1927         WARN_ON(!(buf & DP_TEST_SINK_START));
1928
1929         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1930         if (ret < 0)
1931                 return ret;
1932
1933         count = buf & DP_TEST_COUNT_MASK;
1934         if (count == aux->crc_count)
1935                 return -EAGAIN; /* No CRC yet */
1936
1937         aux->crc_count = count;
1938
1939         /*
1940          * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1941          * per component (RGB or CrYCb).
1942          */
1943         ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1944         if (ret < 0)
1945                 return ret;
1946
1947         return 0;
1948 }
1949
1950 static void drm_dp_aux_crc_work(struct work_struct *work)
1951 {
1952         struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1953                                               crc_work);
1954         struct drm_crtc *crtc;
1955         u8 crc_bytes[6];
1956         uint32_t crcs[3];
1957         int ret;
1958
1959         if (WARN_ON(!aux->crtc))
1960                 return;
1961
1962         crtc = aux->crtc;
1963         while (crtc->crc.opened) {
1964                 drm_crtc_wait_one_vblank(crtc);
1965                 if (!crtc->crc.opened)
1966                         break;
1967
1968                 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1969                 if (ret == -EAGAIN) {
1970                         usleep_range(1000, 2000);
1971                         ret = drm_dp_aux_get_crc(aux, crc_bytes);
1972                 }
1973
1974                 if (ret == -EAGAIN) {
1975                         drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
1976                                     aux->name, ret);
1977                         continue;
1978                 } else if (ret) {
1979                         drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
1980                         continue;
1981                 }
1982
1983                 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1984                 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1985                 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1986                 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1987         }
1988 }
1989
1990 /**
1991  * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1992  * @aux: DisplayPort AUX channel
1993  *
1994  * Used for remote aux channel in general. Merely initialize the crc work
1995  * struct.
1996  */
1997 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1998 {
1999         INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2000 }
2001 EXPORT_SYMBOL(drm_dp_remote_aux_init);
2002
2003 /**
2004  * drm_dp_aux_init() - minimally initialise an aux channel
2005  * @aux: DisplayPort AUX channel
2006  *
2007  * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2008  * the outside world, call drm_dp_aux_init() first. For drivers which are
2009  * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2010  * &drm_connector), you must still call drm_dp_aux_register() once the connector
2011  * has been registered to allow userspace access to the auxiliary DP channel.
2012  * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2013  * early as possible so that the &drm_device that corresponds to the AUX adapter
2014  * may be mentioned in debugging output from the DRM DP helpers.
2015  *
2016  * For devices which use a separate platform device for their AUX adapters, this
2017  * may be called as early as required by the driver.
2018  *
2019  */
2020 void drm_dp_aux_init(struct drm_dp_aux *aux)
2021 {
2022         mutex_init(&aux->hw_mutex);
2023         mutex_init(&aux->cec.lock);
2024         INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2025
2026         aux->ddc.algo = &drm_dp_i2c_algo;
2027         aux->ddc.algo_data = aux;
2028         aux->ddc.retries = 3;
2029
2030         aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2031 }
2032 EXPORT_SYMBOL(drm_dp_aux_init);
2033
2034 /**
2035  * drm_dp_aux_register() - initialise and register aux channel
2036  * @aux: DisplayPort AUX channel
2037  *
2038  * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2039  * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2040  * initialized. For devices which are grandparents of their AUX channels,
2041  * &drm_dp_aux.dev will typically be the &drm_connector &device which
2042  * corresponds to @aux. For these devices, it's advised to call
2043  * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2044  * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2045  * Functions which don't follow this will likely Oops when
2046  * %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
2047  *
2048  * For devices where the AUX channel is a device that exists independently of
2049  * the &drm_device that uses it, such as SoCs and bridge devices, it is
2050  * recommended to call drm_dp_aux_register() after a &drm_device has been
2051  * assigned to &drm_dp_aux.drm_dev, and likewise to call
2052  * drm_dp_aux_unregister() once the &drm_device should no longer be associated
2053  * with the AUX channel (e.g. on bridge detach).
2054  *
2055  * Drivers which need to use the aux channel before either of the two points
2056  * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2057  * channel before registration.
2058  *
2059  * Returns 0 on success or a negative error code on failure.
2060  */
2061 int drm_dp_aux_register(struct drm_dp_aux *aux)
2062 {
2063         int ret;
2064
2065         WARN_ON_ONCE(!aux->drm_dev);
2066
2067         if (!aux->ddc.algo)
2068                 drm_dp_aux_init(aux);
2069
2070         aux->ddc.class = I2C_CLASS_DDC;
2071         aux->ddc.owner = THIS_MODULE;
2072         aux->ddc.dev.parent = aux->dev;
2073
2074         strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2075                 sizeof(aux->ddc.name));
2076
2077         ret = drm_dp_aux_register_devnode(aux);
2078         if (ret)
2079                 return ret;
2080
2081         ret = i2c_add_adapter(&aux->ddc);
2082         if (ret) {
2083                 drm_dp_aux_unregister_devnode(aux);
2084                 return ret;
2085         }
2086
2087         return 0;
2088 }
2089 EXPORT_SYMBOL(drm_dp_aux_register);
2090
2091 /**
2092  * drm_dp_aux_unregister() - unregister an AUX adapter
2093  * @aux: DisplayPort AUX channel
2094  */
2095 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2096 {
2097         drm_dp_aux_unregister_devnode(aux);
2098         i2c_del_adapter(&aux->ddc);
2099 }
2100 EXPORT_SYMBOL(drm_dp_aux_unregister);
2101
2102 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2103
2104 /**
2105  * drm_dp_psr_setup_time() - PSR setup in time usec
2106  * @psr_cap: PSR capabilities from DPCD
2107  *
2108  * Returns:
2109  * PSR setup time for the panel in microseconds,  negative
2110  * error code on failure.
2111  */
2112 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2113 {
2114         static const u16 psr_setup_time_us[] = {
2115                 PSR_SETUP_TIME(330),
2116                 PSR_SETUP_TIME(275),
2117                 PSR_SETUP_TIME(220),
2118                 PSR_SETUP_TIME(165),
2119                 PSR_SETUP_TIME(110),
2120                 PSR_SETUP_TIME(55),
2121                 PSR_SETUP_TIME(0),
2122         };
2123         int i;
2124
2125         i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2126         if (i >= ARRAY_SIZE(psr_setup_time_us))
2127                 return -EINVAL;
2128
2129         return psr_setup_time_us[i];
2130 }
2131 EXPORT_SYMBOL(drm_dp_psr_setup_time);
2132
2133 #undef PSR_SETUP_TIME
2134
2135 /**
2136  * drm_dp_start_crc() - start capture of frame CRCs
2137  * @aux: DisplayPort AUX channel
2138  * @crtc: CRTC displaying the frames whose CRCs are to be captured
2139  *
2140  * Returns 0 on success or a negative error code on failure.
2141  */
2142 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2143 {
2144         u8 buf;
2145         int ret;
2146
2147         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2148         if (ret < 0)
2149                 return ret;
2150
2151         ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
2152         if (ret < 0)
2153                 return ret;
2154
2155         aux->crc_count = 0;
2156         aux->crtc = crtc;
2157         schedule_work(&aux->crc_work);
2158
2159         return 0;
2160 }
2161 EXPORT_SYMBOL(drm_dp_start_crc);
2162
2163 /**
2164  * drm_dp_stop_crc() - stop capture of frame CRCs
2165  * @aux: DisplayPort AUX channel
2166  *
2167  * Returns 0 on success or a negative error code on failure.
2168  */
2169 int drm_dp_stop_crc(struct drm_dp_aux *aux)
2170 {
2171         u8 buf;
2172         int ret;
2173
2174         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2175         if (ret < 0)
2176                 return ret;
2177
2178         ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
2179         if (ret < 0)
2180                 return ret;
2181
2182         flush_work(&aux->crc_work);
2183         aux->crtc = NULL;
2184
2185         return 0;
2186 }
2187 EXPORT_SYMBOL(drm_dp_stop_crc);
2188
2189 struct dpcd_quirk {
2190         u8 oui[3];
2191         u8 device_id[6];
2192         bool is_branch;
2193         u32 quirks;
2194 };
2195
2196 #define OUI(first, second, third) { (first), (second), (third) }
2197 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2198         { (first), (second), (third), (fourth), (fifth), (sixth) }
2199
2200 #define DEVICE_ID_ANY   DEVICE_ID(0, 0, 0, 0, 0, 0)
2201
2202 static const struct dpcd_quirk dpcd_quirk_list[] = {
2203         /* Analogix 7737 needs reduced M and N at HBR2 link rates */
2204         { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2205         /* LG LP140WF6-SPM1 eDP panel */
2206         { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2207         /* Apple panels need some additional handling to support PSR */
2208         { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2209         /* CH7511 seems to leave SINK_COUNT zeroed */
2210         { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2211         /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2212         { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2213         /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2214         { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2215 };
2216
2217 #undef OUI
2218
2219 /*
2220  * Get a bit mask of DPCD quirks for the sink/branch device identified by
2221  * ident. The quirk data is shared but it's up to the drivers to act on the
2222  * data.
2223  *
2224  * For now, only the OUI (first three bytes) is used, but this may be extended
2225  * to device identification string and hardware/firmware revisions later.
2226  */
2227 static u32
2228 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2229 {
2230         const struct dpcd_quirk *quirk;
2231         u32 quirks = 0;
2232         int i;
2233         u8 any_device[] = DEVICE_ID_ANY;
2234
2235         for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2236                 quirk = &dpcd_quirk_list[i];
2237
2238                 if (quirk->is_branch != is_branch)
2239                         continue;
2240
2241                 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
2242                         continue;
2243
2244                 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
2245                     memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
2246                         continue;
2247
2248                 quirks |= quirk->quirks;
2249         }
2250
2251         return quirks;
2252 }
2253
2254 #undef DEVICE_ID_ANY
2255 #undef DEVICE_ID
2256
2257 /**
2258  * drm_dp_read_desc - read sink/branch descriptor from DPCD
2259  * @aux: DisplayPort AUX channel
2260  * @desc: Device descriptor to fill from DPCD
2261  * @is_branch: true for branch devices, false for sink devices
2262  *
2263  * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2264  * identification.
2265  *
2266  * Returns 0 on success or a negative error code on failure.
2267  */
2268 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2269                      bool is_branch)
2270 {
2271         struct drm_dp_dpcd_ident *ident = &desc->ident;
2272         unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2273         int ret, dev_id_len;
2274
2275         ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2276         if (ret < 0)
2277                 return ret;
2278
2279         desc->quirks = drm_dp_get_quirks(ident, is_branch);
2280
2281         dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2282
2283         drm_dbg_kms(aux->drm_dev,
2284                     "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2285                     aux->name, is_branch ? "branch" : "sink",
2286                     (int)sizeof(ident->oui), ident->oui, dev_id_len,
2287                     ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,
2288                     ident->sw_major_rev, ident->sw_minor_rev, desc->quirks);
2289
2290         return 0;
2291 }
2292 EXPORT_SYMBOL(drm_dp_read_desc);
2293
2294 /**
2295  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2296  * supported by the DSC sink.
2297  * @dsc_dpcd: DSC capabilities from DPCD
2298  * @is_edp: true if its eDP, false for DP
2299  *
2300  * Read the slice capabilities DPCD register from DSC sink to get
2301  * the maximum slice count supported. This is used to populate
2302  * the DSC parameters in the &struct drm_dsc_config by the driver.
2303  * Driver creates an infoframe using these parameters to populate
2304  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2305  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2306  *
2307  * Returns:
2308  * Maximum slice count supported by DSC sink or 0 its invalid
2309  */
2310 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2311                                    bool is_edp)
2312 {
2313         u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2314
2315         if (is_edp) {
2316                 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2317                 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2318                         return 4;
2319                 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2320                         return 2;
2321                 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2322                         return 1;
2323         } else {
2324                 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2325                 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2326
2327                 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2328                         return 24;
2329                 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2330                         return 20;
2331                 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2332                         return 16;
2333                 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2334                         return 12;
2335                 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2336                         return 10;
2337                 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2338                         return 8;
2339                 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2340                         return 6;
2341                 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2342                         return 4;
2343                 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2344                         return 2;
2345                 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2346                         return 1;
2347         }
2348
2349         return 0;
2350 }
2351 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2352
2353 /**
2354  * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2355  * @dsc_dpcd: DSC capabilities from DPCD
2356  *
2357  * Read the DSC DPCD register to parse the line buffer depth in bits which is
2358  * number of bits of precision within the decoder line buffer supported by
2359  * the DSC sink. This is used to populate the DSC parameters in the
2360  * &struct drm_dsc_config by the driver.
2361  * Driver creates an infoframe using these parameters to populate
2362  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2363  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2364  *
2365  * Returns:
2366  * Line buffer depth supported by DSC panel or 0 its invalid
2367  */
2368 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2369 {
2370         u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2371
2372         switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2373         case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2374                 return 9;
2375         case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2376                 return 10;
2377         case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2378                 return 11;
2379         case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2380                 return 12;
2381         case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2382                 return 13;
2383         case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2384                 return 14;
2385         case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2386                 return 15;
2387         case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2388                 return 16;
2389         case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2390                 return 8;
2391         }
2392
2393         return 0;
2394 }
2395 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2396
2397 /**
2398  * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2399  * values supported by the DSC sink.
2400  * @dsc_dpcd: DSC capabilities from DPCD
2401  * @dsc_bpc: An array to be filled by this helper with supported
2402  *           input bpcs.
2403  *
2404  * Read the DSC DPCD from the sink device to parse the supported bits per
2405  * component values. This is used to populate the DSC parameters
2406  * in the &struct drm_dsc_config by the driver.
2407  * Driver creates an infoframe using these parameters to populate
2408  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2409  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2410  *
2411  * Returns:
2412  * Number of input BPC values parsed from the DPCD
2413  */
2414 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2415                                          u8 dsc_bpc[3])
2416 {
2417         int num_bpc = 0;
2418         u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2419
2420         if (color_depth & DP_DSC_12_BPC)
2421                 dsc_bpc[num_bpc++] = 12;
2422         if (color_depth & DP_DSC_10_BPC)
2423                 dsc_bpc[num_bpc++] = 10;
2424         if (color_depth & DP_DSC_8_BPC)
2425                 dsc_bpc[num_bpc++] = 8;
2426
2427         return num_bpc;
2428 }
2429 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2430
2431 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
2432                                   const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2433                                   u8 *buf, int buf_size)
2434 {
2435         /*
2436          * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
2437          * corrupted values when reading from the 0xF0000- range with a block
2438          * size bigger than 1.
2439          */
2440         int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2441         int offset;
2442         int ret;
2443
2444         for (offset = 0; offset < buf_size; offset += block_size) {
2445                 ret = drm_dp_dpcd_read(aux,
2446                                        address + offset,
2447                                        &buf[offset], block_size);
2448                 if (ret < 0)
2449                         return ret;
2450
2451                 WARN_ON(ret != block_size);
2452         }
2453
2454         return 0;
2455 }
2456
2457 /**
2458  * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2459  * @aux: DisplayPort AUX channel
2460  * @dpcd: DisplayPort configuration data
2461  * @caps: buffer to return the capability info in
2462  *
2463  * Read capabilities common to all LTTPRs.
2464  *
2465  * Returns 0 on success or a negative error code on failure.
2466  */
2467 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2468                                   const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2469                                   u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2470 {
2471         return drm_dp_read_lttpr_regs(aux, dpcd,
2472                                       DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2473                                       caps, DP_LTTPR_COMMON_CAP_SIZE);
2474 }
2475 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2476
2477 /**
2478  * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2479  * @aux: DisplayPort AUX channel
2480  * @dpcd: DisplayPort configuration data
2481  * @dp_phy: LTTPR PHY to read the capabilities for
2482  * @caps: buffer to return the capability info in
2483  *
2484  * Read the capabilities for the given LTTPR PHY.
2485  *
2486  * Returns 0 on success or a negative error code on failure.
2487  */
2488 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2489                                const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2490                                enum drm_dp_phy dp_phy,
2491                                u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2492 {
2493         return drm_dp_read_lttpr_regs(aux, dpcd,
2494                                       DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2495                                       caps, DP_LTTPR_PHY_CAP_SIZE);
2496 }
2497 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2498
2499 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2500 {
2501         return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2502 }
2503
2504 /**
2505  * drm_dp_lttpr_count - get the number of detected LTTPRs
2506  * @caps: LTTPR common capabilities
2507  *
2508  * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2509  *
2510  * Returns:
2511  *   -ERANGE if more than supported number (8) of LTTPRs are detected
2512  *   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2513  *   otherwise the number of detected LTTPRs
2514  */
2515 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2516 {
2517         u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2518
2519         switch (hweight8(count)) {
2520         case 0:
2521                 return 0;
2522         case 1:
2523                 return 8 - ilog2(count);
2524         case 8:
2525                 return -ERANGE;
2526         default:
2527                 return -EINVAL;
2528         }
2529 }
2530 EXPORT_SYMBOL(drm_dp_lttpr_count);
2531
2532 /**
2533  * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2534  * @caps: LTTPR common capabilities
2535  *
2536  * Returns the maximum link rate supported by all detected LTTPRs.
2537  */
2538 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2539 {
2540         u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2541
2542         return drm_dp_bw_code_to_link_rate(rate);
2543 }
2544 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2545
2546 /**
2547  * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2548  * @caps: LTTPR common capabilities
2549  *
2550  * Returns the maximum lane count supported by all detected LTTPRs.
2551  */
2552 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2553 {
2554         u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2555
2556         return max_lanes & DP_MAX_LANE_COUNT_MASK;
2557 }
2558 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2559
2560 /**
2561  * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2562  * @caps: LTTPR PHY capabilities
2563  *
2564  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2565  * voltage swing level 3.
2566  */
2567 bool
2568 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2569 {
2570         u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2571
2572         return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2573 }
2574 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2575
2576 /**
2577  * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2578  * @caps: LTTPR PHY capabilities
2579  *
2580  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2581  * pre-emphasis level 3.
2582  */
2583 bool
2584 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2585 {
2586         u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2587
2588         return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2589 }
2590 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2591
2592 /**
2593  * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2594  * @aux: DisplayPort AUX channel
2595  * @data: DP phy compliance test parameters.
2596  *
2597  * Returns 0 on success or a negative error code on failure.
2598  */
2599 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2600                                 struct drm_dp_phy_test_params *data)
2601 {
2602         int err;
2603         u8 rate, lanes;
2604
2605         err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2606         if (err < 0)
2607                 return err;
2608         data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2609
2610         err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2611         if (err < 0)
2612                 return err;
2613         data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2614
2615         if (lanes & DP_ENHANCED_FRAME_CAP)
2616                 data->enhanced_frame_cap = true;
2617
2618         err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2619         if (err < 0)
2620                 return err;
2621
2622         switch (data->phy_pattern) {
2623         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2624                 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2625                                        &data->custom80, sizeof(data->custom80));
2626                 if (err < 0)
2627                         return err;
2628
2629                 break;
2630         case DP_PHY_TEST_PATTERN_CP2520:
2631                 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2632                                        &data->hbr2_reset,
2633                                        sizeof(data->hbr2_reset));
2634                 if (err < 0)
2635                         return err;
2636         }
2637
2638         return 0;
2639 }
2640 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2641
2642 /**
2643  * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2644  * @aux: DisplayPort AUX channel
2645  * @data: DP phy compliance test parameters.
2646  * @dp_rev: DP revision to use for compliance testing
2647  *
2648  * Returns 0 on success or a negative error code on failure.
2649  */
2650 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2651                                 struct drm_dp_phy_test_params *data, u8 dp_rev)
2652 {
2653         int err, i;
2654         u8 link_config[2];
2655         u8 test_pattern;
2656
2657         link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
2658         link_config[1] = data->num_lanes;
2659         if (data->enhanced_frame_cap)
2660                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2661         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
2662         if (err < 0)
2663                 return err;
2664
2665         test_pattern = data->phy_pattern;
2666         if (dp_rev < 0x12) {
2667                 test_pattern = (test_pattern << 2) &
2668                                DP_LINK_QUAL_PATTERN_11_MASK;
2669                 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2670                                          test_pattern);
2671                 if (err < 0)
2672                         return err;
2673         } else {
2674                 for (i = 0; i < data->num_lanes; i++) {
2675                         err = drm_dp_dpcd_writeb(aux,
2676                                                  DP_LINK_QUAL_LANE0_SET + i,
2677                                                  test_pattern);
2678                         if (err < 0)
2679                                 return err;
2680                 }
2681         }
2682
2683         return 0;
2684 }
2685 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2686
2687 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2688 {
2689         if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2690                 return "Invalid";
2691
2692         switch (pixelformat) {
2693         case DP_PIXELFORMAT_RGB:
2694                 return "RGB";
2695         case DP_PIXELFORMAT_YUV444:
2696                 return "YUV444";
2697         case DP_PIXELFORMAT_YUV422:
2698                 return "YUV422";
2699         case DP_PIXELFORMAT_YUV420:
2700                 return "YUV420";
2701         case DP_PIXELFORMAT_Y_ONLY:
2702                 return "Y_ONLY";
2703         case DP_PIXELFORMAT_RAW:
2704                 return "RAW";
2705         default:
2706                 return "Reserved";
2707         }
2708 }
2709
2710 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2711                                            enum dp_colorimetry colorimetry)
2712 {
2713         if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2714                 return "Invalid";
2715
2716         switch (colorimetry) {
2717         case DP_COLORIMETRY_DEFAULT:
2718                 switch (pixelformat) {
2719                 case DP_PIXELFORMAT_RGB:
2720                         return "sRGB";
2721                 case DP_PIXELFORMAT_YUV444:
2722                 case DP_PIXELFORMAT_YUV422:
2723                 case DP_PIXELFORMAT_YUV420:
2724                         return "BT.601";
2725                 case DP_PIXELFORMAT_Y_ONLY:
2726                         return "DICOM PS3.14";
2727                 case DP_PIXELFORMAT_RAW:
2728                         return "Custom Color Profile";
2729                 default:
2730                         return "Reserved";
2731                 }
2732         case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2733                 switch (pixelformat) {
2734                 case DP_PIXELFORMAT_RGB:
2735                         return "Wide Fixed";
2736                 case DP_PIXELFORMAT_YUV444:
2737                 case DP_PIXELFORMAT_YUV422:
2738                 case DP_PIXELFORMAT_YUV420:
2739                         return "BT.709";
2740                 default:
2741                         return "Reserved";
2742                 }
2743         case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2744                 switch (pixelformat) {
2745                 case DP_PIXELFORMAT_RGB:
2746                         return "Wide Float";
2747                 case DP_PIXELFORMAT_YUV444:
2748                 case DP_PIXELFORMAT_YUV422:
2749                 case DP_PIXELFORMAT_YUV420:
2750                         return "xvYCC 601";
2751                 default:
2752                         return "Reserved";
2753                 }
2754         case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2755                 switch (pixelformat) {
2756                 case DP_PIXELFORMAT_RGB:
2757                         return "OpRGB";
2758                 case DP_PIXELFORMAT_YUV444:
2759                 case DP_PIXELFORMAT_YUV422:
2760                 case DP_PIXELFORMAT_YUV420:
2761                         return "xvYCC 709";
2762                 default:
2763                         return "Reserved";
2764                 }
2765         case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2766                 switch (pixelformat) {
2767                 case DP_PIXELFORMAT_RGB:
2768                         return "DCI-P3";
2769                 case DP_PIXELFORMAT_YUV444:
2770                 case DP_PIXELFORMAT_YUV422:
2771                 case DP_PIXELFORMAT_YUV420:
2772                         return "sYCC 601";
2773                 default:
2774                         return "Reserved";
2775                 }
2776         case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2777                 switch (pixelformat) {
2778                 case DP_PIXELFORMAT_RGB:
2779                         return "Custom Profile";
2780                 case DP_PIXELFORMAT_YUV444:
2781                 case DP_PIXELFORMAT_YUV422:
2782                 case DP_PIXELFORMAT_YUV420:
2783                         return "OpYCC 601";
2784                 default:
2785                         return "Reserved";
2786                 }
2787         case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2788                 switch (pixelformat) {
2789                 case DP_PIXELFORMAT_RGB:
2790                         return "BT.2020 RGB";
2791                 case DP_PIXELFORMAT_YUV444:
2792                 case DP_PIXELFORMAT_YUV422:
2793                 case DP_PIXELFORMAT_YUV420:
2794                         return "BT.2020 CYCC";
2795                 default:
2796                         return "Reserved";
2797                 }
2798         case DP_COLORIMETRY_BT2020_YCC:
2799                 switch (pixelformat) {
2800                 case DP_PIXELFORMAT_YUV444:
2801                 case DP_PIXELFORMAT_YUV422:
2802                 case DP_PIXELFORMAT_YUV420:
2803                         return "BT.2020 YCC";
2804                 default:
2805                         return "Reserved";
2806                 }
2807         default:
2808                 return "Invalid";
2809         }
2810 }
2811
2812 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2813 {
2814         switch (dynamic_range) {
2815         case DP_DYNAMIC_RANGE_VESA:
2816                 return "VESA range";
2817         case DP_DYNAMIC_RANGE_CTA:
2818                 return "CTA range";
2819         default:
2820                 return "Invalid";
2821         }
2822 }
2823
2824 static const char *dp_content_type_get_name(enum dp_content_type content_type)
2825 {
2826         switch (content_type) {
2827         case DP_CONTENT_TYPE_NOT_DEFINED:
2828                 return "Not defined";
2829         case DP_CONTENT_TYPE_GRAPHICS:
2830                 return "Graphics";
2831         case DP_CONTENT_TYPE_PHOTO:
2832                 return "Photo";
2833         case DP_CONTENT_TYPE_VIDEO:
2834                 return "Video";
2835         case DP_CONTENT_TYPE_GAME:
2836                 return "Game";
2837         default:
2838                 return "Reserved";
2839         }
2840 }
2841
2842 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2843                         const struct drm_dp_vsc_sdp *vsc)
2844 {
2845 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2846         DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2847                    vsc->revision, vsc->length);
2848         DP_SDP_LOG("    pixelformat: %s\n",
2849                    dp_pixelformat_get_name(vsc->pixelformat));
2850         DP_SDP_LOG("    colorimetry: %s\n",
2851                    dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2852         DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
2853         DP_SDP_LOG("    dynamic range: %s\n",
2854                    dp_dynamic_range_get_name(vsc->dynamic_range));
2855         DP_SDP_LOG("    content type: %s\n",
2856                    dp_content_type_get_name(vsc->content_type));
2857 #undef DP_SDP_LOG
2858 }
2859 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2860
2861 /**
2862  * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2863  * @dpcd: DisplayPort configuration data
2864  * @port_cap: port capabilities
2865  *
2866  * Returns maximum frl bandwidth supported by PCON in GBPS,
2867  * returns 0 if not supported.
2868  */
2869 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2870                                const u8 port_cap[4])
2871 {
2872         int bw;
2873         u8 buf;
2874
2875         buf = port_cap[2];
2876         bw = buf & DP_PCON_MAX_FRL_BW;
2877
2878         switch (bw) {
2879         case DP_PCON_MAX_9GBPS:
2880                 return 9;
2881         case DP_PCON_MAX_18GBPS:
2882                 return 18;
2883         case DP_PCON_MAX_24GBPS:
2884                 return 24;
2885         case DP_PCON_MAX_32GBPS:
2886                 return 32;
2887         case DP_PCON_MAX_40GBPS:
2888                 return 40;
2889         case DP_PCON_MAX_48GBPS:
2890                 return 48;
2891         case DP_PCON_MAX_0GBPS:
2892         default:
2893                 return 0;
2894         }
2895
2896         return 0;
2897 }
2898 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
2899
2900 /**
2901  * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2902  * @aux: DisplayPort AUX channel
2903  * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
2904  *
2905  * Returns 0 if success, else returns negative error code.
2906  */
2907 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
2908 {
2909         int ret;
2910         u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
2911                  DP_PCON_ENABLE_LINK_FRL_MODE;
2912
2913         if (enable_frl_ready_hpd)
2914                 buf |= DP_PCON_ENABLE_HPD_READY;
2915
2916         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2917
2918         return ret;
2919 }
2920 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
2921
2922 /**
2923  * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
2924  * @aux: DisplayPort AUX channel
2925  *
2926  * Returns true if success, else returns false.
2927  */
2928 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2929 {
2930         int ret;
2931         u8 buf;
2932
2933         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2934         if (ret < 0)
2935                 return false;
2936
2937         if (buf & DP_PCON_FRL_READY)
2938                 return true;
2939
2940         return false;
2941 }
2942 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
2943
2944 /**
2945  * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
2946  * @aux: DisplayPort AUX channel
2947  * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
2948  * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
2949  * In Concurrent Mode, the FRL link bring up can be done along with
2950  * DP Link training. In Sequential mode, the FRL link bring up is done prior to
2951  * the DP Link training.
2952  *
2953  * Returns 0 if success, else returns negative error code.
2954  */
2955
2956 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2957                                 u8 frl_mode)
2958 {
2959         int ret;
2960         u8 buf;
2961
2962         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2963         if (ret < 0)
2964                 return ret;
2965
2966         if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
2967                 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
2968         else
2969                 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
2970
2971         switch (max_frl_gbps) {
2972         case 9:
2973                 buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
2974                 break;
2975         case 18:
2976                 buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
2977                 break;
2978         case 24:
2979                 buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
2980                 break;
2981         case 32:
2982                 buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
2983                 break;
2984         case 40:
2985                 buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
2986                 break;
2987         case 48:
2988                 buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
2989                 break;
2990         case 0:
2991                 buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
2992                 break;
2993         default:
2994                 return -EINVAL;
2995         }
2996
2997         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2998         if (ret < 0)
2999                 return ret;
3000
3001         return 0;
3002 }
3003 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3004
3005 /**
3006  * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3007  * @aux: DisplayPort AUX channel
3008  * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3009  * @frl_type : FRL training type, can be Extended, or Normal.
3010  * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3011  * starting from min, and stops when link training is successful. In Extended
3012  * FRL training, all frl bw selected in the mask are trained by the PCON.
3013  *
3014  * Returns 0 if success, else returns negative error code.
3015  */
3016 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3017                                 u8 frl_type)
3018 {
3019         int ret;
3020         u8 buf = max_frl_mask;
3021
3022         if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3023                 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3024         else
3025                 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3026
3027         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
3028         if (ret < 0)
3029                 return ret;
3030
3031         return 0;
3032 }
3033 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3034
3035 /**
3036  * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3037  * @aux: DisplayPort AUX channel
3038  *
3039  * Returns 0 if success, else returns negative error code.
3040  */
3041 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3042 {
3043         int ret;
3044
3045         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
3046         if (ret < 0)
3047                 return ret;
3048
3049         return 0;
3050 }
3051 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3052
3053 /**
3054  * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3055  * @aux: DisplayPort AUX channel
3056  *
3057  * Returns 0 if success, else returns negative error code.
3058  */
3059 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3060 {
3061         int ret;
3062         u8 buf = 0;
3063
3064         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3065         if (ret < 0)
3066                 return ret;
3067         if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3068                 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3069                             aux->name);
3070                 return -EINVAL;
3071         }
3072         buf |= DP_PCON_ENABLE_HDMI_LINK;
3073         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3074         if (ret < 0)
3075                 return ret;
3076
3077         return 0;
3078 }
3079 EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3080
3081 /**
3082  * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3083  * @aux: DisplayPort AUX channel
3084  *
3085  * Returns true if link is active else returns false.
3086  */
3087 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3088 {
3089         u8 buf;
3090         int ret;
3091
3092         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3093         if (ret < 0)
3094                 return false;
3095
3096         return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3097 }
3098 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3099
3100 /**
3101  * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3102  * @aux: DisplayPort AUX channel
3103  * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3104  * Valid only if the MODE returned is FRL. For Normal Link training mode
3105  * only 1 of the bits will be set, but in case of Extended mode, more than
3106  * one bits can be set.
3107  *
3108  * Returns the link mode : TMDS or FRL on success, else returns negative error
3109  * code.
3110  */
3111 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3112 {
3113         u8 buf;
3114         int mode;
3115         int ret;
3116
3117         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
3118         if (ret < 0)
3119                 return ret;
3120
3121         mode = buf & DP_PCON_HDMI_LINK_MODE;
3122
3123         if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3124                 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3125
3126         return mode;
3127 }
3128 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3129
3130 /**
3131  * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3132  * during link failure between PCON and HDMI sink
3133  * @aux: DisplayPort AUX channel
3134  * @connector: DRM connector
3135  * code.
3136  **/
3137
3138 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3139                                            struct drm_connector *connector)
3140 {
3141         u8 buf, error_count;
3142         int i, num_error;
3143         struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3144
3145         for (i = 0; i < hdmi->max_lanes; i++) {
3146                 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
3147                         return;
3148
3149                 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3150                 switch (error_count) {
3151                 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3152                         num_error = 100;
3153                         break;
3154                 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3155                         num_error = 10;
3156                         break;
3157                 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3158                         num_error = 3;
3159                         break;
3160                 default:
3161                         num_error = 0;
3162                 }
3163
3164                 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3165                         aux->name, num_error, i);
3166         }
3167 }
3168 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3169
3170 /*
3171  * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3172  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3173  *
3174  * Returns true is PCON encoder is DSC 1.2 else returns false.
3175  */
3176 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3177 {
3178         u8 buf;
3179         u8 major_v, minor_v;
3180
3181         buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3182         major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3183         minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3184
3185         if (major_v == 1 && minor_v == 2)
3186                 return true;
3187
3188         return false;
3189 }
3190 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3191
3192 /*
3193  * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3194  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3195  *
3196  * Returns maximum no. of slices supported by the PCON DSC Encoder.
3197  */
3198 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3199 {
3200         u8 slice_cap1, slice_cap2;
3201
3202         slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3203         slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3204
3205         if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3206                 return 24;
3207         if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3208                 return 20;
3209         if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3210                 return 16;
3211         if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3212                 return 12;
3213         if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3214                 return 10;
3215         if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3216                 return 8;
3217         if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3218                 return 6;
3219         if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3220                 return 4;
3221         if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3222                 return 2;
3223         if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3224                 return 1;
3225
3226         return 0;
3227 }
3228 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3229
3230 /*
3231  * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3232  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3233  *
3234  * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3235  */
3236 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3237 {
3238         u8 buf;
3239
3240         buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3241
3242         return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3243 }
3244 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3245
3246 /*
3247  * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3248  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3249  *
3250  * Returns the bpp precision supported by the PCON encoder.
3251  */
3252 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3253 {
3254         u8 buf;
3255
3256         buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3257
3258         switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3259         case DP_PCON_DSC_ONE_16TH_BPP:
3260                 return 16;
3261         case DP_PCON_DSC_ONE_8TH_BPP:
3262                 return 8;
3263         case DP_PCON_DSC_ONE_4TH_BPP:
3264                 return 4;
3265         case DP_PCON_DSC_ONE_HALF_BPP:
3266                 return 2;
3267         case DP_PCON_DSC_ONE_BPP:
3268                 return 1;
3269         }
3270
3271         return 0;
3272 }
3273 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
3274
3275 static
3276 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3277 {
3278         u8 buf;
3279         int ret;
3280
3281         ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3282         if (ret < 0)
3283                 return ret;
3284
3285         buf |= DP_PCON_ENABLE_DSC_ENCODER;
3286
3287         if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3288                 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3289                 buf |= pps_buf_config << 2;
3290         }
3291
3292         ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3293         if (ret < 0)
3294                 return ret;
3295
3296         return 0;
3297 }
3298
3299 /**
3300  * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3301  * for DSC1.2 between PCON & HDMI2.1 sink
3302  * @aux: DisplayPort AUX channel
3303  *
3304  * Returns 0 on success, else returns negative error code.
3305  */
3306 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3307 {
3308         int ret;
3309
3310         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3311         if (ret < 0)
3312                 return ret;
3313
3314         return 0;
3315 }
3316 EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3317
3318 /**
3319  * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3320  * HDMI sink
3321  * @aux: DisplayPort AUX channel
3322  * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3323  *
3324  * Returns 0 on success, else returns negative error code.
3325  */
3326 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3327 {
3328         int ret;
3329
3330         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3331         if (ret < 0)
3332                 return ret;
3333
3334         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3335         if (ret < 0)
3336                 return ret;
3337
3338         return 0;
3339 }
3340 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3341
3342 /*
3343  * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3344  * override registers
3345  * @aux: DisplayPort AUX channel
3346  * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3347  * bits_per_pixel.
3348  *
3349  * Returns 0 on success, else returns negative error code.
3350  */
3351 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3352 {
3353         int ret;
3354
3355         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3356         if (ret < 0)
3357                 return ret;
3358         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3359         if (ret < 0)
3360                 return ret;
3361         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3362         if (ret < 0)
3363                 return ret;
3364
3365         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3366         if (ret < 0)
3367                 return ret;
3368
3369         return 0;
3370 }
3371 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3372
3373 /*
3374  * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3375  * @aux: displayPort AUX channel
3376  * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3377  *
3378  * Returns 0 on success, else returns negative error code.
3379  */
3380 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3381 {
3382         int ret;
3383         u8 buf;
3384
3385         ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3386         if (ret < 0)
3387                 return ret;
3388
3389         if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3390                 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3391         else
3392                 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3393
3394         ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3395         if (ret < 0)
3396                 return ret;
3397
3398         return 0;
3399 }
3400 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3401
3402 /**
3403  * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3404  * @aux: The DP AUX channel to use
3405  * @bl: Backlight capability info from drm_edp_backlight_init()
3406  * @level: The brightness level to set
3407  *
3408  * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
3409  * already have been enabled by the driver by calling drm_edp_backlight_enable().
3410  *
3411  * Returns: %0 on success, negative error code on failure
3412  */
3413 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3414                                 u16 level)
3415 {
3416         int ret;
3417         u8 buf[2] = { 0 };
3418
3419         /* The panel uses the PWM for controlling brightness levels */
3420         if (!bl->aux_set)
3421                 return 0;
3422
3423         if (bl->lsb_reg_used) {
3424                 buf[0] = (level & 0xff00) >> 8;
3425                 buf[1] = (level & 0x00ff);
3426         } else {
3427                 buf[0] = level;
3428         }
3429
3430         ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
3431         if (ret != sizeof(buf)) {
3432                 drm_err(aux->drm_dev,
3433                         "%s: Failed to write aux backlight level: %d\n",
3434                         aux->name, ret);
3435                 return ret < 0 ? ret : -EIO;
3436         }
3437
3438         return 0;
3439 }
3440 EXPORT_SYMBOL(drm_edp_backlight_set_level);
3441
3442 static int
3443 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3444                              bool enable)
3445 {
3446         int ret;
3447         u8 buf;
3448
3449         /* This panel uses the EDP_BL_PWR GPIO for enablement */
3450         if (!bl->aux_enable)
3451                 return 0;
3452
3453         ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
3454         if (ret != 1) {
3455                 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3456                         aux->name, ret);
3457                 return ret < 0 ? ret : -EIO;
3458         }
3459         if (enable)
3460                 buf |= DP_EDP_BACKLIGHT_ENABLE;
3461         else
3462                 buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3463
3464         ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
3465         if (ret != 1) {
3466                 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3467                         aux->name, ret);
3468                 return ret < 0 ? ret : -EIO;
3469         }
3470
3471         return 0;
3472 }
3473
3474 /**
3475  * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3476  * @aux: The DP AUX channel to use
3477  * @bl: Backlight capability info from drm_edp_backlight_init()
3478  * @level: The initial backlight level to set via AUX, if there is one
3479  *
3480  * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
3481  * restoring any important backlight state such as the given backlight level, the brightness byte
3482  * count, backlight frequency, etc.
3483  *
3484  * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3485  * that the driver handle enabling/disabling the panel through implementation-specific means using
3486  * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3487  * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3488  * the EDP_BL_PWR GPIO.
3489  *
3490  * Returns: %0 on success, negative error code on failure.
3491  */
3492 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3493                              const u16 level)
3494 {
3495         int ret;
3496         u8 dpcd_buf;
3497
3498         if (bl->aux_set)
3499                 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
3500         else
3501                 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
3502
3503         if (bl->pwmgen_bit_count) {
3504                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
3505                 if (ret != 1)
3506                         drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3507                                     aux->name, ret);
3508         }
3509
3510         if (bl->pwm_freq_pre_divider) {
3511                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
3512                 if (ret != 1)
3513                         drm_dbg_kms(aux->drm_dev,
3514                                     "%s: Failed to write aux backlight frequency: %d\n",
3515                                     aux->name, ret);
3516                 else
3517                         dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
3518         }
3519
3520         ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf);
3521         if (ret != 1) {
3522                 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
3523                             aux->name, ret);
3524                 return ret < 0 ? ret : -EIO;
3525         }
3526
3527         ret = drm_edp_backlight_set_level(aux, bl, level);
3528         if (ret < 0)
3529                 return ret;
3530         ret = drm_edp_backlight_set_enable(aux, bl, true);
3531         if (ret < 0)
3532                 return ret;
3533
3534         return 0;
3535 }
3536 EXPORT_SYMBOL(drm_edp_backlight_enable);
3537
3538 /**
3539  * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3540  * @aux: The DP AUX channel to use
3541  * @bl: Backlight capability info from drm_edp_backlight_init()
3542  *
3543  * This function handles disabling DPCD backlight controls on a panel over AUX.
3544  *
3545  * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3546  * that the driver handle enabling/disabling the panel through implementation-specific means using
3547  * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3548  * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3549  * the EDP_BL_PWR GPIO.
3550  *
3551  * Returns: %0 on success or no-op, negative error code on failure.
3552  */
3553 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3554 {
3555         int ret;
3556
3557         ret = drm_edp_backlight_set_enable(aux, bl, false);
3558         if (ret < 0)
3559                 return ret;
3560
3561         return 0;
3562 }
3563 EXPORT_SYMBOL(drm_edp_backlight_disable);
3564
3565 static inline int
3566 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3567                             u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3568 {
3569         int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
3570         int ret;
3571         u8 pn, pn_min, pn_max;
3572
3573         if (!bl->aux_set)
3574                 return 0;
3575
3576         ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
3577         if (ret != 1) {
3578                 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
3579                             aux->name, ret);
3580                 return -ENODEV;
3581         }
3582
3583         pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3584         bl->max = (1 << pn) - 1;
3585         if (!driver_pwm_freq_hz)
3586                 return 0;
3587
3588         /*
3589          * Set PWM Frequency divider to match desired frequency provided by the driver.
3590          * The PWM Frequency is calculated as 27Mhz / (F x P).
3591          * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
3592          *             EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
3593          * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
3594          *             EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
3595          */
3596
3597         /* Find desired value of (F x P)
3598          * Note that, if F x P is out of supported range, the maximum value or minimum value will
3599          * applied automatically. So no need to check that.
3600          */
3601         fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
3602
3603         /* Use highest possible value of Pn for more granularity of brightness adjustment while
3604          * satisfying the conditions below.
3605          * - Pn is in the range of Pn_min and Pn_max
3606          * - F is in the range of 1 and 255
3607          * - FxP is within 25% of desired value.
3608          *   Note: 25% is arbitrary value and may need some tweak.
3609          */
3610         ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
3611         if (ret != 1) {
3612                 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
3613                             aux->name, ret);
3614                 return 0;
3615         }
3616         ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
3617         if (ret != 1) {
3618                 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
3619                             aux->name, ret);
3620                 return 0;
3621         }
3622         pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3623         pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3624
3625         /* Ensure frequency is within 25% of desired value */
3626         fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
3627         fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
3628         if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
3629                 drm_dbg_kms(aux->drm_dev,
3630                             "%s: Driver defined backlight frequency (%d) out of range\n",
3631                             aux->name, driver_pwm_freq_hz);
3632                 return 0;
3633         }
3634
3635         for (pn = pn_max; pn >= pn_min; pn--) {
3636                 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
3637                 fxp_actual = f << pn;
3638                 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
3639                         break;
3640         }
3641
3642         ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
3643         if (ret != 1) {
3644                 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3645                             aux->name, ret);
3646                 return 0;
3647         }
3648         bl->pwmgen_bit_count = pn;
3649         bl->max = (1 << pn) - 1;
3650
3651         if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3652                 bl->pwm_freq_pre_divider = f;
3653                 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
3654                             aux->name, driver_pwm_freq_hz);
3655         }
3656
3657         return 0;
3658 }
3659
3660 static inline int
3661 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3662                               u8 *current_mode)
3663 {
3664         int ret;
3665         u8 buf[2];
3666         u8 mode_reg;
3667
3668         ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
3669         if (ret != 1) {
3670                 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
3671                             aux->name, ret);
3672                 return ret < 0 ? ret : -EIO;
3673         }
3674
3675         *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
3676         if (!bl->aux_set)
3677                 return 0;
3678
3679         if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3680                 int size = 1 + bl->lsb_reg_used;
3681
3682                 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
3683                 if (ret != size) {
3684                         drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
3685                                     aux->name, ret);
3686                         return ret < 0 ? ret : -EIO;
3687                 }
3688
3689                 if (bl->lsb_reg_used)
3690                         return (buf[0] << 8) | buf[1];
3691                 else
3692                         return buf[0];
3693         }
3694
3695         /*
3696          * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
3697          * the driver should assume max brightness
3698          */
3699         return bl->max;
3700 }
3701
3702 /**
3703  * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3704  * interface.
3705  * @aux: The DP aux device to use for probing
3706  * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
3707  * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
3708  * @edp_dpcd: A cached copy of the eDP DPCD
3709  * @current_level: Where to store the probed brightness level, if any
3710  * @current_mode: Where to store the currently set backlight control mode
3711  *
3712  * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
3713  * along with also probing the current and maximum supported brightness levels.
3714  *
3715  * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3716  * default frequency from the panel is used.
3717  *
3718  * Returns: %0 on success, negative error code on failure.
3719  */
3720 int
3721 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3722                        u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3723                        u16 *current_level, u8 *current_mode)
3724 {
3725         int ret;
3726
3727         if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
3728                 bl->aux_enable = true;
3729         if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
3730                 bl->aux_set = true;
3731         if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
3732                 bl->lsb_reg_used = true;
3733
3734         /* Sanity check caps */
3735         if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
3736                 drm_dbg_kms(aux->drm_dev,
3737                             "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
3738                             aux->name);
3739                 return -EINVAL;
3740         }
3741
3742         ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
3743         if (ret < 0)
3744                 return ret;
3745
3746         ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
3747         if (ret < 0)
3748                 return ret;
3749         *current_level = ret;
3750
3751         drm_dbg_kms(aux->drm_dev,
3752                     "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
3753                     aux->name, bl->aux_set, bl->aux_enable, *current_mode);
3754         if (bl->aux_set) {
3755                 drm_dbg_kms(aux->drm_dev,
3756                             "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
3757                             aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
3758                             bl->lsb_reg_used);
3759         }
3760
3761         return 0;
3762 }
3763 EXPORT_SYMBOL(drm_edp_backlight_init);
3764
3765 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
3766         (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
3767
3768 static int dp_aux_backlight_update_status(struct backlight_device *bd)
3769 {
3770         struct dp_aux_backlight *bl = bl_get_data(bd);
3771         u16 brightness = backlight_get_brightness(bd);
3772         int ret = 0;
3773
3774         if (!backlight_is_blank(bd)) {
3775                 if (!bl->enabled) {
3776                         drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
3777                         bl->enabled = true;
3778                         return 0;
3779                 }
3780                 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
3781         } else {
3782                 if (bl->enabled) {
3783                         drm_edp_backlight_disable(bl->aux, &bl->info);
3784                         bl->enabled = false;
3785                 }
3786         }
3787
3788         return ret;
3789 }
3790
3791 static const struct backlight_ops dp_aux_bl_ops = {
3792         .update_status = dp_aux_backlight_update_status,
3793 };
3794
3795 /**
3796  * drm_panel_dp_aux_backlight - create and use DP AUX backlight
3797  * @panel: DRM panel
3798  * @aux: The DP AUX channel to use
3799  *
3800  * Use this function to create and handle backlight if your panel
3801  * supports backlight control over DP AUX channel using DPCD
3802  * registers as per VESA's standard backlight control interface.
3803  *
3804  * When the panel is enabled backlight will be enabled after a
3805  * successful call to &drm_panel_funcs.enable()
3806  *
3807  * When the panel is disabled backlight will be disabled before the
3808  * call to &drm_panel_funcs.disable().
3809  *
3810  * A typical implementation for a panel driver supporting backlight
3811  * control over DP AUX will call this function at probe time.
3812  * Backlight will then be handled transparently without requiring
3813  * any intervention from the driver.
3814  *
3815  * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
3816  *
3817  * Return: 0 on success or a negative error code on failure.
3818  */
3819 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
3820 {
3821         struct dp_aux_backlight *bl;
3822         struct backlight_properties props = { 0 };
3823         u16 current_level;
3824         u8 current_mode;
3825         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
3826         int ret;
3827
3828         if (!panel || !panel->dev || !aux)
3829                 return -EINVAL;
3830
3831         ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd,
3832                                EDP_DISPLAY_CTL_CAP_SIZE);
3833         if (ret < 0)
3834                 return ret;
3835
3836         if (!drm_edp_backlight_supported(edp_dpcd)) {
3837                 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
3838                 return 0;
3839         }
3840
3841         bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL);
3842         if (!bl)
3843                 return -ENOMEM;
3844
3845         bl->aux = aux;
3846
3847         ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
3848                                      &current_level, &current_mode);
3849         if (ret < 0)
3850                 return ret;
3851
3852         props.type = BACKLIGHT_RAW;
3853         props.brightness = current_level;
3854         props.max_brightness = bl->info.max;
3855
3856         bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
3857                                                   panel->dev, bl,
3858                                                   &dp_aux_bl_ops, &props);
3859         if (IS_ERR(bl->base))
3860                 return PTR_ERR(bl->base);
3861
3862         backlight_disable(bl->base);
3863
3864         panel->backlight = bl->base;
3865
3866         return 0;
3867 }
3868 EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
3869
3870 #endif