drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "gfxhub_v1_2.h"
  53 #include "mmhub_v9_4.h"
  54 #include "mmhub_v1_7.h"
  55 #include "mmhub_v1_8.h"
  56 #include "umc_v6_1.h"
  57 #include "umc_v6_0.h"
  58 #include "umc_v6_7.h"
  59 #include "umc_v12_0.h"
  60 #include "hdp_v4_0.h"
  61 #include "mca_v3_0.h"
  62
  63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  64
  65 #include "amdgpu_ras.h"
  66 #include "amdgpu_xgmi.h"
  67
  68 /* add these here since we already include dce12 headers and these are for DCN */
  69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  77
  78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2                                                          0x05ea
  79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX                                                 2
  80
  81 #define MAX_MEM_RANGES 8
  82
  83 static const char * const gfxhub_client_ids[] = {
  84         "CB",
  85         "DB",
  86         "IA",
  87         "WD",
  88         "CPF",
  89         "CPC",
  90         "CPG",
  91         "RLC",
  92         "TCP",
  93         "SQC (inst)",
  94         "SQC (data)",
  95         "SQG",
  96         "PA",
  97 };
  98
  99 static const char *mmhub_client_ids_raven[][2] = {
 100         [0][0] = "MP1",
 101         [1][0] = "MP0",
 102         [2][0] = "VCN",
 103         [3][0] = "VCNU",
 104         [4][0] = "HDP",
 105         [5][0] = "DCE",
 106         [13][0] = "UTCL2",
 107         [19][0] = "TLS",
 108         [26][0] = "OSS",
 109         [27][0] = "SDMA0",
 110         [0][1] = "MP1",
 111         [1][1] = "MP0",
 112         [2][1] = "VCN",
 113         [3][1] = "VCNU",
 114         [4][1] = "HDP",
 115         [5][1] = "XDP",
 116         [6][1] = "DBGU0",
 117         [7][1] = "DCE",
 118         [8][1] = "DCEDWB0",
 119         [9][1] = "DCEDWB1",
 120         [26][1] = "OSS",
 121         [27][1] = "SDMA0",
 122 };
 123
 124 static const char *mmhub_client_ids_renoir[][2] = {
 125         [0][0] = "MP1",
 126         [1][0] = "MP0",
 127         [2][0] = "HDP",
 128         [4][0] = "DCEDMC",
 129         [5][0] = "DCEVGA",
 130         [13][0] = "UTCL2",
 131         [19][0] = "TLS",
 132         [26][0] = "OSS",
 133         [27][0] = "SDMA0",
 134         [28][0] = "VCN",
 135         [29][0] = "VCNU",
 136         [30][0] = "JPEG",
 137         [0][1] = "MP1",
 138         [1][1] = "MP0",
 139         [2][1] = "HDP",
 140         [3][1] = "XDP",
 141         [6][1] = "DBGU0",
 142         [7][1] = "DCEDMC",
 143         [8][1] = "DCEVGA",
 144         [9][1] = "DCEDWB",
 145         [26][1] = "OSS",
 146         [27][1] = "SDMA0",
 147         [28][1] = "VCN",
 148         [29][1] = "VCNU",
 149         [30][1] = "JPEG",
 150 };
 151
 152 static const char *mmhub_client_ids_vega10[][2] = {
 153         [0][0] = "MP0",
 154         [1][0] = "UVD",
 155         [2][0] = "UVDU",
 156         [3][0] = "HDP",
 157         [13][0] = "UTCL2",
 158         [14][0] = "OSS",
 159         [15][0] = "SDMA1",
 160         [32+0][0] = "VCE0",
 161         [32+1][0] = "VCE0U",
 162         [32+2][0] = "XDMA",
 163         [32+3][0] = "DCE",
 164         [32+4][0] = "MP1",
 165         [32+14][0] = "SDMA0",
 166         [0][1] = "MP0",
 167         [1][1] = "UVD",
 168         [2][1] = "UVDU",
 169         [3][1] = "DBGU0",
 170         [4][1] = "HDP",
 171         [5][1] = "XDP",
 172         [14][1] = "OSS",
 173         [15][1] = "SDMA0",
 174         [32+0][1] = "VCE0",
 175         [32+1][1] = "VCE0U",
 176         [32+2][1] = "XDMA",
 177         [32+3][1] = "DCE",
 178         [32+4][1] = "DCEDWB",
 179         [32+5][1] = "MP1",
 180         [32+6][1] = "DBGU1",
 181         [32+14][1] = "SDMA1",
 182 };
 183
 184 static const char *mmhub_client_ids_vega12[][2] = {
 185         [0][0] = "MP0",
 186         [1][0] = "VCE0",
 187         [2][0] = "VCE0U",
 188         [3][0] = "HDP",
 189         [13][0] = "UTCL2",
 190         [14][0] = "OSS",
 191         [15][0] = "SDMA1",
 192         [32+0][0] = "DCE",
 193         [32+1][0] = "XDMA",
 194         [32+2][0] = "UVD",
 195         [32+3][0] = "UVDU",
 196         [32+4][0] = "MP1",
 197         [32+15][0] = "SDMA0",
 198         [0][1] = "MP0",
 199         [1][1] = "VCE0",
 200         [2][1] = "VCE0U",
 201         [3][1] = "DBGU0",
 202         [4][1] = "HDP",
 203         [5][1] = "XDP",
 204         [14][1] = "OSS",
 205         [15][1] = "SDMA0",
 206         [32+0][1] = "DCE",
 207         [32+1][1] = "DCEDWB",
 208         [32+2][1] = "XDMA",
 209         [32+3][1] = "UVD",
 210         [32+4][1] = "UVDU",
 211         [32+5][1] = "MP1",
 212         [32+6][1] = "DBGU1",
 213         [32+15][1] = "SDMA1",
 214 };
 215
 216 static const char *mmhub_client_ids_vega20[][2] = {
 217         [0][0] = "XDMA",
 218         [1][0] = "DCE",
 219         [2][0] = "VCE0",
 220         [3][0] = "VCE0U",
 221         [4][0] = "UVD",
 222         [5][0] = "UVD1U",
 223         [13][0] = "OSS",
 224         [14][0] = "HDP",
 225         [15][0] = "SDMA0",
 226         [32+0][0] = "UVD",
 227         [32+1][0] = "UVDU",
 228         [32+2][0] = "MP1",
 229         [32+3][0] = "MP0",
 230         [32+12][0] = "UTCL2",
 231         [32+14][0] = "SDMA1",
 232         [0][1] = "XDMA",
 233         [1][1] = "DCE",
 234         [2][1] = "DCEDWB",
 235         [3][1] = "VCE0",
 236         [4][1] = "VCE0U",
 237         [5][1] = "UVD1",
 238         [6][1] = "UVD1U",
 239         [7][1] = "DBGU0",
 240         [8][1] = "XDP",
 241         [13][1] = "OSS",
 242         [14][1] = "HDP",
 243         [15][1] = "SDMA0",
 244         [32+0][1] = "UVD",
 245         [32+1][1] = "UVDU",
 246         [32+2][1] = "DBGU1",
 247         [32+3][1] = "MP1",
 248         [32+4][1] = "MP0",
 249         [32+14][1] = "SDMA1",
 250 };
 251
 252 static const char *mmhub_client_ids_arcturus[][2] = {
 253         [0][0] = "DBGU1",
 254         [1][0] = "XDP",
 255         [2][0] = "MP1",
 256         [14][0] = "HDP",
 257         [171][0] = "JPEG",
 258         [172][0] = "VCN",
 259         [173][0] = "VCNU",
 260         [203][0] = "JPEG1",
 261         [204][0] = "VCN1",
 262         [205][0] = "VCN1U",
 263         [256][0] = "SDMA0",
 264         [257][0] = "SDMA1",
 265         [258][0] = "SDMA2",
 266         [259][0] = "SDMA3",
 267         [260][0] = "SDMA4",
 268         [261][0] = "SDMA5",
 269         [262][0] = "SDMA6",
 270         [263][0] = "SDMA7",
 271         [384][0] = "OSS",
 272         [0][1] = "DBGU1",
 273         [1][1] = "XDP",
 274         [2][1] = "MP1",
 275         [14][1] = "HDP",
 276         [171][1] = "JPEG",
 277         [172][1] = "VCN",
 278         [173][1] = "VCNU",
 279         [203][1] = "JPEG1",
 280         [204][1] = "VCN1",
 281         [205][1] = "VCN1U",
 282         [256][1] = "SDMA0",
 283         [257][1] = "SDMA1",
 284         [258][1] = "SDMA2",
 285         [259][1] = "SDMA3",
 286         [260][1] = "SDMA4",
 287         [261][1] = "SDMA5",
 288         [262][1] = "SDMA6",
 289         [263][1] = "SDMA7",
 290         [384][1] = "OSS",
 291 };
 292
 293 static const char *mmhub_client_ids_aldebaran[][2] = {
 294         [2][0] = "MP1",
 295         [3][0] = "MP0",
 296         [32+1][0] = "DBGU_IO0",
 297         [32+2][0] = "DBGU_IO2",
 298         [32+4][0] = "MPIO",
 299         [96+11][0] = "JPEG0",
 300         [96+12][0] = "VCN0",
 301         [96+13][0] = "VCNU0",
 302         [128+11][0] = "JPEG1",
 303         [128+12][0] = "VCN1",
 304         [128+13][0] = "VCNU1",
 305         [160+1][0] = "XDP",
 306         [160+14][0] = "HDP",
 307         [256+0][0] = "SDMA0",
 308         [256+1][0] = "SDMA1",
 309         [256+2][0] = "SDMA2",
 310         [256+3][0] = "SDMA3",
 311         [256+4][0] = "SDMA4",
 312         [384+0][0] = "OSS",
 313         [2][1] = "MP1",
 314         [3][1] = "MP0",
 315         [32+1][1] = "DBGU_IO0",
 316         [32+2][1] = "DBGU_IO2",
 317         [32+4][1] = "MPIO",
 318         [96+11][1] = "JPEG0",
 319         [96+12][1] = "VCN0",
 320         [96+13][1] = "VCNU0",
 321         [128+11][1] = "JPEG1",
 322         [128+12][1] = "VCN1",
 323         [128+13][1] = "VCNU1",
 324         [160+1][1] = "XDP",
 325         [160+14][1] = "HDP",
 326         [256+0][1] = "SDMA0",
 327         [256+1][1] = "SDMA1",
 328         [256+2][1] = "SDMA2",
 329         [256+3][1] = "SDMA3",
 330         [256+4][1] = "SDMA4",
 331         [384+0][1] = "OSS",
 332 };
 333
 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
 335         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 336         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 337 };
 338
 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
 340         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 341         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 342 };
 343
 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 345         (0x000143c0 + 0x00000000),
 346         (0x000143c0 + 0x00000800),
 347         (0x000143c0 + 0x00001000),
 348         (0x000143c0 + 0x00001800),
 349         (0x000543c0 + 0x00000000),
 350         (0x000543c0 + 0x00000800),
 351         (0x000543c0 + 0x00001000),
 352         (0x000543c0 + 0x00001800),
 353         (0x000943c0 + 0x00000000),
 354         (0x000943c0 + 0x00000800),
 355         (0x000943c0 + 0x00001000),
 356         (0x000943c0 + 0x00001800),
 357         (0x000d43c0 + 0x00000000),
 358         (0x000d43c0 + 0x00000800),
 359         (0x000d43c0 + 0x00001000),
 360         (0x000d43c0 + 0x00001800),
 361         (0x001143c0 + 0x00000000),
 362         (0x001143c0 + 0x00000800),
 363         (0x001143c0 + 0x00001000),
 364         (0x001143c0 + 0x00001800),
 365         (0x001543c0 + 0x00000000),
 366         (0x001543c0 + 0x00000800),
 367         (0x001543c0 + 0x00001000),
 368         (0x001543c0 + 0x00001800),
 369         (0x001943c0 + 0x00000000),
 370         (0x001943c0 + 0x00000800),
 371         (0x001943c0 + 0x00001000),
 372         (0x001943c0 + 0x00001800),
 373         (0x001d43c0 + 0x00000000),
 374         (0x001d43c0 + 0x00000800),
 375         (0x001d43c0 + 0x00001000),
 376         (0x001d43c0 + 0x00001800),
 377 };
 378
 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 380         (0x000143e0 + 0x00000000),
 381         (0x000143e0 + 0x00000800),
 382         (0x000143e0 + 0x00001000),
 383         (0x000143e0 + 0x00001800),
 384         (0x000543e0 + 0x00000000),
 385         (0x000543e0 + 0x00000800),
 386         (0x000543e0 + 0x00001000),
 387         (0x000543e0 + 0x00001800),
 388         (0x000943e0 + 0x00000000),
 389         (0x000943e0 + 0x00000800),
 390         (0x000943e0 + 0x00001000),
 391         (0x000943e0 + 0x00001800),
 392         (0x000d43e0 + 0x00000000),
 393         (0x000d43e0 + 0x00000800),
 394         (0x000d43e0 + 0x00001000),
 395         (0x000d43e0 + 0x00001800),
 396         (0x001143e0 + 0x00000000),
 397         (0x001143e0 + 0x00000800),
 398         (0x001143e0 + 0x00001000),
 399         (0x001143e0 + 0x00001800),
 400         (0x001543e0 + 0x00000000),
 401         (0x001543e0 + 0x00000800),
 402         (0x001543e0 + 0x00001000),
 403         (0x001543e0 + 0x00001800),
 404         (0x001943e0 + 0x00000000),
 405         (0x001943e0 + 0x00000800),
 406         (0x001943e0 + 0x00001000),
 407         (0x001943e0 + 0x00001800),
 408         (0x001d43e0 + 0x00000000),
 409         (0x001d43e0 + 0x00000800),
 410         (0x001d43e0 + 0x00001000),
 411         (0x001d43e0 + 0x00001800),
 412 };
 413
 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 415                 struct amdgpu_irq_src *src,
 416                 unsigned int type,
 417                 enum amdgpu_interrupt_state state)
 418 {
 419         u32 bits, i, tmp, reg;
 420
 421         /* Devices newer then VEGA10/12 shall have these programming
 422          * sequences performed by PSP BL
 423          */
 424         if (adev->asic_type >= CHIP_VEGA20)
 425                 return 0;
 426
 427         bits = 0x7f;
 428
 429         switch (state) {
 430         case AMDGPU_IRQ_STATE_DISABLE:
 431                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 432                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 433                         tmp = RREG32(reg);
 434                         tmp &= ~bits;
 435                         WREG32(reg, tmp);
 436                 }
 437                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 438                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 439                         tmp = RREG32(reg);
 440                         tmp &= ~bits;
 441                         WREG32(reg, tmp);
 442                 }
 443                 break;
 444         case AMDGPU_IRQ_STATE_ENABLE:
 445                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 446                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 447                         tmp = RREG32(reg);
 448                         tmp |= bits;
 449                         WREG32(reg, tmp);
 450                 }
 451                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 452                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 453                         tmp = RREG32(reg);
 454                         tmp |= bits;
 455                         WREG32(reg, tmp);
 456                 }
 457                 break;
 458         default:
 459                 break;
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 466                                         struct amdgpu_irq_src *src,
 467                                         unsigned int type,
 468                                         enum amdgpu_interrupt_state state)
 469 {
 470         struct amdgpu_vmhub *hub;
 471         u32 tmp, reg, bits, i, j;
 472
 473         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 474                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 475                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 476                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 477                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 478                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 479                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 480
 481         switch (state) {
 482         case AMDGPU_IRQ_STATE_DISABLE:
 483                 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
 484                         hub = &adev->vmhub[j];
 485                         for (i = 0; i < 16; i++) {
 486                                 reg = hub->vm_context0_cntl + i;
 487
 488                                 /* This works because this interrupt is only
 489                                  * enabled at init/resume and disabled in
 490                                  * fini/suspend, so the overall state doesn't
 491                                  * change over the course of suspend/resume.
 492                                  */
 493                                 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
 494                                         continue;
 495
 496                                 if (j >= AMDGPU_MMHUB0(0))
 497                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 498                                 else
 499                                         tmp = RREG32_XCC(reg, j);
 500
 501                                 tmp &= ~bits;
 502
 503                                 if (j >= AMDGPU_MMHUB0(0))
 504                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 505                                 else
 506                                         WREG32_XCC(reg, tmp, j);
 507                         }
 508                 }
 509                 break;
 510         case AMDGPU_IRQ_STATE_ENABLE:
 511                 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
 512                         hub = &adev->vmhub[j];
 513                         for (i = 0; i < 16; i++) {
 514                                 reg = hub->vm_context0_cntl + i;
 515
 516                                 /* This works because this interrupt is only
 517                                  * enabled at init/resume and disabled in
 518                                  * fini/suspend, so the overall state doesn't
 519                                  * change over the course of suspend/resume.
 520                                  */
 521                                 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
 522                                         continue;
 523
 524                                 if (j >= AMDGPU_MMHUB0(0))
 525                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 526                                 else
 527                                         tmp = RREG32_XCC(reg, j);
 528
 529                                 tmp |= bits;
 530
 531                                 if (j >= AMDGPU_MMHUB0(0))
 532                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 533                                 else
 534                                         WREG32_XCC(reg, tmp, j);
 535                         }
 536                 }
 537                 break;
 538         default:
 539                 break;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 546                                       struct amdgpu_irq_src *source,
 547                                       struct amdgpu_iv_entry *entry)
 548 {
 549         bool retry_fault = !!(entry->src_data[1] & 0x80);
 550         bool write_fault = !!(entry->src_data[1] & 0x20);
 551         uint32_t status = 0, cid = 0, rw = 0, fed = 0;
 552         struct amdgpu_task_info *task_info;
 553         struct amdgpu_vmhub *hub;
 554         const char *mmhub_cid;
 555         const char *hub_name;
 556         unsigned int vmhub;
 557         u64 addr;
 558         uint32_t cam_index = 0;
 559         int ret, xcc_id = 0;
 560         uint32_t node_id;
 561
 562         node_id = entry->node_id;
 563
 564         addr = (u64)entry->src_data[0] << 12;
 565         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 566
 567         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 568                 hub_name = "mmhub0";
 569                 vmhub = AMDGPU_MMHUB0(node_id / 4);
 570         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 571                 hub_name = "mmhub1";
 572                 vmhub = AMDGPU_MMHUB1(0);
 573         } else {
 574                 hub_name = "gfxhub0";
 575                 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
 576                         xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
 577                                 node_id);
 578                         if (xcc_id < 0)
 579                                 xcc_id = 0;
 580                 }
 581                 vmhub = xcc_id;
 582         }
 583         hub = &adev->vmhub[vmhub];
 584
 585         if (retry_fault) {
 586                 if (adev->irq.retry_cam_enabled) {
 587                         /* Delegate it to a different ring if the hardware hasn't
 588                          * already done it.
 589                          */
 590                         if (entry->ih == &adev->irq.ih) {
 591                                 amdgpu_irq_delegate(adev, entry, 8);
 592                                 return 1;
 593                         }
 594
 595                         cam_index = entry->src_data[2] & 0x3ff;
 596
 597                         ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
 598                                                      addr, entry->timestamp, write_fault);
 599                         WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
 600                         if (ret)
 601                                 return 1;
 602                 } else {
 603                         /* Process it onyl if it's the first fault for this address */
 604                         if (entry->ih != &adev->irq.ih_soft &&
 605                             amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
 606                                              entry->timestamp))
 607                                 return 1;
 608
 609                         /* Delegate it to a different ring if the hardware hasn't
 610                          * already done it.
 611                          */
 612                         if (entry->ih == &adev->irq.ih) {
 613                                 amdgpu_irq_delegate(adev, entry, 8);
 614                                 return 1;
 615                         }
 616
 617                         /* Try to handle the recoverable page faults by filling page
 618                          * tables
 619                          */
 620                         if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
 621                                                    addr, entry->timestamp, write_fault))
 622                                 return 1;
 623                 }
 624         }
 625
 626         if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault))
 627                 return 1;
 628
 629         if (!printk_ratelimit())
 630                 return 0;
 631
 632         dev_err(adev->dev,
 633                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name,
 634                 retry_fault ? "retry" : "no-retry",
 635                 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
 636
 637         task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
 638         if (task_info) {
 639                 dev_err(adev->dev,
 640                         " for process %s pid %d thread %s pid %d)\n",
 641                         task_info->process_name, task_info->tgid,
 642                         task_info->task_name, task_info->pid);
 643                 amdgpu_vm_put_task_info(task_info);
 644         }
 645
 646         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 647                 addr, entry->client_id,
 648                 soc15_ih_clientid_name[entry->client_id]);
 649
 650         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
 651             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
 652             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
 653                 dev_err(adev->dev, "  cookie node_id %d fault from die %s%d%s\n",
 654                         node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,
 655                         node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");
 656
 657         if (amdgpu_sriov_vf(adev))
 658                 return 0;
 659
 660         /*
 661          * Issue a dummy read to wait for the status register to
 662          * be updated to avoid reading an incorrect value due to
 663          * the new fast GRBM interface.
 664          */
 665         if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
 666             (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
 667                 RREG32(hub->vm_l2_pro_fault_status);
 668
 669         status = RREG32(hub->vm_l2_pro_fault_status);
 670         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 671         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 672         fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
 673
 674         /* for fed error, kfd will handle it, return directly */
 675         if (fed && amdgpu_ras_is_poison_mode_supported(adev) &&
 676             (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2)))
 677                 return 0;
 678
 679         /* Only print L2 fault status if the status register could be read and
 680          * contains useful information
 681          */
 682         if (!status)
 683                 return 0;
 684
 685         if (!amdgpu_sriov_vf(adev))
 686                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 687
 688         amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
 689
 690         dev_err(adev->dev,
 691                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 692                 status);
 693         if (entry->vmid_src == AMDGPU_GFXHUB(0)) {
 694                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 695                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 696                         gfxhub_client_ids[cid],
 697                         cid);
 698         } else {
 699                 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
 700                 case IP_VERSION(9, 0, 0):
 701                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 702                         break;
 703                 case IP_VERSION(9, 3, 0):
 704                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 705                         break;
 706                 case IP_VERSION(9, 4, 0):
 707                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 708                         break;
 709                 case IP_VERSION(9, 4, 1):
 710                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 711                         break;
 712                 case IP_VERSION(9, 1, 0):
 713                 case IP_VERSION(9, 2, 0):
 714                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 715                         break;
 716                 case IP_VERSION(1, 5, 0):
 717                 case IP_VERSION(2, 4, 0):
 718                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 719                         break;
 720                 case IP_VERSION(1, 8, 0):
 721                 case IP_VERSION(9, 4, 2):
 722                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 723                         break;
 724                 default:
 725                         mmhub_cid = NULL;
 726                         break;
 727                 }
 728                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 729                         mmhub_cid ? mmhub_cid : "unknown", cid);
 730         }
 731         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 732                 REG_GET_FIELD(status,
 733                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 734         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 735                 REG_GET_FIELD(status,
 736                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 737         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 738                 REG_GET_FIELD(status,
 739                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 740         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 741                 REG_GET_FIELD(status,
 742                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 743         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 744         return 0;
 745 }
 746
 747 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 748         .set = gmc_v9_0_vm_fault_interrupt_state,
 749         .process = gmc_v9_0_process_interrupt,
 750 };
 751
 752
 753 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 754         .set = gmc_v9_0_ecc_interrupt_state,
 755         .process = amdgpu_umc_process_ecc_irq,
 756 };
 757
 758 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 759 {
 760         adev->gmc.vm_fault.num_types = 1;
 761         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 762
 763         if (!amdgpu_sriov_vf(adev) &&
 764             !adev->gmc.xgmi.connected_to_cpu &&
 765             !adev->gmc.is_app_apu) {
 766                 adev->gmc.ecc_irq.num_types = 1;
 767                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 768         }
 769 }
 770
 771 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 772                                         uint32_t flush_type)
 773 {
 774         u32 req = 0;
 775
 776         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 777                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 778         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 779         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 780         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 781         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 782         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 783         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 784         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 785                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 786
 787         return req;
 788 }
 789
 790 /**
 791  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 792  *
 793  * @adev: amdgpu_device pointer
 794  * @vmhub: vmhub type
 795  *
 796  */
 797 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 798                                        uint32_t vmhub)
 799 {
 800         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
 801             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
 802             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
 803             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
 804                 return false;
 805
 806         return ((vmhub == AMDGPU_MMHUB0(0) ||
 807                  vmhub == AMDGPU_MMHUB1(0)) &&
 808                 (!amdgpu_sriov_vf(adev)) &&
 809                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 810                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 811 }
 812
 813 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 814                                         uint8_t vmid, uint16_t *p_pasid)
 815 {
 816         uint32_t value;
 817
 818         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 819                      + vmid);
 820         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 821
 822         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 823 }
 824
 825 /*
 826  * GART
 827  * VMID 0 is the physical GPU addresses as used by the kernel.
 828  * VMIDs 1-15 are used for userspace clients and are handled
 829  * by the amdgpu vm/hsa code.
 830  */
 831
 832 /**
 833  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 834  *
 835  * @adev: amdgpu_device pointer
 836  * @vmid: vm instance to flush
 837  * @vmhub: which hub to flush
 838  * @flush_type: the flush type
 839  *
 840  * Flush the TLB for the requested page table using certain type.
 841  */
 842 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 843                                         uint32_t vmhub, uint32_t flush_type)
 844 {
 845         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 846         u32 j, inv_req, tmp, sem, req, ack, inst;
 847         const unsigned int eng = 17;
 848         struct amdgpu_vmhub *hub;
 849
 850         BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
 851
 852         hub = &adev->vmhub[vmhub];
 853         inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 854         sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
 855         req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 856         ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 857
 858         if (vmhub >= AMDGPU_MMHUB0(0))
 859                 inst = 0;
 860         else
 861                 inst = vmhub;
 862
 863         /* This is necessary for SRIOV as well as for GFXOFF to function
 864          * properly under bare metal
 865          */
 866         if (adev->gfx.kiq[inst].ring.sched.ready &&
 867             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 868                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 869                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 870
 871                 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
 872                                                  1 << vmid, inst);
 873                 return;
 874         }
 875
 876         /* This path is needed before KIQ/MES/GFXOFF are set up */
 877         spin_lock(&adev->gmc.invalidate_lock);
 878
 879         /*
 880          * It may lose gpuvm invalidate acknowldege state across power-gating
 881          * off cycle, add semaphore acquire before invalidation and semaphore
 882          * release after invalidation to avoid entering power gated state
 883          * to WA the Issue
 884          */
 885
 886         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 887         if (use_semaphore) {
 888                 for (j = 0; j < adev->usec_timeout; j++) {
 889                         /* a read return value of 1 means semaphore acquire */
 890                         if (vmhub >= AMDGPU_MMHUB0(0))
 891                                 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));
 892                         else
 893                                 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));
 894                         if (tmp & 0x1)
 895                                 break;
 896                         udelay(1);
 897                 }
 898
 899                 if (j >= adev->usec_timeout)
 900                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 901         }
 902
 903         if (vmhub >= AMDGPU_MMHUB0(0))
 904                 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));
 905         else
 906                 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));
 907
 908         /*
 909          * Issue a dummy read to wait for the ACK register to
 910          * be cleared to avoid a false ACK due to the new fast
 911          * GRBM interface.
 912          */
 913         if ((vmhub == AMDGPU_GFXHUB(0)) &&
 914             (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
 915                 RREG32_NO_KIQ(req);
 916
 917         for (j = 0; j < adev->usec_timeout; j++) {
 918                 if (vmhub >= AMDGPU_MMHUB0(0))
 919                         tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));
 920                 else
 921                         tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));
 922                 if (tmp & (1 << vmid))
 923                         break;
 924                 udelay(1);
 925         }
 926
 927         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 928         if (use_semaphore) {
 929                 /*
 930                  * add semaphore release after invalidation,
 931                  * write with 0 means semaphore release
 932                  */
 933                 if (vmhub >= AMDGPU_MMHUB0(0))
 934                         WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));
 935                 else
 936                         WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));
 937         }
 938
 939         spin_unlock(&adev->gmc.invalidate_lock);
 940
 941         if (j < adev->usec_timeout)
 942                 return;
 943
 944         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 945 }
 946
 947 /**
 948  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 949  *
 950  * @adev: amdgpu_device pointer
 951  * @pasid: pasid to be flush
 952  * @flush_type: the flush type
 953  * @all_hub: flush all hubs
 954  * @inst: is used to select which instance of KIQ to use for the invalidation
 955  *
 956  * Flush the TLB for the requested pasid.
 957  */
 958 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 959                                          uint16_t pasid, uint32_t flush_type,
 960                                          bool all_hub, uint32_t inst)
 961 {
 962         uint16_t queried;
 963         int i, vmid;
 964
 965         for (vmid = 1; vmid < 16; vmid++) {
 966                 bool valid;
 967
 968                 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 969                                                                  &queried);
 970                 if (!valid || queried != pasid)
 971                         continue;
 972
 973                 if (all_hub) {
 974                         for_each_set_bit(i, adev->vmhubs_mask,
 975                                          AMDGPU_MAX_VMHUBS)
 976                                 gmc_v9_0_flush_gpu_tlb(adev, vmid, i,
 977                                                        flush_type);
 978                 } else {
 979                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 980                                                AMDGPU_GFXHUB(0),
 981                                                flush_type);
 982                 }
 983         }
 984 }
 985
 986 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 987                                             unsigned int vmid, uint64_t pd_addr)
 988 {
 989         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
 990         struct amdgpu_device *adev = ring->adev;
 991         struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
 992         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 993         unsigned int eng = ring->vm_inv_eng;
 994
 995         /*
 996          * It may lose gpuvm invalidate acknowldege state across power-gating
 997          * off cycle, add semaphore acquire before invalidation and semaphore
 998          * release after invalidation to avoid entering power gated state
 999          * to WA the Issue
1000          */
1001
1002         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1003         if (use_semaphore)
1004                 /* a read return value of 1 means semaphore acuqire */
1005                 amdgpu_ring_emit_reg_wait(ring,
1006                                           hub->vm_inv_eng0_sem +
1007                                           hub->eng_distance * eng, 0x1, 0x1);
1008
1009         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1010                               (hub->ctx_addr_distance * vmid),
1011                               lower_32_bits(pd_addr));
1012
1013         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1014                               (hub->ctx_addr_distance * vmid),
1015                               upper_32_bits(pd_addr));
1016
1017         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
1018                                             hub->eng_distance * eng,
1019                                             hub->vm_inv_eng0_ack +
1020                                             hub->eng_distance * eng,
1021                                             req, 1 << vmid);
1022
1023         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1024         if (use_semaphore)
1025                 /*
1026                  * add semaphore release after invalidation,
1027                  * write with 0 means semaphore release
1028                  */
1029                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1030                                       hub->eng_distance * eng, 0);
1031
1032         return pd_addr;
1033 }
1034
1035 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
1036                                         unsigned int pasid)
1037 {
1038         struct amdgpu_device *adev = ring->adev;
1039         uint32_t reg;
1040
1041         /* Do nothing because there's no lut register for mmhub1. */
1042         if (ring->vm_hub == AMDGPU_MMHUB1(0))
1043                 return;
1044
1045         if (ring->vm_hub == AMDGPU_GFXHUB(0))
1046                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1047         else
1048                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1049
1050         amdgpu_ring_emit_wreg(ring, reg, pasid);
1051 }
1052
1053 /*
1054  * PTE format on VEGA 10:
1055  * 63:59 reserved
1056  * 58:57 mtype
1057  * 56 F
1058  * 55 L
1059  * 54 P
1060  * 53 SW
1061  * 52 T
1062  * 50:48 reserved
1063  * 47:12 4k physical page base address
1064  * 11:7 fragment
1065  * 6 write
1066  * 5 read
1067  * 4 exe
1068  * 3 Z
1069  * 2 snooped
1070  * 1 system
1071  * 0 valid
1072  *
1073  * PDE format on VEGA 10:
1074  * 63:59 block fragment size
1075  * 58:55 reserved
1076  * 54 P
1077  * 53:48 reserved
1078  * 47:6 physical base address of PD or PTE
1079  * 5:3 reserved
1080  * 2 C
1081  * 1 system
1082  * 0 valid
1083  */
1084
1085 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1086
1087 {
1088         switch (flags) {
1089         case AMDGPU_VM_MTYPE_DEFAULT:
1090                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1091         case AMDGPU_VM_MTYPE_NC:
1092                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1093         case AMDGPU_VM_MTYPE_WC:
1094                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC);
1095         case AMDGPU_VM_MTYPE_RW:
1096                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW);
1097         case AMDGPU_VM_MTYPE_CC:
1098                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC);
1099         case AMDGPU_VM_MTYPE_UC:
1100                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC);
1101         default:
1102                 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1103         }
1104 }
1105
1106 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1107                                 uint64_t *addr, uint64_t *flags)
1108 {
1109         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1110                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1111         BUG_ON(*addr & 0xFFFF00000000003FULL);
1112
1113         if (!adev->gmc.translate_further)
1114                 return;
1115
1116         if (level == AMDGPU_VM_PDB1) {
1117                 /* Set the block fragment size */
1118                 if (!(*flags & AMDGPU_PDE_PTE))
1119                         *flags |= AMDGPU_PDE_BFS(0x9);
1120
1121         } else if (level == AMDGPU_VM_PDB0) {
1122                 if (*flags & AMDGPU_PDE_PTE) {
1123                         *flags &= ~AMDGPU_PDE_PTE;
1124                         if (!(*flags & AMDGPU_PTE_VALID))
1125                                 *addr |= 1 << PAGE_SHIFT;
1126                 } else {
1127                         *flags |= AMDGPU_PTE_TF;
1128                 }
1129         }
1130 }
1131
1132 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1133                                          struct amdgpu_bo *bo,
1134                                          struct amdgpu_bo_va_mapping *mapping,
1135                                          uint64_t *flags)
1136 {
1137         struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1138         bool is_vram = bo->tbo.resource &&
1139                 bo->tbo.resource->mem_type == TTM_PL_VRAM;
1140         bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
1141                                      AMDGPU_GEM_CREATE_EXT_COHERENT);
1142         bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1143         bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1144         struct amdgpu_vm *vm = mapping->bo_va->base.vm;
1145         unsigned int mtype_local, mtype;
1146         uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0);
1147         bool snoop = false;
1148         bool is_local;
1149
1150         dma_resv_assert_held(bo->tbo.base.resv);
1151
1152         switch (gc_ip_version) {
1153         case IP_VERSION(9, 4, 1):
1154         case IP_VERSION(9, 4, 2):
1155                 if (is_vram) {
1156                         if (bo_adev == adev) {
1157                                 if (uncached)
1158                                         mtype = MTYPE_UC;
1159                                 else if (coherent)
1160                                         mtype = MTYPE_CC;
1161                                 else
1162                                         mtype = MTYPE_RW;
1163                                 /* FIXME: is this still needed? Or does
1164                                  * amdgpu_ttm_tt_pde_flags already handle this?
1165                                  */
1166                                 if (gc_ip_version == IP_VERSION(9, 4, 2) &&
1167                                     adev->gmc.xgmi.connected_to_cpu)
1168                                         snoop = true;
1169                         } else {
1170                                 if (uncached || coherent)
1171                                         mtype = MTYPE_UC;
1172                                 else
1173                                         mtype = MTYPE_NC;
1174                                 if (mapping->bo_va->is_xgmi)
1175                                         snoop = true;
1176                         }
1177                 } else {
1178                         if (uncached || coherent)
1179                                 mtype = MTYPE_UC;
1180                         else
1181                                 mtype = MTYPE_NC;
1182                         /* FIXME: is this still needed? Or does
1183                          * amdgpu_ttm_tt_pde_flags already handle this?
1184                          */
1185                         snoop = true;
1186                 }
1187                 break;
1188         case IP_VERSION(9, 4, 3):
1189         case IP_VERSION(9, 4, 4):
1190         case IP_VERSION(9, 5, 0):
1191                 /* Only local VRAM BOs or system memory on non-NUMA APUs
1192                  * can be assumed to be local in their entirety. Choose
1193                  * MTYPE_NC as safe fallback for all system memory BOs on
1194                  * NUMA systems. Their MTYPE can be overridden per-page in
1195                  * gmc_v9_0_override_vm_pte_flags.
1196                  */
1197                 mtype_local = MTYPE_RW;
1198                 if (amdgpu_mtype_local == 1) {
1199                         DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
1200                         mtype_local = MTYPE_NC;
1201                 } else if (amdgpu_mtype_local == 2) {
1202                         DRM_INFO_ONCE("Using MTYPE_CC for local memory\n");
1203                         mtype_local = MTYPE_CC;
1204                 } else {
1205                         DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
1206                 }
1207                 is_local = (!is_vram && (adev->flags & AMD_IS_APU) &&
1208                             num_possible_nodes() <= 1) ||
1209                            (is_vram && adev == bo_adev &&
1210                             KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id);
1211                 snoop = true;
1212                 if (uncached) {
1213                         mtype = MTYPE_UC;
1214                 } else if (ext_coherent) {
1215                         if (gc_ip_version == IP_VERSION(9, 5, 0) || adev->rev_id)
1216                                 mtype = is_local ? MTYPE_CC : MTYPE_UC;
1217                         else
1218                                 mtype = MTYPE_UC;
1219                 } else if (adev->flags & AMD_IS_APU) {
1220                         mtype = is_local ? mtype_local : MTYPE_NC;
1221                 } else {
1222                         /* dGPU */
1223                         if (is_local)
1224                                 mtype = mtype_local;
1225                         else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram)
1226                                 mtype = MTYPE_UC;
1227                         else
1228                                 mtype = MTYPE_NC;
1229                 }
1230
1231                 break;
1232         default:
1233                 if (uncached || coherent)
1234                         mtype = MTYPE_UC;
1235                 else
1236                         mtype = MTYPE_NC;
1237
1238                 /* FIXME: is this still needed? Or does
1239                  * amdgpu_ttm_tt_pde_flags already handle this?
1240                  */
1241                 if (!is_vram)
1242                         snoop = true;
1243         }
1244
1245         if (mtype != MTYPE_NC)
1246                 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype);
1247
1248         *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1249 }
1250
1251 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1252                                 struct amdgpu_bo_va_mapping *mapping,
1253                                 uint64_t *flags)
1254 {
1255         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
1256
1257         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1258         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1259
1260         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1261         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1262
1263         if (mapping->flags & AMDGPU_PTE_PRT) {
1264                 *flags |= AMDGPU_PTE_PRT;
1265                 *flags &= ~AMDGPU_PTE_VALID;
1266         }
1267
1268         if ((*flags & AMDGPU_PTE_VALID) && bo)
1269                 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags);
1270 }
1271
1272 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
1273                                            struct amdgpu_vm *vm,
1274                                            uint64_t addr, uint64_t *flags)
1275 {
1276         int local_node, nid;
1277
1278         /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system
1279          * memory can use more efficient MTYPEs.
1280          */
1281         if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) &&
1282             amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) &&
1283             amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 5, 0))
1284                 return;
1285
1286         /* Only direct-mapped memory allows us to determine the NUMA node from
1287          * the DMA address.
1288          */
1289         if (!adev->ram_is_direct_mapped) {
1290                 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n");
1291                 return;
1292         }
1293
1294         /* MTYPE_NC is the same default and can be overridden.
1295          * MTYPE_UC will be present if the memory is extended-coherent
1296          * and can also be overridden.
1297          */
1298         if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1299             AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) &&
1300             (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1301             AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) {
1302                 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n");
1303                 return;
1304         }
1305
1306         /* FIXME: Only supported on native mode for now. For carve-out, the
1307          * NUMA affinity of the GPU/VM needs to come from the PCI info because
1308          * memory partitions are not associated with different NUMA nodes.
1309          */
1310         if (adev->gmc.is_app_apu && vm->mem_id >= 0) {
1311                 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node;
1312         } else {
1313                 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n");
1314                 return;
1315         }
1316
1317         /* Only handle real RAM. Mappings of PCIe resources don't have struct
1318          * page or NUMA nodes.
1319          */
1320         if (!page_is_ram(addr >> PAGE_SHIFT)) {
1321                 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n");
1322                 return;
1323         }
1324         nid = pfn_to_nid(addr >> PAGE_SHIFT);
1325         dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n",
1326                             vm->mem_id, local_node, nid);
1327         if (nid == local_node) {
1328                 uint64_t old_flags = *flags;
1329                 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) ==
1330                         AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) {
1331                         unsigned int mtype_local = MTYPE_RW;
1332
1333                         if (amdgpu_mtype_local == 1)
1334                                 mtype_local = MTYPE_NC;
1335                         else if (amdgpu_mtype_local == 2)
1336                                 mtype_local = MTYPE_CC;
1337
1338                         *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local);
1339                 } else if (adev->rev_id) {
1340                         /* MTYPE_UC case */
1341                         *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);
1342                 }
1343
1344                 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n",
1345                                     old_flags, *flags);
1346         }
1347 }
1348
1349 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1350 {
1351         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1352         unsigned int size;
1353
1354         /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1355
1356         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1357                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1358         } else {
1359                 u32 viewport;
1360
1361                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1362                 case IP_VERSION(1, 0, 0):
1363                 case IP_VERSION(1, 0, 1):
1364                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1365                         size = (REG_GET_FIELD(viewport,
1366                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1367                                 REG_GET_FIELD(viewport,
1368                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1369                                 4);
1370                         break;
1371                 case IP_VERSION(2, 1, 0):
1372                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1373                         size = (REG_GET_FIELD(viewport,
1374                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1375                                 REG_GET_FIELD(viewport,
1376                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1377                                 4);
1378                         break;
1379                 default:
1380                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1381                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1382                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1383                                 4);
1384                         break;
1385                 }
1386         }
1387
1388         return size;
1389 }
1390
1391 static enum amdgpu_memory_partition
1392 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)
1393 {
1394         enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
1395
1396         if (adev->nbio.funcs->get_memory_partition_mode)
1397                 mode = adev->nbio.funcs->get_memory_partition_mode(adev,
1398                                                                    supp_modes);
1399
1400         return mode;
1401 }
1402
1403 static enum amdgpu_memory_partition
1404 gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev)
1405 {
1406         switch (adev->gmc.num_mem_partitions) {
1407         case 0:
1408                 return UNKNOWN_MEMORY_PARTITION_MODE;
1409         case 1:
1410                 return AMDGPU_NPS1_PARTITION_MODE;
1411         case 2:
1412                 return AMDGPU_NPS2_PARTITION_MODE;
1413         case 4:
1414                 return AMDGPU_NPS4_PARTITION_MODE;
1415         default:
1416                 return AMDGPU_NPS1_PARTITION_MODE;
1417         }
1418
1419         return AMDGPU_NPS1_PARTITION_MODE;
1420 }
1421
1422 static enum amdgpu_memory_partition
1423 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
1424 {
1425         if (amdgpu_sriov_vf(adev))
1426                 return gmc_v9_0_query_vf_memory_partition(adev);
1427
1428         return gmc_v9_0_get_memory_partition(adev, NULL);
1429 }
1430
1431 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev)
1432 {
1433         if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested &&
1434             adev->nbio.funcs->is_nps_switch_requested(adev)) {
1435                 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS;
1436                 return true;
1437         }
1438
1439         return false;
1440 }
1441
1442 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1443         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1444         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1445         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1446         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1447         .map_mtype = gmc_v9_0_map_mtype,
1448         .get_vm_pde = gmc_v9_0_get_vm_pde,
1449         .get_vm_pte = gmc_v9_0_get_vm_pte,
1450         .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,
1451         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1452         .query_mem_partition_mode = &gmc_v9_0_query_memory_partition,
1453         .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition,
1454         .need_reset_on_init = &gmc_v9_0_need_reset_on_init,
1455 };
1456
1457 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1458 {
1459         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1460 }
1461
1462 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1463 {
1464         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1465         case IP_VERSION(6, 0, 0):
1466                 adev->umc.funcs = &umc_v6_0_funcs;
1467                 break;
1468         case IP_VERSION(6, 1, 1):
1469                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1470                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1471                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1472                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1473                 adev->umc.retire_unit = 1;
1474                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1475                 adev->umc.ras = &umc_v6_1_ras;
1476                 break;
1477         case IP_VERSION(6, 1, 2):
1478                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1479                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1480                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1481                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1482                 adev->umc.retire_unit = 1;
1483                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1484                 adev->umc.ras = &umc_v6_1_ras;
1485                 break;
1486         case IP_VERSION(6, 7, 0):
1487                 adev->umc.max_ras_err_cnt_per_query =
1488                         UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1489                 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1490                 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1491                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1492                 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1493                 if (!adev->gmc.xgmi.connected_to_cpu)
1494                         adev->umc.ras = &umc_v6_7_ras;
1495                 if (1 & adev->smuio.funcs->get_die_id(adev))
1496                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1497                 else
1498                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1499                 break;
1500         case IP_VERSION(12, 0, 0):
1501                 adev->umc.max_ras_err_cnt_per_query =
1502                         UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1503                 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
1504                 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
1505                 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
1506                 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
1507                 adev->umc.active_mask = adev->aid_mask;
1508                 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1509                 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1510                         adev->umc.ras = &umc_v12_0_ras;
1511                 break;
1512         default:
1513                 break;
1514         }
1515 }
1516
1517 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1518 {
1519         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1520         case IP_VERSION(9, 4, 1):
1521                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1522                 break;
1523         case IP_VERSION(9, 4, 2):
1524                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1525                 break;
1526         case IP_VERSION(1, 8, 0):
1527                 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1528                 break;
1529         default:
1530                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1531                 break;
1532         }
1533 }
1534
1535 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1536 {
1537         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1538         case IP_VERSION(9, 4, 0):
1539                 adev->mmhub.ras = &mmhub_v1_0_ras;
1540                 break;
1541         case IP_VERSION(9, 4, 1):
1542                 adev->mmhub.ras = &mmhub_v9_4_ras;
1543                 break;
1544         case IP_VERSION(9, 4, 2):
1545                 adev->mmhub.ras = &mmhub_v1_7_ras;
1546                 break;
1547         case IP_VERSION(1, 8, 0):
1548         case IP_VERSION(1, 8, 1):
1549                 adev->mmhub.ras = &mmhub_v1_8_ras;
1550                 break;
1551         default:
1552                 /* mmhub ras is not available */
1553                 break;
1554         }
1555 }
1556
1557 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1558 {
1559         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1560             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
1561             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
1562                 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1563         else
1564                 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1565 }
1566
1567 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1568 {
1569         adev->hdp.ras = &hdp_v4_0_ras;
1570 }
1571
1572 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1573 {
1574         struct amdgpu_mca *mca = &adev->mca;
1575
1576         /* is UMC the right IP to check for MCA?  Maybe DF? */
1577         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1578         case IP_VERSION(6, 7, 0):
1579                 if (!adev->gmc.xgmi.connected_to_cpu) {
1580                         mca->mp0.ras = &mca_v3_0_mp0_ras;
1581                         mca->mp1.ras = &mca_v3_0_mp1_ras;
1582                         mca->mpio.ras = &mca_v3_0_mpio_ras;
1583                 }
1584                 break;
1585         default:
1586                 break;
1587         }
1588 }
1589
1590 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1591 {
1592         if (!adev->gmc.xgmi.connected_to_cpu)
1593                 adev->gmc.xgmi.ras = &xgmi_ras;
1594 }
1595
1596 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev)
1597 {
1598         adev->gmc.supported_nps_modes = 0;
1599
1600         if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
1601                 return;
1602
1603         /*TODO: Check PSP version also which supports NPS switch. Otherwise keep
1604          * supported modes as 0.
1605          */
1606         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1607         case IP_VERSION(9, 4, 3):
1608         case IP_VERSION(9, 4, 4):
1609                 adev->gmc.supported_nps_modes =
1610                         BIT(AMDGPU_NPS1_PARTITION_MODE) |
1611                         BIT(AMDGPU_NPS4_PARTITION_MODE);
1612                 break;
1613         default:
1614                 break;
1615         }
1616 }
1617
1618 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block)
1619 {
1620         struct amdgpu_device *adev = ip_block->adev;
1621
1622         /*
1623          * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
1624          * in their IP discovery tables
1625          */
1626         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||
1627             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
1628             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1629             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
1630             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
1631                 adev->gmc.xgmi.supported = true;
1632
1633         if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {
1634                 adev->gmc.xgmi.supported = true;
1635                 adev->gmc.xgmi.connected_to_cpu =
1636                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1637         }
1638
1639         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1640             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) {
1641                 enum amdgpu_pkg_type pkg_type =
1642                         adev->smuio.funcs->get_pkg_type(adev);
1643                 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present
1644                  * and the APU, can be in used two possible modes:
1645                  *  - carveout mode
1646                  *  - native APU mode
1647                  * "is_app_apu" can be used to identify the APU in the native
1648                  * mode.
1649                  */
1650                 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU &&
1651                                         !pci_resource_len(adev->pdev, 0));
1652         }
1653
1654         gmc_v9_0_set_gmc_funcs(adev);
1655         gmc_v9_0_set_irq_funcs(adev);
1656         gmc_v9_0_set_umc_funcs(adev);
1657         gmc_v9_0_set_mmhub_funcs(adev);
1658         gmc_v9_0_set_mmhub_ras_funcs(adev);
1659         gmc_v9_0_set_gfxhub_funcs(adev);
1660         gmc_v9_0_set_hdp_ras_funcs(adev);
1661         gmc_v9_0_set_mca_ras_funcs(adev);
1662         gmc_v9_0_set_xgmi_ras_funcs(adev);
1663
1664         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1665         adev->gmc.shared_aperture_end =
1666                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1667         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1668         adev->gmc.private_aperture_end =
1669                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1670         adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1671
1672         return 0;
1673 }
1674
1675 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block)
1676 {
1677         struct amdgpu_device *adev = ip_block->adev;
1678         int r;
1679
1680         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1681         if (r)
1682                 return r;
1683
1684         /*
1685          * Workaround performance drop issue with VBIOS enables partial
1686          * writes, while disables HBM ECC for vega10.
1687          */
1688         if (!amdgpu_sriov_vf(adev) &&
1689             (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {
1690                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1691                         if (adev->df.funcs &&
1692                             adev->df.funcs->enable_ecc_force_par_wr_rmw)
1693                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1694                 }
1695         }
1696
1697         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1698                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
1699                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
1700         }
1701
1702         r = amdgpu_gmc_ras_late_init(adev);
1703         if (r)
1704                 return r;
1705
1706         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1707 }
1708
1709 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1710                                         struct amdgpu_gmc *mc)
1711 {
1712         u64 base = adev->mmhub.funcs->get_fb_location(adev);
1713
1714         amdgpu_gmc_set_agp_default(adev, mc);
1715
1716         /* add the xgmi offset of the physical node */
1717         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1718         if (adev->gmc.xgmi.connected_to_cpu) {
1719                 amdgpu_gmc_sysvm_location(adev, mc);
1720         } else {
1721                 amdgpu_gmc_vram_location(adev, mc, base);
1722                 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
1723                 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
1724                         amdgpu_gmc_agp_location(adev, mc);
1725         }
1726         /* base offset of vram pages */
1727         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1728
1729         /* XXX: add the xgmi offset of the physical node? */
1730         adev->vm_manager.vram_base_offset +=
1731                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1732 }
1733
1734 /**
1735  * gmc_v9_0_mc_init - initialize the memory controller driver params
1736  *
1737  * @adev: amdgpu_device pointer
1738  *
1739  * Look up the amount of vram, vram width, and decide how to place
1740  * vram and gart within the GPU's physical address space.
1741  * Returns 0 for success.
1742  */
1743 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1744 {
1745         int r;
1746
1747         /* size in MB on si */
1748         if (!adev->gmc.is_app_apu) {
1749                 adev->gmc.mc_vram_size =
1750                         adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1751         } else {
1752                 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n");
1753                 adev->gmc.mc_vram_size = 0;
1754         }
1755         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1756
1757         if (!(adev->flags & AMD_IS_APU) &&
1758             !adev->gmc.xgmi.connected_to_cpu) {
1759                 r = amdgpu_device_resize_fb_bar(adev);
1760                 if (r)
1761                         return r;
1762         }
1763         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1764         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1765
1766 #ifdef CONFIG_X86_64
1767         /*
1768          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1769          * interface can use VRAM through here as it appears system reserved
1770          * memory in host address space.
1771          *
1772          * For APUs, VRAM is just the stolen system memory and can be accessed
1773          * directly.
1774          *
1775          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1776          */
1777
1778         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1779         if ((!amdgpu_sriov_vf(adev) &&
1780                 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1781             (adev->gmc.xgmi.supported &&
1782              adev->gmc.xgmi.connected_to_cpu)) {
1783                 adev->gmc.aper_base =
1784                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1785                         adev->gmc.xgmi.physical_node_id *
1786                         adev->gmc.xgmi.node_segment_size;
1787                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1788         }
1789
1790 #endif
1791         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1792
1793         /* set the gart size */
1794         if (amdgpu_gart_size == -1) {
1795                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1796                 case IP_VERSION(9, 0, 1):  /* all engines support GPUVM */
1797                 case IP_VERSION(9, 2, 1):  /* all engines support GPUVM */
1798                 case IP_VERSION(9, 4, 0):
1799                 case IP_VERSION(9, 4, 1):
1800                 case IP_VERSION(9, 4, 2):
1801                 case IP_VERSION(9, 4, 3):
1802                 case IP_VERSION(9, 4, 4):
1803                 case IP_VERSION(9, 5, 0):
1804                 default:
1805                         adev->gmc.gart_size = 512ULL << 20;
1806                         break;
1807                 case IP_VERSION(9, 1, 0):   /* DCE SG support */
1808                 case IP_VERSION(9, 2, 2):   /* DCE SG support */
1809                 case IP_VERSION(9, 3, 0):
1810                         adev->gmc.gart_size = 1024ULL << 20;
1811                         break;
1812                 }
1813         } else {
1814                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1815         }
1816
1817         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1818
1819         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1820
1821         return 0;
1822 }
1823
1824 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1825 {
1826         int r;
1827
1828         if (adev->gart.bo) {
1829                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1830                 return 0;
1831         }
1832
1833         if (adev->gmc.xgmi.connected_to_cpu) {
1834                 adev->gmc.vmid0_page_table_depth = 1;
1835                 adev->gmc.vmid0_page_table_block_size = 12;
1836         } else {
1837                 adev->gmc.vmid0_page_table_depth = 0;
1838                 adev->gmc.vmid0_page_table_block_size = 0;
1839         }
1840
1841         /* Initialize common gart structure */
1842         r = amdgpu_gart_init(adev);
1843         if (r)
1844                 return r;
1845         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1846         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) |
1847                                  AMDGPU_PTE_EXECUTABLE;
1848
1849         if (!adev->gmc.real_vram_size) {
1850                 dev_info(adev->dev, "Put GART in system memory for APU\n");
1851                 r = amdgpu_gart_table_ram_alloc(adev);
1852                 if (r)
1853                         dev_err(adev->dev, "Failed to allocate GART in system memory\n");
1854         } else {
1855                 r = amdgpu_gart_table_vram_alloc(adev);
1856                 if (r)
1857                         return r;
1858
1859                 if (adev->gmc.xgmi.connected_to_cpu)
1860                         r = amdgpu_gmc_pdb0_alloc(adev);
1861         }
1862
1863         return r;
1864 }
1865
1866 /**
1867  * gmc_v9_0_save_registers - saves regs
1868  *
1869  * @adev: amdgpu_device pointer
1870  *
1871  * This saves potential register values that should be
1872  * restored upon resume
1873  */
1874 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1875 {
1876         if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1877             (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1)))
1878                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1879 }
1880
1881 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)
1882 {
1883         enum amdgpu_memory_partition mode;
1884         u32 supp_modes;
1885         bool valid;
1886
1887         mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1888
1889         /* Mode detected by hardware not present in supported modes */
1890         if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &&
1891             !(BIT(mode - 1) & supp_modes))
1892                 return false;
1893
1894         switch (mode) {
1895         case UNKNOWN_MEMORY_PARTITION_MODE:
1896         case AMDGPU_NPS1_PARTITION_MODE:
1897                 valid = (adev->gmc.num_mem_partitions == 1);
1898                 break;
1899         case AMDGPU_NPS2_PARTITION_MODE:
1900                 valid = (adev->gmc.num_mem_partitions == 2);
1901                 break;
1902         case AMDGPU_NPS4_PARTITION_MODE:
1903                 valid = (adev->gmc.num_mem_partitions == 3 ||
1904                          adev->gmc.num_mem_partitions == 4);
1905                 break;
1906         default:
1907                 valid = false;
1908         }
1909
1910         return valid;
1911 }
1912
1913 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)
1914 {
1915         int i;
1916
1917         /* Check if node with id 'nid' is present in 'node_ids' array */
1918         for (i = 0; i < num_ids; ++i)
1919                 if (node_ids[i] == nid)
1920                         return true;
1921
1922         return false;
1923 }
1924
1925 static void
1926 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,
1927                               struct amdgpu_mem_partition_info *mem_ranges)
1928 {
1929         struct amdgpu_numa_info numa_info;
1930         int node_ids[MAX_MEM_RANGES];
1931         int num_ranges = 0, ret;
1932         int num_xcc, xcc_id;
1933         uint32_t xcc_mask;
1934
1935         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1936         xcc_mask = (1U << num_xcc) - 1;
1937
1938         for_each_inst(xcc_id, xcc_mask) {
1939                 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
1940                 if (ret)
1941                         continue;
1942
1943                 if (numa_info.nid == NUMA_NO_NODE) {
1944                         mem_ranges[0].size = numa_info.size;
1945                         mem_ranges[0].numa.node = numa_info.nid;
1946                         num_ranges = 1;
1947                         break;
1948                 }
1949
1950                 if (gmc_v9_0_is_node_present(node_ids, num_ranges,
1951                                              numa_info.nid))
1952                         continue;
1953
1954                 node_ids[num_ranges] = numa_info.nid;
1955                 mem_ranges[num_ranges].numa.node = numa_info.nid;
1956                 mem_ranges[num_ranges].size = numa_info.size;
1957                 ++num_ranges;
1958         }
1959
1960         adev->gmc.num_mem_partitions = num_ranges;
1961 }
1962
1963 static void
1964 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,
1965                             struct amdgpu_mem_partition_info *mem_ranges)
1966 {
1967         enum amdgpu_memory_partition mode;
1968         u32 start_addr = 0, size;
1969         int i, r, l;
1970
1971         mode = gmc_v9_0_query_memory_partition(adev);
1972
1973         switch (mode) {
1974         case UNKNOWN_MEMORY_PARTITION_MODE:
1975                 adev->gmc.num_mem_partitions = 0;
1976                 break;
1977         case AMDGPU_NPS1_PARTITION_MODE:
1978                 adev->gmc.num_mem_partitions = 1;
1979                 break;
1980         case AMDGPU_NPS2_PARTITION_MODE:
1981                 adev->gmc.num_mem_partitions = 2;
1982                 break;
1983         case AMDGPU_NPS4_PARTITION_MODE:
1984                 if (adev->flags & AMD_IS_APU)
1985                         adev->gmc.num_mem_partitions = 3;
1986                 else
1987                         adev->gmc.num_mem_partitions = 4;
1988                 break;
1989         default:
1990                 adev->gmc.num_mem_partitions = 1;
1991                 break;
1992         }
1993
1994         /* Use NPS range info, if populated */
1995         r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges,
1996                                          &adev->gmc.num_mem_partitions);
1997         if (!r) {
1998                 l = 0;
1999                 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) {
2000                         if (mem_ranges[i].range.lpfn >
2001                             mem_ranges[i - 1].range.lpfn)
2002                                 l = i;
2003                 }
2004
2005         } else {
2006                 if (!adev->gmc.num_mem_partitions) {
2007                         dev_err(adev->dev,
2008                                 "Not able to detect NPS mode, fall back to NPS1");
2009                         adev->gmc.num_mem_partitions = 1;
2010                 }
2011                 /* Fallback to sw based calculation */
2012                 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT;
2013                 size /= adev->gmc.num_mem_partitions;
2014
2015                 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
2016                         mem_ranges[i].range.fpfn = start_addr;
2017                         mem_ranges[i].size =
2018                                 ((u64)size << AMDGPU_GPU_PAGE_SHIFT);
2019                         mem_ranges[i].range.lpfn = start_addr + size - 1;
2020                         start_addr += size;
2021                 }
2022
2023                 l = adev->gmc.num_mem_partitions - 1;
2024         }
2025
2026         /* Adjust the last one */
2027         mem_ranges[l].range.lpfn =
2028                 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1;
2029         mem_ranges[l].size =
2030                 adev->gmc.real_vram_size -
2031                 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT);
2032 }
2033
2034 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)
2035 {
2036         bool valid;
2037
2038         adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES,
2039                                            sizeof(struct amdgpu_mem_partition_info),
2040                                            GFP_KERNEL);
2041         if (!adev->gmc.mem_partitions)
2042                 return -ENOMEM;
2043
2044         /* TODO : Get the range from PSP/Discovery for dGPU */
2045         if (adev->gmc.is_app_apu)
2046                 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions);
2047         else
2048                 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2049
2050         if (amdgpu_sriov_vf(adev))
2051                 valid = true;
2052         else
2053                 valid = gmc_v9_0_validate_partition_info(adev);
2054         if (!valid) {
2055                 /* TODO: handle invalid case */
2056                 dev_WARN(adev->dev,
2057                          "Mem ranges not matching with hardware config");
2058         }
2059
2060         return 0;
2061 }
2062
2063 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
2064 {
2065         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
2066         adev->gmc.vram_width = 128 * 64;
2067 }
2068
2069 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
2070 {
2071         int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
2072         struct amdgpu_device *adev = ip_block->adev;
2073         unsigned long inst_mask = adev->aid_mask;
2074
2075         adev->gfxhub.funcs->init(adev);
2076
2077         adev->mmhub.funcs->init(adev);
2078
2079         spin_lock_init(&adev->gmc.invalidate_lock);
2080
2081         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
2082             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
2083             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) {
2084                 gmc_v9_4_3_init_vram_info(adev);
2085         } else if (!adev->bios) {
2086                 if (adev->flags & AMD_IS_APU) {
2087                         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
2088                         adev->gmc.vram_width = 64 * 64;
2089                 } else {
2090                         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
2091                         adev->gmc.vram_width = 128 * 64;
2092                 }
2093         } else {
2094                 r = amdgpu_atomfirmware_get_vram_info(adev,
2095                         &vram_width, &vram_type, &vram_vendor);
2096                 if (amdgpu_sriov_vf(adev))
2097                         /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
2098                          * and DF related registers is not readable, seems hardcord is the
2099                          * only way to set the correct vram_width
2100                          */
2101                         adev->gmc.vram_width = 2048;
2102                 else if (amdgpu_emu_mode != 1)
2103                         adev->gmc.vram_width = vram_width;
2104
2105                 if (!adev->gmc.vram_width) {
2106                         int chansize, numchan;
2107
2108                         /* hbm memory channel size */
2109                         if (adev->flags & AMD_IS_APU)
2110                                 chansize = 64;
2111                         else
2112                                 chansize = 128;
2113                         if (adev->df.funcs &&
2114                             adev->df.funcs->get_hbm_channel_number) {
2115                                 numchan = adev->df.funcs->get_hbm_channel_number(adev);
2116                                 adev->gmc.vram_width = numchan * chansize;
2117                         }
2118                 }
2119
2120                 adev->gmc.vram_type = vram_type;
2121                 adev->gmc.vram_vendor = vram_vendor;
2122         }
2123         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2124         case IP_VERSION(9, 1, 0):
2125         case IP_VERSION(9, 2, 2):
2126                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2127                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2128
2129                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
2130                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2131                 } else {
2132                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
2133                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
2134                         adev->gmc.translate_further =
2135                                 adev->vm_manager.num_level > 1;
2136                 }
2137                 break;
2138         case IP_VERSION(9, 0, 1):
2139         case IP_VERSION(9, 2, 1):
2140         case IP_VERSION(9, 4, 0):
2141         case IP_VERSION(9, 3, 0):
2142         case IP_VERSION(9, 4, 2):
2143                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2144                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2145
2146                 /*
2147                  * To fulfill 4-level page support,
2148                  * vm size is 256TB (48bit), maximum size of Vega10,
2149                  * block size 512 (9bit)
2150                  */
2151
2152                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2153                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
2154                         adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2155                 break;
2156         case IP_VERSION(9, 4, 1):
2157                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2158                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2159                 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
2160
2161                 /* Keep the vm size same with Vega20 */
2162                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2163                 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2164                 break;
2165         case IP_VERSION(9, 4, 3):
2166         case IP_VERSION(9, 4, 4):
2167         case IP_VERSION(9, 5, 0):
2168                 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
2169                                   NUM_XCC(adev->gfx.xcc_mask));
2170
2171                 inst_mask <<= AMDGPU_MMHUB0(0);
2172                 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
2173
2174                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2175                 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2176                 break;
2177         default:
2178                 break;
2179         }
2180
2181         /* This interrupt is VMC page fault.*/
2182         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
2183                                 &adev->gmc.vm_fault);
2184         if (r)
2185                 return r;
2186
2187         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) {
2188                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
2189                                         &adev->gmc.vm_fault);
2190                 if (r)
2191                         return r;
2192         }
2193
2194         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
2195                                 &adev->gmc.vm_fault);
2196
2197         if (r)
2198                 return r;
2199
2200         if (!amdgpu_sriov_vf(adev) &&
2201             !adev->gmc.xgmi.connected_to_cpu &&
2202             !adev->gmc.is_app_apu) {
2203                 /* interrupt sent to DF. */
2204                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
2205                                       &adev->gmc.ecc_irq);
2206                 if (r)
2207                         return r;
2208         }
2209
2210         /* Set the internal MC address mask
2211          * This is the max address of the GPU's
2212          * internal address space.
2213          */
2214         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
2215
2216         dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
2217                                         IP_VERSION(9, 4, 2) ?
2218                                 48 :
2219                                 44;
2220         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
2221         if (r) {
2222                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
2223                 return r;
2224         }
2225         adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
2226
2227         r = gmc_v9_0_mc_init(adev);
2228         if (r)
2229                 return r;
2230
2231         amdgpu_gmc_get_vbios_allocations(adev);
2232
2233         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
2234             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
2235             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) {
2236                 r = gmc_v9_0_init_mem_ranges(adev);
2237                 if (r)
2238                         return r;
2239         }
2240
2241         /* Memory manager */
2242         r = amdgpu_bo_init(adev);
2243         if (r)
2244                 return r;
2245
2246         r = gmc_v9_0_gart_init(adev);
2247         if (r)
2248                 return r;
2249
2250         gmc_v9_0_init_nps_details(adev);
2251         /*
2252          * number of VMs
2253          * VMID 0 is reserved for System
2254          * amdgpu graphics/compute will use VMIDs 1..n-1
2255          * amdkfd will use VMIDs n..15
2256          *
2257          * The first KFD VMID is 8 for GPUs with graphics, 3 for
2258          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
2259          * for video processing.
2260          */
2261         adev->vm_manager.first_kfd_vmid =
2262                 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
2263                  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
2264                  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
2265                  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
2266                  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) ?
2267                         3 :
2268                         8;
2269
2270         amdgpu_vm_manager_init(adev);
2271
2272         gmc_v9_0_save_registers(adev);
2273
2274         r = amdgpu_gmc_ras_sw_init(adev);
2275         if (r)
2276                 return r;
2277
2278         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
2279             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
2280             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
2281                 amdgpu_gmc_sysfs_init(adev);
2282
2283         return 0;
2284 }
2285
2286 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block)
2287 {
2288         struct amdgpu_device *adev = ip_block->adev;
2289
2290         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
2291             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
2292             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
2293                 amdgpu_gmc_sysfs_fini(adev);
2294
2295         amdgpu_gmc_ras_fini(adev);
2296         amdgpu_gem_force_release(adev);
2297         amdgpu_vm_manager_fini(adev);
2298         if (!adev->gmc.real_vram_size) {
2299                 dev_info(adev->dev, "Put GART in system memory for APU free\n");
2300                 amdgpu_gart_table_ram_free(adev);
2301         } else {
2302                 amdgpu_gart_table_vram_free(adev);
2303         }
2304         amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
2305         amdgpu_bo_fini(adev);
2306
2307         adev->gmc.num_mem_partitions = 0;
2308         kfree(adev->gmc.mem_partitions);
2309
2310         return 0;
2311 }
2312
2313 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
2314 {
2315         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
2316         case IP_VERSION(9, 0, 0):
2317                 if (amdgpu_sriov_vf(adev))
2318                         break;
2319                 fallthrough;
2320         case IP_VERSION(9, 4, 0):
2321                 soc15_program_register_sequence(adev,
2322                                                 golden_settings_mmhub_1_0_0,
2323                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
2324                 soc15_program_register_sequence(adev,
2325                                                 golden_settings_athub_1_0_0,
2326                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
2327                 break;
2328         case IP_VERSION(9, 1, 0):
2329         case IP_VERSION(9, 2, 0):
2330                 /* TODO for renoir */
2331                 soc15_program_register_sequence(adev,
2332                                                 golden_settings_athub_1_0_0,
2333                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
2334                 break;
2335         default:
2336                 break;
2337         }
2338 }
2339
2340 /**
2341  * gmc_v9_0_restore_registers - restores regs
2342  *
2343  * @adev: amdgpu_device pointer
2344  *
2345  * This restores register values, saved at suspend.
2346  */
2347 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
2348 {
2349         if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
2350             (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) {
2351                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
2352                 WARN_ON(adev->gmc.sdpif_register !=
2353                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
2354         }
2355 }
2356
2357 /**
2358  * gmc_v9_0_gart_enable - gart enable
2359  *
2360  * @adev: amdgpu_device pointer
2361  */
2362 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
2363 {
2364         int r;
2365
2366         if (adev->gmc.xgmi.connected_to_cpu)
2367                 amdgpu_gmc_init_pdb0(adev);
2368
2369         if (adev->gart.bo == NULL) {
2370                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
2371                 return -EINVAL;
2372         }
2373
2374         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
2375
2376         if (!adev->in_s0ix) {
2377                 r = adev->gfxhub.funcs->gart_enable(adev);
2378                 if (r)
2379                         return r;
2380         }
2381
2382         r = adev->mmhub.funcs->gart_enable(adev);
2383         if (r)
2384                 return r;
2385
2386         DRM_INFO("PCIE GART of %uM enabled.\n",
2387                  (unsigned int)(adev->gmc.gart_size >> 20));
2388         if (adev->gmc.pdb0_bo)
2389                 DRM_INFO("PDB0 located at 0x%016llX\n",
2390                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
2391         DRM_INFO("PTB located at 0x%016llX\n",
2392                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
2393
2394         return 0;
2395 }
2396
2397 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
2398 {
2399         struct amdgpu_device *adev = ip_block->adev;
2400         bool value;
2401         int i, r;
2402
2403         adev->gmc.flush_pasid_uses_kiq = true;
2404
2405         /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush
2406          * (type 2), which flushes both. Due to a race condition with
2407          * concurrent memory accesses using the same TLB cache line, we still
2408          * need a second TLB flush after this.
2409          */
2410         adev->gmc.flush_tlb_needs_extra_type_2 =
2411                 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
2412                 adev->gmc.xgmi.num_physical_nodes;
2413         /*
2414          * TODO: This workaround is badly documented and had a buggy
2415          * implementation. We should probably verify what we do here.
2416          */
2417         adev->gmc.flush_tlb_needs_extra_type_0 =
2418                 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) &&
2419                 adev->rev_id == 0;
2420
2421         /* The sequence of these two function calls matters.*/
2422         gmc_v9_0_init_golden_registers(adev);
2423
2424         if (adev->mode_info.num_crtc) {
2425                 /* Lockout access through VGA aperture*/
2426                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
2427                 /* disable VGA render */
2428                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
2429         }
2430
2431         if (adev->mmhub.funcs->update_power_gating)
2432                 adev->mmhub.funcs->update_power_gating(adev, true);
2433
2434         adev->hdp.funcs->init_registers(adev);
2435
2436         /* After HDP is initialized, flush HDP.*/
2437         adev->hdp.funcs->flush_hdp(adev, NULL);
2438
2439         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
2440                 value = false;
2441         else
2442                 value = true;
2443
2444         if (!amdgpu_sriov_vf(adev)) {
2445                 if (!adev->in_s0ix)
2446                         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
2447                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
2448         }
2449         for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
2450                 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
2451                         continue;
2452                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
2453         }
2454
2455         if (adev->umc.funcs && adev->umc.funcs->init_registers)
2456                 adev->umc.funcs->init_registers(adev);
2457
2458         r = gmc_v9_0_gart_enable(adev);
2459         if (r)
2460                 return r;
2461
2462         if (amdgpu_emu_mode == 1)
2463                 return amdgpu_gmc_vram_checking(adev);
2464
2465         return 0;
2466 }
2467
2468 /**
2469  * gmc_v9_0_gart_disable - gart disable
2470  *
2471  * @adev: amdgpu_device pointer
2472  *
2473  * This disables all VM page table.
2474  */
2475 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
2476 {
2477         if (!adev->in_s0ix)
2478                 adev->gfxhub.funcs->gart_disable(adev);
2479         adev->mmhub.funcs->gart_disable(adev);
2480 }
2481
2482 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block)
2483 {
2484         struct amdgpu_device *adev = ip_block->adev;
2485
2486         gmc_v9_0_gart_disable(adev);
2487
2488         if (amdgpu_sriov_vf(adev)) {
2489                 /* full access mode, so don't touch any GMC register */
2490                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
2491                 return 0;
2492         }
2493
2494         /*
2495          * Pair the operations did in gmc_v9_0_hw_init and thus maintain
2496          * a correct cached state for GMC. Otherwise, the "gate" again
2497          * operation on S3 resuming will fail due to wrong cached state.
2498          */
2499         if (adev->mmhub.funcs->update_power_gating)
2500                 adev->mmhub.funcs->update_power_gating(adev, false);
2501
2502         /*
2503          * For minimal init, late_init is not called, hence VM fault/RAS irqs
2504          * are not enabled.
2505          */
2506         if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
2507                 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2508
2509                 if (adev->gmc.ecc_irq.funcs &&
2510                     amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2511                         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2512         }
2513
2514         return 0;
2515 }
2516
2517 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block)
2518 {
2519         return gmc_v9_0_hw_fini(ip_block);
2520 }
2521
2522 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)
2523 {
2524         struct amdgpu_device *adev = ip_block->adev;
2525         int r;
2526
2527         /* If a reset is done for NPS mode switch, read the memory range
2528          * information again.
2529          */
2530         if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) {
2531                 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2532                 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS;
2533         }
2534
2535         r = gmc_v9_0_hw_init(ip_block);
2536         if (r)
2537                 return r;
2538
2539         amdgpu_vmid_reset_all(ip_block->adev);
2540
2541         return 0;
2542 }
2543
2544 static bool gmc_v9_0_is_idle(void *handle)
2545 {
2546         /* MC is always ready in GMC v9.*/
2547         return true;
2548 }
2549
2550 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
2551 {
2552         /* There is no need to wait for MC idle in GMC v9.*/
2553         return 0;
2554 }
2555
2556 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
2557 {
2558         /* XXX for emulation.*/
2559         return 0;
2560 }
2561
2562 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2563                                         enum amd_clockgating_state state)
2564 {
2565         struct amdgpu_device *adev = ip_block->adev;
2566
2567         adev->mmhub.funcs->set_clockgating(adev, state);
2568
2569         athub_v1_0_set_clockgating(adev, state);
2570
2571         return 0;
2572 }
2573
2574 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
2575 {
2576         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2577
2578         adev->mmhub.funcs->get_clockgating(adev, flags);
2579
2580         athub_v1_0_get_clockgating(adev, flags);
2581 }
2582
2583 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
2584                                         enum amd_powergating_state state)
2585 {
2586         return 0;
2587 }
2588
2589 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2590         .name = "gmc_v9_0",
2591         .early_init = gmc_v9_0_early_init,
2592         .late_init = gmc_v9_0_late_init,
2593         .sw_init = gmc_v9_0_sw_init,
2594         .sw_fini = gmc_v9_0_sw_fini,
2595         .hw_init = gmc_v9_0_hw_init,
2596         .hw_fini = gmc_v9_0_hw_fini,
2597         .suspend = gmc_v9_0_suspend,
2598         .resume = gmc_v9_0_resume,
2599         .is_idle = gmc_v9_0_is_idle,
2600         .wait_for_idle = gmc_v9_0_wait_for_idle,
2601         .soft_reset = gmc_v9_0_soft_reset,
2602         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2603         .set_powergating_state = gmc_v9_0_set_powergating_state,
2604         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2605 };
2606
2607 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
2608         .type = AMD_IP_BLOCK_TYPE_GMC,
2609         .major = 9,
2610         .minor = 0,
2611         .rev = 0,
2612         .funcs = &gmc_v9_0_ip_funcs,
2613 };