drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <[email protected]>
   6  *           Gerald Baeza <[email protected]>
   7  *           Erwan Le Ray <[email protected]>
   8  *
   9  * Inspired by st-asc.c from STMicroelectronics (c)
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-direction.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/pm_wakeirq.h>
  28 #include <linux/serial_core.h>
  29 #include <linux/serial.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/sysrq.h>
  32 #include <linux/tty_flip.h>
  33 #include <linux/tty.h>
  34
  35 #include "serial_mctrl_gpio.h"
  36 #include "stm32-usart.h"
  37
  38 static void stm32_usart_stop_tx(struct uart_port *port);
  39 static void stm32_usart_transmit_chars(struct uart_port *port);
  40
  41 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  42 {
  43         return container_of(port, struct stm32_port, port);
  44 }
  45
  46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
  47 {
  48         u32 val;
  49
  50         val = readl_relaxed(port->membase + reg);
  51         val |= bits;
  52         writel_relaxed(val, port->membase + reg);
  53 }
  54
  55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  56 {
  57         u32 val;
  58
  59         val = readl_relaxed(port->membase + reg);
  60         val &= ~bits;
  61         writel_relaxed(val, port->membase + reg);
  62 }
  63
  64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
  65                                          u32 delay_DDE, u32 baud)
  66 {
  67         u32 rs485_deat_dedt;
  68         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
  69         bool over8;
  70
  71         *cr3 |= USART_CR3_DEM;
  72         over8 = *cr1 & USART_CR1_OVER8;
  73
  74         if (over8)
  75                 rs485_deat_dedt = delay_ADE * baud * 8;
  76         else
  77                 rs485_deat_dedt = delay_ADE * baud * 16;
  78
  79         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  80         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  81                           rs485_deat_dedt_max : rs485_deat_dedt;
  82         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
  83                            USART_CR1_DEAT_MASK;
  84         *cr1 |= rs485_deat_dedt;
  85
  86         if (over8)
  87                 rs485_deat_dedt = delay_DDE * baud * 8;
  88         else
  89                 rs485_deat_dedt = delay_DDE * baud * 16;
  90
  91         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  92         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  93                           rs485_deat_dedt_max : rs485_deat_dedt;
  94         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
  95                            USART_CR1_DEDT_MASK;
  96         *cr1 |= rs485_deat_dedt;
  97 }
  98
  99 static int stm32_usart_config_rs485(struct uart_port *port,
 100                                     struct serial_rs485 *rs485conf)
 101 {
 102         struct stm32_port *stm32_port = to_stm32_port(port);
 103         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 104         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 105         u32 usartdiv, baud, cr1, cr3;
 106         bool over8;
 107
 108         stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 109
 110         port->rs485 = *rs485conf;
 111
 112         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 113
 114         if (rs485conf->flags & SER_RS485_ENABLED) {
 115                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 116                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 117                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 118                 usartdiv = usartdiv & GENMASK(15, 0);
 119                 over8 = cr1 & USART_CR1_OVER8;
 120
 121                 if (over8)
 122                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 123                                    << USART_BRR_04_R_SHIFT;
 124
 125                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 126                 stm32_usart_config_reg_rs485(&cr1, &cr3,
 127                                              rs485conf->delay_rts_before_send,
 128                                              rs485conf->delay_rts_after_send,
 129                                              baud);
 130
 131                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 132                         cr3 &= ~USART_CR3_DEP;
 133                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 134                 } else {
 135                         cr3 |= USART_CR3_DEP;
 136                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 137                 }
 138
 139                 writel_relaxed(cr3, port->membase + ofs->cr3);
 140                 writel_relaxed(cr1, port->membase + ofs->cr1);
 141         } else {
 142                 stm32_usart_clr_bits(port, ofs->cr3,
 143                                      USART_CR3_DEM | USART_CR3_DEP);
 144                 stm32_usart_clr_bits(port, ofs->cr1,
 145                                      USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 146         }
 147
 148         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 149
 150         return 0;
 151 }
 152
 153 static int stm32_usart_init_rs485(struct uart_port *port,
 154                                   struct platform_device *pdev)
 155 {
 156         struct serial_rs485 *rs485conf = &port->rs485;
 157
 158         rs485conf->flags = 0;
 159         rs485conf->delay_rts_before_send = 0;
 160         rs485conf->delay_rts_after_send = 0;
 161
 162         if (!pdev->dev.of_node)
 163                 return -ENODEV;
 164
 165         return uart_get_rs485_mode(port);
 166 }
 167
 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
 169                                   int *last_res, bool threaded)
 170 {
 171         struct stm32_port *stm32_port = to_stm32_port(port);
 172         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 173         enum dma_status status;
 174         struct dma_tx_state state;
 175
 176         *sr = readl_relaxed(port->membase + ofs->isr);
 177
 178         if (threaded && stm32_port->rx_ch) {
 179                 status = dmaengine_tx_status(stm32_port->rx_ch,
 180                                              stm32_port->rx_ch->cookie,
 181                                              &state);
 182                 if (status == DMA_IN_PROGRESS && (*last_res != state.residue))
 183                         return 1;
 184                 else
 185                         return 0;
 186         } else if (*sr & USART_SR_RXNE) {
 187                 return 1;
 188         }
 189         return 0;
 190 }
 191
 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
 193                                           int *last_res)
 194 {
 195         struct stm32_port *stm32_port = to_stm32_port(port);
 196         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 197         unsigned long c;
 198
 199         if (stm32_port->rx_ch) {
 200                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
 201                 if ((*last_res) == 0)
 202                         *last_res = RX_BUF_L;
 203         } else {
 204                 c = readl_relaxed(port->membase + ofs->rdr);
 205                 /* apply RDR data mask */
 206                 c &= stm32_port->rdr_mask;
 207         }
 208
 209         return c;
 210 }
 211
 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
 213 {
 214         struct tty_port *tport = &port->state->port;
 215         struct stm32_port *stm32_port = to_stm32_port(port);
 216         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 217         unsigned long c;
 218         u32 sr;
 219         char flag;
 220
 221         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 222                 pm_wakeup_event(tport->tty->dev, 0);
 223
 224         while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
 225                                       threaded)) {
 226                 sr |= USART_SR_DUMMY_RX;
 227                 flag = TTY_NORMAL;
 228
 229                 /*
 230                  * Status bits has to be cleared before reading the RDR:
 231                  * In FIFO mode, reading the RDR will pop the next data
 232                  * (if any) along with its status bits into the SR.
 233                  * Not doing so leads to misalignement between RDR and SR,
 234                  * and clear status bits of the next rx data.
 235                  *
 236                  * Clear errors flags for stm32f7 and stm32h7 compatible
 237                  * devices. On stm32f4 compatible devices, the error bit is
 238                  * cleared by the sequence [read SR - read DR].
 239                  */
 240                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 241                         writel_relaxed(sr & USART_SR_ERR_MASK,
 242                                        port->membase + ofs->icr);
 243
 244                 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
 245                 port->icount.rx++;
 246                 if (sr & USART_SR_ERR_MASK) {
 247                         if (sr & USART_SR_ORE) {
 248                                 port->icount.overrun++;
 249                         } else if (sr & USART_SR_PE) {
 250                                 port->icount.parity++;
 251                         } else if (sr & USART_SR_FE) {
 252                                 /* Break detection if character is null */
 253                                 if (!c) {
 254                                         port->icount.brk++;
 255                                         if (uart_handle_break(port))
 256                                                 continue;
 257                                 } else {
 258                                         port->icount.frame++;
 259                                 }
 260                         }
 261
 262                         sr &= port->read_status_mask;
 263
 264                         if (sr & USART_SR_PE) {
 265                                 flag = TTY_PARITY;
 266                         } else if (sr & USART_SR_FE) {
 267                                 if (!c)
 268                                         flag = TTY_BREAK;
 269                                 else
 270                                         flag = TTY_FRAME;
 271                         }
 272                 }
 273
 274                 if (uart_handle_sysrq_char(port, c))
 275                         continue;
 276                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 277         }
 278
 279         spin_unlock(&port->lock);
 280         tty_flip_buffer_push(tport);
 281         spin_lock(&port->lock);
 282 }
 283
 284 static void stm32_usart_tx_dma_complete(void *arg)
 285 {
 286         struct uart_port *port = arg;
 287         struct stm32_port *stm32port = to_stm32_port(port);
 288         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 289
 290         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 291         stm32port->tx_dma_busy = false;
 292
 293         /* Let's see if we have pending data to send */
 294         stm32_usart_transmit_chars(port);
 295 }
 296
 297 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
 298 {
 299         struct stm32_port *stm32_port = to_stm32_port(port);
 300         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 301
 302         /*
 303          * Enables TX FIFO threashold irq when FIFO is enabled,
 304          * or TX empty irq when FIFO is disabled
 305          */
 306         if (stm32_port->fifoen)
 307                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 308         else
 309                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 310 }
 311
 312 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
 313 {
 314         struct stm32_port *stm32_port = to_stm32_port(port);
 315         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 316
 317         if (stm32_port->fifoen)
 318                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 319         else
 320                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 321 }
 322
 323 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
 324 {
 325         struct stm32_port *stm32_port = to_stm32_port(port);
 326         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 327         struct circ_buf *xmit = &port->state->xmit;
 328
 329         if (stm32_port->tx_dma_busy) {
 330                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 331                 stm32_port->tx_dma_busy = false;
 332         }
 333
 334         while (!uart_circ_empty(xmit)) {
 335                 /* Check that TDR is empty before filling FIFO */
 336                 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 337                         break;
 338                 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 339                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 340                 port->icount.tx++;
 341         }
 342
 343         /* rely on TXE irq (mask or unmask) for sending remaining data */
 344         if (uart_circ_empty(xmit))
 345                 stm32_usart_tx_interrupt_disable(port);
 346         else
 347                 stm32_usart_tx_interrupt_enable(port);
 348 }
 349
 350 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
 351 {
 352         struct stm32_port *stm32port = to_stm32_port(port);
 353         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 354         struct circ_buf *xmit = &port->state->xmit;
 355         struct dma_async_tx_descriptor *desc = NULL;
 356         unsigned int count, i;
 357
 358         if (stm32port->tx_dma_busy)
 359                 return;
 360
 361         stm32port->tx_dma_busy = true;
 362
 363         count = uart_circ_chars_pending(xmit);
 364
 365         if (count > TX_BUF_L)
 366                 count = TX_BUF_L;
 367
 368         if (xmit->tail < xmit->head) {
 369                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 370         } else {
 371                 size_t one = UART_XMIT_SIZE - xmit->tail;
 372                 size_t two;
 373
 374                 if (one > count)
 375                         one = count;
 376                 two = count - one;
 377
 378                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 379                 if (two)
 380                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 381         }
 382
 383         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 384                                            stm32port->tx_dma_buf,
 385                                            count,
 386                                            DMA_MEM_TO_DEV,
 387                                            DMA_PREP_INTERRUPT);
 388
 389         if (!desc)
 390                 goto fallback_err;
 391
 392         desc->callback = stm32_usart_tx_dma_complete;
 393         desc->callback_param = port;
 394
 395         /* Push current DMA TX transaction in the pending queue */
 396         if (dma_submit_error(dmaengine_submit(desc))) {
 397                 /* dma no yet started, safe to free resources */
 398                 dmaengine_terminate_async(stm32port->tx_ch);
 399                 goto fallback_err;
 400         }
 401
 402         /* Issue pending DMA TX requests */
 403         dma_async_issue_pending(stm32port->tx_ch);
 404
 405         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 406
 407         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 408         port->icount.tx += count;
 409         return;
 410
 411 fallback_err:
 412         for (i = count; i > 0; i--)
 413                 stm32_usart_transmit_chars_pio(port);
 414 }
 415
 416 static void stm32_usart_transmit_chars(struct uart_port *port)
 417 {
 418         struct stm32_port *stm32_port = to_stm32_port(port);
 419         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 420         struct circ_buf *xmit = &port->state->xmit;
 421
 422         if (port->x_char) {
 423                 if (stm32_port->tx_dma_busy)
 424                         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 425                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 426                 port->x_char = 0;
 427                 port->icount.tx++;
 428                 if (stm32_port->tx_dma_busy)
 429                         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 430                 return;
 431         }
 432
 433         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 434                 stm32_usart_tx_interrupt_disable(port);
 435                 return;
 436         }
 437
 438         if (ofs->icr == UNDEF_REG)
 439                 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
 440         else
 441                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 442
 443         if (stm32_port->tx_ch)
 444                 stm32_usart_transmit_chars_dma(port);
 445         else
 446                 stm32_usart_transmit_chars_pio(port);
 447
 448         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 449                 uart_write_wakeup(port);
 450
 451         if (uart_circ_empty(xmit))
 452                 stm32_usart_tx_interrupt_disable(port);
 453 }
 454
 455 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
 456 {
 457         struct uart_port *port = ptr;
 458         struct stm32_port *stm32_port = to_stm32_port(port);
 459         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 460         u32 sr;
 461
 462         spin_lock(&port->lock);
 463
 464         sr = readl_relaxed(port->membase + ofs->isr);
 465
 466         if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
 467                 writel_relaxed(USART_ICR_RTOCF,
 468                                port->membase + ofs->icr);
 469
 470         if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG)
 471                 writel_relaxed(USART_ICR_WUCF,
 472                                port->membase + ofs->icr);
 473
 474         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 475                 stm32_usart_receive_chars(port, false);
 476
 477         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 478                 stm32_usart_transmit_chars(port);
 479
 480         spin_unlock(&port->lock);
 481
 482         if (stm32_port->rx_ch)
 483                 return IRQ_WAKE_THREAD;
 484         else
 485                 return IRQ_HANDLED;
 486 }
 487
 488 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
 489 {
 490         struct uart_port *port = ptr;
 491         struct stm32_port *stm32_port = to_stm32_port(port);
 492
 493         spin_lock(&port->lock);
 494
 495         if (stm32_port->rx_ch)
 496                 stm32_usart_receive_chars(port, true);
 497
 498         spin_unlock(&port->lock);
 499
 500         return IRQ_HANDLED;
 501 }
 502
 503 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
 504 {
 505         struct stm32_port *stm32_port = to_stm32_port(port);
 506         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 507
 508         return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
 509 }
 510
 511 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 512 {
 513         struct stm32_port *stm32_port = to_stm32_port(port);
 514         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 515
 516         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 517                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 518         else
 519                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 520
 521         mctrl_gpio_set(stm32_port->gpios, mctrl);
 522 }
 523
 524 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
 525 {
 526         struct stm32_port *stm32_port = to_stm32_port(port);
 527         unsigned int ret;
 528
 529         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 530         ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 531
 532         return mctrl_gpio_get(stm32_port->gpios, &ret);
 533 }
 534
 535 static void stm32_usart_enable_ms(struct uart_port *port)
 536 {
 537         mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
 538 }
 539
 540 static void stm32_usart_disable_ms(struct uart_port *port)
 541 {
 542         mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
 543 }
 544
 545 /* Transmit stop */
 546 static void stm32_usart_stop_tx(struct uart_port *port)
 547 {
 548         struct stm32_port *stm32_port = to_stm32_port(port);
 549         struct serial_rs485 *rs485conf = &port->rs485;
 550
 551         stm32_usart_tx_interrupt_disable(port);
 552
 553         if (rs485conf->flags & SER_RS485_ENABLED) {
 554                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 555                         mctrl_gpio_set(stm32_port->gpios,
 556                                         stm32_port->port.mctrl & ~TIOCM_RTS);
 557                 } else {
 558                         mctrl_gpio_set(stm32_port->gpios,
 559                                         stm32_port->port.mctrl | TIOCM_RTS);
 560                 }
 561         }
 562 }
 563
 564 /* There are probably characters waiting to be transmitted. */
 565 static void stm32_usart_start_tx(struct uart_port *port)
 566 {
 567         struct stm32_port *stm32_port = to_stm32_port(port);
 568         struct serial_rs485 *rs485conf = &port->rs485;
 569         struct circ_buf *xmit = &port->state->xmit;
 570
 571         if (uart_circ_empty(xmit))
 572                 return;
 573
 574         if (rs485conf->flags & SER_RS485_ENABLED) {
 575                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 576                         mctrl_gpio_set(stm32_port->gpios,
 577                                         stm32_port->port.mctrl | TIOCM_RTS);
 578                 } else {
 579                         mctrl_gpio_set(stm32_port->gpios,
 580                                         stm32_port->port.mctrl & ~TIOCM_RTS);
 581                 }
 582         }
 583
 584         stm32_usart_transmit_chars(port);
 585 }
 586
 587 /* Throttle the remote when input buffer is about to overflow. */
 588 static void stm32_usart_throttle(struct uart_port *port)
 589 {
 590         struct stm32_port *stm32_port = to_stm32_port(port);
 591         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 592         unsigned long flags;
 593
 594         spin_lock_irqsave(&port->lock, flags);
 595         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
 596         if (stm32_port->cr3_irq)
 597                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
 598
 599         spin_unlock_irqrestore(&port->lock, flags);
 600 }
 601
 602 /* Unthrottle the remote, the input buffer can now accept data. */
 603 static void stm32_usart_unthrottle(struct uart_port *port)
 604 {
 605         struct stm32_port *stm32_port = to_stm32_port(port);
 606         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 607         unsigned long flags;
 608
 609         spin_lock_irqsave(&port->lock, flags);
 610         stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
 611         if (stm32_port->cr3_irq)
 612                 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
 613
 614         spin_unlock_irqrestore(&port->lock, flags);
 615 }
 616
 617 /* Receive stop */
 618 static void stm32_usart_stop_rx(struct uart_port *port)
 619 {
 620         struct stm32_port *stm32_port = to_stm32_port(port);
 621         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 622
 623         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
 624         if (stm32_port->cr3_irq)
 625                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
 626 }
 627
 628 /* Handle breaks - ignored by us */
 629 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
 630 {
 631 }
 632
 633 static int stm32_usart_startup(struct uart_port *port)
 634 {
 635         struct stm32_port *stm32_port = to_stm32_port(port);
 636         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 637         const char *name = to_platform_device(port->dev)->name;
 638         u32 val;
 639         int ret;
 640
 641         ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
 642                                    stm32_usart_threaded_interrupt,
 643                                    IRQF_NO_SUSPEND, name, port);
 644         if (ret)
 645                 return ret;
 646
 647         /* RX FIFO Flush */
 648         if (ofs->rqr != UNDEF_REG)
 649                 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
 650
 651         /* Tx and RX FIFO configuration */
 652         if (stm32_port->fifoen) {
 653                 val = readl_relaxed(port->membase + ofs->cr3);
 654                 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
 655                 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
 656                 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
 657                 writel_relaxed(val, port->membase + ofs->cr3);
 658         }
 659
 660         /* RX FIFO enabling */
 661         val = stm32_port->cr1_irq | USART_CR1_RE;
 662         if (stm32_port->fifoen)
 663                 val |= USART_CR1_FIFOEN;
 664         stm32_usart_set_bits(port, ofs->cr1, val);
 665
 666         return 0;
 667 }
 668
 669 static void stm32_usart_shutdown(struct uart_port *port)
 670 {
 671         struct stm32_port *stm32_port = to_stm32_port(port);
 672         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 673         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 674         u32 val, isr;
 675         int ret;
 676
 677         /* Disable modem control interrupts */
 678         stm32_usart_disable_ms(port);
 679
 680         val = USART_CR1_TXEIE | USART_CR1_TE;
 681         val |= stm32_port->cr1_irq | USART_CR1_RE;
 682         val |= BIT(cfg->uart_enable_bit);
 683         if (stm32_port->fifoen)
 684                 val |= USART_CR1_FIFOEN;
 685
 686         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
 687                                          isr, (isr & USART_SR_TC),
 688                                          10, 100000);
 689
 690         /* Send the TC error message only when ISR_TC is not set */
 691         if (ret)
 692                 dev_err(port->dev, "Transmission is not complete\n");
 693
 694         stm32_usart_clr_bits(port, ofs->cr1, val);
 695
 696         free_irq(port->irq, port);
 697 }
 698
 699 static unsigned int stm32_usart_get_databits(struct ktermios *termios)
 700 {
 701         unsigned int bits;
 702
 703         tcflag_t cflag = termios->c_cflag;
 704
 705         switch (cflag & CSIZE) {
 706         /*
 707          * CSIZE settings are not necessarily supported in hardware.
 708          * CSIZE unsupported configurations are handled here to set word length
 709          * to 8 bits word as default configuration and to print debug message.
 710          */
 711         case CS5:
 712                 bits = 5;
 713                 break;
 714         case CS6:
 715                 bits = 6;
 716                 break;
 717         case CS7:
 718                 bits = 7;
 719                 break;
 720         /* default including CS8 */
 721         default:
 722                 bits = 8;
 723                 break;
 724         }
 725
 726         return bits;
 727 }
 728
 729 static void stm32_usart_set_termios(struct uart_port *port,
 730                                     struct ktermios *termios,
 731                                     struct ktermios *old)
 732 {
 733         struct stm32_port *stm32_port = to_stm32_port(port);
 734         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 735         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 736         struct serial_rs485 *rs485conf = &port->rs485;
 737         unsigned int baud, bits;
 738         u32 usartdiv, mantissa, fraction, oversampling;
 739         tcflag_t cflag = termios->c_cflag;
 740         u32 cr1, cr2, cr3;
 741         unsigned long flags;
 742
 743         if (!stm32_port->hw_flow_control)
 744                 cflag &= ~CRTSCTS;
 745
 746         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 747
 748         spin_lock_irqsave(&port->lock, flags);
 749
 750         /* Stop serial port and reset value */
 751         writel_relaxed(0, port->membase + ofs->cr1);
 752
 753         /* flush RX & TX FIFO */
 754         if (ofs->rqr != UNDEF_REG)
 755                 stm32_usart_set_bits(port, ofs->rqr,
 756                                      USART_RQR_TXFRQ | USART_RQR_RXFRQ);
 757
 758         cr1 = USART_CR1_TE | USART_CR1_RE;
 759         if (stm32_port->fifoen)
 760                 cr1 |= USART_CR1_FIFOEN;
 761         cr2 = 0;
 762         cr3 = readl_relaxed(port->membase + ofs->cr3);
 763         cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
 764                 | USART_CR3_TXFTCFG_MASK;
 765
 766         if (cflag & CSTOPB)
 767                 cr2 |= USART_CR2_STOP_2B;
 768
 769         bits = stm32_usart_get_databits(termios);
 770         stm32_port->rdr_mask = (BIT(bits) - 1);
 771
 772         if (cflag & PARENB) {
 773                 bits++;
 774                 cr1 |= USART_CR1_PCE;
 775         }
 776
 777         /*
 778          * Word length configuration:
 779          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
 780          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
 781          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
 782          * M0 and M1 already cleared by cr1 initialization.
 783          */
 784         if (bits == 9)
 785                 cr1 |= USART_CR1_M0;
 786         else if ((bits == 7) && cfg->has_7bits_data)
 787                 cr1 |= USART_CR1_M1;
 788         else if (bits != 8)
 789                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
 790                         , bits);
 791
 792         if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
 793                                        stm32_port->fifoen)) {
 794                 if (cflag & CSTOPB)
 795                         bits = bits + 3; /* 1 start bit + 2 stop bits */
 796                 else
 797                         bits = bits + 2; /* 1 start bit + 1 stop bit */
 798
 799                 /* RX timeout irq to occur after last stop bit + bits */
 800                 stm32_port->cr1_irq = USART_CR1_RTOIE;
 801                 writel_relaxed(bits, port->membase + ofs->rtor);
 802                 cr2 |= USART_CR2_RTOEN;
 803                 /* Not using dma, enable fifo threshold irq */
 804                 if (!stm32_port->rx_ch)
 805                         stm32_port->cr3_irq =  USART_CR3_RXFTIE;
 806         }
 807
 808         cr1 |= stm32_port->cr1_irq;
 809         cr3 |= stm32_port->cr3_irq;
 810
 811         if (cflag & PARODD)
 812                 cr1 |= USART_CR1_PS;
 813
 814         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 815         if (cflag & CRTSCTS) {
 816                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 817                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 818         }
 819
 820         /* Handle modem control interrupts */
 821         if (UART_ENABLE_MS(port, termios->c_cflag))
 822                 stm32_usart_enable_ms(port);
 823         else
 824                 stm32_usart_disable_ms(port);
 825
 826         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 827
 828         /*
 829          * The USART supports 16 or 8 times oversampling.
 830          * By default we prefer 16 times oversampling, so that the receiver
 831          * has a better tolerance to clock deviations.
 832          * 8 times oversampling is only used to achieve higher speeds.
 833          */
 834         if (usartdiv < 16) {
 835                 oversampling = 8;
 836                 cr1 |= USART_CR1_OVER8;
 837                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 838         } else {
 839                 oversampling = 16;
 840                 cr1 &= ~USART_CR1_OVER8;
 841                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 842         }
 843
 844         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 845         fraction = usartdiv % oversampling;
 846         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 847
 848         uart_update_timeout(port, cflag, baud);
 849
 850         port->read_status_mask = USART_SR_ORE;
 851         if (termios->c_iflag & INPCK)
 852                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 853         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 854                 port->read_status_mask |= USART_SR_FE;
 855
 856         /* Characters to ignore */
 857         port->ignore_status_mask = 0;
 858         if (termios->c_iflag & IGNPAR)
 859                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 860         if (termios->c_iflag & IGNBRK) {
 861                 port->ignore_status_mask |= USART_SR_FE;
 862                 /*
 863                  * If we're ignoring parity and break indicators,
 864                  * ignore overruns too (for real raw support).
 865                  */
 866                 if (termios->c_iflag & IGNPAR)
 867                         port->ignore_status_mask |= USART_SR_ORE;
 868         }
 869
 870         /* Ignore all characters if CREAD is not set */
 871         if ((termios->c_cflag & CREAD) == 0)
 872                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 873
 874         if (stm32_port->rx_ch)
 875                 cr3 |= USART_CR3_DMAR;
 876
 877         if (rs485conf->flags & SER_RS485_ENABLED) {
 878                 stm32_usart_config_reg_rs485(&cr1, &cr3,
 879                                              rs485conf->delay_rts_before_send,
 880                                              rs485conf->delay_rts_after_send,
 881                                              baud);
 882                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 883                         cr3 &= ~USART_CR3_DEP;
 884                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 885                 } else {
 886                         cr3 |= USART_CR3_DEP;
 887                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 888                 }
 889
 890         } else {
 891                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
 892                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 893         }
 894
 895         writel_relaxed(cr3, port->membase + ofs->cr3);
 896         writel_relaxed(cr2, port->membase + ofs->cr2);
 897         writel_relaxed(cr1, port->membase + ofs->cr1);
 898
 899         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 900         spin_unlock_irqrestore(&port->lock, flags);
 901 }
 902
 903 static const char *stm32_usart_type(struct uart_port *port)
 904 {
 905         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 906 }
 907
 908 static void stm32_usart_release_port(struct uart_port *port)
 909 {
 910 }
 911
 912 static int stm32_usart_request_port(struct uart_port *port)
 913 {
 914         return 0;
 915 }
 916
 917 static void stm32_usart_config_port(struct uart_port *port, int flags)
 918 {
 919         if (flags & UART_CONFIG_TYPE)
 920                 port->type = PORT_STM32;
 921 }
 922
 923 static int
 924 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
 925 {
 926         /* No user changeable parameters */
 927         return -EINVAL;
 928 }
 929
 930 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
 931                            unsigned int oldstate)
 932 {
 933         struct stm32_port *stm32port = container_of(port,
 934                         struct stm32_port, port);
 935         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 936         const struct stm32_usart_config *cfg = &stm32port->info->cfg;
 937         unsigned long flags = 0;
 938
 939         switch (state) {
 940         case UART_PM_STATE_ON:
 941                 pm_runtime_get_sync(port->dev);
 942                 break;
 943         case UART_PM_STATE_OFF:
 944                 spin_lock_irqsave(&port->lock, flags);
 945                 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 946                 spin_unlock_irqrestore(&port->lock, flags);
 947                 pm_runtime_put_sync(port->dev);
 948                 break;
 949         }
 950 }
 951
 952 static const struct uart_ops stm32_uart_ops = {
 953         .tx_empty       = stm32_usart_tx_empty,
 954         .set_mctrl      = stm32_usart_set_mctrl,
 955         .get_mctrl      = stm32_usart_get_mctrl,
 956         .stop_tx        = stm32_usart_stop_tx,
 957         .start_tx       = stm32_usart_start_tx,
 958         .throttle       = stm32_usart_throttle,
 959         .unthrottle     = stm32_usart_unthrottle,
 960         .stop_rx        = stm32_usart_stop_rx,
 961         .enable_ms      = stm32_usart_enable_ms,
 962         .break_ctl      = stm32_usart_break_ctl,
 963         .startup        = stm32_usart_startup,
 964         .shutdown       = stm32_usart_shutdown,
 965         .set_termios    = stm32_usart_set_termios,
 966         .pm             = stm32_usart_pm,
 967         .type           = stm32_usart_type,
 968         .release_port   = stm32_usart_release_port,
 969         .request_port   = stm32_usart_request_port,
 970         .config_port    = stm32_usart_config_port,
 971         .verify_port    = stm32_usart_verify_port,
 972 };
 973
 974 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
 975 {
 976         clk_disable_unprepare(stm32port->clk);
 977 }
 978
 979 static int stm32_usart_init_port(struct stm32_port *stm32port,
 980                                  struct platform_device *pdev)
 981 {
 982         struct uart_port *port = &stm32port->port;
 983         struct resource *res;
 984         int ret, irq;
 985
 986         irq = platform_get_irq(pdev, 0);
 987         if (irq <= 0)
 988                 return irq ? : -ENODEV;
 989
 990         port->iotype    = UPIO_MEM;
 991         port->flags     = UPF_BOOT_AUTOCONF;
 992         port->ops       = &stm32_uart_ops;
 993         port->dev       = &pdev->dev;
 994         port->fifosize  = stm32port->info->cfg.fifosize;
 995         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
 996         port->irq = irq;
 997         port->rs485_config = stm32_usart_config_rs485;
 998
 999         ret = stm32_usart_init_rs485(port, pdev);
1000         if (ret)
1001                 return ret;
1002
1003         if (stm32port->info->cfg.has_wakeup) {
1004                 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
1005                 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
1006                         return stm32port->wakeirq ? : -ENODEV;
1007         }
1008
1009         stm32port->fifoen = stm32port->info->cfg.has_fifo;
1010
1011         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012         port->membase = devm_ioremap_resource(&pdev->dev, res);
1013         if (IS_ERR(port->membase))
1014                 return PTR_ERR(port->membase);
1015         port->mapbase = res->start;
1016
1017         spin_lock_init(&port->lock);
1018
1019         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1020         if (IS_ERR(stm32port->clk))
1021                 return PTR_ERR(stm32port->clk);
1022
1023         /* Ensure that clk rate is correct by enabling the clk */
1024         ret = clk_prepare_enable(stm32port->clk);
1025         if (ret)
1026                 return ret;
1027
1028         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1029         if (!stm32port->port.uartclk) {
1030                 ret = -EINVAL;
1031                 goto err_clk;
1032         }
1033
1034         stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1035         if (IS_ERR(stm32port->gpios)) {
1036                 ret = PTR_ERR(stm32port->gpios);
1037                 goto err_clk;
1038         }
1039
1040         /*
1041          * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1042          * properties should not be specified.
1043          */
1044         if (stm32port->hw_flow_control) {
1045                 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1046                     mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1047                         dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1048                         ret = -EINVAL;
1049                         goto err_clk;
1050                 }
1051         }
1052
1053         return ret;
1054
1055 err_clk:
1056         clk_disable_unprepare(stm32port->clk);
1057
1058         return ret;
1059 }
1060
1061 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1062 {
1063         struct device_node *np = pdev->dev.of_node;
1064         int id;
1065
1066         if (!np)
1067                 return NULL;
1068
1069         id = of_alias_get_id(np, "serial");
1070         if (id < 0) {
1071                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1072                 return NULL;
1073         }
1074
1075         if (WARN_ON(id >= STM32_MAX_PORTS))
1076                 return NULL;
1077
1078         stm32_ports[id].hw_flow_control =
1079                 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1080                 of_property_read_bool (np, "uart-has-rtscts");
1081         stm32_ports[id].port.line = id;
1082         stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1083         stm32_ports[id].cr3_irq = 0;
1084         stm32_ports[id].last_res = RX_BUF_L;
1085         return &stm32_ports[id];
1086 }
1087
1088 #ifdef CONFIG_OF
1089 static const struct of_device_id stm32_match[] = {
1090         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1091         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1092         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1093         {},
1094 };
1095
1096 MODULE_DEVICE_TABLE(of, stm32_match);
1097 #endif
1098
1099 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1100                                        struct platform_device *pdev)
1101 {
1102         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1103         struct uart_port *port = &stm32port->port;
1104         struct device *dev = &pdev->dev;
1105         struct dma_slave_config config;
1106         struct dma_async_tx_descriptor *desc = NULL;
1107         int ret;
1108
1109         /* Request DMA RX channel */
1110         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1111         if (!stm32port->rx_ch) {
1112                 dev_info(dev, "rx dma alloc failed\n");
1113                 return -ENODEV;
1114         }
1115         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1116                                                &stm32port->rx_dma_buf,
1117                                                GFP_KERNEL);
1118         if (!stm32port->rx_buf) {
1119                 ret = -ENOMEM;
1120                 goto alloc_err;
1121         }
1122
1123         /* Configure DMA channel */
1124         memset(&config, 0, sizeof(config));
1125         config.src_addr = port->mapbase + ofs->rdr;
1126         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1127
1128         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1129         if (ret < 0) {
1130                 dev_err(dev, "rx dma channel config failed\n");
1131                 ret = -ENODEV;
1132                 goto config_err;
1133         }
1134
1135         /* Prepare a DMA cyclic transaction */
1136         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1137                                          stm32port->rx_dma_buf,
1138                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1139                                          DMA_PREP_INTERRUPT);
1140         if (!desc) {
1141                 dev_err(dev, "rx dma prep cyclic failed\n");
1142                 ret = -ENODEV;
1143                 goto config_err;
1144         }
1145
1146         /* No callback as dma buffer is drained on usart interrupt */
1147         desc->callback = NULL;
1148         desc->callback_param = NULL;
1149
1150         /* Push current DMA transaction in the pending queue */
1151         ret = dma_submit_error(dmaengine_submit(desc));
1152         if (ret) {
1153                 dmaengine_terminate_sync(stm32port->rx_ch);
1154                 goto config_err;
1155         }
1156
1157         /* Issue pending DMA requests */
1158         dma_async_issue_pending(stm32port->rx_ch);
1159
1160         return 0;
1161
1162 config_err:
1163         dma_free_coherent(&pdev->dev,
1164                           RX_BUF_L, stm32port->rx_buf,
1165                           stm32port->rx_dma_buf);
1166
1167 alloc_err:
1168         dma_release_channel(stm32port->rx_ch);
1169         stm32port->rx_ch = NULL;
1170
1171         return ret;
1172 }
1173
1174 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1175                                        struct platform_device *pdev)
1176 {
1177         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1178         struct uart_port *port = &stm32port->port;
1179         struct device *dev = &pdev->dev;
1180         struct dma_slave_config config;
1181         int ret;
1182
1183         stm32port->tx_dma_busy = false;
1184
1185         /* Request DMA TX channel */
1186         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1187         if (!stm32port->tx_ch) {
1188                 dev_info(dev, "tx dma alloc failed\n");
1189                 return -ENODEV;
1190         }
1191         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1192                                                &stm32port->tx_dma_buf,
1193                                                GFP_KERNEL);
1194         if (!stm32port->tx_buf) {
1195                 ret = -ENOMEM;
1196                 goto alloc_err;
1197         }
1198
1199         /* Configure DMA channel */
1200         memset(&config, 0, sizeof(config));
1201         config.dst_addr = port->mapbase + ofs->tdr;
1202         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1203
1204         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1205         if (ret < 0) {
1206                 dev_err(dev, "tx dma channel config failed\n");
1207                 ret = -ENODEV;
1208                 goto config_err;
1209         }
1210
1211         return 0;
1212
1213 config_err:
1214         dma_free_coherent(&pdev->dev,
1215                           TX_BUF_L, stm32port->tx_buf,
1216                           stm32port->tx_dma_buf);
1217
1218 alloc_err:
1219         dma_release_channel(stm32port->tx_ch);
1220         stm32port->tx_ch = NULL;
1221
1222         return ret;
1223 }
1224
1225 static int stm32_usart_serial_probe(struct platform_device *pdev)
1226 {
1227         struct stm32_port *stm32port;
1228         int ret;
1229
1230         stm32port = stm32_usart_of_get_port(pdev);
1231         if (!stm32port)
1232                 return -ENODEV;
1233
1234         stm32port->info = of_device_get_match_data(&pdev->dev);
1235         if (!stm32port->info)
1236                 return -EINVAL;
1237
1238         ret = stm32_usart_init_port(stm32port, pdev);
1239         if (ret)
1240                 return ret;
1241
1242         if (stm32port->wakeirq > 0) {
1243                 ret = device_init_wakeup(&pdev->dev, true);
1244                 if (ret)
1245                         goto err_uninit;
1246
1247                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1248                                                     stm32port->wakeirq);
1249                 if (ret)
1250                         goto err_nowup;
1251
1252                 device_set_wakeup_enable(&pdev->dev, false);
1253         }
1254
1255         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1256         if (ret)
1257                 goto err_wirq;
1258
1259         ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1260         if (ret)
1261                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1262
1263         ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1264         if (ret)
1265                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1266
1267         platform_set_drvdata(pdev, &stm32port->port);
1268
1269         pm_runtime_get_noresume(&pdev->dev);
1270         pm_runtime_set_active(&pdev->dev);
1271         pm_runtime_enable(&pdev->dev);
1272         pm_runtime_put_sync(&pdev->dev);
1273
1274         return 0;
1275
1276 err_wirq:
1277         if (stm32port->wakeirq > 0)
1278                 dev_pm_clear_wake_irq(&pdev->dev);
1279
1280 err_nowup:
1281         if (stm32port->wakeirq > 0)
1282                 device_init_wakeup(&pdev->dev, false);
1283
1284 err_uninit:
1285         stm32_usart_deinit_port(stm32port);
1286
1287         return ret;
1288 }
1289
1290 static int stm32_usart_serial_remove(struct platform_device *pdev)
1291 {
1292         struct uart_port *port = platform_get_drvdata(pdev);
1293         struct stm32_port *stm32_port = to_stm32_port(port);
1294         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1295         int err;
1296
1297         pm_runtime_get_sync(&pdev->dev);
1298
1299         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1300
1301         if (stm32_port->rx_ch)
1302                 dma_release_channel(stm32_port->rx_ch);
1303
1304         if (stm32_port->rx_dma_buf)
1305                 dma_free_coherent(&pdev->dev,
1306                                   RX_BUF_L, stm32_port->rx_buf,
1307                                   stm32_port->rx_dma_buf);
1308
1309         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1310
1311         if (stm32_port->tx_ch)
1312                 dma_release_channel(stm32_port->tx_ch);
1313
1314         if (stm32_port->tx_dma_buf)
1315                 dma_free_coherent(&pdev->dev,
1316                                   TX_BUF_L, stm32_port->tx_buf,
1317                                   stm32_port->tx_dma_buf);
1318
1319         if (stm32_port->wakeirq > 0) {
1320                 dev_pm_clear_wake_irq(&pdev->dev);
1321                 device_init_wakeup(&pdev->dev, false);
1322         }
1323
1324         stm32_usart_deinit_port(stm32_port);
1325
1326         err = uart_remove_one_port(&stm32_usart_driver, port);
1327
1328         pm_runtime_disable(&pdev->dev);
1329         pm_runtime_put_noidle(&pdev->dev);
1330
1331         return err;
1332 }
1333
1334 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1335 static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1336 {
1337         struct stm32_port *stm32_port = to_stm32_port(port);
1338         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1339
1340         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1341                 cpu_relax();
1342
1343         writel_relaxed(ch, port->membase + ofs->tdr);
1344 }
1345
1346 static void stm32_usart_console_write(struct console *co, const char *s,
1347                                       unsigned int cnt)
1348 {
1349         struct uart_port *port = &stm32_ports[co->index].port;
1350         struct stm32_port *stm32_port = to_stm32_port(port);
1351         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1352         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1353         unsigned long flags;
1354         u32 old_cr1, new_cr1;
1355         int locked = 1;
1356
1357         local_irq_save(flags);
1358         if (port->sysrq)
1359                 locked = 0;
1360         else if (oops_in_progress)
1361                 locked = spin_trylock(&port->lock);
1362         else
1363                 spin_lock(&port->lock);
1364
1365         /* Save and disable interrupts, enable the transmitter */
1366         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1367         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1368         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1369         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1370
1371         uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1372
1373         /* Restore interrupt state */
1374         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1375
1376         if (locked)
1377                 spin_unlock(&port->lock);
1378         local_irq_restore(flags);
1379 }
1380
1381 static int stm32_usart_console_setup(struct console *co, char *options)
1382 {
1383         struct stm32_port *stm32port;
1384         int baud = 9600;
1385         int bits = 8;
1386         int parity = 'n';
1387         int flow = 'n';
1388
1389         if (co->index >= STM32_MAX_PORTS)
1390                 return -ENODEV;
1391
1392         stm32port = &stm32_ports[co->index];
1393
1394         /*
1395          * This driver does not support early console initialization
1396          * (use ARM early printk support instead), so we only expect
1397          * this to be called during the uart port registration when the
1398          * driver gets probed and the port should be mapped at that point.
1399          */
1400         if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1401                 return -ENXIO;
1402
1403         if (options)
1404                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1405
1406         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1407 }
1408
1409 static struct console stm32_console = {
1410         .name           = STM32_SERIAL_NAME,
1411         .device         = uart_console_device,
1412         .write          = stm32_usart_console_write,
1413         .setup          = stm32_usart_console_setup,
1414         .flags          = CON_PRINTBUFFER,
1415         .index          = -1,
1416         .data           = &stm32_usart_driver,
1417 };
1418
1419 #define STM32_SERIAL_CONSOLE (&stm32_console)
1420
1421 #else
1422 #define STM32_SERIAL_CONSOLE NULL
1423 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1424
1425 static struct uart_driver stm32_usart_driver = {
1426         .driver_name    = DRIVER_NAME,
1427         .dev_name       = STM32_SERIAL_NAME,
1428         .major          = 0,
1429         .minor          = 0,
1430         .nr             = STM32_MAX_PORTS,
1431         .cons           = STM32_SERIAL_CONSOLE,
1432 };
1433
1434 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1435                                                         bool enable)
1436 {
1437         struct stm32_port *stm32_port = to_stm32_port(port);
1438         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1439         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1440         u32 val;
1441
1442         if (stm32_port->wakeirq <= 0)
1443                 return;
1444
1445         if (enable) {
1446                 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1447                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1448                 val = readl_relaxed(port->membase + ofs->cr3);
1449                 val &= ~USART_CR3_WUS_MASK;
1450                 /* Enable Wake up interrupt from low power on start bit */
1451                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1452                 writel_relaxed(val, port->membase + ofs->cr3);
1453                 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1454         } else {
1455                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1456         }
1457 }
1458
1459 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1460 {
1461         struct uart_port *port = dev_get_drvdata(dev);
1462
1463         uart_suspend_port(&stm32_usart_driver, port);
1464
1465         if (device_may_wakeup(dev))
1466                 stm32_usart_serial_en_wakeup(port, true);
1467         else
1468                 stm32_usart_serial_en_wakeup(port, false);
1469
1470         /*
1471          * When "no_console_suspend" is enabled, keep the pinctrl default state
1472          * and rely on bootloader stage to restore this state upon resume.
1473          * Otherwise, apply the idle or sleep states depending on wakeup
1474          * capabilities.
1475          */
1476         if (console_suspend_enabled || !uart_console(port)) {
1477                 if (device_may_wakeup(dev))
1478                         pinctrl_pm_select_idle_state(dev);
1479                 else
1480                         pinctrl_pm_select_sleep_state(dev);
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1487 {
1488         struct uart_port *port = dev_get_drvdata(dev);
1489
1490         pinctrl_pm_select_default_state(dev);
1491
1492         if (device_may_wakeup(dev))
1493                 stm32_usart_serial_en_wakeup(port, false);
1494
1495         return uart_resume_port(&stm32_usart_driver, port);
1496 }
1497
1498 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1499 {
1500         struct uart_port *port = dev_get_drvdata(dev);
1501         struct stm32_port *stm32port = container_of(port,
1502                         struct stm32_port, port);
1503
1504         clk_disable_unprepare(stm32port->clk);
1505
1506         return 0;
1507 }
1508
1509 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1510 {
1511         struct uart_port *port = dev_get_drvdata(dev);
1512         struct stm32_port *stm32port = container_of(port,
1513                         struct stm32_port, port);
1514
1515         return clk_prepare_enable(stm32port->clk);
1516 }
1517
1518 static const struct dev_pm_ops stm32_serial_pm_ops = {
1519         SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1520                            stm32_usart_runtime_resume, NULL)
1521         SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1522                                 stm32_usart_serial_resume)
1523 };
1524
1525 static struct platform_driver stm32_serial_driver = {
1526         .probe          = stm32_usart_serial_probe,
1527         .remove         = stm32_usart_serial_remove,
1528         .driver = {
1529                 .name   = DRIVER_NAME,
1530                 .pm     = &stm32_serial_pm_ops,
1531                 .of_match_table = of_match_ptr(stm32_match),
1532         },
1533 };
1534
1535 static int __init stm32_usart_init(void)
1536 {
1537         static char banner[] __initdata = "STM32 USART driver initialized";
1538         int ret;
1539
1540         pr_info("%s\n", banner);
1541
1542         ret = uart_register_driver(&stm32_usart_driver);
1543         if (ret)
1544                 return ret;
1545
1546         ret = platform_driver_register(&stm32_serial_driver);
1547         if (ret)
1548                 uart_unregister_driver(&stm32_usart_driver);
1549
1550         return ret;
1551 }
1552
1553 static void __exit stm32_usart_exit(void)
1554 {
1555         platform_driver_unregister(&stm32_serial_driver);
1556         uart_unregister_driver(&stm32_usart_driver);
1557 }
1558
1559 module_init(stm32_usart_init);
1560 module_exit(stm32_usart_exit);
1561
1562 MODULE_ALIAS("platform:" DRIVER_NAME);
1563 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1564 MODULE_LICENSE("GPL v2");