drivers/gpu/drm/panthor/panthor_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 or MIT */
   2 /* Copyright 2018 Marty E. Plummer <[email protected]> */
   3 /* Copyright 2019 Linaro, Ltd, Rob Herring <[email protected]> */
   4 /* Copyright 2023 Collabora ltd. */
   5 /*
   6  * Register definitions based on mali_kbase_gpu_regmap.h and
   7  * mali_kbase_gpu_regmap_csf.h
   8  * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
   9  */
  10 #ifndef __PANTHOR_REGS_H__
  11 #define __PANTHOR_REGS_H__
  12
  13 #define GPU_ID                                          0x0
  14 #define   GPU_ARCH_MAJOR(x)                             ((x) >> 28)
  15 #define   GPU_ARCH_MINOR(x)                             (((x) & GENMASK(27, 24)) >> 24)
  16 #define   GPU_ARCH_REV(x)                               (((x) & GENMASK(23, 20)) >> 20)
  17 #define   GPU_PROD_MAJOR(x)                             (((x) & GENMASK(19, 16)) >> 16)
  18 #define   GPU_VER_MAJOR(x)                              (((x) & GENMASK(15, 12)) >> 12)
  19 #define   GPU_VER_MINOR(x)                              (((x) & GENMASK(11, 4)) >> 4)
  20 #define   GPU_VER_STATUS(x)                             ((x) & GENMASK(3, 0))
  21
  22 #define GPU_L2_FEATURES                                 0x4
  23 #define  GPU_L2_FEATURES_LINE_SIZE(x)                   (1 << ((x) & GENMASK(7, 0)))
  24
  25 #define GPU_CORE_FEATURES                               0x8
  26
  27 #define GPU_TILER_FEATURES                              0xC
  28 #define GPU_MEM_FEATURES                                0x10
  29 #define   GROUPS_L2_COHERENT                            BIT(0)
  30
  31 #define GPU_MMU_FEATURES                                0x14
  32 #define  GPU_MMU_FEATURES_VA_BITS(x)                    ((x) & GENMASK(7, 0))
  33 #define  GPU_MMU_FEATURES_PA_BITS(x)                    (((x) >> 8) & GENMASK(7, 0))
  34 #define GPU_AS_PRESENT                                  0x18
  35 #define GPU_CSF_ID                                      0x1C
  36
  37 #define GPU_INT_RAWSTAT                                 0x20
  38 #define GPU_INT_CLEAR                                   0x24
  39 #define GPU_INT_MASK                                    0x28
  40 #define GPU_INT_STAT                                    0x2c
  41 #define   GPU_IRQ_FAULT                                 BIT(0)
  42 #define   GPU_IRQ_PROTM_FAULT                           BIT(1)
  43 #define   GPU_IRQ_RESET_COMPLETED                       BIT(8)
  44 #define   GPU_IRQ_POWER_CHANGED                         BIT(9)
  45 #define   GPU_IRQ_POWER_CHANGED_ALL                     BIT(10)
  46 #define   GPU_IRQ_CLEAN_CACHES_COMPLETED                BIT(17)
  47 #define   GPU_IRQ_DOORBELL_MIRROR                       BIT(18)
  48 #define   GPU_IRQ_MCU_STATUS_CHANGED                    BIT(19)
  49 #define GPU_CMD                                         0x30
  50 #define   GPU_CMD_DEF(type, payload)                    ((type) | ((payload) << 8))
  51 #define   GPU_SOFT_RESET                                GPU_CMD_DEF(1, 1)
  52 #define   GPU_HARD_RESET                                GPU_CMD_DEF(1, 2)
  53 #define   CACHE_CLEAN                                   BIT(0)
  54 #define   CACHE_INV                                     BIT(1)
  55 #define   GPU_FLUSH_CACHES(l2, lsc, oth)                \
  56           GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8))
  57
  58 #define GPU_STATUS                                      0x34
  59 #define   GPU_STATUS_ACTIVE                             BIT(0)
  60 #define   GPU_STATUS_PWR_ACTIVE                         BIT(1)
  61 #define   GPU_STATUS_PAGE_FAULT                         BIT(4)
  62 #define   GPU_STATUS_PROTM_ACTIVE                       BIT(7)
  63 #define   GPU_STATUS_DBG_ENABLED                        BIT(8)
  64
  65 #define GPU_FAULT_STATUS                                0x3C
  66 #define GPU_FAULT_ADDR_LO                               0x40
  67 #define GPU_FAULT_ADDR_HI                               0x44
  68
  69 #define GPU_PWR_KEY                                     0x50
  70 #define  GPU_PWR_KEY_UNLOCK                             0x2968A819
  71 #define GPU_PWR_OVERRIDE0                               0x54
  72 #define GPU_PWR_OVERRIDE1                               0x58
  73
  74 #define GPU_TIMESTAMP_OFFSET_LO                         0x88
  75 #define GPU_TIMESTAMP_OFFSET_HI                         0x8C
  76 #define GPU_CYCLE_COUNT_LO                              0x90
  77 #define GPU_CYCLE_COUNT_HI                              0x94
  78 #define GPU_TIMESTAMP_LO                                0x98
  79 #define GPU_TIMESTAMP_HI                                0x9C
  80
  81 #define GPU_THREAD_MAX_THREADS                          0xA0
  82 #define GPU_THREAD_MAX_WORKGROUP_SIZE                   0xA4
  83 #define GPU_THREAD_MAX_BARRIER_SIZE                     0xA8
  84 #define GPU_THREAD_FEATURES                             0xAC
  85
  86 #define GPU_TEXTURE_FEATURES(n)                         (0xB0 + ((n) * 4))
  87
  88 #define GPU_SHADER_PRESENT_LO                           0x100
  89 #define GPU_SHADER_PRESENT_HI                           0x104
  90 #define GPU_TILER_PRESENT_LO                            0x110
  91 #define GPU_TILER_PRESENT_HI                            0x114
  92 #define GPU_L2_PRESENT_LO                               0x120
  93 #define GPU_L2_PRESENT_HI                               0x124
  94
  95 #define SHADER_READY_LO                                 0x140
  96 #define SHADER_READY_HI                                 0x144
  97 #define TILER_READY_LO                                  0x150
  98 #define TILER_READY_HI                                  0x154
  99 #define L2_READY_LO                                     0x160
 100 #define L2_READY_HI                                     0x164
 101
 102 #define SHADER_PWRON_LO                                 0x180
 103 #define SHADER_PWRON_HI                                 0x184
 104 #define TILER_PWRON_LO                                  0x190
 105 #define TILER_PWRON_HI                                  0x194
 106 #define L2_PWRON_LO                                     0x1A0
 107 #define L2_PWRON_HI                                     0x1A4
 108
 109 #define SHADER_PWROFF_LO                                0x1C0
 110 #define SHADER_PWROFF_HI                                0x1C4
 111 #define TILER_PWROFF_LO                                 0x1D0
 112 #define TILER_PWROFF_HI                                 0x1D4
 113 #define L2_PWROFF_LO                                    0x1E0
 114 #define L2_PWROFF_HI                                    0x1E4
 115
 116 #define SHADER_PWRTRANS_LO                              0x200
 117 #define SHADER_PWRTRANS_HI                              0x204
 118 #define TILER_PWRTRANS_LO                               0x210
 119 #define TILER_PWRTRANS_HI                               0x214
 120 #define L2_PWRTRANS_LO                                  0x220
 121 #define L2_PWRTRANS_HI                                  0x224
 122
 123 #define SHADER_PWRACTIVE_LO                             0x240
 124 #define SHADER_PWRACTIVE_HI                             0x244
 125 #define TILER_PWRACTIVE_LO                              0x250
 126 #define TILER_PWRACTIVE_HI                              0x254
 127 #define L2_PWRACTIVE_LO                                 0x260
 128 #define L2_PWRACTIVE_HI                                 0x264
 129
 130 #define GPU_REVID                                       0x280
 131
 132 #define GPU_COHERENCY_FEATURES                          0x300
 133 #define GPU_COHERENCY_PROT_BIT(name)                    BIT(GPU_COHERENCY_  ## name)
 134
 135 #define GPU_COHERENCY_PROTOCOL                          0x304
 136 #define   GPU_COHERENCY_ACE                             0
 137 #define   GPU_COHERENCY_ACE_LITE                        1
 138 #define   GPU_COHERENCY_NONE                            31
 139
 140 #define MCU_CONTROL                                     0x700
 141 #define MCU_CONTROL_ENABLE                              1
 142 #define MCU_CONTROL_AUTO                                2
 143 #define MCU_CONTROL_DISABLE                             0
 144
 145 #define MCU_STATUS                                      0x704
 146 #define MCU_STATUS_DISABLED                             0
 147 #define MCU_STATUS_ENABLED                              1
 148 #define MCU_STATUS_HALT                                 2
 149 #define MCU_STATUS_FATAL                                3
 150
 151 /* Job Control regs */
 152 #define JOB_INT_RAWSTAT                                 0x1000
 153 #define JOB_INT_CLEAR                                   0x1004
 154 #define JOB_INT_MASK                                    0x1008
 155 #define JOB_INT_STAT                                    0x100c
 156 #define   JOB_INT_GLOBAL_IF                             BIT(31)
 157 #define   JOB_INT_CSG_IF(x)                             BIT(x)
 158
 159 /* MMU regs */
 160 #define MMU_INT_RAWSTAT                                 0x2000
 161 #define MMU_INT_CLEAR                                   0x2004
 162 #define MMU_INT_MASK                                    0x2008
 163 #define MMU_INT_STAT                                    0x200c
 164
 165 /* AS_COMMAND register commands */
 166
 167 #define MMU_BASE                                        0x2400
 168 #define MMU_AS_SHIFT                                    6
 169 #define MMU_AS(as)                                      (MMU_BASE + ((as) << MMU_AS_SHIFT))
 170
 171 #define AS_TRANSTAB_LO(as)                              (MMU_AS(as) + 0x0)
 172 #define AS_TRANSTAB_HI(as)                              (MMU_AS(as) + 0x4)
 173 #define AS_MEMATTR_LO(as)                               (MMU_AS(as) + 0x8)
 174 #define AS_MEMATTR_HI(as)                               (MMU_AS(as) + 0xC)
 175 #define   AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL           (2 << 2)
 176 #define   AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r)     ((3 << 2) | \
 177                                                          ((w) ? BIT(0) : 0) | \
 178                                                          ((r) ? BIT(1) : 0))
 179 #define   AS_MEMATTR_AARCH64_SH_MIDGARD_INNER           (0 << 4)
 180 #define   AS_MEMATTR_AARCH64_SH_CPU_INNER               (1 << 4)
 181 #define   AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH    (2 << 4)
 182 #define   AS_MEMATTR_AARCH64_SHARED                     (0 << 6)
 183 #define   AS_MEMATTR_AARCH64_INNER_OUTER_NC             (1 << 6)
 184 #define   AS_MEMATTR_AARCH64_INNER_OUTER_WB             (2 << 6)
 185 #define   AS_MEMATTR_AARCH64_FAULT                      (3 << 6)
 186 #define AS_LOCKADDR_LO(as)                              (MMU_AS(as) + 0x10)
 187 #define AS_LOCKADDR_HI(as)                              (MMU_AS(as) + 0x14)
 188 #define AS_COMMAND(as)                                  (MMU_AS(as) + 0x18)
 189 #define   AS_COMMAND_NOP                                0
 190 #define   AS_COMMAND_UPDATE                             1
 191 #define   AS_COMMAND_LOCK                               2
 192 #define   AS_COMMAND_UNLOCK                             3
 193 #define   AS_COMMAND_FLUSH_PT                           4
 194 #define   AS_COMMAND_FLUSH_MEM                          5
 195 #define   AS_LOCK_REGION_MIN_SIZE                       (1ULL << 15)
 196 #define AS_FAULTSTATUS(as)                              (MMU_AS(as) + 0x1C)
 197 #define  AS_FAULTSTATUS_ACCESS_TYPE_MASK                (0x3 << 8)
 198 #define  AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC              (0x0 << 8)
 199 #define  AS_FAULTSTATUS_ACCESS_TYPE_EX                  (0x1 << 8)
 200 #define  AS_FAULTSTATUS_ACCESS_TYPE_READ                (0x2 << 8)
 201 #define  AS_FAULTSTATUS_ACCESS_TYPE_WRITE               (0x3 << 8)
 202 #define AS_FAULTADDRESS_LO(as)                          (MMU_AS(as) + 0x20)
 203 #define AS_FAULTADDRESS_HI(as)                          (MMU_AS(as) + 0x24)
 204 #define AS_STATUS(as)                                   (MMU_AS(as) + 0x28)
 205 #define   AS_STATUS_AS_ACTIVE                           BIT(0)
 206 #define AS_TRANSCFG_LO(as)                              (MMU_AS(as) + 0x30)
 207 #define AS_TRANSCFG_HI(as)                              (MMU_AS(as) + 0x34)
 208 #define   AS_TRANSCFG_ADRMODE_UNMAPPED                  (1 << 0)
 209 #define   AS_TRANSCFG_ADRMODE_IDENTITY                  (2 << 0)
 210 #define   AS_TRANSCFG_ADRMODE_AARCH64_4K                (6 << 0)
 211 #define   AS_TRANSCFG_ADRMODE_AARCH64_64K               (8 << 0)
 212 #define   AS_TRANSCFG_INA_BITS(x)                       ((x) << 6)
 213 #define   AS_TRANSCFG_OUTA_BITS(x)                      ((x) << 14)
 214 #define   AS_TRANSCFG_SL_CONCAT                         BIT(22)
 215 #define   AS_TRANSCFG_PTW_MEMATTR_NC                    (1 << 24)
 216 #define   AS_TRANSCFG_PTW_MEMATTR_WB                    (2 << 24)
 217 #define   AS_TRANSCFG_PTW_SH_NS                         (0 << 28)
 218 #define   AS_TRANSCFG_PTW_SH_OS                         (2 << 28)
 219 #define   AS_TRANSCFG_PTW_SH_IS                         (3 << 28)
 220 #define   AS_TRANSCFG_PTW_RA                            BIT(30)
 221 #define   AS_TRANSCFG_DISABLE_HIER_AP                   BIT(33)
 222 #define   AS_TRANSCFG_DISABLE_AF_FAULT                  BIT(34)
 223 #define   AS_TRANSCFG_WXN                               BIT(35)
 224 #define   AS_TRANSCFG_XREADABLE                         BIT(36)
 225 #define AS_FAULTEXTRA_LO(as)                            (MMU_AS(as) + 0x38)
 226 #define AS_FAULTEXTRA_HI(as)                            (MMU_AS(as) + 0x3C)
 227
 228 #define CSF_GPU_LATEST_FLUSH_ID                         0x10000
 229
 230 #define CSF_DOORBELL(i)                                 (0x80000 + ((i) * 0x10000))
 231 #define CSF_GLB_DOORBELL_ID                             0
 232
 233 #define gpu_write(dev, reg, data) \
 234         writel(data, (dev)->iomem + (reg))
 235
 236 #define gpu_read(dev, reg) \
 237         readl((dev)->iomem + (reg))
 238
 239 #endif