drivers/gpu/drm/omapdrm/omap_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/of.h>
  10 #include <linux/sort.h>
  11 #include <linux/sys_soc.h>
  12
  13 #include <drm/drm_atomic.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_bridge.h>
  16 #include <drm/drm_bridge_connector.h>
  17 #include <drm/drm_drv.h>
  18 #include <drm/drm_file.h>
  19 #include <drm/drm_ioctl.h>
  20 #include <drm/drm_panel.h>
  21 #include <drm/drm_prime.h>
  22 #include <drm/drm_probe_helper.h>
  23 #include <drm/drm_vblank.h>
  24
  25 #include "omap_dmm_tiler.h"
  26 #include "omap_drv.h"
  27 #include "omap_fbdev.h"
  28
  29 #define DRIVER_NAME             MODULE_NAME
  30 #define DRIVER_DESC             "OMAP DRM"
  31 #define DRIVER_MAJOR            1
  32 #define DRIVER_MINOR            0
  33 #define DRIVER_PATCHLEVEL       0
  34
  35 /*
  36  * mode config funcs
  37  */
  38
  39 /* Notes about mapping DSS and DRM entities:
  40  *    CRTC:        overlay
  41  *    encoder:     manager.. with some extension to allow one primary CRTC
  42  *                 and zero or more video CRTC's to be mapped to one encoder?
  43  *    connector:   dssdev.. manager can be attached/detached from different
  44  *                 devices
  45  */
  46
  47 static void omap_atomic_wait_for_completion(struct drm_device *dev,
  48                                             struct drm_atomic_state *old_state)
  49 {
  50         struct drm_crtc_state *new_crtc_state;
  51         struct drm_crtc *crtc;
  52         unsigned int i;
  53         int ret;
  54
  55         for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  56                 if (!new_crtc_state->active)
  57                         continue;
  58
  59                 ret = omap_crtc_wait_pending(crtc);
  60
  61                 if (!ret)
  62                         dev_warn(dev->dev,
  63                                  "atomic complete timeout (pipe %u)!\n", i);
  64         }
  65 }
  66
  67 static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  68 {
  69         struct drm_device *dev = old_state->dev;
  70         struct omap_drm_private *priv = dev->dev_private;
  71
  72         dispc_runtime_get(priv->dispc);
  73
  74         /* Apply the atomic update. */
  75         drm_atomic_helper_commit_modeset_disables(dev, old_state);
  76
  77         if (priv->omaprev != 0x3430) {
  78                 /* With the current dss dispc implementation we have to enable
  79                  * the new modeset before we can commit planes. The dispc ovl
  80                  * configuration relies on the video mode configuration been
  81                  * written into the HW when the ovl configuration is
  82                  * calculated.
  83                  *
  84                  * This approach is not ideal because after a mode change the
  85                  * plane update is executed only after the first vblank
  86                  * interrupt. The dispc implementation should be fixed so that
  87                  * it is able use uncommitted drm state information.
  88                  */
  89                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
  90                 omap_atomic_wait_for_completion(dev, old_state);
  91
  92                 drm_atomic_helper_commit_planes(dev, old_state, 0);
  93
  94                 drm_atomic_helper_commit_hw_done(old_state);
  95         } else {
  96                 /*
  97                  * OMAP3 DSS seems to have issues with the work-around above,
  98                  * resulting in endless sync losts if a crtc is enabled without
  99                  * a plane. For now, skip the WA for OMAP3.
 100                  */
 101                 drm_atomic_helper_commit_planes(dev, old_state, 0);
 102
 103                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
 104
 105                 drm_atomic_helper_commit_hw_done(old_state);
 106         }
 107
 108         /*
 109          * Wait for completion of the page flips to ensure that old buffers
 110          * can't be touched by the hardware anymore before cleaning up planes.
 111          */
 112         omap_atomic_wait_for_completion(dev, old_state);
 113
 114         drm_atomic_helper_cleanup_planes(dev, old_state);
 115
 116         dispc_runtime_put(priv->dispc);
 117 }
 118
 119 static int drm_atomic_state_normalized_zpos_cmp(const void *a, const void *b)
 120 {
 121         const struct drm_plane_state *sa = *(struct drm_plane_state **)a;
 122         const struct drm_plane_state *sb = *(struct drm_plane_state **)b;
 123
 124         if (sa->normalized_zpos != sb->normalized_zpos)
 125                 return sa->normalized_zpos - sb->normalized_zpos;
 126         else
 127                 return sa->plane->base.id - sb->plane->base.id;
 128 }
 129
 130 /*
 131  * This replaces the drm_atomic_normalize_zpos to handle the dual overlay case.
 132  *
 133  * Since both halves need to be 'appear' side by side the zpos is
 134  * recalculated when dealing with dual overlay cases so that the other
 135  * planes zpos is consistent.
 136  */
 137 static int omap_atomic_update_normalize_zpos(struct drm_device *dev,
 138                                              struct drm_atomic_state *state)
 139 {
 140         struct drm_crtc *crtc;
 141         struct drm_crtc_state *old_state, *new_state;
 142         struct drm_plane *plane;
 143         int c, i, n, inc;
 144         int total_planes = dev->mode_config.num_total_plane;
 145         struct drm_plane_state **states;
 146         int ret = 0;
 147
 148         states = kmalloc_array(total_planes, sizeof(*states), GFP_KERNEL);
 149         if (!states)
 150                 return -ENOMEM;
 151
 152         for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, c) {
 153                 if (old_state->plane_mask == new_state->plane_mask &&
 154                     !new_state->zpos_changed)
 155                         continue;
 156
 157                 /* Reset plane increment and index value for every crtc */
 158                 n = 0;
 159
 160                 /*
 161                  * Normalization process might create new states for planes
 162                  * which normalized_zpos has to be recalculated.
 163                  */
 164                 drm_for_each_plane_mask(plane, dev, new_state->plane_mask) {
 165                         struct drm_plane_state *plane_state =
 166                                 drm_atomic_get_plane_state(new_state->state,
 167                                                            plane);
 168                         if (IS_ERR(plane_state)) {
 169                                 ret = PTR_ERR(plane_state);
 170                                 goto done;
 171                         }
 172                         states[n++] = plane_state;
 173                 }
 174
 175                 sort(states, n, sizeof(*states),
 176                      drm_atomic_state_normalized_zpos_cmp, NULL);
 177
 178                 for (i = 0, inc = 0; i < n; i++) {
 179                         plane = states[i]->plane;
 180
 181                         states[i]->normalized_zpos = i + inc;
 182                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] updated normalized zpos value %d\n",
 183                                          plane->base.id, plane->name,
 184                                          states[i]->normalized_zpos);
 185
 186                         if (is_omap_plane_dual_overlay(states[i]))
 187                                 inc++;
 188                 }
 189                 new_state->zpos_changed = true;
 190         }
 191
 192 done:
 193         kfree(states);
 194         return ret;
 195 }
 196
 197 static int omap_atomic_check(struct drm_device *dev,
 198                              struct drm_atomic_state *state)
 199 {
 200         int ret;
 201
 202         ret = drm_atomic_helper_check(dev, state);
 203         if (ret)
 204                 return ret;
 205
 206         if (dev->mode_config.normalize_zpos) {
 207                 ret = omap_atomic_update_normalize_zpos(dev, state);
 208                 if (ret)
 209                         return ret;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
 216         .atomic_commit_tail = omap_atomic_commit_tail,
 217 };
 218
 219 static const struct drm_mode_config_funcs omap_mode_config_funcs = {
 220         .fb_create = omap_framebuffer_create,
 221         .atomic_check = omap_atomic_check,
 222         .atomic_commit = drm_atomic_helper_commit,
 223 };
 224
 225 /* Global/shared object state funcs */
 226
 227 /*
 228  * This is a helper that returns the private state currently in operation.
 229  * Note that this would return the "old_state" if called in the atomic check
 230  * path, and the "new_state" after the atomic swap has been done.
 231  */
 232 struct omap_global_state *
 233 omap_get_existing_global_state(struct omap_drm_private *priv)
 234 {
 235         return to_omap_global_state(priv->glob_obj.state);
 236 }
 237
 238 /*
 239  * This acquires the modeset lock set aside for global state, creates
 240  * a new duplicated private object state.
 241  */
 242 struct omap_global_state *__must_check
 243 omap_get_global_state(struct drm_atomic_state *s)
 244 {
 245         struct omap_drm_private *priv = s->dev->dev_private;
 246         struct drm_private_state *priv_state;
 247
 248         priv_state = drm_atomic_get_private_obj_state(s, &priv->glob_obj);
 249         if (IS_ERR(priv_state))
 250                 return ERR_CAST(priv_state);
 251
 252         return to_omap_global_state(priv_state);
 253 }
 254
 255 static struct drm_private_state *
 256 omap_global_duplicate_state(struct drm_private_obj *obj)
 257 {
 258         struct omap_global_state *state;
 259
 260         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 261         if (!state)
 262                 return NULL;
 263
 264         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 265
 266         return &state->base;
 267 }
 268
 269 static void omap_global_destroy_state(struct drm_private_obj *obj,
 270                                       struct drm_private_state *state)
 271 {
 272         struct omap_global_state *omap_state = to_omap_global_state(state);
 273
 274         kfree(omap_state);
 275 }
 276
 277 static const struct drm_private_state_funcs omap_global_state_funcs = {
 278         .atomic_duplicate_state = omap_global_duplicate_state,
 279         .atomic_destroy_state = omap_global_destroy_state,
 280 };
 281
 282 static int omap_global_obj_init(struct drm_device *dev)
 283 {
 284         struct omap_drm_private *priv = dev->dev_private;
 285         struct omap_global_state *state;
 286
 287         state = kzalloc(sizeof(*state), GFP_KERNEL);
 288         if (!state)
 289                 return -ENOMEM;
 290
 291         drm_atomic_private_obj_init(dev, &priv->glob_obj, &state->base,
 292                                     &omap_global_state_funcs);
 293         return 0;
 294 }
 295
 296 static void omap_global_obj_fini(struct omap_drm_private *priv)
 297 {
 298         drm_atomic_private_obj_fini(&priv->glob_obj);
 299 }
 300
 301 static void omap_disconnect_pipelines(struct drm_device *ddev)
 302 {
 303         struct omap_drm_private *priv = ddev->dev_private;
 304         unsigned int i;
 305
 306         for (i = 0; i < priv->num_pipes; i++) {
 307                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 308
 309                 omapdss_device_disconnect(priv->dss, pipe->output);
 310
 311                 omapdss_device_put(pipe->output);
 312                 pipe->output = NULL;
 313         }
 314
 315         memset(&priv->channels, 0, sizeof(priv->channels));
 316
 317         priv->num_pipes = 0;
 318 }
 319
 320 static int omap_connect_pipelines(struct drm_device *ddev)
 321 {
 322         struct omap_drm_private *priv = ddev->dev_private;
 323         struct omap_dss_device *output = NULL;
 324         int r;
 325
 326         for_each_dss_output(output) {
 327                 r = omapdss_device_connect(priv->dss, output);
 328                 if (r == -EPROBE_DEFER) {
 329                         omapdss_device_put(output);
 330                         return r;
 331                 } else if (r) {
 332                         dev_warn(output->dev, "could not connect output %s\n",
 333                                  output->name);
 334                 } else {
 335                         struct omap_drm_pipeline *pipe;
 336
 337                         pipe = &priv->pipes[priv->num_pipes++];
 338                         pipe->output = omapdss_device_get(output);
 339
 340                         if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
 341                                 /* To balance the 'for_each_dss_output' loop */
 342                                 omapdss_device_put(output);
 343                                 break;
 344                         }
 345                 }
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int omap_compare_pipelines(const void *a, const void *b)
 352 {
 353         const struct omap_drm_pipeline *pipe1 = a;
 354         const struct omap_drm_pipeline *pipe2 = b;
 355
 356         if (pipe1->alias_id > pipe2->alias_id)
 357                 return 1;
 358         else if (pipe1->alias_id < pipe2->alias_id)
 359                 return -1;
 360         return 0;
 361 }
 362
 363 static int omap_modeset_init_properties(struct drm_device *dev)
 364 {
 365         struct omap_drm_private *priv = dev->dev_private;
 366         unsigned int num_planes = dispc_get_num_ovls(priv->dispc);
 367
 368         priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
 369                                                       num_planes - 1);
 370         if (!priv->zorder_prop)
 371                 return -ENOMEM;
 372
 373         return 0;
 374 }
 375
 376 static int omap_display_id(struct omap_dss_device *output)
 377 {
 378         struct device_node *node = NULL;
 379
 380         if (output->bridge) {
 381                 struct drm_bridge *bridge = output->bridge;
 382
 383                 while (drm_bridge_get_next_bridge(bridge))
 384                         bridge = drm_bridge_get_next_bridge(bridge);
 385
 386                 node = bridge->of_node;
 387         }
 388
 389         return node ? of_alias_get_id(node, "display") : -ENODEV;
 390 }
 391
 392 static int omap_modeset_init(struct drm_device *dev)
 393 {
 394         struct omap_drm_private *priv = dev->dev_private;
 395         int num_ovls = dispc_get_num_ovls(priv->dispc);
 396         int num_mgrs = dispc_get_num_mgrs(priv->dispc);
 397         unsigned int i;
 398         int ret;
 399         u32 plane_crtc_mask;
 400
 401         if (!omapdss_stack_is_ready())
 402                 return -EPROBE_DEFER;
 403
 404         ret = omap_modeset_init_properties(dev);
 405         if (ret < 0)
 406                 return ret;
 407
 408         /*
 409          * This function creates exactly one connector, encoder, crtc,
 410          * and primary plane per each connected dss-device. Each
 411          * connector->encoder->crtc chain is expected to be separate
 412          * and each crtc is connect to a single dss-channel. If the
 413          * configuration does not match the expectations or exceeds
 414          * the available resources, the configuration is rejected.
 415          */
 416         ret = omap_connect_pipelines(dev);
 417         if (ret < 0)
 418                 return ret;
 419
 420         if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
 421                 dev_err(dev->dev, "%s(): Too many connected displays\n",
 422                         __func__);
 423                 return -EINVAL;
 424         }
 425
 426         /* Create all planes first. They can all be put to any CRTC. */
 427         plane_crtc_mask = (1 << priv->num_pipes) - 1;
 428
 429         for (i = 0; i < num_ovls; i++) {
 430                 enum drm_plane_type type = i < priv->num_pipes
 431                                          ? DRM_PLANE_TYPE_PRIMARY
 432                                          : DRM_PLANE_TYPE_OVERLAY;
 433                 struct drm_plane *plane;
 434
 435                 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
 436                         return -EINVAL;
 437
 438                 plane = omap_plane_init(dev, i, type, plane_crtc_mask);
 439                 if (IS_ERR(plane))
 440                         return PTR_ERR(plane);
 441
 442                 priv->planes[priv->num_planes++] = plane;
 443         }
 444
 445         /*
 446          * Create the encoders, attach the bridges and get the pipeline alias
 447          * IDs.
 448          */
 449         for (i = 0; i < priv->num_pipes; i++) {
 450                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 451                 int id;
 452
 453                 pipe->encoder = omap_encoder_init(dev, pipe->output);
 454                 if (!pipe->encoder)
 455                         return -ENOMEM;
 456
 457                 if (pipe->output->bridge) {
 458                         ret = drm_bridge_attach(pipe->encoder,
 459                                                 pipe->output->bridge, NULL,
 460                                                 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 461                         if (ret < 0)
 462                                 return ret;
 463                 }
 464
 465                 id = omap_display_id(pipe->output);
 466                 pipe->alias_id = id >= 0 ? id : i;
 467         }
 468
 469         /* Sort the pipelines by DT aliases. */
 470         sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
 471              omap_compare_pipelines, NULL);
 472
 473         /*
 474          * Populate the pipeline lookup table by DISPC channel. Only one display
 475          * is allowed per channel.
 476          */
 477         for (i = 0; i < priv->num_pipes; ++i) {
 478                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 479                 enum omap_channel channel = pipe->output->dispc_channel;
 480
 481                 if (WARN_ON(priv->channels[channel] != NULL))
 482                         return -EINVAL;
 483
 484                 priv->channels[channel] = pipe;
 485         }
 486
 487         /* Create the connectors and CRTCs. */
 488         for (i = 0; i < priv->num_pipes; i++) {
 489                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 490                 struct drm_encoder *encoder = pipe->encoder;
 491                 struct drm_crtc *crtc;
 492
 493                 pipe->connector = drm_bridge_connector_init(dev, encoder);
 494                 if (IS_ERR(pipe->connector)) {
 495                         dev_err(priv->dev,
 496                                 "unable to create bridge connector for %s\n",
 497                                 pipe->output->name);
 498                         return PTR_ERR(pipe->connector);
 499                 }
 500
 501                 drm_connector_attach_encoder(pipe->connector, encoder);
 502
 503                 crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
 504                 if (IS_ERR(crtc))
 505                         return PTR_ERR(crtc);
 506
 507                 encoder->possible_crtcs = 1 << i;
 508                 pipe->crtc = crtc;
 509         }
 510
 511         DBG("registered %u planes, %u crtcs/encoders/connectors\n",
 512             priv->num_planes, priv->num_pipes);
 513
 514         dev->mode_config.min_width = 8;
 515         dev->mode_config.min_height = 2;
 516
 517         /*
 518          * Note: these values are used for multiple independent things:
 519          * connector mode filtering, buffer sizes, crtc sizes...
 520          * Use big enough values here to cover all use cases, and do more
 521          * specific checking in the respective code paths.
 522          */
 523         dev->mode_config.max_width = 8192;
 524         dev->mode_config.max_height = 8192;
 525
 526         /* We want the zpos to be normalized */
 527         dev->mode_config.normalize_zpos = true;
 528
 529         dev->mode_config.funcs = &omap_mode_config_funcs;
 530         dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
 531
 532         drm_mode_config_reset(dev);
 533
 534         omap_drm_irq_install(dev);
 535
 536         return 0;
 537 }
 538
 539 static void omap_modeset_fini(struct drm_device *ddev)
 540 {
 541         omap_drm_irq_uninstall(ddev);
 542
 543         drm_mode_config_cleanup(ddev);
 544 }
 545
 546 /*
 547  * drm ioctl funcs
 548  */
 549
 550
 551 static int ioctl_get_param(struct drm_device *dev, void *data,
 552                 struct drm_file *file_priv)
 553 {
 554         struct omap_drm_private *priv = dev->dev_private;
 555         struct drm_omap_param *args = data;
 556
 557         DBG("%p: param=%llu", dev, args->param);
 558
 559         switch (args->param) {
 560         case OMAP_PARAM_CHIPSET_ID:
 561                 args->value = priv->omaprev;
 562                 break;
 563         default:
 564                 DBG("unknown parameter %lld", args->param);
 565                 return -EINVAL;
 566         }
 567
 568         return 0;
 569 }
 570
 571 #define OMAP_BO_USER_MASK       0x00ffffff      /* flags settable by userspace */
 572
 573 static int ioctl_gem_new(struct drm_device *dev, void *data,
 574                 struct drm_file *file_priv)
 575 {
 576         struct drm_omap_gem_new *args = data;
 577         u32 flags = args->flags & OMAP_BO_USER_MASK;
 578
 579         VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
 580              args->size.bytes, flags);
 581
 582         return omap_gem_new_handle(dev, file_priv, args->size, flags,
 583                                    &args->handle);
 584 }
 585
 586 static int ioctl_gem_info(struct drm_device *dev, void *data,
 587                 struct drm_file *file_priv)
 588 {
 589         struct drm_omap_gem_info *args = data;
 590         struct drm_gem_object *obj;
 591         int ret = 0;
 592
 593         VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
 594
 595         obj = drm_gem_object_lookup(file_priv, args->handle);
 596         if (!obj)
 597                 return -ENOENT;
 598
 599         args->size = omap_gem_mmap_size(obj);
 600         args->offset = omap_gem_mmap_offset(obj);
 601
 602         drm_gem_object_put(obj);
 603
 604         return ret;
 605 }
 606
 607 static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
 608         DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
 609                           DRM_RENDER_ALLOW),
 610         DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
 611                           DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
 612         DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
 613                           DRM_RENDER_ALLOW),
 614         /* Deprecated, to be removed. */
 615         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
 616                           DRM_RENDER_ALLOW),
 617         /* Deprecated, to be removed. */
 618         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
 619                           DRM_RENDER_ALLOW),
 620         DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
 621                           DRM_RENDER_ALLOW),
 622 };
 623
 624 /*
 625  * drm driver funcs
 626  */
 627
 628 static int dev_open(struct drm_device *dev, struct drm_file *file)
 629 {
 630         file->driver_priv = NULL;
 631
 632         DBG("open: dev=%p, file=%p", dev, file);
 633
 634         return 0;
 635 }
 636
 637 DEFINE_DRM_GEM_FOPS(omapdriver_fops);
 638
 639 static const struct drm_driver omap_drm_driver = {
 640         .driver_features = DRIVER_MODESET | DRIVER_GEM  |
 641                 DRIVER_ATOMIC | DRIVER_RENDER,
 642         .open = dev_open,
 643 #ifdef CONFIG_DEBUG_FS
 644         .debugfs_init = omap_debugfs_init,
 645 #endif
 646         .gem_prime_import = omap_gem_prime_import,
 647         .dumb_create = omap_gem_dumb_create,
 648         .dumb_map_offset = omap_gem_dumb_map_offset,
 649         OMAP_FBDEV_DRIVER_OPS,
 650         .ioctls = ioctls,
 651         .num_ioctls = DRM_OMAP_NUM_IOCTLS,
 652         .fops = &omapdriver_fops,
 653         .name = DRIVER_NAME,
 654         .desc = DRIVER_DESC,
 655         .major = DRIVER_MAJOR,
 656         .minor = DRIVER_MINOR,
 657         .patchlevel = DRIVER_PATCHLEVEL,
 658 };
 659
 660 static const struct soc_device_attribute omapdrm_soc_devices[] = {
 661         { .family = "OMAP3", .data = (void *)0x3430 },
 662         { .family = "OMAP4", .data = (void *)0x4430 },
 663         { .family = "OMAP5", .data = (void *)0x5430 },
 664         { .family = "DRA7",  .data = (void *)0x0752 },
 665         { /* sentinel */ }
 666 };
 667
 668 static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 669 {
 670         const struct soc_device_attribute *soc;
 671         struct dss_pdata *pdata = dev->platform_data;
 672         struct drm_device *ddev;
 673         int ret;
 674
 675         DBG("%s", dev_name(dev));
 676
 677         if (drm_firmware_drivers_only())
 678                 return -ENODEV;
 679
 680         /* Allocate and initialize the DRM device. */
 681         ddev = drm_dev_alloc(&omap_drm_driver, dev);
 682         if (IS_ERR(ddev))
 683                 return PTR_ERR(ddev);
 684
 685         priv->ddev = ddev;
 686         ddev->dev_private = priv;
 687
 688         priv->dev = dev;
 689         priv->dss = pdata->dss;
 690         priv->dispc = dispc_get_dispc(priv->dss);
 691
 692         priv->dss->mgr_ops_priv = priv;
 693
 694         soc = soc_device_match(omapdrm_soc_devices);
 695         priv->omaprev = soc ? (uintptr_t)soc->data : 0;
 696         priv->wq = alloc_ordered_workqueue("omapdrm", 0);
 697         if (!priv->wq) {
 698                 ret = -ENOMEM;
 699                 goto err_alloc_workqueue;
 700         }
 701
 702         mutex_init(&priv->list_lock);
 703         INIT_LIST_HEAD(&priv->obj_list);
 704
 705         /* Get memory bandwidth limits */
 706         priv->max_bandwidth = dispc_get_memory_bandwidth_limit(priv->dispc);
 707
 708         omap_gem_init(ddev);
 709
 710         drm_mode_config_init(ddev);
 711
 712         ret = omap_global_obj_init(ddev);
 713         if (ret)
 714                 goto err_gem_deinit;
 715
 716         ret = omap_hwoverlays_init(priv);
 717         if (ret)
 718                 goto err_free_priv_obj;
 719
 720         ret = omap_modeset_init(ddev);
 721         if (ret) {
 722                 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
 723                 goto err_free_overlays;
 724         }
 725
 726         /* Initialize vblank handling, start with all CRTCs disabled. */
 727         ret = drm_vblank_init(ddev, priv->num_pipes);
 728         if (ret) {
 729                 dev_err(priv->dev, "could not init vblank\n");
 730                 goto err_cleanup_modeset;
 731         }
 732
 733         drm_kms_helper_poll_init(ddev);
 734
 735         /*
 736          * Register the DRM device with the core and the connectors with
 737          * sysfs.
 738          */
 739         ret = drm_dev_register(ddev, 0);
 740         if (ret)
 741                 goto err_cleanup_helpers;
 742
 743         omap_fbdev_setup(ddev);
 744
 745         return 0;
 746
 747 err_cleanup_helpers:
 748         drm_kms_helper_poll_fini(ddev);
 749 err_cleanup_modeset:
 750         omap_modeset_fini(ddev);
 751 err_free_overlays:
 752         omap_hwoverlays_destroy(priv);
 753 err_free_priv_obj:
 754         omap_global_obj_fini(priv);
 755 err_gem_deinit:
 756         drm_mode_config_cleanup(ddev);
 757         omap_gem_deinit(ddev);
 758         destroy_workqueue(priv->wq);
 759 err_alloc_workqueue:
 760         omap_disconnect_pipelines(ddev);
 761         drm_dev_put(ddev);
 762         return ret;
 763 }
 764
 765 static void omapdrm_cleanup(struct omap_drm_private *priv)
 766 {
 767         struct drm_device *ddev = priv->ddev;
 768
 769         DBG("");
 770
 771         drm_dev_unregister(ddev);
 772
 773         drm_kms_helper_poll_fini(ddev);
 774
 775         drm_atomic_helper_shutdown(ddev);
 776
 777         omap_modeset_fini(ddev);
 778         omap_hwoverlays_destroy(priv);
 779         omap_global_obj_fini(priv);
 780         drm_mode_config_cleanup(ddev);
 781         omap_gem_deinit(ddev);
 782
 783         destroy_workqueue(priv->wq);
 784
 785         omap_disconnect_pipelines(ddev);
 786
 787         drm_dev_put(ddev);
 788 }
 789
 790 static int pdev_probe(struct platform_device *pdev)
 791 {
 792         struct omap_drm_private *priv;
 793         int ret;
 794
 795         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 796         if (ret) {
 797                 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
 798                 return ret;
 799         }
 800
 801         /* Allocate and initialize the driver private structure. */
 802         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 803         if (!priv)
 804                 return -ENOMEM;
 805
 806         platform_set_drvdata(pdev, priv);
 807
 808         ret = omapdrm_init(priv, &pdev->dev);
 809         if (ret < 0)
 810                 kfree(priv);
 811
 812         return ret;
 813 }
 814
 815 static void pdev_remove(struct platform_device *pdev)
 816 {
 817         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 818
 819         omapdrm_cleanup(priv);
 820         kfree(priv);
 821 }
 822
 823 static void pdev_shutdown(struct platform_device *pdev)
 824 {
 825         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 826
 827         drm_atomic_helper_shutdown(priv->ddev);
 828 }
 829
 830 #ifdef CONFIG_PM_SLEEP
 831 static int omap_drm_suspend(struct device *dev)
 832 {
 833         struct omap_drm_private *priv = dev_get_drvdata(dev);
 834         struct drm_device *drm_dev = priv->ddev;
 835
 836         return drm_mode_config_helper_suspend(drm_dev);
 837 }
 838
 839 static int omap_drm_resume(struct device *dev)
 840 {
 841         struct omap_drm_private *priv = dev_get_drvdata(dev);
 842         struct drm_device *drm_dev = priv->ddev;
 843
 844         drm_mode_config_helper_resume(drm_dev);
 845
 846         return omap_gem_resume(drm_dev);
 847 }
 848 #endif
 849
 850 static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
 851
 852 static struct platform_driver pdev = {
 853         .driver = {
 854                 .name = "omapdrm",
 855                 .pm = &omapdrm_pm_ops,
 856         },
 857         .probe = pdev_probe,
 858         .remove = pdev_remove,
 859         .shutdown = pdev_shutdown,
 860 };
 861
 862 static struct platform_driver * const drivers[] = {
 863         &omap_dmm_driver,
 864         &pdev,
 865 };
 866
 867 static int __init omap_drm_init(void)
 868 {
 869         int r;
 870
 871         DBG("init");
 872
 873         r = omap_dss_init();
 874         if (r)
 875                 return r;
 876
 877         r = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 878         if (r) {
 879                 omap_dss_exit();
 880                 return r;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static void __exit omap_drm_fini(void)
 887 {
 888         DBG("fini");
 889
 890         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 891
 892         omap_dss_exit();
 893 }
 894
 895 module_init(omap_drm_init);
 896 module_exit(omap_drm_fini);
 897
 898 MODULE_AUTHOR("Rob Clark <[email protected]>");
 899 MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
 900 MODULE_DESCRIPTION("OMAP DRM Display Driver");
 901 MODULE_ALIAS("platform:" DRIVER_NAME);
 902 MODULE_LICENSE("GPL v2");