drivers/gpu/drm/arm/hdlcd_drv.c

   1 /*
   2  * Copyright (C) 2013-2015 ARM Limited
   3  * Author: Liviu Dudau <[email protected]>
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive
   7  * for more details.
   8  *
   9  *  ARM HDLCD Driver
  10  */
  11
  12 #include <linux/aperture.h>
  13 #include <linux/module.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/clk.h>
  16 #include <linux/component.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/list.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/of_reserved_mem.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24
  25 #include <drm/clients/drm_client_setup.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_debugfs.h>
  29 #include <drm/drm_drv.h>
  30 #include <drm/drm_fbdev_dma.h>
  31 #include <drm/drm_gem_dma_helper.h>
  32 #include <drm/drm_gem_framebuffer_helper.h>
  33 #include <drm/drm_modeset_helper.h>
  34 #include <drm/drm_module.h>
  35 #include <drm/drm_of.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_vblank.h>
  38
  39 #include "hdlcd_drv.h"
  40 #include "hdlcd_regs.h"
  41
  42 static irqreturn_t hdlcd_irq(int irq, void *arg)
  43 {
  44         struct hdlcd_drm_private *hdlcd = arg;
  45         unsigned long irq_status;
  46
  47         irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
  48
  49 #ifdef CONFIG_DEBUG_FS
  50         if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
  51                 atomic_inc(&hdlcd->buffer_underrun_count);
  52
  53         if (irq_status & HDLCD_INTERRUPT_DMA_END)
  54                 atomic_inc(&hdlcd->dma_end_count);
  55
  56         if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
  57                 atomic_inc(&hdlcd->bus_error_count);
  58
  59         if (irq_status & HDLCD_INTERRUPT_VSYNC)
  60                 atomic_inc(&hdlcd->vsync_count);
  61
  62 #endif
  63         if (irq_status & HDLCD_INTERRUPT_VSYNC)
  64                 drm_crtc_handle_vblank(&hdlcd->crtc);
  65
  66         /* acknowledge interrupt(s) */
  67         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
  68
  69         return IRQ_HANDLED;
  70 }
  71
  72 static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
  73 {
  74         int ret;
  75
  76         /* Ensure interrupts are disabled */
  77         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
  78         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
  79
  80         ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
  81         if (ret)
  82                 return ret;
  83
  84 #ifdef CONFIG_DEBUG_FS
  85         /* enable debug interrupts */
  86         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
  87 #endif
  88
  89         return 0;
  90 }
  91
  92 static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
  93 {
  94         /* disable all the interrupts that we might have enabled */
  95         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
  96
  97         free_irq(hdlcd->irq, hdlcd);
  98 }
  99
 100 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
 101 {
 102         struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
 103         struct platform_device *pdev = to_platform_device(drm->dev);
 104         u32 version;
 105         int ret;
 106
 107         hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
 108         if (IS_ERR(hdlcd->clk))
 109                 return PTR_ERR(hdlcd->clk);
 110
 111 #ifdef CONFIG_DEBUG_FS
 112         atomic_set(&hdlcd->buffer_underrun_count, 0);
 113         atomic_set(&hdlcd->bus_error_count, 0);
 114         atomic_set(&hdlcd->vsync_count, 0);
 115         atomic_set(&hdlcd->dma_end_count, 0);
 116 #endif
 117
 118         hdlcd->mmio = devm_platform_ioremap_resource(pdev, 0);
 119         if (IS_ERR(hdlcd->mmio)) {
 120                 DRM_ERROR("failed to map control registers area\n");
 121                 ret = PTR_ERR(hdlcd->mmio);
 122                 hdlcd->mmio = NULL;
 123                 return ret;
 124         }
 125
 126         version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
 127         if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
 128                 DRM_ERROR("unknown product id: 0x%x\n", version);
 129                 return -EINVAL;
 130         }
 131         DRM_INFO("found ARM HDLCD version r%dp%d\n",
 132                 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
 133                 version & HDLCD_VERSION_MINOR_MASK);
 134
 135         /* Get the optional framebuffer memory resource */
 136         ret = of_reserved_mem_device_init(drm->dev);
 137         if (ret && ret != -ENODEV)
 138                 return ret;
 139
 140         ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
 141         if (ret)
 142                 goto setup_fail;
 143
 144         ret = hdlcd_setup_crtc(drm);
 145         if (ret < 0) {
 146                 DRM_ERROR("failed to create crtc\n");
 147                 goto setup_fail;
 148         }
 149
 150         ret = platform_get_irq(pdev, 0);
 151         if (ret < 0)
 152                 goto irq_fail;
 153         hdlcd->irq = ret;
 154
 155         ret = hdlcd_irq_install(hdlcd);
 156         if (ret < 0) {
 157                 DRM_ERROR("failed to install IRQ handler\n");
 158                 goto irq_fail;
 159         }
 160
 161         return 0;
 162
 163 irq_fail:
 164         drm_crtc_cleanup(&hdlcd->crtc);
 165 setup_fail:
 166         of_reserved_mem_device_release(drm->dev);
 167
 168         return ret;
 169 }
 170
 171 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
 172         .fb_create = drm_gem_fb_create,
 173         .atomic_check = drm_atomic_helper_check,
 174         .atomic_commit = drm_atomic_helper_commit,
 175 };
 176
 177 static int hdlcd_setup_mode_config(struct drm_device *drm)
 178 {
 179         int ret;
 180
 181         ret = drmm_mode_config_init(drm);
 182         if (ret)
 183                 return ret;
 184
 185         drm->mode_config.min_width = 0;
 186         drm->mode_config.min_height = 0;
 187         drm->mode_config.max_width = HDLCD_MAX_XRES;
 188         drm->mode_config.max_height = HDLCD_MAX_YRES;
 189         drm->mode_config.funcs = &hdlcd_mode_config_funcs;
 190
 191         return 0;
 192 }
 193
 194 #ifdef CONFIG_DEBUG_FS
 195 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
 196 {
 197         struct drm_debugfs_entry *entry = m->private;
 198         struct drm_device *drm = entry->dev;
 199         struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
 200
 201         seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
 202         seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
 203         seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
 204         seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
 205         return 0;
 206 }
 207
 208 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
 209 {
 210         struct drm_debugfs_entry *entry = m->private;
 211         struct drm_device *drm = entry->dev;
 212         struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
 213         unsigned long clkrate = clk_get_rate(hdlcd->clk);
 214         unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
 215
 216         seq_printf(m, "hw  : %lu\n", clkrate);
 217         seq_printf(m, "mode: %lu\n", mode_clock);
 218         return 0;
 219 }
 220
 221 static struct drm_debugfs_info hdlcd_debugfs_list[] = {
 222         { "interrupt_count", hdlcd_show_underrun_count, 0 },
 223         { "clocks", hdlcd_show_pxlclock, 0 },
 224 };
 225 #endif
 226
 227 DEFINE_DRM_GEM_DMA_FOPS(fops);
 228
 229 static const struct drm_driver hdlcd_driver = {
 230         .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 231         DRM_GEM_DMA_DRIVER_OPS,
 232         DRM_FBDEV_DMA_DRIVER_OPS,
 233         .fops = &fops,
 234         .name = "hdlcd",
 235         .desc = "ARM HDLCD Controller DRM",
 236         .major = 1,
 237         .minor = 0,
 238 };
 239
 240 static int hdlcd_drm_bind(struct device *dev)
 241 {
 242         struct drm_device *drm;
 243         struct hdlcd_drm_private *hdlcd;
 244         int ret;
 245
 246         hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
 247         if (IS_ERR(hdlcd))
 248                 return PTR_ERR(hdlcd);
 249
 250         drm = &hdlcd->base;
 251
 252         dev_set_drvdata(dev, drm);
 253
 254         ret = hdlcd_setup_mode_config(drm);
 255         if (ret)
 256                 goto err_free;
 257
 258         ret = hdlcd_load(drm, 0);
 259         if (ret)
 260                 goto err_free;
 261
 262         /* Set the CRTC's port so that the encoder component can find it */
 263         hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 264
 265         ret = component_bind_all(dev, drm);
 266         if (ret) {
 267                 DRM_ERROR("Failed to bind all components\n");
 268                 goto err_unload;
 269         }
 270
 271         ret = pm_runtime_set_active(dev);
 272         if (ret)
 273                 goto err_pm_active;
 274
 275         pm_runtime_enable(dev);
 276
 277         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 278         if (ret < 0) {
 279                 DRM_ERROR("failed to initialise vblank\n");
 280                 goto err_vblank;
 281         }
 282
 283         /*
 284          * If EFI left us running, take over from simple framebuffer
 285          * drivers. Read HDLCD_REG_COMMAND to see if we are enabled.
 286          */
 287         if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
 288                 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
 289                 aperture_remove_all_conflicting_devices(hdlcd_driver.name);
 290         }
 291
 292         drm_mode_config_reset(drm);
 293         drm_kms_helper_poll_init(drm);
 294
 295 #ifdef CONFIG_DEBUG_FS
 296         drm_debugfs_add_files(drm, hdlcd_debugfs_list, ARRAY_SIZE(hdlcd_debugfs_list));
 297 #endif
 298
 299         ret = drm_dev_register(drm, 0);
 300         if (ret)
 301                 goto err_register;
 302
 303         drm_client_setup(drm, NULL);
 304
 305         return 0;
 306
 307 err_register:
 308         drm_kms_helper_poll_fini(drm);
 309 err_vblank:
 310         pm_runtime_disable(drm->dev);
 311 err_pm_active:
 312         drm_atomic_helper_shutdown(drm);
 313         component_unbind_all(dev, drm);
 314 err_unload:
 315         of_node_put(hdlcd->crtc.port);
 316         hdlcd->crtc.port = NULL;
 317         hdlcd_irq_uninstall(hdlcd);
 318         of_reserved_mem_device_release(drm->dev);
 319 err_free:
 320         dev_set_drvdata(dev, NULL);
 321         return ret;
 322 }
 323
 324 static void hdlcd_drm_unbind(struct device *dev)
 325 {
 326         struct drm_device *drm = dev_get_drvdata(dev);
 327         struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
 328
 329         drm_dev_unregister(drm);
 330         drm_kms_helper_poll_fini(drm);
 331         component_unbind_all(dev, drm);
 332         of_node_put(hdlcd->crtc.port);
 333         hdlcd->crtc.port = NULL;
 334         pm_runtime_get_sync(dev);
 335         drm_atomic_helper_shutdown(drm);
 336         hdlcd_irq_uninstall(hdlcd);
 337         pm_runtime_put(dev);
 338         if (pm_runtime_enabled(dev))
 339                 pm_runtime_disable(dev);
 340         of_reserved_mem_device_release(dev);
 341         dev_set_drvdata(dev, NULL);
 342 }
 343
 344 static const struct component_master_ops hdlcd_master_ops = {
 345         .bind           = hdlcd_drm_bind,
 346         .unbind         = hdlcd_drm_unbind,
 347 };
 348
 349 static int compare_dev(struct device *dev, void *data)
 350 {
 351         return dev->of_node == data;
 352 }
 353
 354 static int hdlcd_probe(struct platform_device *pdev)
 355 {
 356         struct device_node *port;
 357         struct component_match *match = NULL;
 358
 359         /* there is only one output port inside each device, find it */
 360         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 361         if (!port)
 362                 return -ENODEV;
 363
 364         drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
 365         of_node_put(port);
 366
 367         return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
 368                                                match);
 369 }
 370
 371 static void hdlcd_remove(struct platform_device *pdev)
 372 {
 373         component_master_del(&pdev->dev, &hdlcd_master_ops);
 374 }
 375
 376 static void hdlcd_shutdown(struct platform_device *pdev)
 377 {
 378         drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
 379 }
 380
 381 static const struct of_device_id  hdlcd_of_match[] = {
 382         { .compatible   = "arm,hdlcd" },
 383         {},
 384 };
 385 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
 386
 387 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
 388 {
 389         struct drm_device *drm = dev_get_drvdata(dev);
 390
 391         return drm_mode_config_helper_suspend(drm);
 392 }
 393
 394 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
 395 {
 396         struct drm_device *drm = dev_get_drvdata(dev);
 397
 398         drm_mode_config_helper_resume(drm);
 399
 400         return 0;
 401 }
 402
 403 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
 404
 405 static struct platform_driver hdlcd_platform_driver = {
 406         .probe          = hdlcd_probe,
 407         .remove         = hdlcd_remove,
 408         .shutdown       = hdlcd_shutdown,
 409         .driver = {
 410                 .name = "hdlcd",
 411                 .pm = &hdlcd_pm_ops,
 412                 .of_match_table = hdlcd_of_match,
 413         },
 414 };
 415
 416 drm_module_platform_driver(hdlcd_platform_driver);
 417
 418 MODULE_AUTHOR("Liviu Dudau");
 419 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
 420 MODULE_LICENSE("GPL v2");