drivers/platform/x86/intel_pmc_core.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Core SoC Power Management Controller Header File
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <[email protected]>
   9  *          Vishwanath Somayaji <[email protected]>
  10  */
  11
  12 #ifndef PMC_CORE_H
  13 #define PMC_CORE_H
  14
  15 #define PMC_BASE_ADDR_DEFAULT                   0xFE000000
  16
  17 /* Sunrise Point Power Management Controller PCI Device ID */
  18 #define SPT_PMC_PCI_DEVICE_ID                   0x9d21
  19 #define SPT_PMC_BASE_ADDR_OFFSET                0x48
  20 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET       0x13c
  21 #define SPT_PMC_PM_CFG_OFFSET                   0x18
  22 #define SPT_PMC_PM_STS_OFFSET                   0x1c
  23 #define SPT_PMC_MTPMC_OFFSET                    0x20
  24 #define SPT_PMC_MFPMC_OFFSET                    0x38
  25 #define SPT_PMC_LTR_IGNORE_OFFSET               0x30C
  26 #define SPT_PMC_MPHY_CORE_STS_0                 0x1143
  27 #define SPT_PMC_MPHY_CORE_STS_1                 0x1142
  28 #define SPT_PMC_MPHY_COM_STS_0                  0x1155
  29 #define SPT_PMC_MMIO_REG_LEN                    0x1000
  30 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP         0x64
  31 #define PMC_BASE_ADDR_MASK                      ~(SPT_PMC_MMIO_REG_LEN - 1)
  32 #define MTPMC_MASK                              0xffff0000
  33 #define PPFEAR_MAX_NUM_ENTRIES                  5
  34 #define SPT_PPFEAR_NUM_ENTRIES                  5
  35 #define SPT_PMC_READ_DISABLE_BIT                0x16
  36 #define SPT_PMC_MSG_FULL_STS_BIT                0x18
  37 #define NUM_RETRIES                             100
  38 #define NUM_IP_IGN_ALLOWED                      17
  39
  40 /* Sunrise Point: PGD PFET Enable Ack Status Registers */
  41 enum ppfear_regs {
  42         SPT_PMC_XRAM_PPFEAR0A = 0x590,
  43         SPT_PMC_XRAM_PPFEAR0B,
  44         SPT_PMC_XRAM_PPFEAR0C,
  45         SPT_PMC_XRAM_PPFEAR0D,
  46         SPT_PMC_XRAM_PPFEAR1A,
  47 };
  48
  49 #define SPT_PMC_BIT_PMC                         BIT(0)
  50 #define SPT_PMC_BIT_OPI                         BIT(1)
  51 #define SPT_PMC_BIT_SPI                         BIT(2)
  52 #define SPT_PMC_BIT_XHCI                        BIT(3)
  53 #define SPT_PMC_BIT_SPA                         BIT(4)
  54 #define SPT_PMC_BIT_SPB                         BIT(5)
  55 #define SPT_PMC_BIT_SPC                         BIT(6)
  56 #define SPT_PMC_BIT_GBE                         BIT(7)
  57
  58 #define SPT_PMC_BIT_SATA                        BIT(0)
  59 #define SPT_PMC_BIT_HDA_PGD0                    BIT(1)
  60 #define SPT_PMC_BIT_HDA_PGD1                    BIT(2)
  61 #define SPT_PMC_BIT_HDA_PGD2                    BIT(3)
  62 #define SPT_PMC_BIT_HDA_PGD3                    BIT(4)
  63 #define SPT_PMC_BIT_RSVD_0B                     BIT(5)
  64 #define SPT_PMC_BIT_LPSS                        BIT(6)
  65 #define SPT_PMC_BIT_LPC                         BIT(7)
  66
  67 #define SPT_PMC_BIT_SMB                         BIT(0)
  68 #define SPT_PMC_BIT_ISH                         BIT(1)
  69 #define SPT_PMC_BIT_P2SB                        BIT(2)
  70 #define SPT_PMC_BIT_DFX                         BIT(3)
  71 #define SPT_PMC_BIT_SCC                         BIT(4)
  72 #define SPT_PMC_BIT_RSVD_0C                     BIT(5)
  73 #define SPT_PMC_BIT_FUSE                        BIT(6)
  74 #define SPT_PMC_BIT_CAMREA                      BIT(7)
  75
  76 #define SPT_PMC_BIT_RSVD_0D                     BIT(0)
  77 #define SPT_PMC_BIT_USB3_OTG                    BIT(1)
  78 #define SPT_PMC_BIT_EXI                         BIT(2)
  79 #define SPT_PMC_BIT_CSE                         BIT(3)
  80 #define SPT_PMC_BIT_CSME_KVM                    BIT(4)
  81 #define SPT_PMC_BIT_CSME_PMT                    BIT(5)
  82 #define SPT_PMC_BIT_CSME_CLINK                  BIT(6)
  83 #define SPT_PMC_BIT_CSME_PTIO                   BIT(7)
  84
  85 #define SPT_PMC_BIT_CSME_USBR                   BIT(0)
  86 #define SPT_PMC_BIT_CSME_SUSRAM                 BIT(1)
  87 #define SPT_PMC_BIT_CSME_SMT                    BIT(2)
  88 #define SPT_PMC_BIT_RSVD_1A                     BIT(3)
  89 #define SPT_PMC_BIT_CSME_SMS2                   BIT(4)
  90 #define SPT_PMC_BIT_CSME_SMS1                   BIT(5)
  91 #define SPT_PMC_BIT_CSME_RTC                    BIT(6)
  92 #define SPT_PMC_BIT_CSME_PSF                    BIT(7)
  93
  94 #define SPT_PMC_BIT_MPHY_LANE0                  BIT(0)
  95 #define SPT_PMC_BIT_MPHY_LANE1                  BIT(1)
  96 #define SPT_PMC_BIT_MPHY_LANE2                  BIT(2)
  97 #define SPT_PMC_BIT_MPHY_LANE3                  BIT(3)
  98 #define SPT_PMC_BIT_MPHY_LANE4                  BIT(4)
  99 #define SPT_PMC_BIT_MPHY_LANE5                  BIT(5)
 100 #define SPT_PMC_BIT_MPHY_LANE6                  BIT(6)
 101 #define SPT_PMC_BIT_MPHY_LANE7                  BIT(7)
 102
 103 #define SPT_PMC_BIT_MPHY_LANE8                  BIT(0)
 104 #define SPT_PMC_BIT_MPHY_LANE9                  BIT(1)
 105 #define SPT_PMC_BIT_MPHY_LANE10                 BIT(2)
 106 #define SPT_PMC_BIT_MPHY_LANE11                 BIT(3)
 107 #define SPT_PMC_BIT_MPHY_LANE12                 BIT(4)
 108 #define SPT_PMC_BIT_MPHY_LANE13                 BIT(5)
 109 #define SPT_PMC_BIT_MPHY_LANE14                 BIT(6)
 110 #define SPT_PMC_BIT_MPHY_LANE15                 BIT(7)
 111
 112 #define SPT_PMC_BIT_MPHY_CMN_LANE0              BIT(0)
 113 #define SPT_PMC_BIT_MPHY_CMN_LANE1              BIT(1)
 114 #define SPT_PMC_BIT_MPHY_CMN_LANE2              BIT(2)
 115 #define SPT_PMC_BIT_MPHY_CMN_LANE3              BIT(3)
 116
 117 /* Cannonlake Power Management Controller register offsets */
 118 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET      0x193C
 119 #define CNP_PMC_LTR_IGNORE_OFFSET              0x1B0C
 120 #define CNP_PMC_PM_CFG_OFFSET                  0x1818
 121 #define CNP_PMC_SLPS0_DBG_OFFSET                0x10B4
 122 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
 123 #define CNP_PMC_HOST_PPFEAR0A                  0x1D90
 124
 125 #define CNP_PMC_MMIO_REG_LEN                   0x2000
 126 #define CNP_PPFEAR_NUM_ENTRIES                 8
 127 #define CNP_PMC_READ_DISABLE_BIT               22
 128 #define CNP_PMC_LATCH_SLPS0_EVENTS              BIT(31)
 129
 130 struct pmc_bit_map {
 131         const char *name;
 132         u32 bit_mask;
 133 };
 134
 135 /**
 136  * struct pmc_reg_map - Structure used to define parameter unique to a
 137                         PCH family
 138  * @pfear_sts:          Maps name of IP block to PPFEAR* bit
 139  * @mphy_sts:           Maps name of MPHY lane to MPHY status lane status bit
 140  * @pll_sts:            Maps name of PLL to corresponding bit status
 141  * @slps0_dbg_maps:     Array of SLP_S0_DBG* registers containing debug info
 142  * @slp_s0_offset:      PWRMBASE offset to read SLP_S0 residency
 143  * @ltr_ignore_offset:  PWRMBASE offset to read/write LTR ignore bit
 144  * @regmap_length:      Length of memory to map from PWRMBASE address to access
 145  * @ppfear0_offset:     PWRMBASE offset to to read PPFEAR*
 146  * @ppfear_buckets:     Number of 8 bits blocks to read all IP blocks from
 147  *                      PPFEAR
 148  * @pm_cfg_offset:      PWRMBASE offset to PM_CFG register
 149  * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
 150  * @slps0_dbg_offset:   PWRMBASE offset to SLP_S0_DEBUG_REG*
 151  *
 152  * Each PCH has unique set of register offsets and bit indexes. This structure
 153  * captures them to have a common implementation.
 154  */
 155 struct pmc_reg_map {
 156         const struct pmc_bit_map *pfear_sts;
 157         const struct pmc_bit_map *mphy_sts;
 158         const struct pmc_bit_map *pll_sts;
 159         const struct pmc_bit_map **slps0_dbg_maps;
 160         const u32 slp_s0_offset;
 161         const u32 ltr_ignore_offset;
 162         const int regmap_length;
 163         const u32 ppfear0_offset;
 164         const int ppfear_buckets;
 165         const u32 pm_cfg_offset;
 166         const int pm_read_disable_bit;
 167         const u32 slps0_dbg_offset;
 168 };
 169
 170 /**
 171  * struct pmc_dev - pmc device structure
 172  * @base_addr:          contains pmc base address
 173  * @regbase:            pointer to io-remapped memory location
 174  * @map:                pointer to pmc_reg_map struct that contains platform
 175  *                      specific attributes
 176  * @dbgfs_dir:          path to debugfs interface
 177  * @pmc_xram_read_bit:  flag to indicate whether PMC XRAM shadow registers
 178  *                      used to read MPHY PG and PLL status are available
 179  * @mutex_lock:         mutex to complete one transcation
 180  *
 181  * pmc_dev contains info about power management controller device.
 182  */
 183 struct pmc_dev {
 184         u32 base_addr;
 185         void __iomem *regbase;
 186         const struct pmc_reg_map *map;
 187 #if IS_ENABLED(CONFIG_DEBUG_FS)
 188         struct dentry *dbgfs_dir;
 189 #endif /* CONFIG_DEBUG_FS */
 190         int pmc_xram_read_bit;
 191         struct mutex lock; /* generic mutex lock for PMC Core */
 192 };
 193
 194 #endif /* PMC_CORE_H */