drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Zou Nan hai <[email protected]>
  26  *    Xiang Hai hao<[email protected]>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int
 321 gen7_render_ring_flush(struct intel_engine_cs *ring,
 322                        u32 invalidate_domains, u32 flush_domains)
 323 {
 324         u32 flags = 0;
 325         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 326         int ret;
 327
 328         /*
 329          * Ensure that any following seqno writes only happen when the render
 330          * cache is indeed flushed.
 331          *
 332          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 333          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 334          * don't try to be clever and just set it unconditionally.
 335          */
 336         flags |= PIPE_CONTROL_CS_STALL;
 337
 338         /* Just flush everything.  Experiments have shown that reducing the
 339          * number of bits based on the write domains has little performance
 340          * impact.
 341          */
 342         if (flush_domains) {
 343                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 344                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 345         }
 346         if (invalidate_domains) {
 347                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 348                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 349                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 350                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 351                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 352                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 353                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 354                 /*
 355                  * TLB invalidate requires a post-sync write.
 356                  */
 357                 flags |= PIPE_CONTROL_QW_WRITE;
 358                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 359
 360                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 361
 362                 /* Workaround: we must issue a pipe_control with CS-stall bit
 363                  * set before a pipe_control command that has the state cache
 364                  * invalidate bit set. */
 365                 gen7_render_ring_cs_stall_wa(ring);
 366         }
 367
 368         ret = intel_ring_begin(ring, 4);
 369         if (ret)
 370                 return ret;
 371
 372         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 373         intel_ring_emit(ring, flags);
 374         intel_ring_emit(ring, scratch_addr);
 375         intel_ring_emit(ring, 0);
 376         intel_ring_advance(ring);
 377
 378         return 0;
 379 }
 380
 381 static int
 382 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 383                        u32 flags, u32 scratch_addr)
 384 {
 385         int ret;
 386
 387         ret = intel_ring_begin(ring, 6);
 388         if (ret)
 389                 return ret;
 390
 391         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 392         intel_ring_emit(ring, flags);
 393         intel_ring_emit(ring, scratch_addr);
 394         intel_ring_emit(ring, 0);
 395         intel_ring_emit(ring, 0);
 396         intel_ring_emit(ring, 0);
 397         intel_ring_advance(ring);
 398
 399         return 0;
 400 }
 401
 402 static int
 403 gen8_render_ring_flush(struct intel_engine_cs *ring,
 404                        u32 invalidate_domains, u32 flush_domains)
 405 {
 406         u32 flags = 0;
 407         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 408         int ret;
 409
 410         flags |= PIPE_CONTROL_CS_STALL;
 411
 412         if (flush_domains) {
 413                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 414                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 415         }
 416         if (invalidate_domains) {
 417                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 418                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 419                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 420                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 421                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 422                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 423                 flags |= PIPE_CONTROL_QW_WRITE;
 424                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 425
 426                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 427                 ret = gen8_emit_pipe_control(ring,
 428                                              PIPE_CONTROL_CS_STALL |
 429                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 430                                              0);
 431                 if (ret)
 432                         return ret;
 433         }
 434
 435         return gen8_emit_pipe_control(ring, flags, scratch_addr);
 436 }
 437
 438 static void ring_write_tail(struct intel_engine_cs *ring,
 439                             u32 value)
 440 {
 441         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 442         I915_WRITE_TAIL(ring, value);
 443 }
 444
 445 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 446 {
 447         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 448         u64 acthd;
 449
 450         if (INTEL_INFO(ring->dev)->gen >= 8)
 451                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 452                                          RING_ACTHD_UDW(ring->mmio_base));
 453         else if (INTEL_INFO(ring->dev)->gen >= 4)
 454                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 455         else
 456                 acthd = I915_READ(ACTHD);
 457
 458         return acthd;
 459 }
 460
 461 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 462 {
 463         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 464         u32 addr;
 465
 466         addr = dev_priv->status_page_dmah->busaddr;
 467         if (INTEL_INFO(ring->dev)->gen >= 4)
 468                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 469         I915_WRITE(HWS_PGA, addr);
 470 }
 471
 472 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 473 {
 474         struct drm_device *dev = ring->dev;
 475         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 476         u32 mmio = 0;
 477
 478         /* The ring status page addresses are no longer next to the rest of
 479          * the ring registers as of gen7.
 480          */
 481         if (IS_GEN7(dev)) {
 482                 switch (ring->id) {
 483                 case RCS:
 484                         mmio = RENDER_HWS_PGA_GEN7;
 485                         break;
 486                 case BCS:
 487                         mmio = BLT_HWS_PGA_GEN7;
 488                         break;
 489                 /*
 490                  * VCS2 actually doesn't exist on Gen7. Only shut up
 491                  * gcc switch check warning
 492                  */
 493                 case VCS2:
 494                 case VCS:
 495                         mmio = BSD_HWS_PGA_GEN7;
 496                         break;
 497                 case VECS:
 498                         mmio = VEBOX_HWS_PGA_GEN7;
 499                         break;
 500                 }
 501         } else if (IS_GEN6(ring->dev)) {
 502                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 503         } else {
 504                 /* XXX: gen8 returns to sanity */
 505                 mmio = RING_HWS_PGA(ring->mmio_base);
 506         }
 507
 508         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 509         POSTING_READ(mmio);
 510
 511         /*
 512          * Flush the TLB for this page
 513          *
 514          * FIXME: These two bits have disappeared on gen8, so a question
 515          * arises: do we still need this and if so how should we go about
 516          * invalidating the TLB?
 517          */
 518         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 519                 u32 reg = RING_INSTPM(ring->mmio_base);
 520
 521                 /* ring should be idle before issuing a sync flush*/
 522                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 523
 524                 I915_WRITE(reg,
 525                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 526                                               INSTPM_SYNC_FLUSH));
 527                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 528                              1000))
 529                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 530                                   ring->name);
 531         }
 532 }
 533
 534 static bool stop_ring(struct intel_engine_cs *ring)
 535 {
 536         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 537
 538         if (!IS_GEN2(ring->dev)) {
 539                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 540                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 541                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 542                         /* Sometimes we observe that the idle flag is not
 543                          * set even though the ring is empty. So double
 544                          * check before giving up.
 545                          */
 546                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 547                                 return false;
 548                 }
 549         }
 550
 551         I915_WRITE_CTL(ring, 0);
 552         I915_WRITE_HEAD(ring, 0);
 553         ring->write_tail(ring, 0);
 554
 555         if (!IS_GEN2(ring->dev)) {
 556                 (void)I915_READ_CTL(ring);
 557                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 558         }
 559
 560         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 561 }
 562
 563 static int init_ring_common(struct intel_engine_cs *ring)
 564 {
 565         struct drm_device *dev = ring->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_ringbuffer *ringbuf = ring->buffer;
 568         struct drm_i915_gem_object *obj = ringbuf->obj;
 569         int ret = 0;
 570
 571         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 572
 573         if (!stop_ring(ring)) {
 574                 /* G45 ring initialization often fails to reset head to zero */
 575                 DRM_DEBUG_KMS("%s head not reset to zero "
 576                               "ctl %08x head %08x tail %08x start %08x\n",
 577                               ring->name,
 578                               I915_READ_CTL(ring),
 579                               I915_READ_HEAD(ring),
 580                               I915_READ_TAIL(ring),
 581                               I915_READ_START(ring));
 582
 583                 if (!stop_ring(ring)) {
 584                         DRM_ERROR("failed to set %s head to zero "
 585                                   "ctl %08x head %08x tail %08x start %08x\n",
 586                                   ring->name,
 587                                   I915_READ_CTL(ring),
 588                                   I915_READ_HEAD(ring),
 589                                   I915_READ_TAIL(ring),
 590                                   I915_READ_START(ring));
 591                         ret = -EIO;
 592                         goto out;
 593                 }
 594         }
 595
 596         if (I915_NEED_GFX_HWS(dev))
 597                 intel_ring_setup_status_page(ring);
 598         else
 599                 ring_setup_phys_status_page(ring);
 600
 601         /* Enforce ordering by reading HEAD register back */
 602         I915_READ_HEAD(ring);
 603
 604         /* Initialize the ring. This must happen _after_ we've cleared the ring
 605          * registers with the above sequence (the readback of the HEAD registers
 606          * also enforces ordering), otherwise the hw might lose the new ring
 607          * register values. */
 608         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 609
 610         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 611         if (I915_READ_HEAD(ring))
 612                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 613                           ring->name, I915_READ_HEAD(ring));
 614         I915_WRITE_HEAD(ring, 0);
 615         (void)I915_READ_HEAD(ring);
 616
 617         I915_WRITE_CTL(ring,
 618                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 619                         | RING_VALID);
 620
 621         /* If the head is still not zero, the ring is dead */
 622         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 623                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 624                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 625                 DRM_ERROR("%s initialization failed "
 626                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 627                           ring->name,
 628                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 629                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 630                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 631                 ret = -EIO;
 632                 goto out;
 633         }
 634
 635         ringbuf->last_retired_head = -1;
 636         ringbuf->head = I915_READ_HEAD(ring);
 637         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 638         intel_ring_update_space(ringbuf);
 639
 640         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 641
 642 out:
 643         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 644
 645         return ret;
 646 }
 647
 648 void
 649 intel_fini_pipe_control(struct intel_engine_cs *ring)
 650 {
 651         struct drm_device *dev = ring->dev;
 652
 653         if (ring->scratch.obj == NULL)
 654                 return;
 655
 656         if (INTEL_INFO(dev)->gen >= 5) {
 657                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 658                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 659         }
 660
 661         drm_gem_object_unreference(&ring->scratch.obj->base);
 662         ring->scratch.obj = NULL;
 663 }
 664
 665 int
 666 intel_init_pipe_control(struct intel_engine_cs *ring)
 667 {
 668         int ret;
 669
 670         WARN_ON(ring->scratch.obj);
 671
 672         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 673         if (ring->scratch.obj == NULL) {
 674                 DRM_ERROR("Failed to allocate seqno page\n");
 675                 ret = -ENOMEM;
 676                 goto err;
 677         }
 678
 679         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 680         if (ret)
 681                 goto err_unref;
 682
 683         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 684         if (ret)
 685                 goto err_unref;
 686
 687         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 688         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 689         if (ring->scratch.cpu_page == NULL) {
 690                 ret = -ENOMEM;
 691                 goto err_unpin;
 692         }
 693
 694         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 695                          ring->name, ring->scratch.gtt_offset);
 696         return 0;
 697
 698 err_unpin:
 699         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 700 err_unref:
 701         drm_gem_object_unreference(&ring->scratch.obj->base);
 702 err:
 703         return ret;
 704 }
 705
 706 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 707                                        struct intel_context *ctx)
 708 {
 709         int ret, i;
 710         struct drm_device *dev = ring->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct i915_workarounds *w = &dev_priv->workarounds;
 713
 714         if (WARN_ON_ONCE(w->count == 0))
 715                 return 0;
 716
 717         ring->gpu_caches_dirty = true;
 718         ret = intel_ring_flush_all_caches(ring);
 719         if (ret)
 720                 return ret;
 721
 722         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 723         if (ret)
 724                 return ret;
 725
 726         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 727         for (i = 0; i < w->count; i++) {
 728                 intel_ring_emit(ring, w->reg[i].addr);
 729                 intel_ring_emit(ring, w->reg[i].value);
 730         }
 731         intel_ring_emit(ring, MI_NOOP);
 732
 733         intel_ring_advance(ring);
 734
 735         ring->gpu_caches_dirty = true;
 736         ret = intel_ring_flush_all_caches(ring);
 737         if (ret)
 738                 return ret;
 739
 740         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 741
 742         return 0;
 743 }
 744
 745 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 746                               struct intel_context *ctx)
 747 {
 748         int ret;
 749
 750         ret = intel_ring_workarounds_emit(ring, ctx);
 751         if (ret != 0)
 752                 return ret;
 753
 754         ret = i915_gem_render_state_init(ring);
 755         if (ret)
 756                 DRM_ERROR("init render state: %d\n", ret);
 757
 758         return ret;
 759 }
 760
 761 static int wa_add(struct drm_i915_private *dev_priv,
 762                   const u32 addr, const u32 mask, const u32 val)
 763 {
 764         const u32 idx = dev_priv->workarounds.count;
 765
 766         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 767                 return -ENOSPC;
 768
 769         dev_priv->workarounds.reg[idx].addr = addr;
 770         dev_priv->workarounds.reg[idx].value = val;
 771         dev_priv->workarounds.reg[idx].mask = mask;
 772
 773         dev_priv->workarounds.count++;
 774
 775         return 0;
 776 }
 777
 778 #define WA_REG(addr, mask, val) { \
 779                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 780                 if (r) \
 781                         return r; \
 782         }
 783
 784 #define WA_SET_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 786
 787 #define WA_CLR_BIT_MASKED(addr, mask) \
 788         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 789
 790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 791         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 792
 793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 795
 796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 797
 798 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 799 {
 800         struct drm_device *dev = ring->dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802
 803         /* WaDisablePartialInstShootdown:bdw */
 804         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 805         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 806                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 807                           STALL_DOP_GATING_DISABLE);
 808
 809         /* WaDisableDopClockGating:bdw */
 810         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 811                           DOP_CLOCK_GATING_DISABLE);
 812
 813         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 814                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 815
 816         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 817          * workaround for for a possible hang in the unlikely event a TLB
 818          * invalidation occurs during a PSD flush.
 819          */
 820         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 821                           /* WaForceEnableNonCoherent:bdw */
 822                           HDC_FORCE_NON_COHERENT |
 823                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 824                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 825                           /* WaHdcDisableFetchWhenMasked:bdw */
 826                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 827                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 828                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 829
 830         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 831          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 832          *  polygons in the same 8x4 pixel/sample area to be processed without
 833          *  stalling waiting for the earlier ones to write to Hierarchical Z
 834          *  buffer."
 835          *
 836          * This optimization is off by default for Broadwell; turn it on.
 837          */
 838         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 839
 840         /* Wa4x4STCOptimizationDisable:bdw */
 841         WA_SET_BIT_MASKED(CACHE_MODE_1,
 842                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 843
 844         /*
 845          * BSpec recommends 8x4 when MSAA is used,
 846          * however in practice 16x4 seems fastest.
 847          *
 848          * Note that PS/WM thread counts depend on the WIZ hashing
 849          * disable bit, which we don't touch here, but it's good
 850          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 851          */
 852         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 853                             GEN6_WIZ_HASHING_MASK,
 854                             GEN6_WIZ_HASHING_16x4);
 855
 856         return 0;
 857 }
 858
 859 static int chv_init_workarounds(struct intel_engine_cs *ring)
 860 {
 861         struct drm_device *dev = ring->dev;
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863
 864         /* WaDisablePartialInstShootdown:chv */
 865         /* WaDisableThreadStallDopClockGating:chv */
 866         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 867                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 868                           STALL_DOP_GATING_DISABLE);
 869
 870         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 871          * workaround for a possible hang in the unlikely event a TLB
 872          * invalidation occurs during a PSD flush.
 873          */
 874         /* WaForceEnableNonCoherent:chv */
 875         /* WaHdcDisableFetchWhenMasked:chv */
 876         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 877                           HDC_FORCE_NON_COHERENT |
 878                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 879
 880         /* According to the CACHE_MODE_0 default value documentation, some
 881          * CHV platforms disable this optimization by default.  Turn it on.
 882          */
 883         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 884
 885         /* Wa4x4STCOptimizationDisable:chv */
 886         WA_SET_BIT_MASKED(CACHE_MODE_1,
 887                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 888
 889         /* Improve HiZ throughput on CHV. */
 890         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 891
 892         /*
 893          * BSpec recommends 8x4 when MSAA is used,
 894          * however in practice 16x4 seems fastest.
 895          *
 896          * Note that PS/WM thread counts depend on the WIZ hashing
 897          * disable bit, which we don't touch here, but it's good
 898          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 899          */
 900         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 901                             GEN6_WIZ_HASHING_MASK,
 902                             GEN6_WIZ_HASHING_16x4);
 903
 904         return 0;
 905 }
 906
 907 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 908 {
 909         struct drm_device *dev = ring->dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         uint32_t tmp;
 912
 913         /* WaDisablePartialInstShootdown:skl,bxt */
 914         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 915                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 916
 917         /* Syncing dependencies between camera and graphics:skl,bxt */
 918         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 919                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 920
 921         if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 922             INTEL_REVID(dev) == SKL_REVID_B0)) ||
 923             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 924                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 925                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 926                                   GEN9_DG_MIRROR_FIX_ENABLE);
 927         }
 928
 929         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
 930             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 931                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 932                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 933                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 934                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 935                                   DISABLE_PIXEL_MASK_CAMMING);
 936         }
 937
 938         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 939             IS_BROXTON(dev)) {
 940                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 941                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 942                                   GEN9_ENABLE_YV12_BUGFIX);
 943         }
 944
 945         /* Wa4x4STCOptimizationDisable:skl,bxt */
 946         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 947
 948         /* WaDisablePartialResolveInVc:skl,bxt */
 949         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 950
 951         /* WaCcsTlbPrefetchDisable:skl,bxt */
 952         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 953                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 954
 955         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 956         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
 957             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 958                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 959                                   PIXEL_MASK_CAMMING_DISABLE);
 960
 961         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 962         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 963         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
 964             (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
 965                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 966         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 967
 968         return 0;
 969 }
 970
 971 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 972 {
 973         struct drm_device *dev = ring->dev;
 974         struct drm_i915_private *dev_priv = dev->dev_private;
 975         u8 vals[3] = { 0, 0, 0 };
 976         unsigned int i;
 977
 978         for (i = 0; i < 3; i++) {
 979                 u8 ss;
 980
 981                 /*
 982                  * Only consider slices where one, and only one, subslice has 7
 983                  * EUs
 984                  */
 985                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
 986                         continue;
 987
 988                 /*
 989                  * subslice_7eu[i] != 0 (because of the check above) and
 990                  * ss_max == 4 (maximum number of subslices possible per slice)
 991                  *
 992                  * ->    0 <= ss <= 3;
 993                  */
 994                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
 995                 vals[i] = 3 - ss;
 996         }
 997
 998         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 999                 return 0;
1000
1001         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1002         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1003                             GEN9_IZ_HASHING_MASK(2) |
1004                             GEN9_IZ_HASHING_MASK(1) |
1005                             GEN9_IZ_HASHING_MASK(0),
1006                             GEN9_IZ_HASHING(2, vals[2]) |
1007                             GEN9_IZ_HASHING(1, vals[1]) |
1008                             GEN9_IZ_HASHING(0, vals[0]));
1009
1010         return 0;
1011 }
1012
1013
1014 static int skl_init_workarounds(struct intel_engine_cs *ring)
1015 {
1016         struct drm_device *dev = ring->dev;
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018
1019         gen9_init_workarounds(ring);
1020
1021         /* WaDisablePowerCompilerClockGating:skl */
1022         if (INTEL_REVID(dev) == SKL_REVID_B0)
1023                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1024                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1025
1026         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1027             INTEL_REVID(dev) == SKL_REVID_D0)
1028                 /* WaBarrierPerformanceFixDisable:skl */
1029                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1030                                   HDC_FENCE_DEST_SLM_DISABLE |
1031                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1032
1033         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1034                 /*
1035                  *Use Force Non-Coherent whenever executing a 3D context. This
1036                  * is a workaround for a possible hang in the unlikely event
1037                  * a TLB invalidation occurs during a PSD flush.
1038                  */
1039                 /* WaForceEnableNonCoherent:skl */
1040                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1041                                   HDC_FORCE_NON_COHERENT);
1042         }
1043
1044         return skl_tune_iz_hashing(ring);
1045 }
1046
1047 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1048 {
1049         struct drm_device *dev = ring->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051
1052         gen9_init_workarounds(ring);
1053
1054         /* WaDisableThreadStallDopClockGating:bxt */
1055         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1056                           STALL_DOP_GATING_DISABLE);
1057
1058         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1059         if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1060                 WA_SET_BIT_MASKED(
1061                         GEN7_HALF_SLICE_CHICKEN1,
1062                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1063         }
1064
1065         return 0;
1066 }
1067
1068 int init_workarounds_ring(struct intel_engine_cs *ring)
1069 {
1070         struct drm_device *dev = ring->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072
1073         WARN_ON(ring->id != RCS);
1074
1075         dev_priv->workarounds.count = 0;
1076
1077         if (IS_BROADWELL(dev))
1078                 return bdw_init_workarounds(ring);
1079
1080         if (IS_CHERRYVIEW(dev))
1081                 return chv_init_workarounds(ring);
1082
1083         if (IS_SKYLAKE(dev))
1084                 return skl_init_workarounds(ring);
1085
1086         if (IS_BROXTON(dev))
1087                 return bxt_init_workarounds(ring);
1088
1089         return 0;
1090 }
1091
1092 static int init_render_ring(struct intel_engine_cs *ring)
1093 {
1094         struct drm_device *dev = ring->dev;
1095         struct drm_i915_private *dev_priv = dev->dev_private;
1096         int ret = init_ring_common(ring);
1097         if (ret)
1098                 return ret;
1099
1100         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1101         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1102                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1103
1104         /* We need to disable the AsyncFlip performance optimisations in order
1105          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1106          * programmed to '1' on all products.
1107          *
1108          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1109          */
1110         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1111                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1112
1113         /* Required for the hardware to program scanline values for waiting */
1114         /* WaEnableFlushTlbInvalidationMode:snb */
1115         if (INTEL_INFO(dev)->gen == 6)
1116                 I915_WRITE(GFX_MODE,
1117                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1118
1119         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1120         if (IS_GEN7(dev))
1121                 I915_WRITE(GFX_MODE_GEN7,
1122                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1123                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1124
1125         if (IS_GEN6(dev)) {
1126                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1127                  * "If this bit is set, STCunit will have LRA as replacement
1128                  *  policy. [...] This bit must be reset.  LRA replacement
1129                  *  policy is not supported."
1130                  */
1131                 I915_WRITE(CACHE_MODE_0,
1132                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1133         }
1134
1135         if (INTEL_INFO(dev)->gen >= 6)
1136                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1137
1138         if (HAS_L3_DPF(dev))
1139                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1140
1141         return init_workarounds_ring(ring);
1142 }
1143
1144 static void render_ring_cleanup(struct intel_engine_cs *ring)
1145 {
1146         struct drm_device *dev = ring->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         if (dev_priv->semaphore_obj) {
1150                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1151                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1152                 dev_priv->semaphore_obj = NULL;
1153         }
1154
1155         intel_fini_pipe_control(ring);
1156 }
1157
1158 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1159                            unsigned int num_dwords)
1160 {
1161 #define MBOX_UPDATE_DWORDS 8
1162         struct drm_device *dev = signaller->dev;
1163         struct drm_i915_private *dev_priv = dev->dev_private;
1164         struct intel_engine_cs *waiter;
1165         int i, ret, num_rings;
1166
1167         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1168         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1169 #undef MBOX_UPDATE_DWORDS
1170
1171         ret = intel_ring_begin(signaller, num_dwords);
1172         if (ret)
1173                 return ret;
1174
1175         for_each_ring(waiter, dev_priv, i) {
1176                 u32 seqno;
1177                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1178                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1179                         continue;
1180
1181                 seqno = i915_gem_request_get_seqno(
1182                                            signaller->outstanding_lazy_request);
1183                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1184                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1185                                            PIPE_CONTROL_QW_WRITE |
1186                                            PIPE_CONTROL_FLUSH_ENABLE);
1187                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1188                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1189                 intel_ring_emit(signaller, seqno);
1190                 intel_ring_emit(signaller, 0);
1191                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1192                                            MI_SEMAPHORE_TARGET(waiter->id));
1193                 intel_ring_emit(signaller, 0);
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1200                            unsigned int num_dwords)
1201 {
1202 #define MBOX_UPDATE_DWORDS 6
1203         struct drm_device *dev = signaller->dev;
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         struct intel_engine_cs *waiter;
1206         int i, ret, num_rings;
1207
1208         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1209         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1210 #undef MBOX_UPDATE_DWORDS
1211
1212         ret = intel_ring_begin(signaller, num_dwords);
1213         if (ret)
1214                 return ret;
1215
1216         for_each_ring(waiter, dev_priv, i) {
1217                 u32 seqno;
1218                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1219                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1220                         continue;
1221
1222                 seqno = i915_gem_request_get_seqno(
1223                                            signaller->outstanding_lazy_request);
1224                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1225                                            MI_FLUSH_DW_OP_STOREDW);
1226                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1227                                            MI_FLUSH_DW_USE_GTT);
1228                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1229                 intel_ring_emit(signaller, seqno);
1230                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1231                                            MI_SEMAPHORE_TARGET(waiter->id));
1232                 intel_ring_emit(signaller, 0);
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int gen6_signal(struct intel_engine_cs *signaller,
1239                        unsigned int num_dwords)
1240 {
1241         struct drm_device *dev = signaller->dev;
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         struct intel_engine_cs *useless;
1244         int i, ret, num_rings;
1245
1246 #define MBOX_UPDATE_DWORDS 3
1247         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1248         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1249 #undef MBOX_UPDATE_DWORDS
1250
1251         ret = intel_ring_begin(signaller, num_dwords);
1252         if (ret)
1253                 return ret;
1254
1255         for_each_ring(useless, dev_priv, i) {
1256                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1257                 if (mbox_reg != GEN6_NOSYNC) {
1258                         u32 seqno = i915_gem_request_get_seqno(
1259                                            signaller->outstanding_lazy_request);
1260                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1261                         intel_ring_emit(signaller, mbox_reg);
1262                         intel_ring_emit(signaller, seqno);
1263                 }
1264         }
1265
1266         /* If num_dwords was rounded, make sure the tail pointer is correct */
1267         if (num_rings % 2 == 0)
1268                 intel_ring_emit(signaller, MI_NOOP);
1269
1270         return 0;
1271 }
1272
1273 /**
1274  * gen6_add_request - Update the semaphore mailbox registers
1275  *
1276  * @ring - ring that is adding a request
1277  * @seqno - return seqno stuck into the ring
1278  *
1279  * Update the mailbox registers in the *other* rings with the current seqno.
1280  * This acts like a signal in the canonical semaphore.
1281  */
1282 static int
1283 gen6_add_request(struct intel_engine_cs *ring)
1284 {
1285         int ret;
1286
1287         if (ring->semaphore.signal)
1288                 ret = ring->semaphore.signal(ring, 4);
1289         else
1290                 ret = intel_ring_begin(ring, 4);
1291
1292         if (ret)
1293                 return ret;
1294
1295         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1296         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1297         intel_ring_emit(ring,
1298                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1299         intel_ring_emit(ring, MI_USER_INTERRUPT);
1300         __intel_ring_advance(ring);
1301
1302         return 0;
1303 }
1304
1305 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1306                                               u32 seqno)
1307 {
1308         struct drm_i915_private *dev_priv = dev->dev_private;
1309         return dev_priv->last_seqno < seqno;
1310 }
1311
1312 /**
1313  * intel_ring_sync - sync the waiter to the signaller on seqno
1314  *
1315  * @waiter - ring that is waiting
1316  * @signaller - ring which has, or will signal
1317  * @seqno - seqno which the waiter will block on
1318  */
1319
1320 static int
1321 gen8_ring_sync(struct intel_engine_cs *waiter,
1322                struct intel_engine_cs *signaller,
1323                u32 seqno)
1324 {
1325         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1326         int ret;
1327
1328         ret = intel_ring_begin(waiter, 4);
1329         if (ret)
1330                 return ret;
1331
1332         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1333                                 MI_SEMAPHORE_GLOBAL_GTT |
1334                                 MI_SEMAPHORE_POLL |
1335                                 MI_SEMAPHORE_SAD_GTE_SDD);
1336         intel_ring_emit(waiter, seqno);
1337         intel_ring_emit(waiter,
1338                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1339         intel_ring_emit(waiter,
1340                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1341         intel_ring_advance(waiter);
1342         return 0;
1343 }
1344
1345 static int
1346 gen6_ring_sync(struct intel_engine_cs *waiter,
1347                struct intel_engine_cs *signaller,
1348                u32 seqno)
1349 {
1350         u32 dw1 = MI_SEMAPHORE_MBOX |
1351                   MI_SEMAPHORE_COMPARE |
1352                   MI_SEMAPHORE_REGISTER;
1353         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1354         int ret;
1355
1356         /* Throughout all of the GEM code, seqno passed implies our current
1357          * seqno is >= the last seqno executed. However for hardware the
1358          * comparison is strictly greater than.
1359          */
1360         seqno -= 1;
1361
1362         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1363
1364         ret = intel_ring_begin(waiter, 4);
1365         if (ret)
1366                 return ret;
1367
1368         /* If seqno wrap happened, omit the wait with no-ops */
1369         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1370                 intel_ring_emit(waiter, dw1 | wait_mbox);
1371                 intel_ring_emit(waiter, seqno);
1372                 intel_ring_emit(waiter, 0);
1373                 intel_ring_emit(waiter, MI_NOOP);
1374         } else {
1375                 intel_ring_emit(waiter, MI_NOOP);
1376                 intel_ring_emit(waiter, MI_NOOP);
1377                 intel_ring_emit(waiter, MI_NOOP);
1378                 intel_ring_emit(waiter, MI_NOOP);
1379         }
1380         intel_ring_advance(waiter);
1381
1382         return 0;
1383 }
1384
1385 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1386 do {                                                                    \
1387         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1388                  PIPE_CONTROL_DEPTH_STALL);                             \
1389         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1390         intel_ring_emit(ring__, 0);                                                     \
1391         intel_ring_emit(ring__, 0);                                                     \
1392 } while (0)
1393
1394 static int
1395 pc_render_add_request(struct intel_engine_cs *ring)
1396 {
1397         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1398         int ret;
1399
1400         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1401          * incoherent with writes to memory, i.e. completely fubar,
1402          * so we need to use PIPE_NOTIFY instead.
1403          *
1404          * However, we also need to workaround the qword write
1405          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1406          * memory before requesting an interrupt.
1407          */
1408         ret = intel_ring_begin(ring, 32);
1409         if (ret)
1410                 return ret;
1411
1412         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1413                         PIPE_CONTROL_WRITE_FLUSH |
1414                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1415         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1416         intel_ring_emit(ring,
1417                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1418         intel_ring_emit(ring, 0);
1419         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1420         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1421         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1422         scratch_addr += 2 * CACHELINE_BYTES;
1423         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1424         scratch_addr += 2 * CACHELINE_BYTES;
1425         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1426         scratch_addr += 2 * CACHELINE_BYTES;
1427         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1428         scratch_addr += 2 * CACHELINE_BYTES;
1429         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1430
1431         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1432                         PIPE_CONTROL_WRITE_FLUSH |
1433                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1434                         PIPE_CONTROL_NOTIFY);
1435         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1436         intel_ring_emit(ring,
1437                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1438         intel_ring_emit(ring, 0);
1439         __intel_ring_advance(ring);
1440
1441         return 0;
1442 }
1443
1444 static u32
1445 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1446 {
1447         /* Workaround to force correct ordering between irq and seqno writes on
1448          * ivb (and maybe also on snb) by reading from a CS register (like
1449          * ACTHD) before reading the status page. */
1450         if (!lazy_coherency) {
1451                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1452                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1453         }
1454
1455         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1456 }
1457
1458 static u32
1459 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1460 {
1461         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1462 }
1463
1464 static void
1465 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1466 {
1467         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1468 }
1469
1470 static u32
1471 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1472 {
1473         return ring->scratch.cpu_page[0];
1474 }
1475
1476 static void
1477 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1478 {
1479         ring->scratch.cpu_page[0] = seqno;
1480 }
1481
1482 static bool
1483 gen5_ring_get_irq(struct intel_engine_cs *ring)
1484 {
1485         struct drm_device *dev = ring->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         unsigned long flags;
1488
1489         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1490                 return false;
1491
1492         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1493         if (ring->irq_refcount++ == 0)
1494                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1495         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1496
1497         return true;
1498 }
1499
1500 static void
1501 gen5_ring_put_irq(struct intel_engine_cs *ring)
1502 {
1503         struct drm_device *dev = ring->dev;
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         unsigned long flags;
1506
1507         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1508         if (--ring->irq_refcount == 0)
1509                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1510         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1511 }
1512
1513 static bool
1514 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1515 {
1516         struct drm_device *dev = ring->dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         unsigned long flags;
1519
1520         if (!intel_irqs_enabled(dev_priv))
1521                 return false;
1522
1523         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1524         if (ring->irq_refcount++ == 0) {
1525                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1526                 I915_WRITE(IMR, dev_priv->irq_mask);
1527                 POSTING_READ(IMR);
1528         }
1529         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1530
1531         return true;
1532 }
1533
1534 static void
1535 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1536 {
1537         struct drm_device *dev = ring->dev;
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         unsigned long flags;
1540
1541         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1542         if (--ring->irq_refcount == 0) {
1543                 dev_priv->irq_mask |= ring->irq_enable_mask;
1544                 I915_WRITE(IMR, dev_priv->irq_mask);
1545                 POSTING_READ(IMR);
1546         }
1547         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1548 }
1549
1550 static bool
1551 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1552 {
1553         struct drm_device *dev = ring->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         unsigned long flags;
1556
1557         if (!intel_irqs_enabled(dev_priv))
1558                 return false;
1559
1560         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1561         if (ring->irq_refcount++ == 0) {
1562                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1563                 I915_WRITE16(IMR, dev_priv->irq_mask);
1564                 POSTING_READ16(IMR);
1565         }
1566         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1567
1568         return true;
1569 }
1570
1571 static void
1572 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1573 {
1574         struct drm_device *dev = ring->dev;
1575         struct drm_i915_private *dev_priv = dev->dev_private;
1576         unsigned long flags;
1577
1578         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1579         if (--ring->irq_refcount == 0) {
1580                 dev_priv->irq_mask |= ring->irq_enable_mask;
1581                 I915_WRITE16(IMR, dev_priv->irq_mask);
1582                 POSTING_READ16(IMR);
1583         }
1584         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1585 }
1586
1587 static int
1588 bsd_ring_flush(struct intel_engine_cs *ring,
1589                u32     invalidate_domains,
1590                u32     flush_domains)
1591 {
1592         int ret;
1593
1594         ret = intel_ring_begin(ring, 2);
1595         if (ret)
1596                 return ret;
1597
1598         intel_ring_emit(ring, MI_FLUSH);
1599         intel_ring_emit(ring, MI_NOOP);
1600         intel_ring_advance(ring);
1601         return 0;
1602 }
1603
1604 static int
1605 i9xx_add_request(struct intel_engine_cs *ring)
1606 {
1607         int ret;
1608
1609         ret = intel_ring_begin(ring, 4);
1610         if (ret)
1611                 return ret;
1612
1613         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1614         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1615         intel_ring_emit(ring,
1616                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1617         intel_ring_emit(ring, MI_USER_INTERRUPT);
1618         __intel_ring_advance(ring);
1619
1620         return 0;
1621 }
1622
1623 static bool
1624 gen6_ring_get_irq(struct intel_engine_cs *ring)
1625 {
1626         struct drm_device *dev = ring->dev;
1627         struct drm_i915_private *dev_priv = dev->dev_private;
1628         unsigned long flags;
1629
1630         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1631                 return false;
1632
1633         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1634         if (ring->irq_refcount++ == 0) {
1635                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1636                         I915_WRITE_IMR(ring,
1637                                        ~(ring->irq_enable_mask |
1638                                          GT_PARITY_ERROR(dev)));
1639                 else
1640                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1641                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1642         }
1643         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1644
1645         return true;
1646 }
1647
1648 static void
1649 gen6_ring_put_irq(struct intel_engine_cs *ring)
1650 {
1651         struct drm_device *dev = ring->dev;
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         unsigned long flags;
1654
1655         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1656         if (--ring->irq_refcount == 0) {
1657                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1658                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1659                 else
1660                         I915_WRITE_IMR(ring, ~0);
1661                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1662         }
1663         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1664 }
1665
1666 static bool
1667 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1668 {
1669         struct drm_device *dev = ring->dev;
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         unsigned long flags;
1672
1673         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1674                 return false;
1675
1676         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1677         if (ring->irq_refcount++ == 0) {
1678                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1679                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1680         }
1681         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1682
1683         return true;
1684 }
1685
1686 static void
1687 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1688 {
1689         struct drm_device *dev = ring->dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         unsigned long flags;
1692
1693         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1694         if (--ring->irq_refcount == 0) {
1695                 I915_WRITE_IMR(ring, ~0);
1696                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1697         }
1698         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1699 }
1700
1701 static bool
1702 gen8_ring_get_irq(struct intel_engine_cs *ring)
1703 {
1704         struct drm_device *dev = ring->dev;
1705         struct drm_i915_private *dev_priv = dev->dev_private;
1706         unsigned long flags;
1707
1708         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1709                 return false;
1710
1711         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1712         if (ring->irq_refcount++ == 0) {
1713                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1714                         I915_WRITE_IMR(ring,
1715                                        ~(ring->irq_enable_mask |
1716                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1717                 } else {
1718                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1719                 }
1720                 POSTING_READ(RING_IMR(ring->mmio_base));
1721         }
1722         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1723
1724         return true;
1725 }
1726
1727 static void
1728 gen8_ring_put_irq(struct intel_engine_cs *ring)
1729 {
1730         struct drm_device *dev = ring->dev;
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         unsigned long flags;
1733
1734         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1735         if (--ring->irq_refcount == 0) {
1736                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1737                         I915_WRITE_IMR(ring,
1738                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1739                 } else {
1740                         I915_WRITE_IMR(ring, ~0);
1741                 }
1742                 POSTING_READ(RING_IMR(ring->mmio_base));
1743         }
1744         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1745 }
1746
1747 static int
1748 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1749                          u64 offset, u32 length,
1750                          unsigned dispatch_flags)
1751 {
1752         int ret;
1753
1754         ret = intel_ring_begin(ring, 2);
1755         if (ret)
1756                 return ret;
1757
1758         intel_ring_emit(ring,
1759                         MI_BATCH_BUFFER_START |
1760                         MI_BATCH_GTT |
1761                         (dispatch_flags & I915_DISPATCH_SECURE ?
1762                          0 : MI_BATCH_NON_SECURE_I965));
1763         intel_ring_emit(ring, offset);
1764         intel_ring_advance(ring);
1765
1766         return 0;
1767 }
1768
1769 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1770 #define I830_BATCH_LIMIT (256*1024)
1771 #define I830_TLB_ENTRIES (2)
1772 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1773 static int
1774 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1775                          u64 offset, u32 len,
1776                          unsigned dispatch_flags)
1777 {
1778         u32 cs_offset = ring->scratch.gtt_offset;
1779         int ret;
1780
1781         ret = intel_ring_begin(ring, 6);
1782         if (ret)
1783                 return ret;
1784
1785         /* Evict the invalid PTE TLBs */
1786         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1787         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1788         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1789         intel_ring_emit(ring, cs_offset);
1790         intel_ring_emit(ring, 0xdeadbeef);
1791         intel_ring_emit(ring, MI_NOOP);
1792         intel_ring_advance(ring);
1793
1794         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1795                 if (len > I830_BATCH_LIMIT)
1796                         return -ENOSPC;
1797
1798                 ret = intel_ring_begin(ring, 6 + 2);
1799                 if (ret)
1800                         return ret;
1801
1802                 /* Blit the batch (which has now all relocs applied) to the
1803                  * stable batch scratch bo area (so that the CS never
1804                  * stumbles over its tlb invalidation bug) ...
1805                  */
1806                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1807                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1808                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1809                 intel_ring_emit(ring, cs_offset);
1810                 intel_ring_emit(ring, 4096);
1811                 intel_ring_emit(ring, offset);
1812
1813                 intel_ring_emit(ring, MI_FLUSH);
1814                 intel_ring_emit(ring, MI_NOOP);
1815                 intel_ring_advance(ring);
1816
1817                 /* ... and execute it. */
1818                 offset = cs_offset;
1819         }
1820
1821         ret = intel_ring_begin(ring, 4);
1822         if (ret)
1823                 return ret;
1824
1825         intel_ring_emit(ring, MI_BATCH_BUFFER);
1826         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1827                                         0 : MI_BATCH_NON_SECURE));
1828         intel_ring_emit(ring, offset + len - 8);
1829         intel_ring_emit(ring, MI_NOOP);
1830         intel_ring_advance(ring);
1831
1832         return 0;
1833 }
1834
1835 static int
1836 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1837                          u64 offset, u32 len,
1838                          unsigned dispatch_flags)
1839 {
1840         int ret;
1841
1842         ret = intel_ring_begin(ring, 2);
1843         if (ret)
1844                 return ret;
1845
1846         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1847         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1848                                         0 : MI_BATCH_NON_SECURE));
1849         intel_ring_advance(ring);
1850
1851         return 0;
1852 }
1853
1854 static void cleanup_status_page(struct intel_engine_cs *ring)
1855 {
1856         struct drm_i915_gem_object *obj;
1857
1858         obj = ring->status_page.obj;
1859         if (obj == NULL)
1860                 return;
1861
1862         kunmap(sg_page(obj->pages->sgl));
1863         i915_gem_object_ggtt_unpin(obj);
1864         drm_gem_object_unreference(&obj->base);
1865         ring->status_page.obj = NULL;
1866 }
1867
1868 static int init_status_page(struct intel_engine_cs *ring)
1869 {
1870         struct drm_i915_gem_object *obj;
1871
1872         if ((obj = ring->status_page.obj) == NULL) {
1873                 unsigned flags;
1874                 int ret;
1875
1876                 obj = i915_gem_alloc_object(ring->dev, 4096);
1877                 if (obj == NULL) {
1878                         DRM_ERROR("Failed to allocate status page\n");
1879                         return -ENOMEM;
1880                 }
1881
1882                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1883                 if (ret)
1884                         goto err_unref;
1885
1886                 flags = 0;
1887                 if (!HAS_LLC(ring->dev))
1888                         /* On g33, we cannot place HWS above 256MiB, so
1889                          * restrict its pinning to the low mappable arena.
1890                          * Though this restriction is not documented for
1891                          * gen4, gen5, or byt, they also behave similarly
1892                          * and hang if the HWS is placed at the top of the
1893                          * GTT. To generalise, it appears that all !llc
1894                          * platforms have issues with us placing the HWS
1895                          * above the mappable region (even though we never
1896                          * actualy map it).
1897                          */
1898                         flags |= PIN_MAPPABLE;
1899                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1900                 if (ret) {
1901 err_unref:
1902                         drm_gem_object_unreference(&obj->base);
1903                         return ret;
1904                 }
1905
1906                 ring->status_page.obj = obj;
1907         }
1908
1909         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1910         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1911         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1912
1913         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1914                         ring->name, ring->status_page.gfx_addr);
1915
1916         return 0;
1917 }
1918
1919 static int init_phys_status_page(struct intel_engine_cs *ring)
1920 {
1921         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1922
1923         if (!dev_priv->status_page_dmah) {
1924                 dev_priv->status_page_dmah =
1925                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1926                 if (!dev_priv->status_page_dmah)
1927                         return -ENOMEM;
1928         }
1929
1930         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1931         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1932
1933         return 0;
1934 }
1935
1936 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1937 {
1938         iounmap(ringbuf->virtual_start);
1939         ringbuf->virtual_start = NULL;
1940         i915_gem_object_ggtt_unpin(ringbuf->obj);
1941 }
1942
1943 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1944                                      struct intel_ringbuffer *ringbuf)
1945 {
1946         struct drm_i915_private *dev_priv = to_i915(dev);
1947         struct drm_i915_gem_object *obj = ringbuf->obj;
1948         int ret;
1949
1950         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1951         if (ret)
1952                 return ret;
1953
1954         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1955         if (ret) {
1956                 i915_gem_object_ggtt_unpin(obj);
1957                 return ret;
1958         }
1959
1960         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1961                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1962         if (ringbuf->virtual_start == NULL) {
1963                 i915_gem_object_ggtt_unpin(obj);
1964                 return -EINVAL;
1965         }
1966
1967         return 0;
1968 }
1969
1970 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1971 {
1972         drm_gem_object_unreference(&ringbuf->obj->base);
1973         ringbuf->obj = NULL;
1974 }
1975
1976 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1977                                struct intel_ringbuffer *ringbuf)
1978 {
1979         struct drm_i915_gem_object *obj;
1980
1981         obj = NULL;
1982         if (!HAS_LLC(dev))
1983                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1984         if (obj == NULL)
1985                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1986         if (obj == NULL)
1987                 return -ENOMEM;
1988
1989         /* mark ring buffers as read-only from GPU side by default */
1990         obj->gt_ro = 1;
1991
1992         ringbuf->obj = obj;
1993
1994         return 0;
1995 }
1996
1997 static int intel_init_ring_buffer(struct drm_device *dev,
1998                                   struct intel_engine_cs *ring)
1999 {
2000         struct intel_ringbuffer *ringbuf;
2001         int ret;
2002
2003         WARN_ON(ring->buffer);
2004
2005         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2006         if (!ringbuf)
2007                 return -ENOMEM;
2008         ring->buffer = ringbuf;
2009
2010         ring->dev = dev;
2011         INIT_LIST_HEAD(&ring->active_list);
2012         INIT_LIST_HEAD(&ring->request_list);
2013         INIT_LIST_HEAD(&ring->execlist_queue);
2014         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2015         ringbuf->size = 32 * PAGE_SIZE;
2016         ringbuf->ring = ring;
2017         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2018
2019         init_waitqueue_head(&ring->irq_queue);
2020
2021         if (I915_NEED_GFX_HWS(dev)) {
2022                 ret = init_status_page(ring);
2023                 if (ret)
2024                         goto error;
2025         } else {
2026                 BUG_ON(ring->id != RCS);
2027                 ret = init_phys_status_page(ring);
2028                 if (ret)
2029                         goto error;
2030         }
2031
2032         WARN_ON(ringbuf->obj);
2033
2034         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2035         if (ret) {
2036                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2037                                 ring->name, ret);
2038                 goto error;
2039         }
2040
2041         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2042         if (ret) {
2043                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2044                                 ring->name, ret);
2045                 intel_destroy_ringbuffer_obj(ringbuf);
2046                 goto error;
2047         }
2048
2049         /* Workaround an erratum on the i830 which causes a hang if
2050          * the TAIL pointer points to within the last 2 cachelines
2051          * of the buffer.
2052          */
2053         ringbuf->effective_size = ringbuf->size;
2054         if (IS_I830(dev) || IS_845G(dev))
2055                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2056
2057         ret = i915_cmd_parser_init_ring(ring);
2058         if (ret)
2059                 goto error;
2060
2061         return 0;
2062
2063 error:
2064         kfree(ringbuf);
2065         ring->buffer = NULL;
2066         return ret;
2067 }
2068
2069 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2070 {
2071         struct drm_i915_private *dev_priv;
2072         struct intel_ringbuffer *ringbuf;
2073
2074         if (!intel_ring_initialized(ring))
2075                 return;
2076
2077         dev_priv = to_i915(ring->dev);
2078         ringbuf = ring->buffer;
2079
2080         intel_stop_ring_buffer(ring);
2081         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2082
2083         intel_unpin_ringbuffer_obj(ringbuf);
2084         intel_destroy_ringbuffer_obj(ringbuf);
2085         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2086
2087         if (ring->cleanup)
2088                 ring->cleanup(ring);
2089
2090         cleanup_status_page(ring);
2091
2092         i915_cmd_parser_fini_ring(ring);
2093         i915_gem_batch_pool_fini(&ring->batch_pool);
2094
2095         kfree(ringbuf);
2096         ring->buffer = NULL;
2097 }
2098
2099 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2100 {
2101         struct intel_ringbuffer *ringbuf = ring->buffer;
2102         struct drm_i915_gem_request *request;
2103         unsigned space;
2104         int ret;
2105
2106         if (intel_ring_space(ringbuf) >= n)
2107                 return 0;
2108
2109         list_for_each_entry(request, &ring->request_list, list) {
2110                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2111                                            ringbuf->size);
2112                 if (space >= n)
2113                         break;
2114         }
2115
2116         if (WARN_ON(&request->list == &ring->request_list))
2117                 return -ENOSPC;
2118
2119         ret = i915_wait_request(request);
2120         if (ret)
2121                 return ret;
2122
2123         ringbuf->space = space;
2124         return 0;
2125 }
2126
2127 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2128 {
2129         uint32_t __iomem *virt;
2130         struct intel_ringbuffer *ringbuf = ring->buffer;
2131         int rem = ringbuf->size - ringbuf->tail;
2132
2133         if (ringbuf->space < rem) {
2134                 int ret = ring_wait_for_space(ring, rem);
2135                 if (ret)
2136                         return ret;
2137         }
2138
2139         virt = ringbuf->virtual_start + ringbuf->tail;
2140         rem /= 4;
2141         while (rem--)
2142                 iowrite32(MI_NOOP, virt++);
2143
2144         ringbuf->tail = 0;
2145         intel_ring_update_space(ringbuf);
2146
2147         return 0;
2148 }
2149
2150 int intel_ring_idle(struct intel_engine_cs *ring)
2151 {
2152         struct drm_i915_gem_request *req;
2153         int ret;
2154
2155         /* We need to add any requests required to flush the objects and ring */
2156         if (ring->outstanding_lazy_request) {
2157                 ret = i915_add_request(ring);
2158                 if (ret)
2159                         return ret;
2160         }
2161
2162         /* Wait upon the last request to be completed */
2163         if (list_empty(&ring->request_list))
2164                 return 0;
2165
2166         req = list_entry(ring->request_list.prev,
2167                         struct drm_i915_gem_request,
2168                         list);
2169
2170         /* Make sure we do not trigger any retires */
2171         return __i915_wait_request(req,
2172                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2173                                    to_i915(ring->dev)->mm.interruptible,
2174                                    NULL, NULL);
2175 }
2176
2177 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2178 {
2179         request->ringbuf = request->ring->buffer;
2180         return 0;
2181 }
2182
2183 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2184                                 int bytes)
2185 {
2186         struct intel_ringbuffer *ringbuf = ring->buffer;
2187         int ret;
2188
2189         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2190                 ret = intel_wrap_ring_buffer(ring);
2191                 if (unlikely(ret))
2192                         return ret;
2193         }
2194
2195         if (unlikely(ringbuf->space < bytes)) {
2196                 ret = ring_wait_for_space(ring, bytes);
2197                 if (unlikely(ret))
2198                         return ret;
2199         }
2200
2201         return 0;
2202 }
2203
2204 int intel_ring_begin(struct intel_engine_cs *ring,
2205                      int num_dwords)
2206 {
2207         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2208         int ret;
2209
2210         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2211                                    dev_priv->mm.interruptible);
2212         if (ret)
2213                 return ret;
2214
2215         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2216         if (ret)
2217                 return ret;
2218
2219         /* Preallocate the olr before touching the ring */
2220         ret = i915_gem_request_alloc(ring, ring->default_context);
2221         if (ret)
2222                 return ret;
2223
2224         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2225         return 0;
2226 }
2227
2228 /* Align the ring tail to a cacheline boundary */
2229 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2230 {
2231         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2232         int ret;
2233
2234         if (num_dwords == 0)
2235                 return 0;
2236
2237         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2238         ret = intel_ring_begin(ring, num_dwords);
2239         if (ret)
2240                 return ret;
2241
2242         while (num_dwords--)
2243                 intel_ring_emit(ring, MI_NOOP);
2244
2245         intel_ring_advance(ring);
2246
2247         return 0;
2248 }
2249
2250 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2251 {
2252         struct drm_device *dev = ring->dev;
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255         BUG_ON(ring->outstanding_lazy_request);
2256
2257         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2258                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2259                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2260                 if (HAS_VEBOX(dev))
2261                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2262         }
2263
2264         ring->set_seqno(ring, seqno);
2265         ring->hangcheck.seqno = seqno;
2266 }
2267
2268 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2269                                      u32 value)
2270 {
2271         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2272
2273        /* Every tail move must follow the sequence below */
2274
2275         /* Disable notification that the ring is IDLE. The GT
2276          * will then assume that it is busy and bring it out of rc6.
2277          */
2278         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2279                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2280
2281         /* Clear the context id. Here be magic! */
2282         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2283
2284         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2285         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2286                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2287                      50))
2288                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2289
2290         /* Now that the ring is fully powered up, update the tail */
2291         I915_WRITE_TAIL(ring, value);
2292         POSTING_READ(RING_TAIL(ring->mmio_base));
2293
2294         /* Let the ring send IDLE messages to the GT again,
2295          * and so let it sleep to conserve power when idle.
2296          */
2297         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2298                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2299 }
2300
2301 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2302                                u32 invalidate, u32 flush)
2303 {
2304         uint32_t cmd;
2305         int ret;
2306
2307         ret = intel_ring_begin(ring, 4);
2308         if (ret)
2309                 return ret;
2310
2311         cmd = MI_FLUSH_DW;
2312         if (INTEL_INFO(ring->dev)->gen >= 8)
2313                 cmd += 1;
2314
2315         /* We always require a command barrier so that subsequent
2316          * commands, such as breadcrumb interrupts, are strictly ordered
2317          * wrt the contents of the write cache being flushed to memory
2318          * (and thus being coherent from the CPU).
2319          */
2320         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2321
2322         /*
2323          * Bspec vol 1c.5 - video engine command streamer:
2324          * "If ENABLED, all TLBs will be invalidated once the flush
2325          * operation is complete. This bit is only valid when the
2326          * Post-Sync Operation field is a value of 1h or 3h."
2327          */
2328         if (invalidate & I915_GEM_GPU_DOMAINS)
2329                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2330
2331         intel_ring_emit(ring, cmd);
2332         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2333         if (INTEL_INFO(ring->dev)->gen >= 8) {
2334                 intel_ring_emit(ring, 0); /* upper addr */
2335                 intel_ring_emit(ring, 0); /* value */
2336         } else  {
2337                 intel_ring_emit(ring, 0);
2338                 intel_ring_emit(ring, MI_NOOP);
2339         }
2340         intel_ring_advance(ring);
2341         return 0;
2342 }
2343
2344 static int
2345 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2346                               u64 offset, u32 len,
2347                               unsigned dispatch_flags)
2348 {
2349         bool ppgtt = USES_PPGTT(ring->dev) &&
2350                         !(dispatch_flags & I915_DISPATCH_SECURE);
2351         int ret;
2352
2353         ret = intel_ring_begin(ring, 4);
2354         if (ret)
2355                 return ret;
2356
2357         /* FIXME(BDW): Address space and security selectors. */
2358         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2359         intel_ring_emit(ring, lower_32_bits(offset));
2360         intel_ring_emit(ring, upper_32_bits(offset));
2361         intel_ring_emit(ring, MI_NOOP);
2362         intel_ring_advance(ring);
2363
2364         return 0;
2365 }
2366
2367 static int
2368 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2369                              u64 offset, u32 len,
2370                              unsigned dispatch_flags)
2371 {
2372         int ret;
2373
2374         ret = intel_ring_begin(ring, 2);
2375         if (ret)
2376                 return ret;
2377
2378         intel_ring_emit(ring,
2379                         MI_BATCH_BUFFER_START |
2380                         (dispatch_flags & I915_DISPATCH_SECURE ?
2381                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2382         /* bit0-7 is the length on GEN6+ */
2383         intel_ring_emit(ring, offset);
2384         intel_ring_advance(ring);
2385
2386         return 0;
2387 }
2388
2389 static int
2390 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2391                               u64 offset, u32 len,
2392                               unsigned dispatch_flags)
2393 {
2394         int ret;
2395
2396         ret = intel_ring_begin(ring, 2);
2397         if (ret)
2398                 return ret;
2399
2400         intel_ring_emit(ring,
2401                         MI_BATCH_BUFFER_START |
2402                         (dispatch_flags & I915_DISPATCH_SECURE ?
2403                          0 : MI_BATCH_NON_SECURE_I965));
2404         /* bit0-7 is the length on GEN6+ */
2405         intel_ring_emit(ring, offset);
2406         intel_ring_advance(ring);
2407
2408         return 0;
2409 }
2410
2411 /* Blitter support (SandyBridge+) */
2412
2413 static int gen6_ring_flush(struct intel_engine_cs *ring,
2414                            u32 invalidate, u32 flush)
2415 {
2416         struct drm_device *dev = ring->dev;
2417         uint32_t cmd;
2418         int ret;
2419
2420         ret = intel_ring_begin(ring, 4);
2421         if (ret)
2422                 return ret;
2423
2424         cmd = MI_FLUSH_DW;
2425         if (INTEL_INFO(dev)->gen >= 8)
2426                 cmd += 1;
2427
2428         /* We always require a command barrier so that subsequent
2429          * commands, such as breadcrumb interrupts, are strictly ordered
2430          * wrt the contents of the write cache being flushed to memory
2431          * (and thus being coherent from the CPU).
2432          */
2433         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2434
2435         /*
2436          * Bspec vol 1c.3 - blitter engine command streamer:
2437          * "If ENABLED, all TLBs will be invalidated once the flush
2438          * operation is complete. This bit is only valid when the
2439          * Post-Sync Operation field is a value of 1h or 3h."
2440          */
2441         if (invalidate & I915_GEM_DOMAIN_RENDER)
2442                 cmd |= MI_INVALIDATE_TLB;
2443         intel_ring_emit(ring, cmd);
2444         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2445         if (INTEL_INFO(dev)->gen >= 8) {
2446                 intel_ring_emit(ring, 0); /* upper addr */
2447                 intel_ring_emit(ring, 0); /* value */
2448         } else  {
2449                 intel_ring_emit(ring, 0);
2450                 intel_ring_emit(ring, MI_NOOP);
2451         }
2452         intel_ring_advance(ring);
2453
2454         return 0;
2455 }
2456
2457 int intel_init_render_ring_buffer(struct drm_device *dev)
2458 {
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2461         struct drm_i915_gem_object *obj;
2462         int ret;
2463
2464         ring->name = "render ring";
2465         ring->id = RCS;
2466         ring->mmio_base = RENDER_RING_BASE;
2467
2468         if (INTEL_INFO(dev)->gen >= 8) {
2469                 if (i915_semaphore_is_enabled(dev)) {
2470                         obj = i915_gem_alloc_object(dev, 4096);
2471                         if (obj == NULL) {
2472                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2473                                 i915.semaphores = 0;
2474                         } else {
2475                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2476                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2477                                 if (ret != 0) {
2478                                         drm_gem_object_unreference(&obj->base);
2479                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2480                                         i915.semaphores = 0;
2481                                 } else
2482                                         dev_priv->semaphore_obj = obj;
2483                         }
2484                 }
2485
2486                 ring->init_context = intel_rcs_ctx_init;
2487                 ring->add_request = gen6_add_request;
2488                 ring->flush = gen8_render_ring_flush;
2489                 ring->irq_get = gen8_ring_get_irq;
2490                 ring->irq_put = gen8_ring_put_irq;
2491                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2492                 ring->get_seqno = gen6_ring_get_seqno;
2493                 ring->set_seqno = ring_set_seqno;
2494                 if (i915_semaphore_is_enabled(dev)) {
2495                         WARN_ON(!dev_priv->semaphore_obj);
2496                         ring->semaphore.sync_to = gen8_ring_sync;
2497                         ring->semaphore.signal = gen8_rcs_signal;
2498                         GEN8_RING_SEMAPHORE_INIT;
2499                 }
2500         } else if (INTEL_INFO(dev)->gen >= 6) {
2501                 ring->add_request = gen6_add_request;
2502                 ring->flush = gen7_render_ring_flush;
2503                 if (INTEL_INFO(dev)->gen == 6)
2504                         ring->flush = gen6_render_ring_flush;
2505                 ring->irq_get = gen6_ring_get_irq;
2506                 ring->irq_put = gen6_ring_put_irq;
2507                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2508                 ring->get_seqno = gen6_ring_get_seqno;
2509                 ring->set_seqno = ring_set_seqno;
2510                 if (i915_semaphore_is_enabled(dev)) {
2511                         ring->semaphore.sync_to = gen6_ring_sync;
2512                         ring->semaphore.signal = gen6_signal;
2513                         /*
2514                          * The current semaphore is only applied on pre-gen8
2515                          * platform.  And there is no VCS2 ring on the pre-gen8
2516                          * platform. So the semaphore between RCS and VCS2 is
2517                          * initialized as INVALID.  Gen8 will initialize the
2518                          * sema between VCS2 and RCS later.
2519                          */
2520                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2521                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2522                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2523                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2524                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2525                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2526                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2527                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2528                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2529                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2530                 }
2531         } else if (IS_GEN5(dev)) {
2532                 ring->add_request = pc_render_add_request;
2533                 ring->flush = gen4_render_ring_flush;
2534                 ring->get_seqno = pc_render_get_seqno;
2535                 ring->set_seqno = pc_render_set_seqno;
2536                 ring->irq_get = gen5_ring_get_irq;
2537                 ring->irq_put = gen5_ring_put_irq;
2538                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2539                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2540         } else {
2541                 ring->add_request = i9xx_add_request;
2542                 if (INTEL_INFO(dev)->gen < 4)
2543                         ring->flush = gen2_render_ring_flush;
2544                 else
2545                         ring->flush = gen4_render_ring_flush;
2546                 ring->get_seqno = ring_get_seqno;
2547                 ring->set_seqno = ring_set_seqno;
2548                 if (IS_GEN2(dev)) {
2549                         ring->irq_get = i8xx_ring_get_irq;
2550                         ring->irq_put = i8xx_ring_put_irq;
2551                 } else {
2552                         ring->irq_get = i9xx_ring_get_irq;
2553                         ring->irq_put = i9xx_ring_put_irq;
2554                 }
2555                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2556         }
2557         ring->write_tail = ring_write_tail;
2558
2559         if (IS_HASWELL(dev))
2560                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2561         else if (IS_GEN8(dev))
2562                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2563         else if (INTEL_INFO(dev)->gen >= 6)
2564                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2565         else if (INTEL_INFO(dev)->gen >= 4)
2566                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2567         else if (IS_I830(dev) || IS_845G(dev))
2568                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2569         else
2570                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2571         ring->init_hw = init_render_ring;
2572         ring->cleanup = render_ring_cleanup;
2573
2574         /* Workaround batchbuffer to combat CS tlb bug. */
2575         if (HAS_BROKEN_CS_TLB(dev)) {
2576                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2577                 if (obj == NULL) {
2578                         DRM_ERROR("Failed to allocate batch bo\n");
2579                         return -ENOMEM;
2580                 }
2581
2582                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2583                 if (ret != 0) {
2584                         drm_gem_object_unreference(&obj->base);
2585                         DRM_ERROR("Failed to ping batch bo\n");
2586                         return ret;
2587                 }
2588
2589                 ring->scratch.obj = obj;
2590                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2591         }
2592
2593         ret = intel_init_ring_buffer(dev, ring);
2594         if (ret)
2595                 return ret;
2596
2597         if (INTEL_INFO(dev)->gen >= 5) {
2598                 ret = intel_init_pipe_control(ring);
2599                 if (ret)
2600                         return ret;
2601         }
2602
2603         return 0;
2604 }
2605
2606 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2607 {
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2610
2611         ring->name = "bsd ring";
2612         ring->id = VCS;
2613
2614         ring->write_tail = ring_write_tail;
2615         if (INTEL_INFO(dev)->gen >= 6) {
2616                 ring->mmio_base = GEN6_BSD_RING_BASE;
2617                 /* gen6 bsd needs a special wa for tail updates */
2618                 if (IS_GEN6(dev))
2619                         ring->write_tail = gen6_bsd_ring_write_tail;
2620                 ring->flush = gen6_bsd_ring_flush;
2621                 ring->add_request = gen6_add_request;
2622                 ring->get_seqno = gen6_ring_get_seqno;
2623                 ring->set_seqno = ring_set_seqno;
2624                 if (INTEL_INFO(dev)->gen >= 8) {
2625                         ring->irq_enable_mask =
2626                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2627                         ring->irq_get = gen8_ring_get_irq;
2628                         ring->irq_put = gen8_ring_put_irq;
2629                         ring->dispatch_execbuffer =
2630                                 gen8_ring_dispatch_execbuffer;
2631                         if (i915_semaphore_is_enabled(dev)) {
2632                                 ring->semaphore.sync_to = gen8_ring_sync;
2633                                 ring->semaphore.signal = gen8_xcs_signal;
2634                                 GEN8_RING_SEMAPHORE_INIT;
2635                         }
2636                 } else {
2637                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2638                         ring->irq_get = gen6_ring_get_irq;
2639                         ring->irq_put = gen6_ring_put_irq;
2640                         ring->dispatch_execbuffer =
2641                                 gen6_ring_dispatch_execbuffer;
2642                         if (i915_semaphore_is_enabled(dev)) {
2643                                 ring->semaphore.sync_to = gen6_ring_sync;
2644                                 ring->semaphore.signal = gen6_signal;
2645                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2646                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2647                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2648                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2649                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2650                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2651                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2652                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2653                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2654                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2655                         }
2656                 }
2657         } else {
2658                 ring->mmio_base = BSD_RING_BASE;
2659                 ring->flush = bsd_ring_flush;
2660                 ring->add_request = i9xx_add_request;
2661                 ring->get_seqno = ring_get_seqno;
2662                 ring->set_seqno = ring_set_seqno;
2663                 if (IS_GEN5(dev)) {
2664                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2665                         ring->irq_get = gen5_ring_get_irq;
2666                         ring->irq_put = gen5_ring_put_irq;
2667                 } else {
2668                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2669                         ring->irq_get = i9xx_ring_get_irq;
2670                         ring->irq_put = i9xx_ring_put_irq;
2671                 }
2672                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2673         }
2674         ring->init_hw = init_ring_common;
2675
2676         return intel_init_ring_buffer(dev, ring);
2677 }
2678
2679 /**
2680  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2681  */
2682 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2683 {
2684         struct drm_i915_private *dev_priv = dev->dev_private;
2685         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2686
2687         ring->name = "bsd2 ring";
2688         ring->id = VCS2;
2689
2690         ring->write_tail = ring_write_tail;
2691         ring->mmio_base = GEN8_BSD2_RING_BASE;
2692         ring->flush = gen6_bsd_ring_flush;
2693         ring->add_request = gen6_add_request;
2694         ring->get_seqno = gen6_ring_get_seqno;
2695         ring->set_seqno = ring_set_seqno;
2696         ring->irq_enable_mask =
2697                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2698         ring->irq_get = gen8_ring_get_irq;
2699         ring->irq_put = gen8_ring_put_irq;
2700         ring->dispatch_execbuffer =
2701                         gen8_ring_dispatch_execbuffer;
2702         if (i915_semaphore_is_enabled(dev)) {
2703                 ring->semaphore.sync_to = gen8_ring_sync;
2704                 ring->semaphore.signal = gen8_xcs_signal;
2705                 GEN8_RING_SEMAPHORE_INIT;
2706         }
2707         ring->init_hw = init_ring_common;
2708
2709         return intel_init_ring_buffer(dev, ring);
2710 }
2711
2712 int intel_init_blt_ring_buffer(struct drm_device *dev)
2713 {
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2716
2717         ring->name = "blitter ring";
2718         ring->id = BCS;
2719
2720         ring->mmio_base = BLT_RING_BASE;
2721         ring->write_tail = ring_write_tail;
2722         ring->flush = gen6_ring_flush;
2723         ring->add_request = gen6_add_request;
2724         ring->get_seqno = gen6_ring_get_seqno;
2725         ring->set_seqno = ring_set_seqno;
2726         if (INTEL_INFO(dev)->gen >= 8) {
2727                 ring->irq_enable_mask =
2728                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2729                 ring->irq_get = gen8_ring_get_irq;
2730                 ring->irq_put = gen8_ring_put_irq;
2731                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2732                 if (i915_semaphore_is_enabled(dev)) {
2733                         ring->semaphore.sync_to = gen8_ring_sync;
2734                         ring->semaphore.signal = gen8_xcs_signal;
2735                         GEN8_RING_SEMAPHORE_INIT;
2736                 }
2737         } else {
2738                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2739                 ring->irq_get = gen6_ring_get_irq;
2740                 ring->irq_put = gen6_ring_put_irq;
2741                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2742                 if (i915_semaphore_is_enabled(dev)) {
2743                         ring->semaphore.signal = gen6_signal;
2744                         ring->semaphore.sync_to = gen6_ring_sync;
2745                         /*
2746                          * The current semaphore is only applied on pre-gen8
2747                          * platform.  And there is no VCS2 ring on the pre-gen8
2748                          * platform. So the semaphore between BCS and VCS2 is
2749                          * initialized as INVALID.  Gen8 will initialize the
2750                          * sema between BCS and VCS2 later.
2751                          */
2752                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2753                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2754                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2755                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2756                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2757                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2758                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2759                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2760                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2761                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2762                 }
2763         }
2764         ring->init_hw = init_ring_common;
2765
2766         return intel_init_ring_buffer(dev, ring);
2767 }
2768
2769 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2770 {
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2773
2774         ring->name = "video enhancement ring";
2775         ring->id = VECS;
2776
2777         ring->mmio_base = VEBOX_RING_BASE;
2778         ring->write_tail = ring_write_tail;
2779         ring->flush = gen6_ring_flush;
2780         ring->add_request = gen6_add_request;
2781         ring->get_seqno = gen6_ring_get_seqno;
2782         ring->set_seqno = ring_set_seqno;
2783
2784         if (INTEL_INFO(dev)->gen >= 8) {
2785                 ring->irq_enable_mask =
2786                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2787                 ring->irq_get = gen8_ring_get_irq;
2788                 ring->irq_put = gen8_ring_put_irq;
2789                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2790                 if (i915_semaphore_is_enabled(dev)) {
2791                         ring->semaphore.sync_to = gen8_ring_sync;
2792                         ring->semaphore.signal = gen8_xcs_signal;
2793                         GEN8_RING_SEMAPHORE_INIT;
2794                 }
2795         } else {
2796                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2797                 ring->irq_get = hsw_vebox_get_irq;
2798                 ring->irq_put = hsw_vebox_put_irq;
2799                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2800                 if (i915_semaphore_is_enabled(dev)) {
2801                         ring->semaphore.sync_to = gen6_ring_sync;
2802                         ring->semaphore.signal = gen6_signal;
2803                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2804                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2805                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2806                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2807                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2808                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2809                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2810                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2811                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2812                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2813                 }
2814         }
2815         ring->init_hw = init_ring_common;
2816
2817         return intel_init_ring_buffer(dev, ring);
2818 }
2819
2820 int
2821 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2822 {
2823         int ret;
2824
2825         if (!ring->gpu_caches_dirty)
2826                 return 0;
2827
2828         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2829         if (ret)
2830                 return ret;
2831
2832         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2833
2834         ring->gpu_caches_dirty = false;
2835         return 0;
2836 }
2837
2838 int
2839 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2840 {
2841         uint32_t flush_domains;
2842         int ret;
2843
2844         flush_domains = 0;
2845         if (ring->gpu_caches_dirty)
2846                 flush_domains = I915_GEM_GPU_DOMAINS;
2847
2848         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2849         if (ret)
2850                 return ret;
2851
2852         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2853
2854         ring->gpu_caches_dirty = false;
2855         return 0;
2856 }
2857
2858 void
2859 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2860 {
2861         int ret;
2862
2863         if (!intel_ring_initialized(ring))
2864                 return;
2865
2866         ret = intel_ring_idle(ring);
2867         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2868                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2869                           ring->name, ret);
2870
2871         stop_ring(ring);
2872 }