drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 #include "amdgpu_atombios.h"
  41
  42 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v7_0_wait_for_idle(void *handle);
  45
  46 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  47 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  49
  50 static const u32 golden_settings_iceland_a11[] =
  51 {
  52         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  53         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  54         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  56 };
  57
  58 static const u32 iceland_mgcg_cgcg_init[] =
  59 {
  60         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  61 };
  62
  63 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  64 {
  65         switch (adev->asic_type) {
  66         case CHIP_TOPAZ:
  67                 amdgpu_program_register_sequence(adev,
  68                                                  iceland_mgcg_cgcg_init,
  69                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  70                 amdgpu_program_register_sequence(adev,
  71                                                  golden_settings_iceland_a11,
  72                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  73                 break;
  74         default:
  75                 break;
  76         }
  77 }
  78
  79 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  80 {
  81         u32 blackout;
  82
  83         gmc_v7_0_wait_for_idle((void *)adev);
  84
  85         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  86         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  87                 /* Block CPU access */
  88                 WREG32(mmBIF_FB_EN, 0);
  89                 /* blackout the MC */
  90                 blackout = REG_SET_FIELD(blackout,
  91                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  92                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  93         }
  94         /* wait for the MC to settle */
  95         udelay(100);
  96 }
  97
  98 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
  99 {
 100         u32 tmp;
 101
 102         /* unblackout the MC */
 103         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 104         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 105         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 106         /* allow CPU access */
 107         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 108         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 109         WREG32(mmBIF_FB_EN, tmp);
 110 }
 111
 112 /**
 113  * gmc_v7_0_init_microcode - load ucode images from disk
 114  *
 115  * @adev: amdgpu_device pointer
 116  *
 117  * Use the firmware interface to load the ucode images into
 118  * the driver (not loaded into hw).
 119  * Returns 0 on success, error on failure.
 120  */
 121 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 122 {
 123         const char *chip_name;
 124         char fw_name[30];
 125         int err;
 126
 127         DRM_DEBUG("\n");
 128
 129         switch (adev->asic_type) {
 130         case CHIP_BONAIRE:
 131                 chip_name = "bonaire";
 132                 break;
 133         case CHIP_HAWAII:
 134                 chip_name = "hawaii";
 135                 break;
 136         case CHIP_TOPAZ:
 137                 chip_name = "topaz";
 138                 break;
 139         case CHIP_KAVERI:
 140         case CHIP_KABINI:
 141         case CHIP_MULLINS:
 142                 return 0;
 143         default: BUG();
 144         }
 145
 146         if (adev->asic_type == CHIP_TOPAZ)
 147                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 148         else
 149                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 150
 151         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 152         if (err)
 153                 goto out;
 154         err = amdgpu_ucode_validate(adev->mc.fw);
 155
 156 out:
 157         if (err) {
 158                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 159                 release_firmware(adev->mc.fw);
 160                 adev->mc.fw = NULL;
 161         }
 162         return err;
 163 }
 164
 165 /**
 166  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 167  *
 168  * @adev: amdgpu_device pointer
 169  *
 170  * Load the GDDR MC ucode into the hw (CIK).
 171  * Returns 0 on success, error on failure.
 172  */
 173 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 174 {
 175         const struct mc_firmware_header_v1_0 *hdr;
 176         const __le32 *fw_data = NULL;
 177         const __le32 *io_mc_regs = NULL;
 178         u32 running;
 179         int i, ucode_size, regs_size;
 180
 181         if (!adev->mc.fw)
 182                 return -EINVAL;
 183
 184         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 185         amdgpu_ucode_print_mc_hdr(&hdr->header);
 186
 187         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 188         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 189         io_mc_regs = (const __le32 *)
 190                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 191         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 192         fw_data = (const __le32 *)
 193                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 194
 195         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 196
 197         if (running == 0) {
 198                 /* reset the engine and set to writable */
 199                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 200                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 201
 202                 /* load mc io regs */
 203                 for (i = 0; i < regs_size; i++) {
 204                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 205                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 206                 }
 207                 /* load the MC ucode */
 208                 for (i = 0; i < ucode_size; i++)
 209                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 210
 211                 /* put the engine back into the active state */
 212                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 213                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 214                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 215
 216                 /* wait for training to complete */
 217                 for (i = 0; i < adev->usec_timeout; i++) {
 218                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 219                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 220                                 break;
 221                         udelay(1);
 222                 }
 223                 for (i = 0; i < adev->usec_timeout; i++) {
 224                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 225                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 226                                 break;
 227                         udelay(1);
 228                 }
 229         }
 230
 231         return 0;
 232 }
 233
 234 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 235                                        struct amdgpu_mc *mc)
 236 {
 237         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 238         base <<= 24;
 239
 240         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 241                 /* leave room for at least 1024M GTT */
 242                 dev_warn(adev->dev, "limiting VRAM\n");
 243                 mc->real_vram_size = 0xFFC0000000ULL;
 244                 mc->mc_vram_size = 0xFFC0000000ULL;
 245         }
 246         amdgpu_vram_location(adev, &adev->mc, base);
 247         adev->mc.gtt_base_align = 0;
 248         amdgpu_gtt_location(adev, mc);
 249 }
 250
 251 /**
 252  * gmc_v7_0_mc_program - program the GPU memory controller
 253  *
 254  * @adev: amdgpu_device pointer
 255  *
 256  * Set the location of vram, gart, and AGP in the GPU's
 257  * physical address space (CIK).
 258  */
 259 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 260 {
 261         u32 tmp;
 262         int i, j;
 263
 264         /* Initialize HDP */
 265         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 266                 WREG32((0xb05 + j), 0x00000000);
 267                 WREG32((0xb06 + j), 0x00000000);
 268                 WREG32((0xb07 + j), 0x00000000);
 269                 WREG32((0xb08 + j), 0x00000000);
 270                 WREG32((0xb09 + j), 0x00000000);
 271         }
 272         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 273
 274         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 275                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 276         }
 277         /* Update configuration */
 278         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 279                adev->mc.vram_start >> 12);
 280         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 281                adev->mc.vram_end >> 12);
 282         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 283                adev->vram_scratch.gpu_addr >> 12);
 284         WREG32(mmMC_VM_AGP_BASE, 0);
 285         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 286         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 287         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 288                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 289         }
 290
 291         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 292
 293         tmp = RREG32(mmHDP_MISC_CNTL);
 294         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 295         WREG32(mmHDP_MISC_CNTL, tmp);
 296
 297         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 298         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 299 }
 300
 301 /**
 302  * gmc_v7_0_mc_init - initialize the memory controller driver params
 303  *
 304  * @adev: amdgpu_device pointer
 305  *
 306  * Look up the amount of vram, vram width, and decide how to place
 307  * vram and gart within the GPU's physical address space (CIK).
 308  * Returns 0 for success.
 309  */
 310 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 311 {
 312         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 313         if (!adev->mc.vram_width) {
 314                 u32 tmp;
 315                 int chansize, numchan;
 316
 317                 /* Get VRAM informations */
 318                 tmp = RREG32(mmMC_ARB_RAMCFG);
 319                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 320                         chansize = 64;
 321                 } else {
 322                         chansize = 32;
 323                 }
 324                 tmp = RREG32(mmMC_SHARED_CHMAP);
 325                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 326                 case 0:
 327                 default:
 328                         numchan = 1;
 329                         break;
 330                 case 1:
 331                         numchan = 2;
 332                         break;
 333                 case 2:
 334                         numchan = 4;
 335                         break;
 336                 case 3:
 337                         numchan = 8;
 338                         break;
 339                 case 4:
 340                         numchan = 3;
 341                         break;
 342                 case 5:
 343                         numchan = 6;
 344                         break;
 345                 case 6:
 346                         numchan = 10;
 347                         break;
 348                 case 7:
 349                         numchan = 12;
 350                         break;
 351                 case 8:
 352                         numchan = 16;
 353                         break;
 354                 }
 355                 adev->mc.vram_width = numchan * chansize;
 356         }
 357         /* Could aper size report 0 ? */
 358         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 359         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 360         /* size in MB on si */
 361         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 362         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 363
 364 #ifdef CONFIG_X86_64
 365         if (adev->flags & AMD_IS_APU) {
 366                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 367                 adev->mc.aper_size = adev->mc.real_vram_size;
 368         }
 369 #endif
 370
 371         /* In case the PCI BAR is larger than the actual amount of vram */
 372         adev->mc.visible_vram_size = adev->mc.aper_size;
 373         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 374                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 375
 376         amdgpu_gart_set_defaults(adev);
 377         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 378
 379         return 0;
 380 }
 381
 382 /*
 383  * GART
 384  * VMID 0 is the physical GPU addresses as used by the kernel.
 385  * VMIDs 1-15 are used for userspace clients and are handled
 386  * by the amdgpu vm/hsa code.
 387  */
 388
 389 /**
 390  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 391  *
 392  * @adev: amdgpu_device pointer
 393  * @vmid: vm instance to flush
 394  *
 395  * Flush the TLB for the requested page table (CIK).
 396  */
 397 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 398                                         uint32_t vmid)
 399 {
 400         /* flush hdp cache */
 401         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 402
 403         /* bits 0-15 are the VM contexts0-15 */
 404         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 405 }
 406
 407 /**
 408  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 409  *
 410  * @adev: amdgpu_device pointer
 411  * @cpu_pt_addr: cpu address of the page table
 412  * @gpu_page_idx: entry in the page table to update
 413  * @addr: dst addr to write into pte/pde
 414  * @flags: access flags
 415  *
 416  * Update the page tables using the CPU.
 417  */
 418 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 419                                      void *cpu_pt_addr,
 420                                      uint32_t gpu_page_idx,
 421                                      uint64_t addr,
 422                                      uint64_t flags)
 423 {
 424         void __iomem *ptr = (void *)cpu_pt_addr;
 425         uint64_t value;
 426
 427         value = addr & 0xFFFFFFFFFFFFF000ULL;
 428         value |= flags;
 429         writeq(value, ptr + (gpu_page_idx * 8));
 430
 431         return 0;
 432 }
 433
 434 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
 435                                           uint32_t flags)
 436 {
 437         uint64_t pte_flag = 0;
 438
 439         if (flags & AMDGPU_VM_PAGE_READABLE)
 440                 pte_flag |= AMDGPU_PTE_READABLE;
 441         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 442                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 443         if (flags & AMDGPU_VM_PAGE_PRT)
 444                 pte_flag |= AMDGPU_PTE_PRT;
 445
 446         return pte_flag;
 447 }
 448
 449 static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 450 {
 451         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 452         return addr;
 453 }
 454
 455 /**
 456  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 457  *
 458  * @adev: amdgpu_device pointer
 459  * @value: true redirects VM faults to the default page
 460  */
 461 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 462                                               bool value)
 463 {
 464         u32 tmp;
 465
 466         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 467         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 468                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 469         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 470                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 471         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 472                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 473         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 474                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 475         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 476                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 477         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 478                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 479         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 480 }
 481
 482 /**
 483  * gmc_v7_0_set_prt - set PRT VM fault
 484  *
 485  * @adev: amdgpu_device pointer
 486  * @enable: enable/disable VM fault handling for PRT
 487  */
 488 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 489 {
 490         uint32_t tmp;
 491
 492         if (enable && !adev->mc.prt_warning) {
 493                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 494                 adev->mc.prt_warning = true;
 495         }
 496
 497         tmp = RREG32(mmVM_PRT_CNTL);
 498         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 499                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 500         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 501                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 502         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 503                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 504         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 505                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 506         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 507                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 508         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 509                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 510         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 511                             MASK_PDE0_FAULT, enable);
 512         WREG32(mmVM_PRT_CNTL, tmp);
 513
 514         if (enable) {
 515                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 516                 uint32_t high = adev->vm_manager.max_pfn;
 517
 518                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 519                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 520                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 521                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 522                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 523                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 524                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 525                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 526         } else {
 527                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 528                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 529                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 530                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 531                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 532                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 533                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 534                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 535         }
 536 }
 537
 538 /**
 539  * gmc_v7_0_gart_enable - gart enable
 540  *
 541  * @adev: amdgpu_device pointer
 542  *
 543  * This sets up the TLBs, programs the page tables for VMID0,
 544  * sets up the hw for VMIDs 1-15 which are allocated on
 545  * demand, and sets up the global locations for the LDS, GDS,
 546  * and GPUVM for FSA64 clients (CIK).
 547  * Returns 0 for success, errors for failure.
 548  */
 549 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 550 {
 551         int r, i;
 552         u32 tmp;
 553
 554         if (adev->gart.robj == NULL) {
 555                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 556                 return -EINVAL;
 557         }
 558         r = amdgpu_gart_table_vram_pin(adev);
 559         if (r)
 560                 return r;
 561         /* Setup TLB control */
 562         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 563         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 564         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 565         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 566         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 567         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 568         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 569         /* Setup L2 cache */
 570         tmp = RREG32(mmVM_L2_CNTL);
 571         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 572         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 573         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 574         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 575         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 576         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 577         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 578         WREG32(mmVM_L2_CNTL, tmp);
 579         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 580         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 581         WREG32(mmVM_L2_CNTL2, tmp);
 582         tmp = RREG32(mmVM_L2_CNTL3);
 583         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 584         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 585         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 586         WREG32(mmVM_L2_CNTL3, tmp);
 587         /* setup context0 */
 588         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 589         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 590         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 591         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 592                         (u32)(adev->dummy_page.addr >> 12));
 593         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 594         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 595         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 596         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 597         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 598         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 599
 600         WREG32(0x575, 0);
 601         WREG32(0x576, 0);
 602         WREG32(0x577, 0);
 603
 604         /* empty context1-15 */
 605         /* FIXME start with 4G, once using 2 level pt switch to full
 606          * vm size space
 607          */
 608         /* set vm size, must be a multiple of 4 */
 609         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 610         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 611         for (i = 1; i < 16; i++) {
 612                 if (i < 8)
 613                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 614                                adev->gart.table_addr >> 12);
 615                 else
 616                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 617                                adev->gart.table_addr >> 12);
 618         }
 619
 620         /* enable context1-15 */
 621         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 622                (u32)(adev->dummy_page.addr >> 12));
 623         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 624         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 625         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 626         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 627         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 628                             adev->vm_manager.block_size - 9);
 629         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 630         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 631                 gmc_v7_0_set_fault_enable_default(adev, false);
 632         else
 633                 gmc_v7_0_set_fault_enable_default(adev, true);
 634
 635         if (adev->asic_type == CHIP_KAVERI) {
 636                 tmp = RREG32(mmCHUB_CONTROL);
 637                 tmp &= ~BYPASS_VM;
 638                 WREG32(mmCHUB_CONTROL, tmp);
 639         }
 640
 641         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 642         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 643                  (unsigned)(adev->mc.gtt_size >> 20),
 644                  (unsigned long long)adev->gart.table_addr);
 645         adev->gart.ready = true;
 646         return 0;
 647 }
 648
 649 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 650 {
 651         int r;
 652
 653         if (adev->gart.robj) {
 654                 WARN(1, "R600 PCIE GART already initialized\n");
 655                 return 0;
 656         }
 657         /* Initialize common gart structure */
 658         r = amdgpu_gart_init(adev);
 659         if (r)
 660                 return r;
 661         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 662         adev->gart.gart_pte_flags = 0;
 663         return amdgpu_gart_table_vram_alloc(adev);
 664 }
 665
 666 /**
 667  * gmc_v7_0_gart_disable - gart disable
 668  *
 669  * @adev: amdgpu_device pointer
 670  *
 671  * This disables all VM page table (CIK).
 672  */
 673 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 674 {
 675         u32 tmp;
 676
 677         /* Disable all tables */
 678         WREG32(mmVM_CONTEXT0_CNTL, 0);
 679         WREG32(mmVM_CONTEXT1_CNTL, 0);
 680         /* Setup TLB control */
 681         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 682         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 683         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 684         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 685         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 686         /* Setup L2 cache */
 687         tmp = RREG32(mmVM_L2_CNTL);
 688         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 689         WREG32(mmVM_L2_CNTL, tmp);
 690         WREG32(mmVM_L2_CNTL2, 0);
 691         amdgpu_gart_table_vram_unpin(adev);
 692 }
 693
 694 /**
 695  * gmc_v7_0_gart_fini - vm fini callback
 696  *
 697  * @adev: amdgpu_device pointer
 698  *
 699  * Tears down the driver GART/VM setup (CIK).
 700  */
 701 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 702 {
 703         amdgpu_gart_table_vram_free(adev);
 704         amdgpu_gart_fini(adev);
 705 }
 706
 707 /**
 708  * gmc_v7_0_vm_decode_fault - print human readable fault info
 709  *
 710  * @adev: amdgpu_device pointer
 711  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 712  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 713  *
 714  * Print human readable fault information (CIK).
 715  */
 716 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 717                                      u32 status, u32 addr, u32 mc_client)
 718 {
 719         u32 mc_id;
 720         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 721         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 722                                         PROTECTIONS);
 723         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 724                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 725
 726         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 727                               MEMORY_CLIENT_ID);
 728
 729         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 730                protections, vmid, addr,
 731                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 732                              MEMORY_CLIENT_RW) ?
 733                "write" : "read", block, mc_client, mc_id);
 734 }
 735
 736
 737 static const u32 mc_cg_registers[] = {
 738         mmMC_HUB_MISC_HUB_CG,
 739         mmMC_HUB_MISC_SIP_CG,
 740         mmMC_HUB_MISC_VM_CG,
 741         mmMC_XPB_CLK_GAT,
 742         mmATC_MISC_CG,
 743         mmMC_CITF_MISC_WR_CG,
 744         mmMC_CITF_MISC_RD_CG,
 745         mmMC_CITF_MISC_VM_CG,
 746         mmVM_L2_CG,
 747 };
 748
 749 static const u32 mc_cg_ls_en[] = {
 750         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 751         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 752         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 753         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 754         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 755         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 756         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 757         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 758         VM_L2_CG__MEM_LS_ENABLE_MASK,
 759 };
 760
 761 static const u32 mc_cg_en[] = {
 762         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 763         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 764         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 765         MC_XPB_CLK_GAT__ENABLE_MASK,
 766         ATC_MISC_CG__ENABLE_MASK,
 767         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 768         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 769         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 770         VM_L2_CG__ENABLE_MASK,
 771 };
 772
 773 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 774                                   bool enable)
 775 {
 776         int i;
 777         u32 orig, data;
 778
 779         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 780                 orig = data = RREG32(mc_cg_registers[i]);
 781                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 782                         data |= mc_cg_ls_en[i];
 783                 else
 784                         data &= ~mc_cg_ls_en[i];
 785                 if (data != orig)
 786                         WREG32(mc_cg_registers[i], data);
 787         }
 788 }
 789
 790 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 791                                     bool enable)
 792 {
 793         int i;
 794         u32 orig, data;
 795
 796         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 797                 orig = data = RREG32(mc_cg_registers[i]);
 798                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 799                         data |= mc_cg_en[i];
 800                 else
 801                         data &= ~mc_cg_en[i];
 802                 if (data != orig)
 803                         WREG32(mc_cg_registers[i], data);
 804         }
 805 }
 806
 807 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 808                                      bool enable)
 809 {
 810         u32 orig, data;
 811
 812         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 813
 814         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 815                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 816                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 817                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 818                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 819         } else {
 820                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 821                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 822                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 823                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 824         }
 825
 826         if (orig != data)
 827                 WREG32_PCIE(ixPCIE_CNTL2, data);
 828 }
 829
 830 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 831                                      bool enable)
 832 {
 833         u32 orig, data;
 834
 835         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 836
 837         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 838                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 839         else
 840                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 841
 842         if (orig != data)
 843                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 844 }
 845
 846 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 847                                    bool enable)
 848 {
 849         u32 orig, data;
 850
 851         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 852
 853         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 854                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 855         else
 856                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 857
 858         if (orig != data)
 859                 WREG32(mmHDP_MEM_POWER_LS, data);
 860 }
 861
 862 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 863 {
 864         switch (mc_seq_vram_type) {
 865         case MC_SEQ_MISC0__MT__GDDR1:
 866                 return AMDGPU_VRAM_TYPE_GDDR1;
 867         case MC_SEQ_MISC0__MT__DDR2:
 868                 return AMDGPU_VRAM_TYPE_DDR2;
 869         case MC_SEQ_MISC0__MT__GDDR3:
 870                 return AMDGPU_VRAM_TYPE_GDDR3;
 871         case MC_SEQ_MISC0__MT__GDDR4:
 872                 return AMDGPU_VRAM_TYPE_GDDR4;
 873         case MC_SEQ_MISC0__MT__GDDR5:
 874                 return AMDGPU_VRAM_TYPE_GDDR5;
 875         case MC_SEQ_MISC0__MT__HBM:
 876                 return AMDGPU_VRAM_TYPE_HBM;
 877         case MC_SEQ_MISC0__MT__DDR3:
 878                 return AMDGPU_VRAM_TYPE_DDR3;
 879         default:
 880                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 881         }
 882 }
 883
 884 static int gmc_v7_0_early_init(void *handle)
 885 {
 886         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 887
 888         gmc_v7_0_set_gart_funcs(adev);
 889         gmc_v7_0_set_irq_funcs(adev);
 890
 891         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 892         adev->mc.shared_aperture_end =
 893                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 894         adev->mc.private_aperture_start =
 895                 adev->mc.shared_aperture_end + 1;
 896         adev->mc.private_aperture_end =
 897                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 898
 899         return 0;
 900 }
 901
 902 static int gmc_v7_0_late_init(void *handle)
 903 {
 904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 905
 906         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 907                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 908         else
 909                 return 0;
 910 }
 911
 912 static int gmc_v7_0_sw_init(void *handle)
 913 {
 914         int r;
 915         int dma_bits;
 916         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 917
 918         if (adev->flags & AMD_IS_APU) {
 919                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 920         } else {
 921                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 922                 tmp &= MC_SEQ_MISC0__MT__MASK;
 923                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 924         }
 925
 926         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 927         if (r)
 928                 return r;
 929
 930         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 931         if (r)
 932                 return r;
 933
 934         /* Adjust VM size here.
 935          * Currently set to 4GB ((1 << 20) 4k pages).
 936          * Max GPUVM size for cayman and SI is 40 bits.
 937          */
 938         amdgpu_vm_adjust_size(adev, 64);
 939         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 940
 941         /* Set the internal MC address mask
 942          * This is the max address of the GPU's
 943          * internal address space.
 944          */
 945         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 946
 947         adev->mc.stolen_size = 256 * 1024;
 948
 949         /* set DMA mask + need_dma32 flags.
 950          * PCIE - can handle 40-bits.
 951          * IGP - can handle 40-bits
 952          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 953          */
 954         adev->need_dma32 = false;
 955         dma_bits = adev->need_dma32 ? 32 : 40;
 956         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 957         if (r) {
 958                 adev->need_dma32 = true;
 959                 dma_bits = 32;
 960                 pr_warn("amdgpu: No suitable DMA available\n");
 961         }
 962         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 963         if (r) {
 964                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 965                 pr_warn("amdgpu: No coherent DMA available\n");
 966         }
 967
 968         r = gmc_v7_0_init_microcode(adev);
 969         if (r) {
 970                 DRM_ERROR("Failed to load mc firmware!\n");
 971                 return r;
 972         }
 973
 974         r = gmc_v7_0_mc_init(adev);
 975         if (r)
 976                 return r;
 977
 978         /* Memory manager */
 979         r = amdgpu_bo_init(adev);
 980         if (r)
 981                 return r;
 982
 983         r = gmc_v7_0_gart_init(adev);
 984         if (r)
 985                 return r;
 986
 987         /*
 988          * number of VMs
 989          * VMID 0 is reserved for System
 990          * amdgpu graphics/compute will use VMIDs 1-7
 991          * amdkfd will use VMIDs 8-15
 992          */
 993         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 994         adev->vm_manager.num_level = 1;
 995         amdgpu_vm_manager_init(adev);
 996
 997         /* base offset of vram pages */
 998         if (adev->flags & AMD_IS_APU) {
 999                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1000
1001                 tmp <<= 22;
1002                 adev->vm_manager.vram_base_offset = tmp;
1003         } else {
1004                 adev->vm_manager.vram_base_offset = 0;
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int gmc_v7_0_sw_fini(void *handle)
1011 {
1012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013
1014         amdgpu_vm_manager_fini(adev);
1015         gmc_v7_0_gart_fini(adev);
1016         amdgpu_gem_force_release(adev);
1017         amdgpu_bo_fini(adev);
1018
1019         return 0;
1020 }
1021
1022 static int gmc_v7_0_hw_init(void *handle)
1023 {
1024         int r;
1025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
1027         gmc_v7_0_init_golden_registers(adev);
1028
1029         gmc_v7_0_mc_program(adev);
1030
1031         if (!(adev->flags & AMD_IS_APU)) {
1032                 r = gmc_v7_0_mc_load_microcode(adev);
1033                 if (r) {
1034                         DRM_ERROR("Failed to load MC firmware!\n");
1035                         return r;
1036                 }
1037         }
1038
1039         r = gmc_v7_0_gart_enable(adev);
1040         if (r)
1041                 return r;
1042
1043         return r;
1044 }
1045
1046 static int gmc_v7_0_hw_fini(void *handle)
1047 {
1048         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049
1050         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1051         gmc_v7_0_gart_disable(adev);
1052
1053         return 0;
1054 }
1055
1056 static int gmc_v7_0_suspend(void *handle)
1057 {
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060         gmc_v7_0_hw_fini(adev);
1061
1062         return 0;
1063 }
1064
1065 static int gmc_v7_0_resume(void *handle)
1066 {
1067         int r;
1068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
1070         r = gmc_v7_0_hw_init(adev);
1071         if (r)
1072                 return r;
1073
1074         amdgpu_vm_reset_all_ids(adev);
1075
1076         return 0;
1077 }
1078
1079 static bool gmc_v7_0_is_idle(void *handle)
1080 {
1081         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082         u32 tmp = RREG32(mmSRBM_STATUS);
1083
1084         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1085                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1086                 return false;
1087
1088         return true;
1089 }
1090
1091 static int gmc_v7_0_wait_for_idle(void *handle)
1092 {
1093         unsigned i;
1094         u32 tmp;
1095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097         for (i = 0; i < adev->usec_timeout; i++) {
1098                 /* read MC_STATUS */
1099                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1100                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1101                                                SRBM_STATUS__MCC_BUSY_MASK |
1102                                                SRBM_STATUS__MCD_BUSY_MASK |
1103                                                SRBM_STATUS__VMC_BUSY_MASK);
1104                 if (!tmp)
1105                         return 0;
1106                 udelay(1);
1107         }
1108         return -ETIMEDOUT;
1109
1110 }
1111
1112 static int gmc_v7_0_soft_reset(void *handle)
1113 {
1114         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1115         u32 srbm_soft_reset = 0;
1116         u32 tmp = RREG32(mmSRBM_STATUS);
1117
1118         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1119                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1120                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1121
1122         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1123                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1124                 if (!(adev->flags & AMD_IS_APU))
1125                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1126                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1127         }
1128
1129         if (srbm_soft_reset) {
1130                 gmc_v7_0_mc_stop(adev);
1131                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1132                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1133                 }
1134
1135
1136                 tmp = RREG32(mmSRBM_SOFT_RESET);
1137                 tmp |= srbm_soft_reset;
1138                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1139                 WREG32(mmSRBM_SOFT_RESET, tmp);
1140                 tmp = RREG32(mmSRBM_SOFT_RESET);
1141
1142                 udelay(50);
1143
1144                 tmp &= ~srbm_soft_reset;
1145                 WREG32(mmSRBM_SOFT_RESET, tmp);
1146                 tmp = RREG32(mmSRBM_SOFT_RESET);
1147
1148                 /* Wait a little for things to settle down */
1149                 udelay(50);
1150
1151                 gmc_v7_0_mc_resume(adev);
1152                 udelay(50);
1153         }
1154
1155         return 0;
1156 }
1157
1158 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1159                                              struct amdgpu_irq_src *src,
1160                                              unsigned type,
1161                                              enum amdgpu_interrupt_state state)
1162 {
1163         u32 tmp;
1164         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1165                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1166                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1167                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1168                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1169                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1170
1171         switch (state) {
1172         case AMDGPU_IRQ_STATE_DISABLE:
1173                 /* system context */
1174                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1175                 tmp &= ~bits;
1176                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1177                 /* VMs */
1178                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1179                 tmp &= ~bits;
1180                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1181                 break;
1182         case AMDGPU_IRQ_STATE_ENABLE:
1183                 /* system context */
1184                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1185                 tmp |= bits;
1186                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1187                 /* VMs */
1188                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1189                 tmp |= bits;
1190                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1191                 break;
1192         default:
1193                 break;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1200                                       struct amdgpu_irq_src *source,
1201                                       struct amdgpu_iv_entry *entry)
1202 {
1203         u32 addr, status, mc_client;
1204
1205         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1206         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1207         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1208         /* reset addr and status */
1209         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1210
1211         if (!addr && !status)
1212                 return 0;
1213
1214         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1215                 gmc_v7_0_set_fault_enable_default(adev, false);
1216
1217         if (printk_ratelimit()) {
1218                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1219                         entry->src_id, entry->src_data[0]);
1220                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1221                         addr);
1222                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1223                         status);
1224                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int gmc_v7_0_set_clockgating_state(void *handle,
1231                                           enum amd_clockgating_state state)
1232 {
1233         bool gate = false;
1234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235
1236         if (state == AMD_CG_STATE_GATE)
1237                 gate = true;
1238
1239         if (!(adev->flags & AMD_IS_APU)) {
1240                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1241                 gmc_v7_0_enable_mc_ls(adev, gate);
1242         }
1243         gmc_v7_0_enable_bif_mgls(adev, gate);
1244         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1245         gmc_v7_0_enable_hdp_ls(adev, gate);
1246
1247         return 0;
1248 }
1249
1250 static int gmc_v7_0_set_powergating_state(void *handle,
1251                                           enum amd_powergating_state state)
1252 {
1253         return 0;
1254 }
1255
1256 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1257         .name = "gmc_v7_0",
1258         .early_init = gmc_v7_0_early_init,
1259         .late_init = gmc_v7_0_late_init,
1260         .sw_init = gmc_v7_0_sw_init,
1261         .sw_fini = gmc_v7_0_sw_fini,
1262         .hw_init = gmc_v7_0_hw_init,
1263         .hw_fini = gmc_v7_0_hw_fini,
1264         .suspend = gmc_v7_0_suspend,
1265         .resume = gmc_v7_0_resume,
1266         .is_idle = gmc_v7_0_is_idle,
1267         .wait_for_idle = gmc_v7_0_wait_for_idle,
1268         .soft_reset = gmc_v7_0_soft_reset,
1269         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1270         .set_powergating_state = gmc_v7_0_set_powergating_state,
1271 };
1272
1273 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1274         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1275         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1276         .set_prt = gmc_v7_0_set_prt,
1277         .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
1278         .get_vm_pde = gmc_v7_0_get_vm_pde
1279 };
1280
1281 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1282         .set = gmc_v7_0_vm_fault_interrupt_state,
1283         .process = gmc_v7_0_process_interrupt,
1284 };
1285
1286 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1287 {
1288         if (adev->gart.gart_funcs == NULL)
1289                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1290 }
1291
1292 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1293 {
1294         adev->mc.vm_fault.num_types = 1;
1295         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1296 }
1297
1298 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1299 {
1300         .type = AMD_IP_BLOCK_TYPE_GMC,
1301         .major = 7,
1302         .minor = 0,
1303         .rev = 0,
1304         .funcs = &gmc_v7_0_ip_funcs,
1305 };
1306
1307 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1308 {
1309         .type = AMD_IP_BLOCK_TYPE_GMC,
1310         .major = 7,
1311         .minor = 4,
1312         .rev = 0,
1313         .funcs = &gmc_v7_0_ip_funcs,
1314 };