drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "atom.h"
  39 #include "amdgpu_reset.h"
  40
  41 #ifdef CONFIG_X86_MCE_AMD
  42 #include <asm/mce.h>
  43
  44 static bool notifier_registered;
  45 #endif
  46 static const char *RAS_FS_NAME = "ras";
  47
  48 const char *ras_error_string[] = {
  49         "none",
  50         "parity",
  51         "single_correctable",
  52         "multi_uncorrectable",
  53         "poison",
  54 };
  55
  56 const char *ras_block_string[] = {
  57         "umc",
  58         "sdma",
  59         "gfx",
  60         "mmhub",
  61         "athub",
  62         "pcie_bif",
  63         "hdp",
  64         "xgmi_wafl",
  65         "df",
  66         "smn",
  67         "sem",
  68         "mp0",
  69         "mp1",
  70         "fuse",
  71         "mca",
  72         "vcn",
  73         "jpeg",
  74 };
  75
  76 const char *ras_mca_block_string[] = {
  77         "mca_mp0",
  78         "mca_mp1",
  79         "mca_mpio",
  80         "mca_iohc",
  81 };
  82
  83 struct amdgpu_ras_block_list {
  84         /* ras block link */
  85         struct list_head node;
  86
  87         struct amdgpu_ras_block_object *ras_obj;
  88 };
  89
  90 const char *get_ras_block_str(struct ras_common_if *ras_block)
  91 {
  92         if (!ras_block)
  93                 return "NULL";
  94
  95         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  96                 return "OUT OF RANGE";
  97
  98         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
  99                 return ras_mca_block_string[ras_block->sub_block_index];
 100
 101         return ras_block_string[ras_block->block];
 102 }
 103
 104 #define ras_block_str(_BLOCK_) \
 105         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 106
 107 #define ras_err_str(i) (ras_error_string[ffs(i)])
 108
 109 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 110
 111 /* inject address is 52 bits */
 112 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 113
 114 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 115 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 116
 117 enum amdgpu_ras_retire_page_reservation {
 118         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 119         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 120         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 121 };
 122
 123 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 124
 125 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 126                                 uint64_t addr);
 127 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 128                                 uint64_t addr);
 129 #ifdef CONFIG_X86_MCE_AMD
 130 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 131 struct mce_notifier_adev_list {
 132         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 133         int num_gpu;
 134 };
 135 static struct mce_notifier_adev_list mce_adev_list;
 136 #endif
 137
 138 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 139 {
 140         if (adev && amdgpu_ras_get_context(adev))
 141                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 142 }
 143
 144 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 145 {
 146         if (adev && amdgpu_ras_get_context(adev))
 147                 return amdgpu_ras_get_context(adev)->error_query_ready;
 148
 149         return false;
 150 }
 151
 152 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 153 {
 154         struct ras_err_data err_data = {0, 0, 0, NULL};
 155         struct eeprom_table_record err_rec;
 156
 157         if ((address >= adev->gmc.mc_vram_size) ||
 158             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 159                 dev_warn(adev->dev,
 160                          "RAS WARN: input address 0x%llx is invalid.\n",
 161                          address);
 162                 return -EINVAL;
 163         }
 164
 165         if (amdgpu_ras_check_bad_page(adev, address)) {
 166                 dev_warn(adev->dev,
 167                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 168                          address);
 169                 return 0;
 170         }
 171
 172         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 173         err_data.err_addr = &err_rec;
 174         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 175
 176         if (amdgpu_bad_page_threshold != 0) {
 177                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 178                                          err_data.err_addr_cnt);
 179                 amdgpu_ras_save_bad_pages(adev, NULL);
 180         }
 181
 182         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 183         dev_warn(adev->dev, "Clear EEPROM:\n");
 184         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 185
 186         return 0;
 187 }
 188
 189 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 190                                         size_t size, loff_t *pos)
 191 {
 192         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 193         struct ras_query_if info = {
 194                 .head = obj->head,
 195         };
 196         ssize_t s;
 197         char val[128];
 198
 199         if (amdgpu_ras_query_error_status(obj->adev, &info))
 200                 return -EINVAL;
 201
 202         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 203         if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
 204             obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
 205                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 206                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 207         }
 208
 209         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 210                         "ue", info.ue_count,
 211                         "ce", info.ce_count);
 212         if (*pos >= s)
 213                 return 0;
 214
 215         s -= *pos;
 216         s = min_t(u64, s, size);
 217
 218
 219         if (copy_to_user(buf, &val[*pos], s))
 220                 return -EINVAL;
 221
 222         *pos += s;
 223
 224         return s;
 225 }
 226
 227 static const struct file_operations amdgpu_ras_debugfs_ops = {
 228         .owner = THIS_MODULE,
 229         .read = amdgpu_ras_debugfs_read,
 230         .write = NULL,
 231         .llseek = default_llseek
 232 };
 233
 234 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 235 {
 236         int i;
 237
 238         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 239                 *block_id = i;
 240                 if (strcmp(name, ras_block_string[i]) == 0)
 241                         return 0;
 242         }
 243         return -EINVAL;
 244 }
 245
 246 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 247                 const char __user *buf, size_t size,
 248                 loff_t *pos, struct ras_debug_if *data)
 249 {
 250         ssize_t s = min_t(u64, 64, size);
 251         char str[65];
 252         char block_name[33];
 253         char err[9] = "ue";
 254         int op = -1;
 255         int block_id;
 256         uint32_t sub_block;
 257         u64 address, value;
 258         /* default value is 0 if the mask is not set by user */
 259         u32 instance_mask = 0;
 260
 261         if (*pos)
 262                 return -EINVAL;
 263         *pos = size;
 264
 265         memset(str, 0, sizeof(str));
 266         memset(data, 0, sizeof(*data));
 267
 268         if (copy_from_user(str, buf, s))
 269                 return -EINVAL;
 270
 271         if (sscanf(str, "disable %32s", block_name) == 1)
 272                 op = 0;
 273         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 274                 op = 1;
 275         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 276                 op = 2;
 277         else if (strstr(str, "retire_page") != NULL)
 278                 op = 3;
 279         else if (str[0] && str[1] && str[2] && str[3])
 280                 /* ascii string, but commands are not matched. */
 281                 return -EINVAL;
 282
 283         if (op != -1) {
 284                 if (op == 3) {
 285                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 286                             sscanf(str, "%*s %llu", &address) != 1)
 287                                 return -EINVAL;
 288
 289                         data->op = op;
 290                         data->inject.address = address;
 291
 292                         return 0;
 293                 }
 294
 295                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 296                         return -EINVAL;
 297
 298                 data->head.block = block_id;
 299                 /* only ue and ce errors are supported */
 300                 if (!memcmp("ue", err, 2))
 301                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 302                 else if (!memcmp("ce", err, 2))
 303                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 304                 else
 305                         return -EINVAL;
 306
 307                 data->op = op;
 308
 309                 if (op == 2) {
 310                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 311                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 312                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 313                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 314                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 315                                    &sub_block, &address, &value) != 3 &&
 316                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 317                                    &sub_block, &address, &value) != 3)
 318                                 return -EINVAL;
 319                         data->head.sub_block_index = sub_block;
 320                         data->inject.address = address;
 321                         data->inject.value = value;
 322                         data->inject.instance_mask = instance_mask;
 323                 }
 324         } else {
 325                 if (size < sizeof(*data))
 326                         return -EINVAL;
 327
 328                 if (copy_from_user(data, buf, sizeof(*data)))
 329                         return -EINVAL;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 336                                 struct ras_debug_if *data)
 337 {
 338         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 339         uint32_t mask, inst_mask = data->inject.instance_mask;
 340
 341         /* no need to set instance mask if there is only one instance */
 342         if (num_xcc <= 1 && inst_mask) {
 343                 data->inject.instance_mask = 0;
 344                 dev_dbg(adev->dev,
 345                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 346                         inst_mask);
 347
 348                 return;
 349         }
 350
 351         switch (data->head.block) {
 352         case AMDGPU_RAS_BLOCK__GFX:
 353                 mask = GENMASK(num_xcc - 1, 0);
 354                 break;
 355         case AMDGPU_RAS_BLOCK__SDMA:
 356                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 357                 break;
 358         case AMDGPU_RAS_BLOCK__VCN:
 359         case AMDGPU_RAS_BLOCK__JPEG:
 360                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 361                 break;
 362         default:
 363                 mask = inst_mask;
 364                 break;
 365         }
 366
 367         /* remove invalid bits in instance mask */
 368         data->inject.instance_mask &= mask;
 369         if (inst_mask != data->inject.instance_mask)
 370                 dev_dbg(adev->dev,
 371                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 372                         inst_mask, data->inject.instance_mask);
 373 }
 374
 375 /**
 376  * DOC: AMDGPU RAS debugfs control interface
 377  *
 378  * The control interface accepts struct ras_debug_if which has two members.
 379  *
 380  * First member: ras_debug_if::head or ras_debug_if::inject.
 381  *
 382  * head is used to indicate which IP block will be under control.
 383  *
 384  * head has four members, they are block, type, sub_block_index, name.
 385  * block: which IP will be under control.
 386  * type: what kind of error will be enabled/disabled/injected.
 387  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 388  * name: the name of IP.
 389  *
 390  * inject has three more members than head, they are address, value and mask.
 391  * As their names indicate, inject operation will write the
 392  * value to the address.
 393  *
 394  * The second member: struct ras_debug_if::op.
 395  * It has three kinds of operations.
 396  *
 397  * - 0: disable RAS on the block. Take ::head as its data.
 398  * - 1: enable RAS on the block. Take ::head as its data.
 399  * - 2: inject errors on the block. Take ::inject as its data.
 400  *
 401  * How to use the interface?
 402  *
 403  * In a program
 404  *
 405  * Copy the struct ras_debug_if in your code and initialize it.
 406  * Write the struct to the control interface.
 407  *
 408  * From shell
 409  *
 410  * .. code-block:: bash
 411  *
 412  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 413  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 414  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 415  *
 416  * Where N, is the card which you want to affect.
 417  *
 418  * "disable" requires only the block.
 419  * "enable" requires the block and error type.
 420  * "inject" requires the block, error type, address, and value.
 421  *
 422  * The block is one of: umc, sdma, gfx, etc.
 423  *      see ras_block_string[] for details
 424  *
 425  * The error type is one of: ue, ce, where,
 426  *      ue is multi-uncorrectable
 427  *      ce is single-correctable
 428  *
 429  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 430  * The address and value are hexadecimal numbers, leading 0x is optional.
 431  * The mask means instance mask, is optional, default value is 0x1.
 432  *
 433  * For instance,
 434  *
 435  * .. code-block:: bash
 436  *
 437  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 438  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 439  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 440  *
 441  * How to check the result of the operation?
 442  *
 443  * To check disable/enable, see "ras" features at,
 444  * /sys/class/drm/card[0/1/2...]/device/ras/features
 445  *
 446  * To check inject, see the corresponding error count at,
 447  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 448  *
 449  * .. note::
 450  *      Operations are only allowed on blocks which are supported.
 451  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 452  *      to see which blocks support RAS on a particular asic.
 453  *
 454  */
 455 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 456                                              const char __user *buf,
 457                                              size_t size, loff_t *pos)
 458 {
 459         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 460         struct ras_debug_if data;
 461         int ret = 0;
 462
 463         if (!amdgpu_ras_get_error_query_ready(adev)) {
 464                 dev_warn(adev->dev, "RAS WARN: error injection "
 465                                 "currently inaccessible\n");
 466                 return size;
 467         }
 468
 469         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 470         if (ret)
 471                 return ret;
 472
 473         if (data.op == 3) {
 474                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 475                 if (!ret)
 476                         return size;
 477                 else
 478                         return ret;
 479         }
 480
 481         if (!amdgpu_ras_is_supported(adev, data.head.block))
 482                 return -EINVAL;
 483
 484         switch (data.op) {
 485         case 0:
 486                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 487                 break;
 488         case 1:
 489                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 490                 break;
 491         case 2:
 492                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 493                     adev->gmc.mc_vram_size) ||
 494                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 495                         dev_warn(adev->dev, "RAS WARN: input address "
 496                                         "0x%llx is invalid.",
 497                                         data.inject.address);
 498                         ret = -EINVAL;
 499                         break;
 500                 }
 501
 502                 /* umc ce/ue error injection for a bad page is not allowed */
 503                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 504                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 505                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 506                                  "already been marked as bad!\n",
 507                                  data.inject.address);
 508                         break;
 509                 }
 510
 511                 amdgpu_ras_instance_mask_check(adev, &data);
 512
 513                 /* data.inject.address is offset instead of absolute gpu address */
 514                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 515                 break;
 516         default:
 517                 ret = -EINVAL;
 518                 break;
 519         }
 520
 521         if (ret)
 522                 return ret;
 523
 524         return size;
 525 }
 526
 527 /**
 528  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 529  *
 530  * Some boards contain an EEPROM which is used to persistently store a list of
 531  * bad pages which experiences ECC errors in vram.  This interface provides
 532  * a way to reset the EEPROM, e.g., after testing error injection.
 533  *
 534  * Usage:
 535  *
 536  * .. code-block:: bash
 537  *
 538  *      echo 1 > ../ras/ras_eeprom_reset
 539  *
 540  * will reset EEPROM table to 0 entries.
 541  *
 542  */
 543 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 544                                                const char __user *buf,
 545                                                size_t size, loff_t *pos)
 546 {
 547         struct amdgpu_device *adev =
 548                 (struct amdgpu_device *)file_inode(f)->i_private;
 549         int ret;
 550
 551         ret = amdgpu_ras_eeprom_reset_table(
 552                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 553
 554         if (!ret) {
 555                 /* Something was written to EEPROM.
 556                  */
 557                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 558                 return size;
 559         } else {
 560                 return ret;
 561         }
 562 }
 563
 564 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 565         .owner = THIS_MODULE,
 566         .read = NULL,
 567         .write = amdgpu_ras_debugfs_ctrl_write,
 568         .llseek = default_llseek
 569 };
 570
 571 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 572         .owner = THIS_MODULE,
 573         .read = NULL,
 574         .write = amdgpu_ras_debugfs_eeprom_write,
 575         .llseek = default_llseek
 576 };
 577
 578 /**
 579  * DOC: AMDGPU RAS sysfs Error Count Interface
 580  *
 581  * It allows the user to read the error count for each IP block on the gpu through
 582  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 583  *
 584  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 585  * (ce) error counts.
 586  *
 587  * The format of one line is below,
 588  *
 589  * [ce|ue]: count
 590  *
 591  * Example:
 592  *
 593  * .. code-block:: bash
 594  *
 595  *      ue: 0
 596  *      ce: 1
 597  *
 598  */
 599 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 600                 struct device_attribute *attr, char *buf)
 601 {
 602         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 603         struct ras_query_if info = {
 604                 .head = obj->head,
 605         };
 606
 607         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 608                 return sysfs_emit(buf, "Query currently inaccessible\n");
 609
 610         if (amdgpu_ras_query_error_status(obj->adev, &info))
 611                 return -EINVAL;
 612
 613         if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
 614             obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
 615                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 616                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 617         }
 618
 619         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 620                           "ce", info.ce_count);
 621 }
 622
 623 /* obj begin */
 624
 625 #define get_obj(obj) do { (obj)->use++; } while (0)
 626 #define alive_obj(obj) ((obj)->use)
 627
 628 static inline void put_obj(struct ras_manager *obj)
 629 {
 630         if (obj && (--obj->use == 0))
 631                 list_del(&obj->node);
 632         if (obj && (obj->use < 0))
 633                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 634 }
 635
 636 /* make one obj and return it. */
 637 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 638                 struct ras_common_if *head)
 639 {
 640         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 641         struct ras_manager *obj;
 642
 643         if (!adev->ras_enabled || !con)
 644                 return NULL;
 645
 646         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 647                 return NULL;
 648
 649         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 650                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 651                         return NULL;
 652
 653                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 654         } else
 655                 obj = &con->objs[head->block];
 656
 657         /* already exist. return obj? */
 658         if (alive_obj(obj))
 659                 return NULL;
 660
 661         obj->head = *head;
 662         obj->adev = adev;
 663         list_add(&obj->node, &con->head);
 664         get_obj(obj);
 665
 666         return obj;
 667 }
 668
 669 /* return an obj equal to head, or the first when head is NULL */
 670 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 671                 struct ras_common_if *head)
 672 {
 673         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 674         struct ras_manager *obj;
 675         int i;
 676
 677         if (!adev->ras_enabled || !con)
 678                 return NULL;
 679
 680         if (head) {
 681                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 682                         return NULL;
 683
 684                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 685                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 686                                 return NULL;
 687
 688                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 689                 } else
 690                         obj = &con->objs[head->block];
 691
 692                 if (alive_obj(obj))
 693                         return obj;
 694         } else {
 695                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 696                         obj = &con->objs[i];
 697                         if (alive_obj(obj))
 698                                 return obj;
 699                 }
 700         }
 701
 702         return NULL;
 703 }
 704 /* obj end */
 705
 706 /* feature ctl begin */
 707 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 708                                          struct ras_common_if *head)
 709 {
 710         return adev->ras_hw_enabled & BIT(head->block);
 711 }
 712
 713 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 714                 struct ras_common_if *head)
 715 {
 716         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 717
 718         return con->features & BIT(head->block);
 719 }
 720
 721 /*
 722  * if obj is not created, then create one.
 723  * set feature enable flag.
 724  */
 725 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 726                 struct ras_common_if *head, int enable)
 727 {
 728         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 729         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 730
 731         /* If hardware does not support ras, then do not create obj.
 732          * But if hardware support ras, we can create the obj.
 733          * Ras framework checks con->hw_supported to see if it need do
 734          * corresponding initialization.
 735          * IP checks con->support to see if it need disable ras.
 736          */
 737         if (!amdgpu_ras_is_feature_allowed(adev, head))
 738                 return 0;
 739
 740         if (enable) {
 741                 if (!obj) {
 742                         obj = amdgpu_ras_create_obj(adev, head);
 743                         if (!obj)
 744                                 return -EINVAL;
 745                 } else {
 746                         /* In case we create obj somewhere else */
 747                         get_obj(obj);
 748                 }
 749                 con->features |= BIT(head->block);
 750         } else {
 751                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 752                         con->features &= ~BIT(head->block);
 753                         put_obj(obj);
 754                 }
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int amdgpu_ras_check_feature_allowed(struct amdgpu_device *adev,
 761                 struct ras_common_if *head)
 762 {
 763         if (amdgpu_ras_is_feature_allowed(adev, head) ||
 764                 amdgpu_ras_is_poison_mode_supported(adev))
 765                 return 1;
 766         else
 767                 return 0;
 768 }
 769
 770 /* wrapper of psp_ras_enable_features */
 771 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 772                 struct ras_common_if *head, bool enable)
 773 {
 774         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 775         union ta_ras_cmd_input *info;
 776         int ret = 0;
 777
 778         if (!con)
 779                 return -EINVAL;
 780
 781         if (head->block == AMDGPU_RAS_BLOCK__GFX) {
 782                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 783                 if (!info)
 784                         return -ENOMEM;
 785
 786                 if (!enable) {
 787                         info->disable_features = (struct ta_ras_disable_features_input) {
 788                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 789                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 790                         };
 791                 } else {
 792                         info->enable_features = (struct ta_ras_enable_features_input) {
 793                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 794                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 795                         };
 796                 }
 797         }
 798
 799         /* Do not enable if it is not allowed. */
 800         if (enable && !amdgpu_ras_check_feature_allowed(adev, head))
 801                 goto out;
 802
 803         /* Only enable ras feature operation handle on host side */
 804         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 805                 !amdgpu_sriov_vf(adev) &&
 806                 !amdgpu_ras_intr_triggered()) {
 807                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 808                 if (ret) {
 809                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 810                                 enable ? "enable":"disable",
 811                                 get_ras_block_str(head),
 812                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 813                         goto out;
 814                 }
 815         }
 816
 817         /* setup the obj */
 818         __amdgpu_ras_feature_enable(adev, head, enable);
 819 out:
 820         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 821                 kfree(info);
 822         return ret;
 823 }
 824
 825 /* Only used in device probe stage and called only once. */
 826 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 827                 struct ras_common_if *head, bool enable)
 828 {
 829         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 830         int ret;
 831
 832         if (!con)
 833                 return -EINVAL;
 834
 835         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 836                 if (enable) {
 837                         /* There is no harm to issue a ras TA cmd regardless of
 838                          * the currecnt ras state.
 839                          * If current state == target state, it will do nothing
 840                          * But sometimes it requests driver to reset and repost
 841                          * with error code -EAGAIN.
 842                          */
 843                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 844                         /* With old ras TA, we might fail to enable ras.
 845                          * Log it and just setup the object.
 846                          * TODO need remove this WA in the future.
 847                          */
 848                         if (ret == -EINVAL) {
 849                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 850                                 if (!ret)
 851                                         dev_info(adev->dev,
 852                                                 "RAS INFO: %s setup object\n",
 853                                                 get_ras_block_str(head));
 854                         }
 855                 } else {
 856                         /* setup the object then issue a ras TA disable cmd.*/
 857                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 858                         if (ret)
 859                                 return ret;
 860
 861                         /* gfx block ras dsiable cmd must send to ras-ta */
 862                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 863                                 con->features |= BIT(head->block);
 864
 865                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 866
 867                         /* clean gfx block ras features flag */
 868                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 869                                 con->features &= ~BIT(head->block);
 870                 }
 871         } else
 872                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 873
 874         return ret;
 875 }
 876
 877 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 878                 bool bypass)
 879 {
 880         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 881         struct ras_manager *obj, *tmp;
 882
 883         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 884                 /* bypass psp.
 885                  * aka just release the obj and corresponding flags
 886                  */
 887                 if (bypass) {
 888                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 889                                 break;
 890                 } else {
 891                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 892                                 break;
 893                 }
 894         }
 895
 896         return con->features;
 897 }
 898
 899 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 900                 bool bypass)
 901 {
 902         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 903         int i;
 904         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 905
 906         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 907                 struct ras_common_if head = {
 908                         .block = i,
 909                         .type = default_ras_type,
 910                         .sub_block_index = 0,
 911                 };
 912
 913                 if (i == AMDGPU_RAS_BLOCK__MCA)
 914                         continue;
 915
 916                 if (bypass) {
 917                         /*
 918                          * bypass psp. vbios enable ras for us.
 919                          * so just create the obj
 920                          */
 921                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 922                                 break;
 923                 } else {
 924                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 925                                 break;
 926                 }
 927         }
 928
 929         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 930                 struct ras_common_if head = {
 931                         .block = AMDGPU_RAS_BLOCK__MCA,
 932                         .type = default_ras_type,
 933                         .sub_block_index = i,
 934                 };
 935
 936                 if (bypass) {
 937                         /*
 938                          * bypass psp. vbios enable ras for us.
 939                          * so just create the obj
 940                          */
 941                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 942                                 break;
 943                 } else {
 944                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 945                                 break;
 946                 }
 947         }
 948
 949         return con->features;
 950 }
 951 /* feature ctl end */
 952
 953 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 954                 enum amdgpu_ras_block block)
 955 {
 956         if (!block_obj)
 957                 return -EINVAL;
 958
 959         if (block_obj->ras_comm.block == block)
 960                 return 0;
 961
 962         return -EINVAL;
 963 }
 964
 965 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 966                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 967 {
 968         struct amdgpu_ras_block_list *node, *tmp;
 969         struct amdgpu_ras_block_object *obj;
 970
 971         if (block >= AMDGPU_RAS_BLOCK__LAST)
 972                 return NULL;
 973
 974         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 975                 if (!node->ras_obj) {
 976                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 977                         continue;
 978                 }
 979
 980                 obj = node->ras_obj;
 981                 if (obj->ras_block_match) {
 982                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 983                                 return obj;
 984                 } else {
 985                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 986                                 return obj;
 987                 }
 988         }
 989
 990         return NULL;
 991 }
 992
 993 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
 994 {
 995         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 996         int ret = 0;
 997
 998         /*
 999          * choosing right query method according to
1000          * whether smu support query error information
1001          */
1002         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1003         if (ret == -EOPNOTSUPP) {
1004                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1005                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1006                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1007
1008                 /* umc query_ras_error_address is also responsible for clearing
1009                  * error status
1010                  */
1011                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1012                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1013                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1014         } else if (!ret) {
1015                 if (adev->umc.ras &&
1016                         adev->umc.ras->ecc_info_query_ras_error_count)
1017                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1018
1019                 if (adev->umc.ras &&
1020                         adev->umc.ras->ecc_info_query_ras_error_address)
1021                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1022         }
1023 }
1024
1025 /* query/inject/cure begin */
1026 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
1027                                   struct ras_query_if *info)
1028 {
1029         struct amdgpu_ras_block_object *block_obj = NULL;
1030         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1031         struct ras_err_data err_data = {0, 0, 0, NULL};
1032
1033         if (!obj)
1034                 return -EINVAL;
1035
1036         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1037                 amdgpu_ras_get_ecc_info(adev, &err_data);
1038         } else {
1039                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1040                 if (!block_obj || !block_obj->hw_ops)   {
1041                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1042                                      get_ras_block_str(&info->head));
1043                         return -EINVAL;
1044                 }
1045
1046                 if (block_obj->hw_ops->query_ras_error_count)
1047                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1048
1049                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1050                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1051                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1052                                 if (block_obj->hw_ops->query_ras_error_status)
1053                                         block_obj->hw_ops->query_ras_error_status(adev);
1054                         }
1055         }
1056
1057         obj->err_data.ue_count += err_data.ue_count;
1058         obj->err_data.ce_count += err_data.ce_count;
1059
1060         info->ue_count = obj->err_data.ue_count;
1061         info->ce_count = obj->err_data.ce_count;
1062
1063         if (err_data.ce_count) {
1064                 if (adev->smuio.funcs &&
1065                     adev->smuio.funcs->get_socket_id &&
1066                     adev->smuio.funcs->get_die_id) {
1067                         dev_info(adev->dev, "socket: %d, die: %d "
1068                                         "%ld correctable hardware errors "
1069                                         "detected in %s block, no user "
1070                                         "action is needed.\n",
1071                                         adev->smuio.funcs->get_socket_id(adev),
1072                                         adev->smuio.funcs->get_die_id(adev),
1073                                         obj->err_data.ce_count,
1074                                         get_ras_block_str(&info->head));
1075                 } else {
1076                         dev_info(adev->dev, "%ld correctable hardware errors "
1077                                         "detected in %s block, no user "
1078                                         "action is needed.\n",
1079                                         obj->err_data.ce_count,
1080                                         get_ras_block_str(&info->head));
1081                 }
1082         }
1083         if (err_data.ue_count) {
1084                 if (adev->smuio.funcs &&
1085                     adev->smuio.funcs->get_socket_id &&
1086                     adev->smuio.funcs->get_die_id) {
1087                         dev_info(adev->dev, "socket: %d, die: %d "
1088                                         "%ld uncorrectable hardware errors "
1089                                         "detected in %s block\n",
1090                                         adev->smuio.funcs->get_socket_id(adev),
1091                                         adev->smuio.funcs->get_die_id(adev),
1092                                         obj->err_data.ue_count,
1093                                         get_ras_block_str(&info->head));
1094                 } else {
1095                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1096                                         "detected in %s block\n",
1097                                         obj->err_data.ue_count,
1098                                         get_ras_block_str(&info->head));
1099                 }
1100         }
1101
1102         return 0;
1103 }
1104
1105 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1106                 enum amdgpu_ras_block block)
1107 {
1108         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1109
1110         if (!amdgpu_ras_is_supported(adev, block))
1111                 return -EINVAL;
1112
1113         if (!block_obj || !block_obj->hw_ops)   {
1114                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1115                              ras_block_str(block));
1116                 return -EINVAL;
1117         }
1118
1119         if (block_obj->hw_ops->reset_ras_error_count)
1120                 block_obj->hw_ops->reset_ras_error_count(adev);
1121
1122         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1123             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1124                 if (block_obj->hw_ops->reset_ras_error_status)
1125                         block_obj->hw_ops->reset_ras_error_status(adev);
1126         }
1127
1128         return 0;
1129 }
1130
1131 /* wrapper of psp_ras_trigger_error */
1132 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1133                 struct ras_inject_if *info)
1134 {
1135         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1136         struct ta_ras_trigger_error_input block_info = {
1137                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1138                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1139                 .sub_block_index = info->head.sub_block_index,
1140                 .address = info->address,
1141                 .value = info->value,
1142         };
1143         int ret = -EINVAL;
1144         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1145                                                         info->head.block,
1146                                                         info->head.sub_block_index);
1147
1148         /* inject on guest isn't allowed, return success directly */
1149         if (amdgpu_sriov_vf(adev))
1150                 return 0;
1151
1152         if (!obj)
1153                 return -EINVAL;
1154
1155         if (!block_obj || !block_obj->hw_ops)   {
1156                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1157                              get_ras_block_str(&info->head));
1158                 return -EINVAL;
1159         }
1160
1161         /* Calculate XGMI relative offset */
1162         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1163             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1164                 block_info.address =
1165                         amdgpu_xgmi_get_relative_phy_addr(adev,
1166                                                           block_info.address);
1167         }
1168
1169         if (block_obj->hw_ops->ras_error_inject) {
1170                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1171                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1172                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1173                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1174                                                 info->instance_mask);
1175         } else {
1176                 /* default path */
1177                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1178         }
1179
1180         if (ret)
1181                 dev_err(adev->dev, "ras inject %s failed %d\n",
1182                         get_ras_block_str(&info->head), ret);
1183
1184         return ret;
1185 }
1186
1187 /**
1188  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1189  * @adev: pointer to AMD GPU device
1190  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1191  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1192  * @query_info: pointer to ras_query_if
1193  *
1194  * Return 0 for query success or do nothing, otherwise return an error
1195  * on failures
1196  */
1197 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1198                                                unsigned long *ce_count,
1199                                                unsigned long *ue_count,
1200                                                struct ras_query_if *query_info)
1201 {
1202         int ret;
1203
1204         if (!query_info)
1205                 /* do nothing if query_info is not specified */
1206                 return 0;
1207
1208         ret = amdgpu_ras_query_error_status(adev, query_info);
1209         if (ret)
1210                 return ret;
1211
1212         *ce_count += query_info->ce_count;
1213         *ue_count += query_info->ue_count;
1214
1215         /* some hardware/IP supports read to clear
1216          * no need to explictly reset the err status after the query call */
1217         if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1218             adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1219                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1220                         dev_warn(adev->dev,
1221                                  "Failed to reset error counter and error status\n");
1222         }
1223
1224         return 0;
1225 }
1226
1227 /**
1228  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1229  * @adev: pointer to AMD GPU device
1230  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1231  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1232  * errors.
1233  * @query_info: pointer to ras_query_if if the query request is only for
1234  * specific ip block; if info is NULL, then the qurey request is for
1235  * all the ip blocks that support query ras error counters/status
1236  *
1237  * If set, @ce_count or @ue_count, count and return the corresponding
1238  * error counts in those integer pointers. Return 0 if the device
1239  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1240  */
1241 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1242                                  unsigned long *ce_count,
1243                                  unsigned long *ue_count,
1244                                  struct ras_query_if *query_info)
1245 {
1246         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1247         struct ras_manager *obj;
1248         unsigned long ce, ue;
1249         int ret;
1250
1251         if (!adev->ras_enabled || !con)
1252                 return -EOPNOTSUPP;
1253
1254         /* Don't count since no reporting.
1255          */
1256         if (!ce_count && !ue_count)
1257                 return 0;
1258
1259         ce = 0;
1260         ue = 0;
1261         if (!query_info) {
1262                 /* query all the ip blocks that support ras query interface */
1263                 list_for_each_entry(obj, &con->head, node) {
1264                         struct ras_query_if info = {
1265                                 .head = obj->head,
1266                         };
1267
1268                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1269                 }
1270         } else {
1271                 /* query specific ip block */
1272                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1273         }
1274
1275         if (ret)
1276                 return ret;
1277
1278         if (ce_count)
1279                 *ce_count = ce;
1280
1281         if (ue_count)
1282                 *ue_count = ue;
1283
1284         return 0;
1285 }
1286 /* query/inject/cure end */
1287
1288
1289 /* sysfs begin */
1290
1291 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1292                 struct ras_badpage **bps, unsigned int *count);
1293
1294 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1295 {
1296         switch (flags) {
1297         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1298                 return "R";
1299         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1300                 return "P";
1301         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1302         default:
1303                 return "F";
1304         }
1305 }
1306
1307 /**
1308  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1309  *
1310  * It allows user to read the bad pages of vram on the gpu through
1311  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1312  *
1313  * It outputs multiple lines, and each line stands for one gpu page.
1314  *
1315  * The format of one line is below,
1316  * gpu pfn : gpu page size : flags
1317  *
1318  * gpu pfn and gpu page size are printed in hex format.
1319  * flags can be one of below character,
1320  *
1321  * R: reserved, this gpu page is reserved and not able to use.
1322  *
1323  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1324  * in next window of page_reserve.
1325  *
1326  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1327  *
1328  * Examples:
1329  *
1330  * .. code-block:: bash
1331  *
1332  *      0x00000001 : 0x00001000 : R
1333  *      0x00000002 : 0x00001000 : P
1334  *
1335  */
1336
1337 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1338                 struct kobject *kobj, struct bin_attribute *attr,
1339                 char *buf, loff_t ppos, size_t count)
1340 {
1341         struct amdgpu_ras *con =
1342                 container_of(attr, struct amdgpu_ras, badpages_attr);
1343         struct amdgpu_device *adev = con->adev;
1344         const unsigned int element_size =
1345                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1346         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1347         unsigned int end = div64_ul(ppos + count - 1, element_size);
1348         ssize_t s = 0;
1349         struct ras_badpage *bps = NULL;
1350         unsigned int bps_count = 0;
1351
1352         memset(buf, 0, count);
1353
1354         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1355                 return 0;
1356
1357         for (; start < end && start < bps_count; start++)
1358                 s += scnprintf(&buf[s], element_size + 1,
1359                                 "0x%08x : 0x%08x : %1s\n",
1360                                 bps[start].bp,
1361                                 bps[start].size,
1362                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1363
1364         kfree(bps);
1365
1366         return s;
1367 }
1368
1369 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1370                 struct device_attribute *attr, char *buf)
1371 {
1372         struct amdgpu_ras *con =
1373                 container_of(attr, struct amdgpu_ras, features_attr);
1374
1375         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1376 }
1377
1378 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1379 {
1380         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1381
1382         sysfs_remove_file_from_group(&adev->dev->kobj,
1383                                 &con->badpages_attr.attr,
1384                                 RAS_FS_NAME);
1385 }
1386
1387 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1388 {
1389         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1390         struct attribute *attrs[] = {
1391                 &con->features_attr.attr,
1392                 NULL
1393         };
1394         struct attribute_group group = {
1395                 .name = RAS_FS_NAME,
1396                 .attrs = attrs,
1397         };
1398
1399         sysfs_remove_group(&adev->dev->kobj, &group);
1400
1401         return 0;
1402 }
1403
1404 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1405                 struct ras_common_if *head)
1406 {
1407         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1408
1409         if (!obj || obj->attr_inuse)
1410                 return -EINVAL;
1411
1412         get_obj(obj);
1413
1414         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1415                 "%s_err_count", head->name);
1416
1417         obj->sysfs_attr = (struct device_attribute){
1418                 .attr = {
1419                         .name = obj->fs_data.sysfs_name,
1420                         .mode = S_IRUGO,
1421                 },
1422                         .show = amdgpu_ras_sysfs_read,
1423         };
1424         sysfs_attr_init(&obj->sysfs_attr.attr);
1425
1426         if (sysfs_add_file_to_group(&adev->dev->kobj,
1427                                 &obj->sysfs_attr.attr,
1428                                 RAS_FS_NAME)) {
1429                 put_obj(obj);
1430                 return -EINVAL;
1431         }
1432
1433         obj->attr_inuse = 1;
1434
1435         return 0;
1436 }
1437
1438 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1439                 struct ras_common_if *head)
1440 {
1441         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1442
1443         if (!obj || !obj->attr_inuse)
1444                 return -EINVAL;
1445
1446         sysfs_remove_file_from_group(&adev->dev->kobj,
1447                                 &obj->sysfs_attr.attr,
1448                                 RAS_FS_NAME);
1449         obj->attr_inuse = 0;
1450         put_obj(obj);
1451
1452         return 0;
1453 }
1454
1455 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1456 {
1457         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1458         struct ras_manager *obj, *tmp;
1459
1460         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1461                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1462         }
1463
1464         if (amdgpu_bad_page_threshold != 0)
1465                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1466
1467         amdgpu_ras_sysfs_remove_feature_node(adev);
1468
1469         return 0;
1470 }
1471 /* sysfs end */
1472
1473 /**
1474  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1475  *
1476  * Normally when there is an uncorrectable error, the driver will reset
1477  * the GPU to recover.  However, in the event of an unrecoverable error,
1478  * the driver provides an interface to reboot the system automatically
1479  * in that event.
1480  *
1481  * The following file in debugfs provides that interface:
1482  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1483  *
1484  * Usage:
1485  *
1486  * .. code-block:: bash
1487  *
1488  *      echo true > .../ras/auto_reboot
1489  *
1490  */
1491 /* debugfs begin */
1492 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1493 {
1494         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1495         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1496         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1497         struct dentry     *dir;
1498
1499         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1500         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1501                             &amdgpu_ras_debugfs_ctrl_ops);
1502         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1503                             &amdgpu_ras_debugfs_eeprom_ops);
1504         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1505                            &con->bad_page_cnt_threshold);
1506         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1507         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1508         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1509         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1510                             &amdgpu_ras_debugfs_eeprom_size_ops);
1511         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1512                                                        S_IRUGO, dir, adev,
1513                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1514         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1515
1516         /*
1517          * After one uncorrectable error happens, usually GPU recovery will
1518          * be scheduled. But due to the known problem in GPU recovery failing
1519          * to bring GPU back, below interface provides one direct way to
1520          * user to reboot system automatically in such case within
1521          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1522          * will never be called.
1523          */
1524         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1525
1526         /*
1527          * User could set this not to clean up hardware's error count register
1528          * of RAS IPs during ras recovery.
1529          */
1530         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1531                             &con->disable_ras_err_cnt_harvest);
1532         return dir;
1533 }
1534
1535 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1536                                       struct ras_fs_if *head,
1537                                       struct dentry *dir)
1538 {
1539         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1540
1541         if (!obj || !dir)
1542                 return;
1543
1544         get_obj(obj);
1545
1546         memcpy(obj->fs_data.debugfs_name,
1547                         head->debugfs_name,
1548                         sizeof(obj->fs_data.debugfs_name));
1549
1550         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1551                             obj, &amdgpu_ras_debugfs_ops);
1552 }
1553
1554 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1555 {
1556         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1557         struct dentry *dir;
1558         struct ras_manager *obj;
1559         struct ras_fs_if fs_info;
1560
1561         /*
1562          * it won't be called in resume path, no need to check
1563          * suspend and gpu reset status
1564          */
1565         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1566                 return;
1567
1568         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1569
1570         list_for_each_entry(obj, &con->head, node) {
1571                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1572                         (obj->attr_inuse == 1)) {
1573                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1574                                         get_ras_block_str(&obj->head));
1575                         fs_info.head = obj->head;
1576                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1577                 }
1578         }
1579 }
1580
1581 /* debugfs end */
1582
1583 /* ras fs */
1584 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1585                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1586 static DEVICE_ATTR(features, S_IRUGO,
1587                 amdgpu_ras_sysfs_features_read, NULL);
1588 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1589 {
1590         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1591         struct attribute_group group = {
1592                 .name = RAS_FS_NAME,
1593         };
1594         struct attribute *attrs[] = {
1595                 &con->features_attr.attr,
1596                 NULL
1597         };
1598         struct bin_attribute *bin_attrs[] = {
1599                 NULL,
1600                 NULL,
1601         };
1602         int r;
1603
1604         /* add features entry */
1605         con->features_attr = dev_attr_features;
1606         group.attrs = attrs;
1607         sysfs_attr_init(attrs[0]);
1608
1609         if (amdgpu_bad_page_threshold != 0) {
1610                 /* add bad_page_features entry */
1611                 bin_attr_gpu_vram_bad_pages.private = NULL;
1612                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1613                 bin_attrs[0] = &con->badpages_attr;
1614                 group.bin_attrs = bin_attrs;
1615                 sysfs_bin_attr_init(bin_attrs[0]);
1616         }
1617
1618         r = sysfs_create_group(&adev->dev->kobj, &group);
1619         if (r)
1620                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1621
1622         return 0;
1623 }
1624
1625 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1626 {
1627         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1628         struct ras_manager *con_obj, *ip_obj, *tmp;
1629
1630         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1631                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1632                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1633                         if (ip_obj)
1634                                 put_obj(ip_obj);
1635                 }
1636         }
1637
1638         amdgpu_ras_sysfs_remove_all(adev);
1639         return 0;
1640 }
1641 /* ras fs end */
1642
1643 /* ih begin */
1644
1645 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1646  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1647  * register to check whether the interrupt is triggered or not, and properly
1648  * ack the interrupt if it is there
1649  */
1650 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1651 {
1652         /* Fatal error events are handled on host side */
1653         if (amdgpu_sriov_vf(adev))
1654                 return;
1655
1656         if (adev->nbio.ras &&
1657             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1658                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1659
1660         if (adev->nbio.ras &&
1661             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1662                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1663 }
1664
1665 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1666                                 struct amdgpu_iv_entry *entry)
1667 {
1668         bool poison_stat = false;
1669         struct amdgpu_device *adev = obj->adev;
1670         struct amdgpu_ras_block_object *block_obj =
1671                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1672
1673         if (!block_obj)
1674                 return;
1675
1676         /* both query_poison_status and handle_poison_consumption are optional,
1677          * but at least one of them should be implemented if we need poison
1678          * consumption handler
1679          */
1680         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1681                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1682                 if (!poison_stat) {
1683                         /* Not poison consumption interrupt, no need to handle it */
1684                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1685                                         block_obj->ras_comm.name);
1686
1687                         return;
1688                 }
1689         }
1690
1691         amdgpu_umc_poison_handler(adev, false);
1692
1693         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1694                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1695
1696         /* gpu reset is fallback for failed and default cases */
1697         if (poison_stat) {
1698                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1699                                 block_obj->ras_comm.name);
1700                 amdgpu_ras_reset_gpu(adev);
1701         } else {
1702                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1703         }
1704 }
1705
1706 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1707                                 struct amdgpu_iv_entry *entry)
1708 {
1709         dev_info(obj->adev->dev,
1710                 "Poison is created, no user action is needed.\n");
1711 }
1712
1713 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1714                                 struct amdgpu_iv_entry *entry)
1715 {
1716         struct ras_ih_data *data = &obj->ih_data;
1717         struct ras_err_data err_data = {0, 0, 0, NULL};
1718         int ret;
1719
1720         if (!data->cb)
1721                 return;
1722
1723         /* Let IP handle its data, maybe we need get the output
1724          * from the callback to update the error type/count, etc
1725          */
1726         ret = data->cb(obj->adev, &err_data, entry);
1727         /* ue will trigger an interrupt, and in that case
1728          * we need do a reset to recovery the whole system.
1729          * But leave IP do that recovery, here we just dispatch
1730          * the error.
1731          */
1732         if (ret == AMDGPU_RAS_SUCCESS) {
1733                 /* these counts could be left as 0 if
1734                  * some blocks do not count error number
1735                  */
1736                 obj->err_data.ue_count += err_data.ue_count;
1737                 obj->err_data.ce_count += err_data.ce_count;
1738         }
1739 }
1740
1741 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1742 {
1743         struct ras_ih_data *data = &obj->ih_data;
1744         struct amdgpu_iv_entry entry;
1745
1746         while (data->rptr != data->wptr) {
1747                 rmb();
1748                 memcpy(&entry, &data->ring[data->rptr],
1749                                 data->element_size);
1750
1751                 wmb();
1752                 data->rptr = (data->aligned_element_size +
1753                                 data->rptr) % data->ring_size;
1754
1755                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1756                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1757                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1758                         else
1759                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1760                 } else {
1761                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1762                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1763                         else
1764                                 dev_warn(obj->adev->dev,
1765                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1766                 }
1767         }
1768 }
1769
1770 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1771 {
1772         struct ras_ih_data *data =
1773                 container_of(work, struct ras_ih_data, ih_work);
1774         struct ras_manager *obj =
1775                 container_of(data, struct ras_manager, ih_data);
1776
1777         amdgpu_ras_interrupt_handler(obj);
1778 }
1779
1780 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1781                 struct ras_dispatch_if *info)
1782 {
1783         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1784         struct ras_ih_data *data = &obj->ih_data;
1785
1786         if (!obj)
1787                 return -EINVAL;
1788
1789         if (data->inuse == 0)
1790                 return 0;
1791
1792         /* Might be overflow... */
1793         memcpy(&data->ring[data->wptr], info->entry,
1794                         data->element_size);
1795
1796         wmb();
1797         data->wptr = (data->aligned_element_size +
1798                         data->wptr) % data->ring_size;
1799
1800         schedule_work(&data->ih_work);
1801
1802         return 0;
1803 }
1804
1805 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1806                 struct ras_common_if *head)
1807 {
1808         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1809         struct ras_ih_data *data;
1810
1811         if (!obj)
1812                 return -EINVAL;
1813
1814         data = &obj->ih_data;
1815         if (data->inuse == 0)
1816                 return 0;
1817
1818         cancel_work_sync(&data->ih_work);
1819
1820         kfree(data->ring);
1821         memset(data, 0, sizeof(*data));
1822         put_obj(obj);
1823
1824         return 0;
1825 }
1826
1827 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1828                 struct ras_common_if *head)
1829 {
1830         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1831         struct ras_ih_data *data;
1832         struct amdgpu_ras_block_object *ras_obj;
1833
1834         if (!obj) {
1835                 /* in case we registe the IH before enable ras feature */
1836                 obj = amdgpu_ras_create_obj(adev, head);
1837                 if (!obj)
1838                         return -EINVAL;
1839         } else
1840                 get_obj(obj);
1841
1842         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1843
1844         data = &obj->ih_data;
1845         /* add the callback.etc */
1846         *data = (struct ras_ih_data) {
1847                 .inuse = 0,
1848                 .cb = ras_obj->ras_cb,
1849                 .element_size = sizeof(struct amdgpu_iv_entry),
1850                 .rptr = 0,
1851                 .wptr = 0,
1852         };
1853
1854         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1855
1856         data->aligned_element_size = ALIGN(data->element_size, 8);
1857         /* the ring can store 64 iv entries. */
1858         data->ring_size = 64 * data->aligned_element_size;
1859         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1860         if (!data->ring) {
1861                 put_obj(obj);
1862                 return -ENOMEM;
1863         }
1864
1865         /* IH is ready */
1866         data->inuse = 1;
1867
1868         return 0;
1869 }
1870
1871 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1872 {
1873         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1874         struct ras_manager *obj, *tmp;
1875
1876         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1877                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1878         }
1879
1880         return 0;
1881 }
1882 /* ih end */
1883
1884 /* traversal all IPs except NBIO to query error counter */
1885 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1886 {
1887         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1888         struct ras_manager *obj;
1889
1890         if (!adev->ras_enabled || !con)
1891                 return;
1892
1893         list_for_each_entry(obj, &con->head, node) {
1894                 struct ras_query_if info = {
1895                         .head = obj->head,
1896                 };
1897
1898                 /*
1899                  * PCIE_BIF IP has one different isr by ras controller
1900                  * interrupt, the specific ras counter query will be
1901                  * done in that isr. So skip such block from common
1902                  * sync flood interrupt isr calling.
1903                  */
1904                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1905                         continue;
1906
1907                 /*
1908                  * this is a workaround for aldebaran, skip send msg to
1909                  * smu to get ecc_info table due to smu handle get ecc
1910                  * info table failed temporarily.
1911                  * should be removed until smu fix handle ecc_info table.
1912                  */
1913                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1914                         (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1915                         continue;
1916
1917                 amdgpu_ras_query_error_status(adev, &info);
1918
1919                 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1920                     adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1921                     adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
1922                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
1923                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
1924                 }
1925         }
1926 }
1927
1928 /* Parse RdRspStatus and WrRspStatus */
1929 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1930                                           struct ras_query_if *info)
1931 {
1932         struct amdgpu_ras_block_object *block_obj;
1933         /*
1934          * Only two block need to query read/write
1935          * RspStatus at current state
1936          */
1937         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1938                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1939                 return;
1940
1941         block_obj = amdgpu_ras_get_ras_block(adev,
1942                                         info->head.block,
1943                                         info->head.sub_block_index);
1944
1945         if (!block_obj || !block_obj->hw_ops) {
1946                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1947                              get_ras_block_str(&info->head));
1948                 return;
1949         }
1950
1951         if (block_obj->hw_ops->query_ras_error_status)
1952                 block_obj->hw_ops->query_ras_error_status(adev);
1953
1954 }
1955
1956 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1957 {
1958         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1959         struct ras_manager *obj;
1960
1961         if (!adev->ras_enabled || !con)
1962                 return;
1963
1964         list_for_each_entry(obj, &con->head, node) {
1965                 struct ras_query_if info = {
1966                         .head = obj->head,
1967                 };
1968
1969                 amdgpu_ras_error_status_query(adev, &info);
1970         }
1971 }
1972
1973 /* recovery begin */
1974
1975 /* return 0 on success.
1976  * caller need free bps.
1977  */
1978 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1979                 struct ras_badpage **bps, unsigned int *count)
1980 {
1981         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1982         struct ras_err_handler_data *data;
1983         int i = 0;
1984         int ret = 0, status;
1985
1986         if (!con || !con->eh_data || !bps || !count)
1987                 return -EINVAL;
1988
1989         mutex_lock(&con->recovery_lock);
1990         data = con->eh_data;
1991         if (!data || data->count == 0) {
1992                 *bps = NULL;
1993                 ret = -EINVAL;
1994                 goto out;
1995         }
1996
1997         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1998         if (!*bps) {
1999                 ret = -ENOMEM;
2000                 goto out;
2001         }
2002
2003         for (; i < data->count; i++) {
2004                 (*bps)[i] = (struct ras_badpage){
2005                         .bp = data->bps[i].retired_page,
2006                         .size = AMDGPU_GPU_PAGE_SIZE,
2007                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2008                 };
2009                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2010                                 data->bps[i].retired_page);
2011                 if (status == -EBUSY)
2012                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2013                 else if (status == -ENOENT)
2014                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2015         }
2016
2017         *count = data->count;
2018 out:
2019         mutex_unlock(&con->recovery_lock);
2020         return ret;
2021 }
2022
2023 static void amdgpu_ras_do_recovery(struct work_struct *work)
2024 {
2025         struct amdgpu_ras *ras =
2026                 container_of(work, struct amdgpu_ras, recovery_work);
2027         struct amdgpu_device *remote_adev = NULL;
2028         struct amdgpu_device *adev = ras->adev;
2029         struct list_head device_list, *device_list_handle =  NULL;
2030
2031         if (!ras->disable_ras_err_cnt_harvest) {
2032                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2033
2034                 /* Build list of devices to query RAS related errors */
2035                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2036                         device_list_handle = &hive->device_list;
2037                 } else {
2038                         INIT_LIST_HEAD(&device_list);
2039                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2040                         device_list_handle = &device_list;
2041                 }
2042
2043                 list_for_each_entry(remote_adev,
2044                                 device_list_handle, gmc.xgmi.head) {
2045                         amdgpu_ras_query_err_status(remote_adev);
2046                         amdgpu_ras_log_on_err_counter(remote_adev);
2047                 }
2048
2049                 amdgpu_put_xgmi_hive(hive);
2050         }
2051
2052         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2053                 struct amdgpu_reset_context reset_context;
2054                 memset(&reset_context, 0, sizeof(reset_context));
2055
2056                 reset_context.method = AMD_RESET_METHOD_NONE;
2057                 reset_context.reset_req_dev = adev;
2058
2059                 /* Perform full reset in fatal error mode */
2060                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2061                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2062                 else {
2063                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2064
2065                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2066                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2067                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2068                         }
2069
2070                         /* Fatal error occurs in poison mode, mode1 reset is used to
2071                          * recover gpu.
2072                          */
2073                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2074                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2075                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2076                         }
2077                 }
2078
2079                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2080         }
2081         atomic_set(&ras->in_recovery, 0);
2082 }
2083
2084 /* alloc/realloc bps array */
2085 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2086                 struct ras_err_handler_data *data, int pages)
2087 {
2088         unsigned int old_space = data->count + data->space_left;
2089         unsigned int new_space = old_space + pages;
2090         unsigned int align_space = ALIGN(new_space, 512);
2091         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2092
2093         if (!bps) {
2094                 return -ENOMEM;
2095         }
2096
2097         if (data->bps) {
2098                 memcpy(bps, data->bps,
2099                                 data->count * sizeof(*data->bps));
2100                 kfree(data->bps);
2101         }
2102
2103         data->bps = bps;
2104         data->space_left += align_space - old_space;
2105         return 0;
2106 }
2107
2108 /* it deal with vram only. */
2109 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2110                 struct eeprom_table_record *bps, int pages)
2111 {
2112         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2113         struct ras_err_handler_data *data;
2114         int ret = 0;
2115         uint32_t i;
2116
2117         if (!con || !con->eh_data || !bps || pages <= 0)
2118                 return 0;
2119
2120         mutex_lock(&con->recovery_lock);
2121         data = con->eh_data;
2122         if (!data)
2123                 goto out;
2124
2125         for (i = 0; i < pages; i++) {
2126                 if (amdgpu_ras_check_bad_page_unlock(con,
2127                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2128                         continue;
2129
2130                 if (!data->space_left &&
2131                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2132                         ret = -ENOMEM;
2133                         goto out;
2134                 }
2135
2136                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2137                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2138                         AMDGPU_GPU_PAGE_SIZE);
2139
2140                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2141                 data->count++;
2142                 data->space_left--;
2143         }
2144 out:
2145         mutex_unlock(&con->recovery_lock);
2146
2147         return ret;
2148 }
2149
2150 /*
2151  * write error record array to eeprom, the function should be
2152  * protected by recovery_lock
2153  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2154  */
2155 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2156                 unsigned long *new_cnt)
2157 {
2158         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2159         struct ras_err_handler_data *data;
2160         struct amdgpu_ras_eeprom_control *control;
2161         int save_count;
2162
2163         if (!con || !con->eh_data) {
2164                 if (new_cnt)
2165                         *new_cnt = 0;
2166
2167                 return 0;
2168         }
2169
2170         mutex_lock(&con->recovery_lock);
2171         control = &con->eeprom_control;
2172         data = con->eh_data;
2173         save_count = data->count - control->ras_num_recs;
2174         mutex_unlock(&con->recovery_lock);
2175
2176         if (new_cnt)
2177                 *new_cnt = save_count / adev->umc.retire_unit;
2178
2179         /* only new entries are saved */
2180         if (save_count > 0) {
2181                 if (amdgpu_ras_eeprom_append(control,
2182                                              &data->bps[control->ras_num_recs],
2183                                              save_count)) {
2184                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2185                         return -EIO;
2186                 }
2187
2188                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2189         }
2190
2191         return 0;
2192 }
2193
2194 /*
2195  * read error record array in eeprom and reserve enough space for
2196  * storing new bad pages
2197  */
2198 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2199 {
2200         struct amdgpu_ras_eeprom_control *control =
2201                 &adev->psp.ras_context.ras->eeprom_control;
2202         struct eeprom_table_record *bps;
2203         int ret;
2204
2205         /* no bad page record, skip eeprom access */
2206         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2207                 return 0;
2208
2209         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2210         if (!bps)
2211                 return -ENOMEM;
2212
2213         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2214         if (ret)
2215                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2216         else
2217                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2218
2219         kfree(bps);
2220         return ret;
2221 }
2222
2223 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2224                                 uint64_t addr)
2225 {
2226         struct ras_err_handler_data *data = con->eh_data;
2227         int i;
2228
2229         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2230         for (i = 0; i < data->count; i++)
2231                 if (addr == data->bps[i].retired_page)
2232                         return true;
2233
2234         return false;
2235 }
2236
2237 /*
2238  * check if an address belongs to bad page
2239  *
2240  * Note: this check is only for umc block
2241  */
2242 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2243                                 uint64_t addr)
2244 {
2245         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2246         bool ret = false;
2247
2248         if (!con || !con->eh_data)
2249                 return ret;
2250
2251         mutex_lock(&con->recovery_lock);
2252         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2253         mutex_unlock(&con->recovery_lock);
2254         return ret;
2255 }
2256
2257 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2258                                           uint32_t max_count)
2259 {
2260         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2261
2262         /*
2263          * Justification of value bad_page_cnt_threshold in ras structure
2264          *
2265          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2266          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2267          * scenarios accordingly.
2268          *
2269          * Bad page retirement enablement:
2270          *    - If amdgpu_bad_page_threshold = -2,
2271          *      bad_page_cnt_threshold = typical value by formula.
2272          *
2273          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2274          *      max record length in eeprom, use it directly.
2275          *
2276          * Bad page retirement disablement:
2277          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2278          *      functionality is disabled, and bad_page_cnt_threshold will
2279          *      take no effect.
2280          */
2281
2282         if (amdgpu_bad_page_threshold < 0) {
2283                 u64 val = adev->gmc.mc_vram_size;
2284
2285                 do_div(val, RAS_BAD_PAGE_COVER);
2286                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2287                                                   max_count);
2288         } else {
2289                 con->bad_page_cnt_threshold = min_t(int, max_count,
2290                                                     amdgpu_bad_page_threshold);
2291         }
2292 }
2293
2294 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2295 {
2296         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2297         struct ras_err_handler_data **data;
2298         u32  max_eeprom_records_count = 0;
2299         bool exc_err_limit = false;
2300         int ret;
2301
2302         if (!con || amdgpu_sriov_vf(adev))
2303                 return 0;
2304
2305         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2306          * supports RAS and debugfs is enabled, but when
2307          * adev->ras_enabled is unset, i.e. when "ras_enable"
2308          * module parameter is set to 0.
2309          */
2310         con->adev = adev;
2311
2312         if (!adev->ras_enabled)
2313                 return 0;
2314
2315         data = &con->eh_data;
2316         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2317         if (!*data) {
2318                 ret = -ENOMEM;
2319                 goto out;
2320         }
2321
2322         mutex_init(&con->recovery_lock);
2323         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2324         atomic_set(&con->in_recovery, 0);
2325         con->eeprom_control.bad_channel_bitmap = 0;
2326
2327         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2328         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2329
2330         /* Todo: During test the SMU might fail to read the eeprom through I2C
2331          * when the GPU is pending on XGMI reset during probe time
2332          * (Mostly after second bus reset), skip it now
2333          */
2334         if (adev->gmc.xgmi.pending_reset)
2335                 return 0;
2336         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2337         /*
2338          * This calling fails when exc_err_limit is true or
2339          * ret != 0.
2340          */
2341         if (exc_err_limit || ret)
2342                 goto free;
2343
2344         if (con->eeprom_control.ras_num_recs) {
2345                 ret = amdgpu_ras_load_bad_pages(adev);
2346                 if (ret)
2347                         goto free;
2348
2349                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2350
2351                 if (con->update_channel_flag == true) {
2352                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2353                         con->update_channel_flag = false;
2354                 }
2355         }
2356
2357 #ifdef CONFIG_X86_MCE_AMD
2358         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2359             (adev->gmc.xgmi.connected_to_cpu))
2360                 amdgpu_register_bad_pages_mca_notifier(adev);
2361 #endif
2362         return 0;
2363
2364 free:
2365         kfree((*data)->bps);
2366         kfree(*data);
2367         con->eh_data = NULL;
2368 out:
2369         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2370
2371         /*
2372          * Except error threshold exceeding case, other failure cases in this
2373          * function would not fail amdgpu driver init.
2374          */
2375         if (!exc_err_limit)
2376                 ret = 0;
2377         else
2378                 ret = -EINVAL;
2379
2380         return ret;
2381 }
2382
2383 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2384 {
2385         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2386         struct ras_err_handler_data *data = con->eh_data;
2387
2388         /* recovery_init failed to init it, fini is useless */
2389         if (!data)
2390                 return 0;
2391
2392         cancel_work_sync(&con->recovery_work);
2393
2394         mutex_lock(&con->recovery_lock);
2395         con->eh_data = NULL;
2396         kfree(data->bps);
2397         kfree(data);
2398         mutex_unlock(&con->recovery_lock);
2399
2400         return 0;
2401 }
2402 /* recovery end */
2403
2404 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2405 {
2406         if (amdgpu_sriov_vf(adev)) {
2407                 switch (adev->ip_versions[MP0_HWIP][0]) {
2408                 case IP_VERSION(13, 0, 2):
2409                         return true;
2410                 default:
2411                         return false;
2412                 }
2413         }
2414
2415         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2416                 switch (adev->ip_versions[MP0_HWIP][0]) {
2417                 case IP_VERSION(13, 0, 0):
2418                 case IP_VERSION(13, 0, 6):
2419                 case IP_VERSION(13, 0, 10):
2420                         return true;
2421                 default:
2422                         return false;
2423                 }
2424         }
2425
2426         return adev->asic_type == CHIP_VEGA10 ||
2427                 adev->asic_type == CHIP_VEGA20 ||
2428                 adev->asic_type == CHIP_ARCTURUS ||
2429                 adev->asic_type == CHIP_ALDEBARAN ||
2430                 adev->asic_type == CHIP_SIENNA_CICHLID;
2431 }
2432
2433 /*
2434  * this is workaround for vega20 workstation sku,
2435  * force enable gfx ras, ignore vbios gfx ras flag
2436  * due to GC EDC can not write
2437  */
2438 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2439 {
2440         struct atom_context *ctx = adev->mode_info.atom_context;
2441
2442         if (!ctx)
2443                 return;
2444
2445         if (strnstr(ctx->vbios_pn, "D16406",
2446                     sizeof(ctx->vbios_pn)) ||
2447                 strnstr(ctx->vbios_pn, "D36002",
2448                         sizeof(ctx->vbios_pn)))
2449                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2450 }
2451
2452 /*
2453  * check hardware's ras ability which will be saved in hw_supported.
2454  * if hardware does not support ras, we can skip some ras initializtion and
2455  * forbid some ras operations from IP.
2456  * if software itself, say boot parameter, limit the ras ability. We still
2457  * need allow IP do some limited operations, like disable. In such case,
2458  * we have to initialize ras as normal. but need check if operation is
2459  * allowed or not in each function.
2460  */
2461 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2462 {
2463         adev->ras_hw_enabled = adev->ras_enabled = 0;
2464
2465         if (!amdgpu_ras_asic_supported(adev))
2466                 return;
2467
2468         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2469                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2470                         dev_info(adev->dev, "MEM ECC is active.\n");
2471                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2472                                                    1 << AMDGPU_RAS_BLOCK__DF);
2473                 } else {
2474                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2475                 }
2476
2477                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2478                         dev_info(adev->dev, "SRAM ECC is active.\n");
2479                         if (!amdgpu_sriov_vf(adev))
2480                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2481                                                             1 << AMDGPU_RAS_BLOCK__DF);
2482                         else
2483                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2484                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2485                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2486
2487                         /* VCN/JPEG RAS can be supported on both bare metal and
2488                          * SRIOV environment
2489                          */
2490                         if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) ||
2491                             adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2492                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2493                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2494                         else
2495                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2496                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2497
2498                         /*
2499                          * XGMI RAS is not supported if xgmi num physical nodes
2500                          * is zero
2501                          */
2502                         if (!adev->gmc.xgmi.num_physical_nodes)
2503                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2504                 } else {
2505                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2506                 }
2507         } else {
2508                 /* driver only manages a few IP blocks RAS feature
2509                  * when GPU is connected cpu through XGMI */
2510                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2511                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2512                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2513         }
2514
2515         amdgpu_ras_get_quirks(adev);
2516
2517         /* hw_supported needs to be aligned with RAS block mask. */
2518         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2519
2520
2521         /*
2522          * Disable ras feature for aqua vanjaram
2523          * by default on apu platform.
2524          */
2525         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6) &&
2526             adev->gmc.is_app_apu)
2527                 adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 :
2528                         adev->ras_hw_enabled & amdgpu_ras_mask;
2529         else
2530                 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2531                         adev->ras_hw_enabled & amdgpu_ras_mask;
2532 }
2533
2534 static void amdgpu_ras_counte_dw(struct work_struct *work)
2535 {
2536         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2537                                               ras_counte_delay_work.work);
2538         struct amdgpu_device *adev = con->adev;
2539         struct drm_device *dev = adev_to_drm(adev);
2540         unsigned long ce_count, ue_count;
2541         int res;
2542
2543         res = pm_runtime_get_sync(dev->dev);
2544         if (res < 0)
2545                 goto Out;
2546
2547         /* Cache new values.
2548          */
2549         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2550                 atomic_set(&con->ras_ce_count, ce_count);
2551                 atomic_set(&con->ras_ue_count, ue_count);
2552         }
2553
2554         pm_runtime_mark_last_busy(dev->dev);
2555 Out:
2556         pm_runtime_put_autosuspend(dev->dev);
2557 }
2558
2559 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2560 {
2561         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2562         bool df_poison, umc_poison;
2563
2564         /* poison setting is useless on SRIOV guest */
2565         if (amdgpu_sriov_vf(adev) || !con)
2566                 return;
2567
2568         /* Init poison supported flag, the default value is false */
2569         if (adev->gmc.xgmi.connected_to_cpu) {
2570                 /* enabled by default when GPU is connected to CPU */
2571                 con->poison_supported = true;
2572         } else if (adev->df.funcs &&
2573             adev->df.funcs->query_ras_poison_mode &&
2574             adev->umc.ras &&
2575             adev->umc.ras->query_ras_poison_mode) {
2576                 df_poison =
2577                         adev->df.funcs->query_ras_poison_mode(adev);
2578                 umc_poison =
2579                         adev->umc.ras->query_ras_poison_mode(adev);
2580
2581                 /* Only poison is set in both DF and UMC, we can support it */
2582                 if (df_poison && umc_poison)
2583                         con->poison_supported = true;
2584                 else if (df_poison != umc_poison)
2585                         dev_warn(adev->dev,
2586                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2587                                 df_poison, umc_poison);
2588         }
2589 }
2590
2591 int amdgpu_ras_init(struct amdgpu_device *adev)
2592 {
2593         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2594         int r;
2595
2596         if (con)
2597                 return 0;
2598
2599         con = kmalloc(sizeof(struct amdgpu_ras) +
2600                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2601                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2602                         GFP_KERNEL|__GFP_ZERO);
2603         if (!con)
2604                 return -ENOMEM;
2605
2606         con->adev = adev;
2607         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2608         atomic_set(&con->ras_ce_count, 0);
2609         atomic_set(&con->ras_ue_count, 0);
2610
2611         con->objs = (struct ras_manager *)(con + 1);
2612
2613         amdgpu_ras_set_context(adev, con);
2614
2615         amdgpu_ras_check_supported(adev);
2616
2617         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2618                 /* set gfx block ras context feature for VEGA20 Gaming
2619                  * send ras disable cmd to ras ta during ras late init.
2620                  */
2621                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2622                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2623
2624                         return 0;
2625                 }
2626
2627                 r = 0;
2628                 goto release_con;
2629         }
2630
2631         con->update_channel_flag = false;
2632         con->features = 0;
2633         INIT_LIST_HEAD(&con->head);
2634         /* Might need get this flag from vbios. */
2635         con->flags = RAS_DEFAULT_FLAGS;
2636
2637         /* initialize nbio ras function ahead of any other
2638          * ras functions so hardware fatal error interrupt
2639          * can be enabled as early as possible */
2640         switch (adev->ip_versions[NBIO_HWIP][0]) {
2641         case IP_VERSION(7, 4, 0):
2642         case IP_VERSION(7, 4, 1):
2643         case IP_VERSION(7, 4, 4):
2644                 if (!adev->gmc.xgmi.connected_to_cpu)
2645                         adev->nbio.ras = &nbio_v7_4_ras;
2646                 break;
2647         case IP_VERSION(4, 3, 0):
2648                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2649                         /* unlike other generation of nbio ras,
2650                          * nbio v4_3 only support fatal error interrupt
2651                          * to inform software that DF is freezed due to
2652                          * system fatal error event. driver should not
2653                          * enable nbio ras in such case. Instead,
2654                          * check DF RAS */
2655                         adev->nbio.ras = &nbio_v4_3_ras;
2656                 break;
2657         default:
2658                 /* nbio ras is not available */
2659                 break;
2660         }
2661
2662         /* nbio ras block needs to be enabled ahead of other ras blocks
2663          * to handle fatal error */
2664         r = amdgpu_nbio_ras_sw_init(adev);
2665         if (r)
2666                 return r;
2667
2668         if (adev->nbio.ras &&
2669             adev->nbio.ras->init_ras_controller_interrupt) {
2670                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2671                 if (r)
2672                         goto release_con;
2673         }
2674
2675         if (adev->nbio.ras &&
2676             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2677                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2678                 if (r)
2679                         goto release_con;
2680         }
2681
2682         amdgpu_ras_query_poison_mode(adev);
2683
2684         if (amdgpu_ras_fs_init(adev)) {
2685                 r = -EINVAL;
2686                 goto release_con;
2687         }
2688
2689         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2690                  "hardware ability[%x] ras_mask[%x]\n",
2691                  adev->ras_hw_enabled, adev->ras_enabled);
2692
2693         return 0;
2694 release_con:
2695         amdgpu_ras_set_context(adev, NULL);
2696         kfree(con);
2697
2698         return r;
2699 }
2700
2701 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2702 {
2703         if (adev->gmc.xgmi.connected_to_cpu ||
2704             adev->gmc.is_app_apu)
2705                 return 1;
2706         return 0;
2707 }
2708
2709 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2710                                         struct ras_common_if *ras_block)
2711 {
2712         struct ras_query_if info = {
2713                 .head = *ras_block,
2714         };
2715
2716         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2717                 return 0;
2718
2719         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2720                 DRM_WARN("RAS init harvest failure");
2721
2722         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2723                 DRM_WARN("RAS init harvest reset failure");
2724
2725         return 0;
2726 }
2727
2728 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2729 {
2730        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2731
2732        if (!con)
2733                return false;
2734
2735        return con->poison_supported;
2736 }
2737
2738 /* helper function to handle common stuff in ip late init phase */
2739 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2740                          struct ras_common_if *ras_block)
2741 {
2742         struct amdgpu_ras_block_object *ras_obj = NULL;
2743         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2744         struct ras_query_if *query_info;
2745         unsigned long ue_count, ce_count;
2746         int r;
2747
2748         /* disable RAS feature per IP block if it is not supported */
2749         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2750                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2751                 return 0;
2752         }
2753
2754         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2755         if (r) {
2756                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2757                         /* in resume phase, if fail to enable ras,
2758                          * clean up all ras fs nodes, and disable ras */
2759                         goto cleanup;
2760                 } else
2761                         return r;
2762         }
2763
2764         /* check for errors on warm reset edc persisant supported ASIC */
2765         amdgpu_persistent_edc_harvesting(adev, ras_block);
2766
2767         /* in resume phase, no need to create ras fs node */
2768         if (adev->in_suspend || amdgpu_in_reset(adev))
2769                 return 0;
2770
2771         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2772         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2773             (ras_obj->hw_ops->query_poison_status ||
2774             ras_obj->hw_ops->handle_poison_consumption))) {
2775                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2776                 if (r)
2777                         goto cleanup;
2778         }
2779
2780         r = amdgpu_ras_sysfs_create(adev, ras_block);
2781         if (r)
2782                 goto interrupt;
2783
2784         /* Those are the cached values at init.
2785          */
2786         query_info = kzalloc(sizeof(struct ras_query_if), GFP_KERNEL);
2787         if (!query_info)
2788                 return -ENOMEM;
2789         memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2790
2791         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2792                 atomic_set(&con->ras_ce_count, ce_count);
2793                 atomic_set(&con->ras_ue_count, ue_count);
2794         }
2795
2796         kfree(query_info);
2797         return 0;
2798
2799 interrupt:
2800         if (ras_obj->ras_cb)
2801                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2802 cleanup:
2803         amdgpu_ras_feature_enable(adev, ras_block, 0);
2804         return r;
2805 }
2806
2807 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2808                          struct ras_common_if *ras_block)
2809 {
2810         return amdgpu_ras_block_late_init(adev, ras_block);
2811 }
2812
2813 /* helper function to remove ras fs node and interrupt handler */
2814 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2815                           struct ras_common_if *ras_block)
2816 {
2817         struct amdgpu_ras_block_object *ras_obj;
2818         if (!ras_block)
2819                 return;
2820
2821         amdgpu_ras_sysfs_remove(adev, ras_block);
2822
2823         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2824         if (ras_obj->ras_cb)
2825                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2826 }
2827
2828 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2829                           struct ras_common_if *ras_block)
2830 {
2831         return amdgpu_ras_block_late_fini(adev, ras_block);
2832 }
2833
2834 /* do some init work after IP late init as dependence.
2835  * and it runs in resume/gpu reset/booting up cases.
2836  */
2837 void amdgpu_ras_resume(struct amdgpu_device *adev)
2838 {
2839         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2840         struct ras_manager *obj, *tmp;
2841
2842         if (!adev->ras_enabled || !con) {
2843                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2844                 amdgpu_release_ras_context(adev);
2845
2846                 return;
2847         }
2848
2849         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2850                 /* Set up all other IPs which are not implemented. There is a
2851                  * tricky thing that IP's actual ras error type should be
2852                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2853                  * ERROR_NONE make sense anyway.
2854                  */
2855                 amdgpu_ras_enable_all_features(adev, 1);
2856
2857                 /* We enable ras on all hw_supported block, but as boot
2858                  * parameter might disable some of them and one or more IP has
2859                  * not implemented yet. So we disable them on behalf.
2860                  */
2861                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2862                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2863                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2864                                 /* there should be no any reference. */
2865                                 WARN_ON(alive_obj(obj));
2866                         }
2867                 }
2868         }
2869 }
2870
2871 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2872 {
2873         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2874
2875         if (!adev->ras_enabled || !con)
2876                 return;
2877
2878         amdgpu_ras_disable_all_features(adev, 0);
2879         /* Make sure all ras objects are disabled. */
2880         if (con->features)
2881                 amdgpu_ras_disable_all_features(adev, 1);
2882 }
2883
2884 int amdgpu_ras_late_init(struct amdgpu_device *adev)
2885 {
2886         struct amdgpu_ras_block_list *node, *tmp;
2887         struct amdgpu_ras_block_object *obj;
2888         int r;
2889
2890         /* Guest side doesn't need init ras feature */
2891         if (amdgpu_sriov_vf(adev))
2892                 return 0;
2893
2894         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2895                 if (!node->ras_obj) {
2896                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2897                         continue;
2898                 }
2899
2900                 obj = node->ras_obj;
2901                 if (obj->ras_late_init) {
2902                         r = obj->ras_late_init(adev, &obj->ras_comm);
2903                         if (r) {
2904                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2905                                         obj->ras_comm.name, r);
2906                                 return r;
2907                         }
2908                 } else
2909                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2910         }
2911
2912         return 0;
2913 }
2914
2915 /* do some fini work before IP fini as dependence */
2916 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2917 {
2918         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2919
2920         if (!adev->ras_enabled || !con)
2921                 return 0;
2922
2923
2924         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2925         if (con->features)
2926                 amdgpu_ras_disable_all_features(adev, 0);
2927         amdgpu_ras_recovery_fini(adev);
2928         return 0;
2929 }
2930
2931 int amdgpu_ras_fini(struct amdgpu_device *adev)
2932 {
2933         struct amdgpu_ras_block_list *ras_node, *tmp;
2934         struct amdgpu_ras_block_object *obj = NULL;
2935         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2936
2937         if (!adev->ras_enabled || !con)
2938                 return 0;
2939
2940         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2941                 if (ras_node->ras_obj) {
2942                         obj = ras_node->ras_obj;
2943                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2944                             obj->ras_fini)
2945                                 obj->ras_fini(adev, &obj->ras_comm);
2946                         else
2947                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
2948                 }
2949
2950                 /* Clear ras blocks from ras_list and free ras block list node */
2951                 list_del(&ras_node->node);
2952                 kfree(ras_node);
2953         }
2954
2955         amdgpu_ras_fs_fini(adev);
2956         amdgpu_ras_interrupt_remove_all(adev);
2957
2958         WARN(con->features, "Feature mask is not cleared");
2959
2960         if (con->features)
2961                 amdgpu_ras_disable_all_features(adev, 1);
2962
2963         cancel_delayed_work_sync(&con->ras_counte_delay_work);
2964
2965         amdgpu_ras_set_context(adev, NULL);
2966         kfree(con);
2967
2968         return 0;
2969 }
2970
2971 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2972 {
2973         amdgpu_ras_check_supported(adev);
2974         if (!adev->ras_hw_enabled)
2975                 return;
2976
2977         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2978                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2979
2980                 dev_info(adev->dev, "uncorrectable hardware error"
2981                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2982
2983                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2984                 amdgpu_ras_reset_gpu(adev);
2985         }
2986 }
2987
2988 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2989 {
2990         if (adev->asic_type == CHIP_VEGA20 &&
2991             adev->pm.fw_version <= 0x283400) {
2992                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2993                                 amdgpu_ras_intr_triggered();
2994         }
2995
2996         return false;
2997 }
2998
2999 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3000 {
3001         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3002
3003         if (!con)
3004                 return;
3005
3006         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3007                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3008                 amdgpu_ras_set_context(adev, NULL);
3009                 kfree(con);
3010         }
3011 }
3012
3013 #ifdef CONFIG_X86_MCE_AMD
3014 static struct amdgpu_device *find_adev(uint32_t node_id)
3015 {
3016         int i;
3017         struct amdgpu_device *adev = NULL;
3018
3019         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3020                 adev = mce_adev_list.devs[i];
3021
3022                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3023                     adev->gmc.xgmi.physical_node_id == node_id)
3024                         break;
3025                 adev = NULL;
3026         }
3027
3028         return adev;
3029 }
3030
3031 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3032 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3033 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3034 #define GPU_ID_OFFSET           8
3035
3036 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3037                                     unsigned long val, void *data)
3038 {
3039         struct mce *m = (struct mce *)data;
3040         struct amdgpu_device *adev = NULL;
3041         uint32_t gpu_id = 0;
3042         uint32_t umc_inst = 0, ch_inst = 0;
3043
3044         /*
3045          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3046          * and error occurred in DramECC (Extended error code = 0) then only
3047          * process the error, else bail out.
3048          */
3049         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3050                     (XEC(m->status, 0x3f) == 0x0)))
3051                 return NOTIFY_DONE;
3052
3053         /*
3054          * If it is correctable error, return.
3055          */
3056         if (mce_is_correctable(m))
3057                 return NOTIFY_OK;
3058
3059         /*
3060          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3061          */
3062         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3063
3064         adev = find_adev(gpu_id);
3065         if (!adev) {
3066                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3067                                                                 gpu_id);
3068                 return NOTIFY_DONE;
3069         }
3070
3071         /*
3072          * If it is uncorrectable error, then find out UMC instance and
3073          * channel index.
3074          */
3075         umc_inst = GET_UMC_INST(m->ipid);
3076         ch_inst = GET_CHAN_INDEX(m->ipid);
3077
3078         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3079                              umc_inst, ch_inst);
3080
3081         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3082                 return NOTIFY_OK;
3083         else
3084                 return NOTIFY_DONE;
3085 }
3086
3087 static struct notifier_block amdgpu_bad_page_nb = {
3088         .notifier_call  = amdgpu_bad_page_notifier,
3089         .priority       = MCE_PRIO_UC,
3090 };
3091
3092 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3093 {
3094         /*
3095          * Add the adev to the mce_adev_list.
3096          * During mode2 reset, amdgpu device is temporarily
3097          * removed from the mgpu_info list which can cause
3098          * page retirement to fail.
3099          * Use this list instead of mgpu_info to find the amdgpu
3100          * device on which the UMC error was reported.
3101          */
3102         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3103
3104         /*
3105          * Register the x86 notifier only once
3106          * with MCE subsystem.
3107          */
3108         if (notifier_registered == false) {
3109                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3110                 notifier_registered = true;
3111         }
3112 }
3113 #endif
3114
3115 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3116 {
3117         if (!adev)
3118                 return NULL;
3119
3120         return adev->psp.ras_context.ras;
3121 }
3122
3123 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3124 {
3125         if (!adev)
3126                 return -EINVAL;
3127
3128         adev->psp.ras_context.ras = ras_con;
3129         return 0;
3130 }
3131
3132 /* check if ras is supported on block, say, sdma, gfx */
3133 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3134                 unsigned int block)
3135 {
3136         int ret = 0;
3137         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3138
3139         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3140                 return 0;
3141
3142         ret = ras && (adev->ras_enabled & (1 << block));
3143
3144         /* For the special asic with mem ecc enabled but sram ecc
3145          * not enabled, even if the ras block is not supported on
3146          * .ras_enabled, if the asic supports poison mode and the
3147          * ras block has ras configuration, it can be considered
3148          * that the ras block supports ras function.
3149          */
3150         if (!ret &&
3151             amdgpu_ras_is_poison_mode_supported(adev) &&
3152             amdgpu_ras_get_ras_block(adev, block, 0))
3153                 ret = 1;
3154
3155         return ret;
3156 }
3157
3158 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3159 {
3160         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3161
3162         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3163                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3164         return 0;
3165 }
3166
3167
3168 /* Register each ip ras block into amdgpu ras */
3169 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3170                 struct amdgpu_ras_block_object *ras_block_obj)
3171 {
3172         struct amdgpu_ras_block_list *ras_node;
3173         if (!adev || !ras_block_obj)
3174                 return -EINVAL;
3175
3176         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3177         if (!ras_node)
3178                 return -ENOMEM;
3179
3180         INIT_LIST_HEAD(&ras_node->node);
3181         ras_node->ras_obj = ras_block_obj;
3182         list_add_tail(&ras_node->node, &adev->ras_list);
3183
3184         return 0;
3185 }
3186
3187 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3188 {
3189         if (!err_type_name)
3190                 return;
3191
3192         switch (err_type) {
3193         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3194                 sprintf(err_type_name, "correctable");
3195                 break;
3196         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3197                 sprintf(err_type_name, "uncorrectable");
3198                 break;
3199         default:
3200                 sprintf(err_type_name, "unknown");
3201                 break;
3202         }
3203 }
3204
3205 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3206                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3207                                          uint32_t instance,
3208                                          uint32_t *memory_id)
3209 {
3210         uint32_t err_status_lo_data, err_status_lo_offset;
3211
3212         if (!reg_entry)
3213                 return false;
3214
3215         err_status_lo_offset =
3216                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3217                                             reg_entry->seg_lo, reg_entry->reg_lo);
3218         err_status_lo_data = RREG32(err_status_lo_offset);
3219
3220         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3221             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3222                 return false;
3223
3224         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3225
3226         return true;
3227 }
3228
3229 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3230                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3231                                        uint32_t instance,
3232                                        unsigned long *err_cnt)
3233 {
3234         uint32_t err_status_hi_data, err_status_hi_offset;
3235
3236         if (!reg_entry)
3237                 return false;
3238
3239         err_status_hi_offset =
3240                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3241                                             reg_entry->seg_hi, reg_entry->reg_hi);
3242         err_status_hi_data = RREG32(err_status_hi_offset);
3243
3244         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3245             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3246                 /* keep the check here in case we need to refer to the result later */
3247                 dev_dbg(adev->dev, "Invalid err_info field\n");
3248
3249         /* read err count */
3250         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3251
3252         return true;
3253 }
3254
3255 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3256                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3257                                            uint32_t reg_list_size,
3258                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3259                                            uint32_t mem_list_size,
3260                                            uint32_t instance,
3261                                            uint32_t err_type,
3262                                            unsigned long *err_count)
3263 {
3264         uint32_t memory_id;
3265         unsigned long err_cnt;
3266         char err_type_name[16];
3267         uint32_t i, j;
3268
3269         for (i = 0; i < reg_list_size; i++) {
3270                 /* query memory_id from err_status_lo */
3271                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3272                                                          instance, &memory_id))
3273                         continue;
3274
3275                 /* query err_cnt from err_status_hi */
3276                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3277                                                        instance, &err_cnt) ||
3278                     !err_cnt)
3279                         continue;
3280
3281                 *err_count += err_cnt;
3282
3283                 /* log the errors */
3284                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3285                 if (!mem_list) {
3286                         /* memory_list is not supported */
3287                         dev_info(adev->dev,
3288                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3289                                  err_cnt, err_type_name,
3290                                  reg_list[i].block_name,
3291                                  instance, memory_id);
3292                 } else {
3293                         for (j = 0; j < mem_list_size; j++) {
3294                                 if (memory_id == mem_list[j].memory_id) {
3295                                         dev_info(adev->dev,
3296                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3297                                                  err_cnt, err_type_name,
3298                                                  reg_list[i].block_name,
3299                                                  instance, mem_list[j].name);
3300                                         break;
3301                                 }
3302                         }
3303                 }
3304         }
3305 }
3306
3307 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3308                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3309                                            uint32_t reg_list_size,
3310                                            uint32_t instance)
3311 {
3312         uint32_t err_status_lo_offset, err_status_hi_offset;
3313         uint32_t i;
3314
3315         for (i = 0; i < reg_list_size; i++) {
3316                 err_status_lo_offset =
3317                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3318                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3319                 err_status_hi_offset =
3320                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3321                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3322                 WREG32(err_status_lo_offset, 0);
3323                 WREG32(err_status_hi_offset, 0);
3324         }
3325 }