drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "bif/bif_4_1_d.h"
  63
  64 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  65
  66 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  67                                     unsigned int type,
  68                                     uint64_t size)
  69 {
  70         return ttm_range_man_init(&adev->mman.bdev, type,
  71                                   TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED,
  72                                   false, size >> PAGE_SHIFT);
  73 }
  74
  75 /**
  76  * amdgpu_evict_flags - Compute placement flags
  77  *
  78  * @bo: The buffer object to evict
  79  * @placement: Possible destination(s) for evicted BO
  80  *
  81  * Fill in placement data when ttm_bo_evict() is called
  82  */
  83 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  84                                 struct ttm_placement *placement)
  85 {
  86         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  87         struct amdgpu_bo *abo;
  88         static const struct ttm_place placements = {
  89                 .fpfn = 0,
  90                 .lpfn = 0,
  91                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
  92         };
  93
  94         /* Don't handle scatter gather BOs */
  95         if (bo->type == ttm_bo_type_sg) {
  96                 placement->num_placement = 0;
  97                 placement->num_busy_placement = 0;
  98                 return;
  99         }
 100
 101         /* Object isn't an AMDGPU object so ignore */
 102         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 103                 placement->placement = &placements;
 104                 placement->busy_placement = &placements;
 105                 placement->num_placement = 1;
 106                 placement->num_busy_placement = 1;
 107                 return;
 108         }
 109
 110         abo = ttm_to_amdgpu_bo(bo);
 111         switch (bo->mem.mem_type) {
 112         case AMDGPU_PL_GDS:
 113         case AMDGPU_PL_GWS:
 114         case AMDGPU_PL_OA:
 115                 placement->num_placement = 0;
 116                 placement->num_busy_placement = 0;
 117                 return;
 118
 119         case TTM_PL_VRAM:
 120                 if (!adev->mman.buffer_funcs_enabled) {
 121                         /* Move to system memory */
 122                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 123                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 124                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 125                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 126
 127                         /* Try evicting to the CPU inaccessible part of VRAM
 128                          * first, but only set GTT as busy placement, so this
 129                          * BO will be evicted to GTT rather than causing other
 130                          * BOs to be evicted from VRAM
 131                          */
 132                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 133                                                          AMDGPU_GEM_DOMAIN_GTT);
 134                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 135                         abo->placements[0].lpfn = 0;
 136                         abo->placement.busy_placement = &abo->placements[1];
 137                         abo->placement.num_busy_placement = 1;
 138                 } else {
 139                         /* Move to GTT memory */
 140                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 141                 }
 142                 break;
 143         case TTM_PL_TT:
 144         default:
 145                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 146                 break;
 147         }
 148         *placement = abo->placement;
 149 }
 150
 151 /**
 152  * amdgpu_verify_access - Verify access for a mmap call
 153  *
 154  * @bo: The buffer object to map
 155  * @filp: The file pointer from the process performing the mmap
 156  *
 157  * This is called by ttm_bo_mmap() to verify whether a process
 158  * has the right to mmap a BO to their process space.
 159  */
 160 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 161 {
 162         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 163
 164         /*
 165          * Don't verify access for KFD BOs. They don't have a GEM
 166          * object associated with them.
 167          */
 168         if (abo->kfd_bo)
 169                 return 0;
 170
 171         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 172                 return -EPERM;
 173         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 174                                           filp->private_data);
 175 }
 176
 177 /**
 178  * amdgpu_move_null - Register memory for a buffer object
 179  *
 180  * @bo: The bo to assign the memory to
 181  * @new_mem: The memory to be assigned.
 182  *
 183  * Assign the memory from new_mem to the memory of the buffer object bo.
 184  */
 185 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 186                              struct ttm_resource *new_mem)
 187 {
 188         struct ttm_resource *old_mem = &bo->mem;
 189
 190         BUG_ON(old_mem->mm_node != NULL);
 191         *old_mem = *new_mem;
 192         new_mem->mm_node = NULL;
 193 }
 194
 195 /**
 196  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 197  *
 198  * @bo: The bo to assign the memory to.
 199  * @mm_node: Memory manager node for drm allocator.
 200  * @mem: The region where the bo resides.
 201  *
 202  */
 203 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 204                                     struct drm_mm_node *mm_node,
 205                                     struct ttm_resource *mem)
 206 {
 207         uint64_t addr = 0;
 208
 209         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 210                 addr = mm_node->start << PAGE_SHIFT;
 211                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 212                                                 mem->mem_type);
 213         }
 214         return addr;
 215 }
 216
 217 /**
 218  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 219  * @offset. It also modifies the offset to be within the drm_mm_node returned
 220  *
 221  * @mem: The region where the bo resides.
 222  * @offset: The offset that drm_mm_node is used for finding.
 223  *
 224  */
 225 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 226                                                uint64_t *offset)
 227 {
 228         struct drm_mm_node *mm_node = mem->mm_node;
 229
 230         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 231                 *offset -= (mm_node->size << PAGE_SHIFT);
 232                 ++mm_node;
 233         }
 234         return mm_node;
 235 }
 236
 237 /**
 238  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 239  * @bo: buffer object to map
 240  * @mem: memory object to map
 241  * @mm_node: drm_mm node object to map
 242  * @num_pages: number of pages to map
 243  * @offset: offset into @mm_node where to start
 244  * @window: which GART window to use
 245  * @ring: DMA ring to use for the copy
 246  * @tmz: if we should setup a TMZ enabled mapping
 247  * @addr: resulting address inside the MC address space
 248  *
 249  * Setup one of the GART windows to access a specific piece of memory or return
 250  * the physical address for local memory.
 251  */
 252 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 253                                  struct ttm_resource *mem,
 254                                  struct drm_mm_node *mm_node,
 255                                  unsigned num_pages, uint64_t offset,
 256                                  unsigned window, struct amdgpu_ring *ring,
 257                                  bool tmz, uint64_t *addr)
 258 {
 259         struct amdgpu_device *adev = ring->adev;
 260         struct amdgpu_job *job;
 261         unsigned num_dw, num_bytes;
 262         struct dma_fence *fence;
 263         uint64_t src_addr, dst_addr;
 264         void *cpu_addr;
 265         uint64_t flags;
 266         unsigned int i;
 267         int r;
 268
 269         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 270                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 271
 272         /* Map only what can't be accessed directly */
 273         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 274                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 275                 return 0;
 276         }
 277
 278         *addr = adev->gmc.gart_start;
 279         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 280                 AMDGPU_GPU_PAGE_SIZE;
 281         *addr += offset & ~PAGE_MASK;
 282
 283         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 284         num_bytes = num_pages * 8;
 285
 286         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 287                                      AMDGPU_IB_POOL_DELAYED, &job);
 288         if (r)
 289                 return r;
 290
 291         src_addr = num_dw * 4;
 292         src_addr += job->ibs[0].gpu_addr;
 293
 294         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 295         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 296         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 297                                 dst_addr, num_bytes, false);
 298
 299         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 300         WARN_ON(job->ibs[0].length_dw > num_dw);
 301
 302         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 303         if (tmz)
 304                 flags |= AMDGPU_PTE_TMZ;
 305
 306         cpu_addr = &job->ibs[0].ptr[num_dw];
 307
 308         if (mem->mem_type == TTM_PL_TT) {
 309                 struct ttm_dma_tt *dma;
 310                 dma_addr_t *dma_address;
 311
 312                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 313                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 314                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 315                                     cpu_addr);
 316                 if (r)
 317                         goto error_free;
 318         } else {
 319                 dma_addr_t dma_address;
 320
 321                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 322                 dma_address += adev->vm_manager.vram_base_offset;
 323
 324                 for (i = 0; i < num_pages; ++i) {
 325                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 326                                             &dma_address, flags, cpu_addr);
 327                         if (r)
 328                                 goto error_free;
 329
 330                         dma_address += PAGE_SIZE;
 331                 }
 332         }
 333
 334         r = amdgpu_job_submit(job, &adev->mman.entity,
 335                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 336         if (r)
 337                 goto error_free;
 338
 339         dma_fence_put(fence);
 340
 341         return r;
 342
 343 error_free:
 344         amdgpu_job_free(job);
 345         return r;
 346 }
 347
 348 /**
 349  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 350  * @adev: amdgpu device
 351  * @src: buffer/address where to read from
 352  * @dst: buffer/address where to write to
 353  * @size: number of bytes to copy
 354  * @tmz: if a secure copy should be used
 355  * @resv: resv object to sync to
 356  * @f: Returns the last fence if multiple jobs are submitted.
 357  *
 358  * The function copies @size bytes from {src->mem + src->offset} to
 359  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 360  * move and different for a BO to BO copy.
 361  *
 362  */
 363 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 364                                const struct amdgpu_copy_mem *src,
 365                                const struct amdgpu_copy_mem *dst,
 366                                uint64_t size, bool tmz,
 367                                struct dma_resv *resv,
 368                                struct dma_fence **f)
 369 {
 370         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 371                                         AMDGPU_GPU_PAGE_SIZE);
 372
 373         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 374         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 375         struct drm_mm_node *src_mm, *dst_mm;
 376         struct dma_fence *fence = NULL;
 377         int r = 0;
 378
 379         if (!adev->mman.buffer_funcs_enabled) {
 380                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 381                 return -EINVAL;
 382         }
 383
 384         src_offset = src->offset;
 385         if (src->mem->mm_node) {
 386                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 387                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 388         } else {
 389                 src_mm = NULL;
 390                 src_node_size = ULLONG_MAX;
 391         }
 392
 393         dst_offset = dst->offset;
 394         if (dst->mem->mm_node) {
 395                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 396                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 397         } else {
 398                 dst_mm = NULL;
 399                 dst_node_size = ULLONG_MAX;
 400         }
 401
 402         mutex_lock(&adev->mman.gtt_window_lock);
 403
 404         while (size) {
 405                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 406                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 407                 struct dma_fence *next;
 408                 uint32_t cur_size;
 409                 uint64_t from, to;
 410
 411                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 412                  * begins at an offset, then adjust the size accordingly
 413                  */
 414                 cur_size = max(src_page_offset, dst_page_offset);
 415                 cur_size = min(min3(src_node_size, dst_node_size, size),
 416                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 417
 418                 /* Map src to window 0 and dst to window 1. */
 419                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 420                                           PFN_UP(cur_size + src_page_offset),
 421                                           src_offset, 0, ring, tmz, &from);
 422                 if (r)
 423                         goto error;
 424
 425                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 426                                           PFN_UP(cur_size + dst_page_offset),
 427                                           dst_offset, 1, ring, tmz, &to);
 428                 if (r)
 429                         goto error;
 430
 431                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 432                                        resv, &next, false, true, tmz);
 433                 if (r)
 434                         goto error;
 435
 436                 dma_fence_put(fence);
 437                 fence = next;
 438
 439                 size -= cur_size;
 440                 if (!size)
 441                         break;
 442
 443                 src_node_size -= cur_size;
 444                 if (!src_node_size) {
 445                         ++src_mm;
 446                         src_node_size = src_mm->size << PAGE_SHIFT;
 447                         src_offset = 0;
 448                 } else {
 449                         src_offset += cur_size;
 450                 }
 451
 452                 dst_node_size -= cur_size;
 453                 if (!dst_node_size) {
 454                         ++dst_mm;
 455                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 456                         dst_offset = 0;
 457                 } else {
 458                         dst_offset += cur_size;
 459                 }
 460         }
 461 error:
 462         mutex_unlock(&adev->mman.gtt_window_lock);
 463         if (f)
 464                 *f = dma_fence_get(fence);
 465         dma_fence_put(fence);
 466         return r;
 467 }
 468
 469 /**
 470  * amdgpu_move_blit - Copy an entire buffer to another buffer
 471  *
 472  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 473  * help move buffers to and from VRAM.
 474  */
 475 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 476                             bool evict,
 477                             struct ttm_resource *new_mem,
 478                             struct ttm_resource *old_mem)
 479 {
 480         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 481         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 482         struct amdgpu_copy_mem src, dst;
 483         struct dma_fence *fence = NULL;
 484         int r;
 485
 486         src.bo = bo;
 487         dst.bo = bo;
 488         src.mem = old_mem;
 489         dst.mem = new_mem;
 490         src.offset = 0;
 491         dst.offset = 0;
 492
 493         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 494                                        new_mem->num_pages << PAGE_SHIFT,
 495                                        amdgpu_bo_encrypted(abo),
 496                                        bo->base.resv, &fence);
 497         if (r)
 498                 goto error;
 499
 500         /* clear the space being freed */
 501         if (old_mem->mem_type == TTM_PL_VRAM &&
 502             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 503                 struct dma_fence *wipe_fence = NULL;
 504
 505                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 506                                        NULL, &wipe_fence);
 507                 if (r) {
 508                         goto error;
 509                 } else if (wipe_fence) {
 510                         dma_fence_put(fence);
 511                         fence = wipe_fence;
 512                 }
 513         }
 514
 515         /* Always block for VM page tables before committing the new location */
 516         if (bo->type == ttm_bo_type_kernel)
 517                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 518         else
 519                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 520         dma_fence_put(fence);
 521         return r;
 522
 523 error:
 524         if (fence)
 525                 dma_fence_wait(fence, false);
 526         dma_fence_put(fence);
 527         return r;
 528 }
 529
 530 /**
 531  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 532  *
 533  * Called by amdgpu_bo_move().
 534  */
 535 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 536                                 struct ttm_operation_ctx *ctx,
 537                                 struct ttm_resource *new_mem)
 538 {
 539         struct ttm_resource *old_mem = &bo->mem;
 540         struct ttm_resource tmp_mem;
 541         struct ttm_place placements;
 542         struct ttm_placement placement;
 543         int r;
 544
 545         /* create space/pages for new_mem in GTT space */
 546         tmp_mem = *new_mem;
 547         tmp_mem.mm_node = NULL;
 548         placement.num_placement = 1;
 549         placement.placement = &placements;
 550         placement.num_busy_placement = 1;
 551         placement.busy_placement = &placements;
 552         placements.fpfn = 0;
 553         placements.lpfn = 0;
 554         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 555         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 556         if (unlikely(r)) {
 557                 pr_err("Failed to find GTT space for blit from VRAM\n");
 558                 return r;
 559         }
 560
 561         /* set caching flags */
 562         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 563         if (unlikely(r)) {
 564                 goto out_cleanup;
 565         }
 566
 567         /* Bind the memory to the GTT space */
 568         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 569         if (unlikely(r)) {
 570                 goto out_cleanup;
 571         }
 572
 573         /* blit VRAM to GTT */
 574         r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
 575         if (unlikely(r)) {
 576                 goto out_cleanup;
 577         }
 578
 579         /* move BO (in tmp_mem) to new_mem */
 580         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 581 out_cleanup:
 582         ttm_resource_free(bo, &tmp_mem);
 583         return r;
 584 }
 585
 586 /**
 587  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 588  *
 589  * Called by amdgpu_bo_move().
 590  */
 591 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 592                                 struct ttm_operation_ctx *ctx,
 593                                 struct ttm_resource *new_mem)
 594 {
 595         struct ttm_resource *old_mem = &bo->mem;
 596         struct ttm_resource tmp_mem;
 597         struct ttm_placement placement;
 598         struct ttm_place placements;
 599         int r;
 600
 601         /* make space in GTT for old_mem buffer */
 602         tmp_mem = *new_mem;
 603         tmp_mem.mm_node = NULL;
 604         placement.num_placement = 1;
 605         placement.placement = &placements;
 606         placement.num_busy_placement = 1;
 607         placement.busy_placement = &placements;
 608         placements.fpfn = 0;
 609         placements.lpfn = 0;
 610         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 611         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 612         if (unlikely(r)) {
 613                 pr_err("Failed to find GTT space for blit to VRAM\n");
 614                 return r;
 615         }
 616
 617         /* move/bind old memory to GTT space */
 618         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 619         if (unlikely(r)) {
 620                 goto out_cleanup;
 621         }
 622
 623         /* copy to VRAM */
 624         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 625         if (unlikely(r)) {
 626                 goto out_cleanup;
 627         }
 628 out_cleanup:
 629         ttm_resource_free(bo, &tmp_mem);
 630         return r;
 631 }
 632
 633 /**
 634  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 635  *
 636  * Called by amdgpu_bo_move()
 637  */
 638 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 639                                struct ttm_resource *mem)
 640 {
 641         struct drm_mm_node *nodes = mem->mm_node;
 642
 643         if (mem->mem_type == TTM_PL_SYSTEM ||
 644             mem->mem_type == TTM_PL_TT)
 645                 return true;
 646         if (mem->mem_type != TTM_PL_VRAM)
 647                 return false;
 648
 649         /* ttm_resource_ioremap only supports contiguous memory */
 650         if (nodes->size != mem->num_pages)
 651                 return false;
 652
 653         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 654                 <= adev->gmc.visible_vram_size;
 655 }
 656
 657 /**
 658  * amdgpu_bo_move - Move a buffer object to a new memory location
 659  *
 660  * Called by ttm_bo_handle_move_mem()
 661  */
 662 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 663                           struct ttm_operation_ctx *ctx,
 664                           struct ttm_resource *new_mem)
 665 {
 666         struct amdgpu_device *adev;
 667         struct amdgpu_bo *abo;
 668         struct ttm_resource *old_mem = &bo->mem;
 669         int r;
 670
 671         /* Can't move a pinned BO */
 672         abo = ttm_to_amdgpu_bo(bo);
 673         if (WARN_ON_ONCE(abo->pin_count > 0))
 674                 return -EINVAL;
 675
 676         adev = amdgpu_ttm_adev(bo->bdev);
 677
 678         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 679                 amdgpu_move_null(bo, new_mem);
 680                 return 0;
 681         }
 682         if ((old_mem->mem_type == TTM_PL_TT &&
 683              new_mem->mem_type == TTM_PL_SYSTEM) ||
 684             (old_mem->mem_type == TTM_PL_SYSTEM &&
 685              new_mem->mem_type == TTM_PL_TT)) {
 686                 /* bind is enough */
 687                 amdgpu_move_null(bo, new_mem);
 688                 return 0;
 689         }
 690         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 691             old_mem->mem_type == AMDGPU_PL_GWS ||
 692             old_mem->mem_type == AMDGPU_PL_OA ||
 693             new_mem->mem_type == AMDGPU_PL_GDS ||
 694             new_mem->mem_type == AMDGPU_PL_GWS ||
 695             new_mem->mem_type == AMDGPU_PL_OA) {
 696                 /* Nothing to save here */
 697                 amdgpu_move_null(bo, new_mem);
 698                 return 0;
 699         }
 700
 701         if (!adev->mman.buffer_funcs_enabled) {
 702                 r = -ENODEV;
 703                 goto memcpy;
 704         }
 705
 706         if (old_mem->mem_type == TTM_PL_VRAM &&
 707             new_mem->mem_type == TTM_PL_SYSTEM) {
 708                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 709         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 710                    new_mem->mem_type == TTM_PL_VRAM) {
 711                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 712         } else {
 713                 r = amdgpu_move_blit(bo, evict,
 714                                      new_mem, old_mem);
 715         }
 716
 717         if (r) {
 718 memcpy:
 719                 /* Check that all memory is CPU accessible */
 720                 if (!amdgpu_mem_visible(adev, old_mem) ||
 721                     !amdgpu_mem_visible(adev, new_mem)) {
 722                         pr_err("Move buffer fallback to memcpy unavailable\n");
 723                         return r;
 724                 }
 725
 726                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 727                 if (r)
 728                         return r;
 729         }
 730
 731         if (bo->type == ttm_bo_type_device &&
 732             new_mem->mem_type == TTM_PL_VRAM &&
 733             old_mem->mem_type != TTM_PL_VRAM) {
 734                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 735                  * accesses the BO after it's moved.
 736                  */
 737                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 738         }
 739
 740         /* update statistics */
 741         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 742         return 0;
 743 }
 744
 745 /**
 746  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 747  *
 748  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 749  */
 750 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 751 {
 752         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 753         struct drm_mm_node *mm_node = mem->mm_node;
 754         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 755
 756         switch (mem->mem_type) {
 757         case TTM_PL_SYSTEM:
 758                 /* system memory */
 759                 return 0;
 760         case TTM_PL_TT:
 761                 break;
 762         case TTM_PL_VRAM:
 763                 mem->bus.offset = mem->start << PAGE_SHIFT;
 764                 /* check if it's visible */
 765                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 766                         return -EINVAL;
 767                 /* Only physically contiguous buffers apply. In a contiguous
 768                  * buffer, size of the first mm_node would match the number of
 769                  * pages in ttm_resource.
 770                  */
 771                 if (adev->mman.aper_base_kaddr &&
 772                     (mm_node->size == mem->num_pages))
 773                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 774                                         mem->bus.offset;
 775
 776                 mem->bus.base = adev->gmc.aper_base;
 777                 mem->bus.is_iomem = true;
 778                 break;
 779         default:
 780                 return -EINVAL;
 781         }
 782         return 0;
 783 }
 784
 785 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 786                                            unsigned long page_offset)
 787 {
 788         uint64_t offset = (page_offset << PAGE_SHIFT);
 789         struct drm_mm_node *mm;
 790
 791         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 792         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 793                 (offset >> PAGE_SHIFT);
 794 }
 795
 796 /**
 797  * amdgpu_ttm_domain_start - Returns GPU start address
 798  * @adev: amdgpu device object
 799  * @type: type of the memory
 800  *
 801  * Returns:
 802  * GPU start address of a memory domain
 803  */
 804
 805 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 806 {
 807         switch (type) {
 808         case TTM_PL_TT:
 809                 return adev->gmc.gart_start;
 810         case TTM_PL_VRAM:
 811                 return adev->gmc.vram_start;
 812         }
 813
 814         return 0;
 815 }
 816
 817 /*
 818  * TTM backend functions.
 819  */
 820 struct amdgpu_ttm_tt {
 821         struct ttm_dma_tt       ttm;
 822         struct drm_gem_object   *gobj;
 823         u64                     offset;
 824         uint64_t                userptr;
 825         struct task_struct      *usertask;
 826         uint32_t                userflags;
 827 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 828         struct hmm_range        *range;
 829 #endif
 830 };
 831
 832 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 833 /**
 834  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 835  * memory and start HMM tracking CPU page table update
 836  *
 837  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 838  * once afterwards to stop HMM tracking
 839  */
 840 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 841 {
 842         struct ttm_tt *ttm = bo->tbo.ttm;
 843         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 844         unsigned long start = gtt->userptr;
 845         struct vm_area_struct *vma;
 846         struct hmm_range *range;
 847         unsigned long timeout;
 848         struct mm_struct *mm;
 849         unsigned long i;
 850         int r = 0;
 851
 852         mm = bo->notifier.mm;
 853         if (unlikely(!mm)) {
 854                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 855                 return -EFAULT;
 856         }
 857
 858         /* Another get_user_pages is running at the same time?? */
 859         if (WARN_ON(gtt->range))
 860                 return -EFAULT;
 861
 862         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 863                 return -ESRCH;
 864
 865         range = kzalloc(sizeof(*range), GFP_KERNEL);
 866         if (unlikely(!range)) {
 867                 r = -ENOMEM;
 868                 goto out;
 869         }
 870         range->notifier = &bo->notifier;
 871         range->start = bo->notifier.interval_tree.start;
 872         range->end = bo->notifier.interval_tree.last + 1;
 873         range->default_flags = HMM_PFN_REQ_FAULT;
 874         if (!amdgpu_ttm_tt_is_readonly(ttm))
 875                 range->default_flags |= HMM_PFN_REQ_WRITE;
 876
 877         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 878                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 879         if (unlikely(!range->hmm_pfns)) {
 880                 r = -ENOMEM;
 881                 goto out_free_ranges;
 882         }
 883
 884         mmap_read_lock(mm);
 885         vma = find_vma(mm, start);
 886         if (unlikely(!vma || start < vma->vm_start)) {
 887                 r = -EFAULT;
 888                 goto out_unlock;
 889         }
 890         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 891                 vma->vm_file)) {
 892                 r = -EPERM;
 893                 goto out_unlock;
 894         }
 895         mmap_read_unlock(mm);
 896         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 897
 898 retry:
 899         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 900
 901         mmap_read_lock(mm);
 902         r = hmm_range_fault(range);
 903         mmap_read_unlock(mm);
 904         if (unlikely(r)) {
 905                 /*
 906                  * FIXME: This timeout should encompass the retry from
 907                  * mmu_interval_read_retry() as well.
 908                  */
 909                 if (r == -EBUSY && !time_after(jiffies, timeout))
 910                         goto retry;
 911                 goto out_free_pfns;
 912         }
 913
 914         /*
 915          * Due to default_flags, all pages are HMM_PFN_VALID or
 916          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 917          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 918          */
 919         for (i = 0; i < ttm->num_pages; i++)
 920                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 921
 922         gtt->range = range;
 923         mmput(mm);
 924
 925         return 0;
 926
 927 out_unlock:
 928         mmap_read_unlock(mm);
 929 out_free_pfns:
 930         kvfree(range->hmm_pfns);
 931 out_free_ranges:
 932         kfree(range);
 933 out:
 934         mmput(mm);
 935         return r;
 936 }
 937
 938 /**
 939  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 940  * Check if the pages backing this ttm range have been invalidated
 941  *
 942  * Returns: true if pages are still valid
 943  */
 944 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 945 {
 946         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 947         bool r = false;
 948
 949         if (!gtt || !gtt->userptr)
 950                 return false;
 951
 952         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 953                 gtt->userptr, ttm->num_pages);
 954
 955         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 956                 "No user pages to check\n");
 957
 958         if (gtt->range) {
 959                 /*
 960                  * FIXME: Must always hold notifier_lock for this, and must
 961                  * not ignore the return code.
 962                  */
 963                 r = mmu_interval_read_retry(gtt->range->notifier,
 964                                          gtt->range->notifier_seq);
 965                 kvfree(gtt->range->hmm_pfns);
 966                 kfree(gtt->range);
 967                 gtt->range = NULL;
 968         }
 969
 970         return !r;
 971 }
 972 #endif
 973
 974 /**
 975  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 976  *
 977  * Called by amdgpu_cs_list_validate(). This creates the page list
 978  * that backs user memory and will ultimately be mapped into the device
 979  * address space.
 980  */
 981 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 982 {
 983         unsigned long i;
 984
 985         for (i = 0; i < ttm->num_pages; ++i)
 986                 ttm->pages[i] = pages ? pages[i] : NULL;
 987 }
 988
 989 /**
 990  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 991  *
 992  * Called by amdgpu_ttm_backend_bind()
 993  **/
 994 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 995 {
 996         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 997         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 998         int r;
 999
1000         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1001         enum dma_data_direction direction = write ?
1002                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1003
1004         /* Allocate an SG array and squash pages into it */
1005         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1006                                       ttm->num_pages << PAGE_SHIFT,
1007                                       GFP_KERNEL);
1008         if (r)
1009                 goto release_sg;
1010
1011         /* Map SG to device */
1012         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1013         if (r)
1014                 goto release_sg;
1015
1016         /* convert SG to linear array of pages and dma addresses */
1017         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1018                                          gtt->ttm.dma_address, ttm->num_pages);
1019
1020         return 0;
1021
1022 release_sg:
1023         kfree(ttm->sg);
1024         ttm->sg = NULL;
1025         return r;
1026 }
1027
1028 /**
1029  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1030  */
1031 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1032 {
1033         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1034         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1035
1036         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1037         enum dma_data_direction direction = write ?
1038                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1039
1040         /* double check that we don't free the table twice */
1041         if (!ttm->sg->sgl)
1042                 return;
1043
1044         /* unmap the pages mapped to the device */
1045         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1046         sg_free_table(ttm->sg);
1047
1048 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1049         if (gtt->range) {
1050                 unsigned long i;
1051
1052                 for (i = 0; i < ttm->num_pages; i++) {
1053                         if (ttm->pages[i] !=
1054                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1055                                 break;
1056                 }
1057
1058                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1059         }
1060 #endif
1061 }
1062
1063 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1064                                 struct ttm_buffer_object *tbo,
1065                                 uint64_t flags)
1066 {
1067         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1068         struct ttm_tt *ttm = tbo->ttm;
1069         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1070         int r;
1071
1072         if (amdgpu_bo_encrypted(abo))
1073                 flags |= AMDGPU_PTE_TMZ;
1074
1075         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1076                 uint64_t page_idx = 1;
1077
1078                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1079                                 ttm->pages, gtt->ttm.dma_address, flags);
1080                 if (r)
1081                         goto gart_bind_fail;
1082
1083                 /* The memory type of the first page defaults to UC. Now
1084                  * modify the memory type to NC from the second page of
1085                  * the BO onward.
1086                  */
1087                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1088                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1089
1090                 r = amdgpu_gart_bind(adev,
1091                                 gtt->offset + (page_idx << PAGE_SHIFT),
1092                                 ttm->num_pages - page_idx,
1093                                 &ttm->pages[page_idx],
1094                                 &(gtt->ttm.dma_address[page_idx]), flags);
1095         } else {
1096                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1097                                      ttm->pages, gtt->ttm.dma_address, flags);
1098         }
1099
1100 gart_bind_fail:
1101         if (r)
1102                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1103                           ttm->num_pages, gtt->offset);
1104
1105         return r;
1106 }
1107
1108 /**
1109  * amdgpu_ttm_backend_bind - Bind GTT memory
1110  *
1111  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1112  * This handles binding GTT memory to the device address space.
1113  */
1114 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1115                                    struct ttm_resource *bo_mem)
1116 {
1117         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1118         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1119         uint64_t flags;
1120         int r = 0;
1121
1122         if (gtt->userptr) {
1123                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1124                 if (r) {
1125                         DRM_ERROR("failed to pin userptr\n");
1126                         return r;
1127                 }
1128         }
1129         if (!ttm->num_pages) {
1130                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1131                      ttm->num_pages, bo_mem, ttm);
1132         }
1133
1134         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1135             bo_mem->mem_type == AMDGPU_PL_GWS ||
1136             bo_mem->mem_type == AMDGPU_PL_OA)
1137                 return -EINVAL;
1138
1139         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1140                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1141                 return 0;
1142         }
1143
1144         /* compute PTE flags relevant to this BO memory */
1145         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1146
1147         /* bind pages into GART page tables */
1148         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1149         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1150                 ttm->pages, gtt->ttm.dma_address, flags);
1151
1152         if (r)
1153                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1154                           ttm->num_pages, gtt->offset);
1155         return r;
1156 }
1157
1158 /**
1159  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
1160  * through AGP or GART aperture.
1161  *
1162  * If bo is accessible through AGP aperture, then use AGP aperture
1163  * to access bo; otherwise allocate logical space in GART aperture
1164  * and map bo to GART aperture.
1165  */
1166 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1167 {
1168         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1169         struct ttm_operation_ctx ctx = { false, false };
1170         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1171         struct ttm_resource tmp;
1172         struct ttm_placement placement;
1173         struct ttm_place placements;
1174         uint64_t addr, flags;
1175         int r;
1176
1177         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1178                 return 0;
1179
1180         addr = amdgpu_gmc_agp_addr(bo);
1181         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1182                 bo->mem.start = addr >> PAGE_SHIFT;
1183         } else {
1184
1185                 /* allocate GART space */
1186                 tmp = bo->mem;
1187                 tmp.mm_node = NULL;
1188                 placement.num_placement = 1;
1189                 placement.placement = &placements;
1190                 placement.num_busy_placement = 1;
1191                 placement.busy_placement = &placements;
1192                 placements.fpfn = 0;
1193                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1194                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1195                         TTM_PL_FLAG_TT;
1196
1197                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1198                 if (unlikely(r))
1199                         return r;
1200
1201                 /* compute PTE flags for this buffer object */
1202                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1203
1204                 /* Bind pages */
1205                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1206                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1207                 if (unlikely(r)) {
1208                         ttm_resource_free(bo, &tmp);
1209                         return r;
1210                 }
1211
1212                 ttm_resource_free(bo, &bo->mem);
1213                 bo->mem = tmp;
1214         }
1215
1216         return 0;
1217 }
1218
1219 /**
1220  * amdgpu_ttm_recover_gart - Rebind GTT pages
1221  *
1222  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1223  * rebind GTT pages during a GPU reset.
1224  */
1225 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1226 {
1227         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1228         uint64_t flags;
1229         int r;
1230
1231         if (!tbo->ttm)
1232                 return 0;
1233
1234         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1235         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1236
1237         return r;
1238 }
1239
1240 /**
1241  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1242  *
1243  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1244  * ttm_tt_destroy().
1245  */
1246 static void amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1247 {
1248         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1249         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1250         int r;
1251
1252         /* if the pages have userptr pinning then clear that first */
1253         if (gtt->userptr)
1254                 amdgpu_ttm_tt_unpin_userptr(ttm);
1255
1256         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1257                 return;
1258
1259         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1260         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1261         if (r)
1262                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1263                           gtt->ttm.ttm.num_pages, gtt->offset);
1264 }
1265
1266 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1267 {
1268         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1269
1270         if (gtt->usertask)
1271                 put_task_struct(gtt->usertask);
1272
1273         ttm_dma_tt_fini(&gtt->ttm);
1274         kfree(gtt);
1275 }
1276
1277 static struct ttm_backend_func amdgpu_backend_func = {
1278         .bind = &amdgpu_ttm_backend_bind,
1279         .unbind = &amdgpu_ttm_backend_unbind,
1280         .destroy = &amdgpu_ttm_backend_destroy,
1281 };
1282
1283 /**
1284  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1285  *
1286  * @bo: The buffer object to create a GTT ttm_tt object around
1287  *
1288  * Called by ttm_tt_create().
1289  */
1290 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1291                                            uint32_t page_flags)
1292 {
1293         struct amdgpu_ttm_tt *gtt;
1294
1295         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1296         if (gtt == NULL) {
1297                 return NULL;
1298         }
1299         gtt->ttm.ttm.func = &amdgpu_backend_func;
1300         gtt->gobj = &bo->base;
1301
1302         /* allocate space for the uninitialized page entries */
1303         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1304                 kfree(gtt);
1305                 return NULL;
1306         }
1307         return &gtt->ttm.ttm;
1308 }
1309
1310 /**
1311  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1312  *
1313  * Map the pages of a ttm_tt object to an address space visible
1314  * to the underlying device.
1315  */
1316 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1317                         struct ttm_operation_ctx *ctx)
1318 {
1319         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1320         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1321
1322         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1323         if (gtt && gtt->userptr) {
1324                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1325                 if (!ttm->sg)
1326                         return -ENOMEM;
1327
1328                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1329                 ttm->state = tt_unbound;
1330                 return 0;
1331         }
1332
1333         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1334                 if (!ttm->sg) {
1335                         struct dma_buf_attachment *attach;
1336                         struct sg_table *sgt;
1337
1338                         attach = gtt->gobj->import_attach;
1339                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1340                         if (IS_ERR(sgt))
1341                                 return PTR_ERR(sgt);
1342
1343                         ttm->sg = sgt;
1344                 }
1345
1346                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1347                                                  gtt->ttm.dma_address,
1348                                                  ttm->num_pages);
1349                 ttm->state = tt_unbound;
1350                 return 0;
1351         }
1352
1353 #ifdef CONFIG_SWIOTLB
1354         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1355                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1356         }
1357 #endif
1358
1359         /* fall back to generic helper to populate the page array
1360          * and map them to the device */
1361         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1362 }
1363
1364 /**
1365  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1366  *
1367  * Unmaps pages of a ttm_tt object from the device address space and
1368  * unpopulates the page array backing it.
1369  */
1370 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1371 {
1372         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1373         struct amdgpu_device *adev;
1374
1375         if (gtt && gtt->userptr) {
1376                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1377                 kfree(ttm->sg);
1378                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1379                 return;
1380         }
1381
1382         if (ttm->sg && gtt->gobj->import_attach) {
1383                 struct dma_buf_attachment *attach;
1384
1385                 attach = gtt->gobj->import_attach;
1386                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1387                 ttm->sg = NULL;
1388                 return;
1389         }
1390
1391         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1392                 return;
1393
1394         adev = amdgpu_ttm_adev(ttm->bdev);
1395
1396 #ifdef CONFIG_SWIOTLB
1397         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1398                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1399                 return;
1400         }
1401 #endif
1402
1403         /* fall back to generic helper to unmap and unpopulate array */
1404         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1405 }
1406
1407 /**
1408  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1409  * task
1410  *
1411  * @bo: The ttm_buffer_object to bind this userptr to
1412  * @addr:  The address in the current tasks VM space to use
1413  * @flags: Requirements of userptr object.
1414  *
1415  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1416  * to current task
1417  */
1418 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1419                               uint64_t addr, uint32_t flags)
1420 {
1421         struct amdgpu_ttm_tt *gtt;
1422
1423         if (!bo->ttm) {
1424                 /* TODO: We want a separate TTM object type for userptrs */
1425                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1426                 if (bo->ttm == NULL)
1427                         return -ENOMEM;
1428         }
1429
1430         gtt = (void*)bo->ttm;
1431         gtt->userptr = addr;
1432         gtt->userflags = flags;
1433
1434         if (gtt->usertask)
1435                 put_task_struct(gtt->usertask);
1436         gtt->usertask = current->group_leader;
1437         get_task_struct(gtt->usertask);
1438
1439         return 0;
1440 }
1441
1442 /**
1443  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1444  */
1445 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1446 {
1447         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1448
1449         if (gtt == NULL)
1450                 return NULL;
1451
1452         if (gtt->usertask == NULL)
1453                 return NULL;
1454
1455         return gtt->usertask->mm;
1456 }
1457
1458 /**
1459  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1460  * address range for the current task.
1461  *
1462  */
1463 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1464                                   unsigned long end)
1465 {
1466         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1467         unsigned long size;
1468
1469         if (gtt == NULL || !gtt->userptr)
1470                 return false;
1471
1472         /* Return false if no part of the ttm_tt object lies within
1473          * the range
1474          */
1475         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1476         if (gtt->userptr > end || gtt->userptr + size <= start)
1477                 return false;
1478
1479         return true;
1480 }
1481
1482 /**
1483  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1484  */
1485 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1486 {
1487         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1488
1489         if (gtt == NULL || !gtt->userptr)
1490                 return false;
1491
1492         return true;
1493 }
1494
1495 /**
1496  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1497  */
1498 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1499 {
1500         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1501
1502         if (gtt == NULL)
1503                 return false;
1504
1505         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1506 }
1507
1508 /**
1509  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1510  *
1511  * @ttm: The ttm_tt object to compute the flags for
1512  * @mem: The memory registry backing this ttm_tt object
1513  *
1514  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1515  */
1516 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1517 {
1518         uint64_t flags = 0;
1519
1520         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1521                 flags |= AMDGPU_PTE_VALID;
1522
1523         if (mem && mem->mem_type == TTM_PL_TT) {
1524                 flags |= AMDGPU_PTE_SYSTEM;
1525
1526                 if (ttm->caching_state == tt_cached)
1527                         flags |= AMDGPU_PTE_SNOOPED;
1528         }
1529
1530         return flags;
1531 }
1532
1533 /**
1534  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1535  *
1536  * @ttm: The ttm_tt object to compute the flags for
1537  * @mem: The memory registry backing this ttm_tt object
1538
1539  * Figure out the flags to use for a VM PTE (Page Table Entry).
1540  */
1541 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1542                                  struct ttm_resource *mem)
1543 {
1544         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1545
1546         flags |= adev->gart.gart_pte_flags;
1547         flags |= AMDGPU_PTE_READABLE;
1548
1549         if (!amdgpu_ttm_tt_is_readonly(ttm))
1550                 flags |= AMDGPU_PTE_WRITEABLE;
1551
1552         return flags;
1553 }
1554
1555 /**
1556  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1557  * object.
1558  *
1559  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1560  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1561  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1562  * used to clean out a memory space.
1563  */
1564 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1565                                             const struct ttm_place *place)
1566 {
1567         unsigned long num_pages = bo->mem.num_pages;
1568         struct drm_mm_node *node = bo->mem.mm_node;
1569         struct dma_resv_list *flist;
1570         struct dma_fence *f;
1571         int i;
1572
1573         if (bo->type == ttm_bo_type_kernel &&
1574             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1575                 return false;
1576
1577         /* If bo is a KFD BO, check if the bo belongs to the current process.
1578          * If true, then return false as any KFD process needs all its BOs to
1579          * be resident to run successfully
1580          */
1581         flist = dma_resv_get_list(bo->base.resv);
1582         if (flist) {
1583                 for (i = 0; i < flist->shared_count; ++i) {
1584                         f = rcu_dereference_protected(flist->shared[i],
1585                                 dma_resv_held(bo->base.resv));
1586                         if (amdkfd_fence_check_mm(f, current->mm))
1587                                 return false;
1588                 }
1589         }
1590
1591         switch (bo->mem.mem_type) {
1592         case TTM_PL_TT:
1593                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1594                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1595                         return false;
1596                 return true;
1597
1598         case TTM_PL_VRAM:
1599                 /* Check each drm MM node individually */
1600                 while (num_pages) {
1601                         if (place->fpfn < (node->start + node->size) &&
1602                             !(place->lpfn && place->lpfn <= node->start))
1603                                 return true;
1604
1605                         num_pages -= node->size;
1606                         ++node;
1607                 }
1608                 return false;
1609
1610         default:
1611                 break;
1612         }
1613
1614         return ttm_bo_eviction_valuable(bo, place);
1615 }
1616
1617 /**
1618  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1619  *
1620  * @bo:  The buffer object to read/write
1621  * @offset:  Offset into buffer object
1622  * @buf:  Secondary buffer to write/read from
1623  * @len: Length in bytes of access
1624  * @write:  true if writing
1625  *
1626  * This is used to access VRAM that backs a buffer object via MMIO
1627  * access for debugging purposes.
1628  */
1629 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1630                                     unsigned long offset,
1631                                     void *buf, int len, int write)
1632 {
1633         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1634         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1635         struct drm_mm_node *nodes;
1636         uint32_t value = 0;
1637         int ret = 0;
1638         uint64_t pos;
1639         unsigned long flags;
1640
1641         if (bo->mem.mem_type != TTM_PL_VRAM)
1642                 return -EIO;
1643
1644         pos = offset;
1645         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1646         pos += (nodes->start << PAGE_SHIFT);
1647
1648         while (len && pos < adev->gmc.mc_vram_size) {
1649                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1650                 uint64_t bytes = 4 - (pos & 3);
1651                 uint32_t shift = (pos & 3) * 8;
1652                 uint32_t mask = 0xffffffff << shift;
1653
1654                 if (len < bytes) {
1655                         mask &= 0xffffffff >> (bytes - len) * 8;
1656                         bytes = len;
1657                 }
1658
1659                 if (mask != 0xffffffff) {
1660                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1661                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1662                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1663                         if (!write || mask != 0xffffffff)
1664                                 value = RREG32_NO_KIQ(mmMM_DATA);
1665                         if (write) {
1666                                 value &= ~mask;
1667                                 value |= (*(uint32_t *)buf << shift) & mask;
1668                                 WREG32_NO_KIQ(mmMM_DATA, value);
1669                         }
1670                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1671                         if (!write) {
1672                                 value = (value & mask) >> shift;
1673                                 memcpy(buf, &value, bytes);
1674                         }
1675                 } else {
1676                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1677                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1678
1679                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1680                                                   bytes, write);
1681                 }
1682
1683                 ret += bytes;
1684                 buf = (uint8_t *)buf + bytes;
1685                 pos += bytes;
1686                 len -= bytes;
1687                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1688                         ++nodes;
1689                         pos = (nodes->start << PAGE_SHIFT);
1690                 }
1691         }
1692
1693         return ret;
1694 }
1695
1696 static struct ttm_bo_driver amdgpu_bo_driver = {
1697         .ttm_tt_create = &amdgpu_ttm_tt_create,
1698         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1699         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1700         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1701         .evict_flags = &amdgpu_evict_flags,
1702         .move = &amdgpu_bo_move,
1703         .verify_access = &amdgpu_verify_access,
1704         .move_notify = &amdgpu_bo_move_notify,
1705         .release_notify = &amdgpu_bo_release_notify,
1706         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1707         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1708         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1709         .access_memory = &amdgpu_ttm_access_memory,
1710         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1711 };
1712
1713 /*
1714  * Firmware Reservation functions
1715  */
1716 /**
1717  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1718  *
1719  * @adev: amdgpu_device pointer
1720  *
1721  * free fw reserved vram if it has been reserved.
1722  */
1723 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1724 {
1725         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1726                 NULL, &adev->mman.fw_vram_usage_va);
1727 }
1728
1729 /**
1730  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1731  *
1732  * @adev: amdgpu_device pointer
1733  *
1734  * create bo vram reservation from fw.
1735  */
1736 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1737 {
1738         uint64_t vram_size = adev->gmc.visible_vram_size;
1739
1740         adev->mman.fw_vram_usage_va = NULL;
1741         adev->mman.fw_vram_usage_reserved_bo = NULL;
1742
1743         if (adev->mman.fw_vram_usage_size == 0 ||
1744             adev->mman.fw_vram_usage_size > vram_size)
1745                 return 0;
1746
1747         return amdgpu_bo_create_kernel_at(adev,
1748                                           adev->mman.fw_vram_usage_start_offset,
1749                                           adev->mman.fw_vram_usage_size,
1750                                           AMDGPU_GEM_DOMAIN_VRAM,
1751                                           &adev->mman.fw_vram_usage_reserved_bo,
1752                                           &adev->mman.fw_vram_usage_va);
1753 }
1754
1755 /*
1756  * Memoy training reservation functions
1757  */
1758
1759 /**
1760  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1761  *
1762  * @adev: amdgpu_device pointer
1763  *
1764  * free memory training reserved vram if it has been reserved.
1765  */
1766 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1767 {
1768         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1769
1770         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1771         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1772         ctx->c2p_bo = NULL;
1773
1774         return 0;
1775 }
1776
1777 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1778 {
1779         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1780
1781         memset(ctx, 0, sizeof(*ctx));
1782
1783         ctx->c2p_train_data_offset =
1784                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1785         ctx->p2c_train_data_offset =
1786                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1787         ctx->train_data_size =
1788                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1789
1790         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1791                         ctx->train_data_size,
1792                         ctx->p2c_train_data_offset,
1793                         ctx->c2p_train_data_offset);
1794 }
1795
1796 /*
1797  * reserve TMR memory at the top of VRAM which holds
1798  * IP Discovery data and is protected by PSP.
1799  */
1800 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1801 {
1802         int ret;
1803         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1804         bool mem_train_support = false;
1805
1806         if (!amdgpu_sriov_vf(adev)) {
1807                 ret = amdgpu_mem_train_support(adev);
1808                 if (ret == 1)
1809                         mem_train_support = true;
1810                 else if (ret == -1)
1811                         return -EINVAL;
1812                 else
1813                         DRM_DEBUG("memory training does not support!\n");
1814         }
1815
1816         /*
1817          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1818          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1819          *
1820          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1821          * discovery data and G6 memory training data respectively
1822          */
1823         adev->mman.discovery_tmr_size =
1824                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1825         if (!adev->mman.discovery_tmr_size)
1826                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1827
1828         if (mem_train_support) {
1829                 /* reserve vram for mem train according to TMR location */
1830                 amdgpu_ttm_training_data_block_init(adev);
1831                 ret = amdgpu_bo_create_kernel_at(adev,
1832                                          ctx->c2p_train_data_offset,
1833                                          ctx->train_data_size,
1834                                          AMDGPU_GEM_DOMAIN_VRAM,
1835                                          &ctx->c2p_bo,
1836                                          NULL);
1837                 if (ret) {
1838                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1839                         amdgpu_ttm_training_reserve_vram_fini(adev);
1840                         return ret;
1841                 }
1842                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1843         }
1844
1845         ret = amdgpu_bo_create_kernel_at(adev,
1846                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1847                                 adev->mman.discovery_tmr_size,
1848                                 AMDGPU_GEM_DOMAIN_VRAM,
1849                                 &adev->mman.discovery_memory,
1850                                 NULL);
1851         if (ret) {
1852                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1853                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1854                 return ret;
1855         }
1856
1857         return 0;
1858 }
1859
1860 /**
1861  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1862  * gtt/vram related fields.
1863  *
1864  * This initializes all of the memory space pools that the TTM layer
1865  * will need such as the GTT space (system memory mapped to the device),
1866  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1867  * can be mapped per VMID.
1868  */
1869 int amdgpu_ttm_init(struct amdgpu_device *adev)
1870 {
1871         uint64_t gtt_size;
1872         int r;
1873         u64 vis_vram_limit;
1874
1875         mutex_init(&adev->mman.gtt_window_lock);
1876
1877         /* No others user of address space so set it to 0 */
1878         r = ttm_bo_device_init(&adev->mman.bdev,
1879                                &amdgpu_bo_driver,
1880                                adev_to_drm(adev)->anon_inode->i_mapping,
1881                                adev_to_drm(adev)->vma_offset_manager,
1882                                dma_addressing_limited(adev->dev));
1883         if (r) {
1884                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1885                 return r;
1886         }
1887         adev->mman.initialized = true;
1888
1889         /* We opt to avoid OOM on system pages allocations */
1890         adev->mman.bdev.no_retry = true;
1891
1892         /* Initialize VRAM pool with all of VRAM divided into pages */
1893         r = amdgpu_vram_mgr_init(adev);
1894         if (r) {
1895                 DRM_ERROR("Failed initializing VRAM heap.\n");
1896                 return r;
1897         }
1898
1899         /* Reduce size of CPU-visible VRAM if requested */
1900         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1901         if (amdgpu_vis_vram_limit > 0 &&
1902             vis_vram_limit <= adev->gmc.visible_vram_size)
1903                 adev->gmc.visible_vram_size = vis_vram_limit;
1904
1905         /* Change the size here instead of the init above so only lpfn is affected */
1906         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1907 #ifdef CONFIG_64BIT
1908         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1909                                                 adev->gmc.visible_vram_size);
1910 #endif
1911
1912         /*
1913          *The reserved vram for firmware must be pinned to the specified
1914          *place on the VRAM, so reserve it early.
1915          */
1916         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1917         if (r) {
1918                 return r;
1919         }
1920
1921         /*
1922          * only NAVI10 and onwards ASIC support for IP discovery.
1923          * If IP discovery enabled, a block of memory should be
1924          * reserved for IP discovey.
1925          */
1926         if (adev->mman.discovery_bin) {
1927                 r = amdgpu_ttm_reserve_tmr(adev);
1928                 if (r)
1929                         return r;
1930         }
1931
1932         /* allocate memory as required for VGA
1933          * This is used for VGA emulation and pre-OS scanout buffers to
1934          * avoid display artifacts while transitioning between pre-OS
1935          * and driver.  */
1936         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1937                                        AMDGPU_GEM_DOMAIN_VRAM,
1938                                        &adev->mman.stolen_vga_memory,
1939                                        NULL);
1940         if (r)
1941                 return r;
1942         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1943                                        adev->mman.stolen_extended_size,
1944                                        AMDGPU_GEM_DOMAIN_VRAM,
1945                                        &adev->mman.stolen_extended_memory,
1946                                        NULL);
1947         if (r)
1948                 return r;
1949
1950         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1951                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1952
1953         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1954          * or whatever the user passed on module init */
1955         if (amdgpu_gtt_size == -1) {
1956                 struct sysinfo si;
1957
1958                 si_meminfo(&si);
1959                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1960                                adev->gmc.mc_vram_size),
1961                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1962         }
1963         else
1964                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1965
1966         /* Initialize GTT memory pool */
1967         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1968         if (r) {
1969                 DRM_ERROR("Failed initializing GTT heap.\n");
1970                 return r;
1971         }
1972         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1973                  (unsigned)(gtt_size / (1024 * 1024)));
1974
1975         /* Initialize various on-chip memory pools */
1976         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1977         if (r) {
1978                 DRM_ERROR("Failed initializing GDS heap.\n");
1979                 return r;
1980         }
1981
1982         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1983         if (r) {
1984                 DRM_ERROR("Failed initializing gws heap.\n");
1985                 return r;
1986         }
1987
1988         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1989         if (r) {
1990                 DRM_ERROR("Failed initializing oa heap.\n");
1991                 return r;
1992         }
1993
1994         return 0;
1995 }
1996
1997 /**
1998  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1999  */
2000 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2001 {
2002         /* return the VGA stolen memory (if any) back to VRAM */
2003         if (!adev->mman.keep_stolen_vga_memory)
2004                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2005         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2006 }
2007
2008 /**
2009  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2010  */
2011 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2012 {
2013         if (!adev->mman.initialized)
2014                 return;
2015
2016         amdgpu_ttm_training_reserve_vram_fini(adev);
2017         /* return the stolen vga memory back to VRAM */
2018         if (adev->mman.keep_stolen_vga_memory)
2019                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2020         /* return the IP Discovery TMR memory back to VRAM */
2021         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2022         amdgpu_ttm_fw_reserve_vram_fini(adev);
2023
2024         if (adev->mman.aper_base_kaddr)
2025                 iounmap(adev->mman.aper_base_kaddr);
2026         adev->mman.aper_base_kaddr = NULL;
2027
2028         amdgpu_vram_mgr_fini(adev);
2029         amdgpu_gtt_mgr_fini(adev);
2030         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2031         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2032         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2033         ttm_bo_device_release(&adev->mman.bdev);
2034         adev->mman.initialized = false;
2035         DRM_INFO("amdgpu: ttm finalized\n");
2036 }
2037
2038 /**
2039  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2040  *
2041  * @adev: amdgpu_device pointer
2042  * @enable: true when we can use buffer functions.
2043  *
2044  * Enable/disable use of buffer functions during suspend/resume. This should
2045  * only be called at bootup or when userspace isn't running.
2046  */
2047 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2048 {
2049         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2050         uint64_t size;
2051         int r;
2052
2053         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2054             adev->mman.buffer_funcs_enabled == enable)
2055                 return;
2056
2057         if (enable) {
2058                 struct amdgpu_ring *ring;
2059                 struct drm_gpu_scheduler *sched;
2060
2061                 ring = adev->mman.buffer_funcs_ring;
2062                 sched = &ring->sched;
2063                 r = drm_sched_entity_init(&adev->mman.entity,
2064                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2065                                           1, NULL);
2066                 if (r) {
2067                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2068                                   r);
2069                         return;
2070                 }
2071         } else {
2072                 drm_sched_entity_destroy(&adev->mman.entity);
2073                 dma_fence_put(man->move);
2074                 man->move = NULL;
2075         }
2076
2077         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2078         if (enable)
2079                 size = adev->gmc.real_vram_size;
2080         else
2081                 size = adev->gmc.visible_vram_size;
2082         man->size = size >> PAGE_SHIFT;
2083         adev->mman.buffer_funcs_enabled = enable;
2084 }
2085
2086 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2087 {
2088         struct drm_file *file_priv = filp->private_data;
2089         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2090
2091         if (adev == NULL)
2092                 return -EINVAL;
2093
2094         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2095 }
2096
2097 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2098                        uint64_t dst_offset, uint32_t byte_count,
2099                        struct dma_resv *resv,
2100                        struct dma_fence **fence, bool direct_submit,
2101                        bool vm_needs_flush, bool tmz)
2102 {
2103         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2104                 AMDGPU_IB_POOL_DELAYED;
2105         struct amdgpu_device *adev = ring->adev;
2106         struct amdgpu_job *job;
2107
2108         uint32_t max_bytes;
2109         unsigned num_loops, num_dw;
2110         unsigned i;
2111         int r;
2112
2113         if (direct_submit && !ring->sched.ready) {
2114                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2115                 return -EINVAL;
2116         }
2117
2118         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2119         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2120         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2121
2122         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2123         if (r)
2124                 return r;
2125
2126         if (vm_needs_flush) {
2127                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2128                 job->vm_needs_flush = true;
2129         }
2130         if (resv) {
2131                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2132                                      AMDGPU_SYNC_ALWAYS,
2133                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2134                 if (r) {
2135                         DRM_ERROR("sync failed (%d).\n", r);
2136                         goto error_free;
2137                 }
2138         }
2139
2140         for (i = 0; i < num_loops; i++) {
2141                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2142
2143                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2144                                         dst_offset, cur_size_in_bytes, tmz);
2145
2146                 src_offset += cur_size_in_bytes;
2147                 dst_offset += cur_size_in_bytes;
2148                 byte_count -= cur_size_in_bytes;
2149         }
2150
2151         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2152         WARN_ON(job->ibs[0].length_dw > num_dw);
2153         if (direct_submit)
2154                 r = amdgpu_job_submit_direct(job, ring, fence);
2155         else
2156                 r = amdgpu_job_submit(job, &adev->mman.entity,
2157                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2158         if (r)
2159                 goto error_free;
2160
2161         return r;
2162
2163 error_free:
2164         amdgpu_job_free(job);
2165         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2166         return r;
2167 }
2168
2169 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2170                        uint32_t src_data,
2171                        struct dma_resv *resv,
2172                        struct dma_fence **fence)
2173 {
2174         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2175         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2176         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2177
2178         struct drm_mm_node *mm_node;
2179         unsigned long num_pages;
2180         unsigned int num_loops, num_dw;
2181
2182         struct amdgpu_job *job;
2183         int r;
2184
2185         if (!adev->mman.buffer_funcs_enabled) {
2186                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2187                 return -EINVAL;
2188         }
2189
2190         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2191                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2192                 if (r)
2193                         return r;
2194         }
2195
2196         num_pages = bo->tbo.num_pages;
2197         mm_node = bo->tbo.mem.mm_node;
2198         num_loops = 0;
2199         while (num_pages) {
2200                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2201
2202                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2203                 num_pages -= mm_node->size;
2204                 ++mm_node;
2205         }
2206         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2207
2208         /* for IB padding */
2209         num_dw += 64;
2210
2211         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2212                                      &job);
2213         if (r)
2214                 return r;
2215
2216         if (resv) {
2217                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2218                                      AMDGPU_SYNC_ALWAYS,
2219                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2220                 if (r) {
2221                         DRM_ERROR("sync failed (%d).\n", r);
2222                         goto error_free;
2223                 }
2224         }
2225
2226         num_pages = bo->tbo.num_pages;
2227         mm_node = bo->tbo.mem.mm_node;
2228
2229         while (num_pages) {
2230                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2231                 uint64_t dst_addr;
2232
2233                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2234                 while (byte_count) {
2235                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2236                                                            max_bytes);
2237
2238                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2239                                                 dst_addr, cur_size_in_bytes);
2240
2241                         dst_addr += cur_size_in_bytes;
2242                         byte_count -= cur_size_in_bytes;
2243                 }
2244
2245                 num_pages -= mm_node->size;
2246                 ++mm_node;
2247         }
2248
2249         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2250         WARN_ON(job->ibs[0].length_dw > num_dw);
2251         r = amdgpu_job_submit(job, &adev->mman.entity,
2252                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2253         if (r)
2254                 goto error_free;
2255
2256         return 0;
2257
2258 error_free:
2259         amdgpu_job_free(job);
2260         return r;
2261 }
2262
2263 #if defined(CONFIG_DEBUG_FS)
2264
2265 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2266 {
2267         struct drm_info_node *node = (struct drm_info_node *)m->private;
2268         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2269         struct drm_device *dev = node->minor->dev;
2270         struct amdgpu_device *adev = drm_to_adev(dev);
2271         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2272         struct drm_printer p = drm_seq_file_printer(m);
2273
2274         man->func->debug(man, &p);
2275         return 0;
2276 }
2277
2278 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2279         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2280         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2281         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2282         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2283         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2284         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2285 #ifdef CONFIG_SWIOTLB
2286         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2287 #endif
2288 };
2289
2290 /**
2291  * amdgpu_ttm_vram_read - Linear read access to VRAM
2292  *
2293  * Accesses VRAM via MMIO for debugging purposes.
2294  */
2295 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2296                                     size_t size, loff_t *pos)
2297 {
2298         struct amdgpu_device *adev = file_inode(f)->i_private;
2299         ssize_t result = 0;
2300
2301         if (size & 0x3 || *pos & 0x3)
2302                 return -EINVAL;
2303
2304         if (*pos >= adev->gmc.mc_vram_size)
2305                 return -ENXIO;
2306
2307         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2308         while (size) {
2309                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2310                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2311
2312                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2313                 if (copy_to_user(buf, value, bytes))
2314                         return -EFAULT;
2315
2316                 result += bytes;
2317                 buf += bytes;
2318                 *pos += bytes;
2319                 size -= bytes;
2320         }
2321
2322         return result;
2323 }
2324
2325 /**
2326  * amdgpu_ttm_vram_write - Linear write access to VRAM
2327  *
2328  * Accesses VRAM via MMIO for debugging purposes.
2329  */
2330 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2331                                     size_t size, loff_t *pos)
2332 {
2333         struct amdgpu_device *adev = file_inode(f)->i_private;
2334         ssize_t result = 0;
2335         int r;
2336
2337         if (size & 0x3 || *pos & 0x3)
2338                 return -EINVAL;
2339
2340         if (*pos >= adev->gmc.mc_vram_size)
2341                 return -ENXIO;
2342
2343         while (size) {
2344                 unsigned long flags;
2345                 uint32_t value;
2346
2347                 if (*pos >= adev->gmc.mc_vram_size)
2348                         return result;
2349
2350                 r = get_user(value, (uint32_t *)buf);
2351                 if (r)
2352                         return r;
2353
2354                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2355                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2356                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2357                 WREG32_NO_KIQ(mmMM_DATA, value);
2358                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2359
2360                 result += 4;
2361                 buf += 4;
2362                 *pos += 4;
2363                 size -= 4;
2364         }
2365
2366         return result;
2367 }
2368
2369 static const struct file_operations amdgpu_ttm_vram_fops = {
2370         .owner = THIS_MODULE,
2371         .read = amdgpu_ttm_vram_read,
2372         .write = amdgpu_ttm_vram_write,
2373         .llseek = default_llseek,
2374 };
2375
2376 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2377
2378 /**
2379  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2380  */
2381 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2382                                    size_t size, loff_t *pos)
2383 {
2384         struct amdgpu_device *adev = file_inode(f)->i_private;
2385         ssize_t result = 0;
2386         int r;
2387
2388         while (size) {
2389                 loff_t p = *pos / PAGE_SIZE;
2390                 unsigned off = *pos & ~PAGE_MASK;
2391                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2392                 struct page *page;
2393                 void *ptr;
2394
2395                 if (p >= adev->gart.num_cpu_pages)
2396                         return result;
2397
2398                 page = adev->gart.pages[p];
2399                 if (page) {
2400                         ptr = kmap(page);
2401                         ptr += off;
2402
2403                         r = copy_to_user(buf, ptr, cur_size);
2404                         kunmap(adev->gart.pages[p]);
2405                 } else
2406                         r = clear_user(buf, cur_size);
2407
2408                 if (r)
2409                         return -EFAULT;
2410
2411                 result += cur_size;
2412                 buf += cur_size;
2413                 *pos += cur_size;
2414                 size -= cur_size;
2415         }
2416
2417         return result;
2418 }
2419
2420 static const struct file_operations amdgpu_ttm_gtt_fops = {
2421         .owner = THIS_MODULE,
2422         .read = amdgpu_ttm_gtt_read,
2423         .llseek = default_llseek
2424 };
2425
2426 #endif
2427
2428 /**
2429  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2430  *
2431  * This function is used to read memory that has been mapped to the
2432  * GPU and the known addresses are not physical addresses but instead
2433  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2434  */
2435 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2436                                  size_t size, loff_t *pos)
2437 {
2438         struct amdgpu_device *adev = file_inode(f)->i_private;
2439         struct iommu_domain *dom;
2440         ssize_t result = 0;
2441         int r;
2442
2443         /* retrieve the IOMMU domain if any for this device */
2444         dom = iommu_get_domain_for_dev(adev->dev);
2445
2446         while (size) {
2447                 phys_addr_t addr = *pos & PAGE_MASK;
2448                 loff_t off = *pos & ~PAGE_MASK;
2449                 size_t bytes = PAGE_SIZE - off;
2450                 unsigned long pfn;
2451                 struct page *p;
2452                 void *ptr;
2453
2454                 bytes = bytes < size ? bytes : size;
2455
2456                 /* Translate the bus address to a physical address.  If
2457                  * the domain is NULL it means there is no IOMMU active
2458                  * and the address translation is the identity
2459                  */
2460                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2461
2462                 pfn = addr >> PAGE_SHIFT;
2463                 if (!pfn_valid(pfn))
2464                         return -EPERM;
2465
2466                 p = pfn_to_page(pfn);
2467                 if (p->mapping != adev->mman.bdev.dev_mapping)
2468                         return -EPERM;
2469
2470                 ptr = kmap(p);
2471                 r = copy_to_user(buf, ptr + off, bytes);
2472                 kunmap(p);
2473                 if (r)
2474                         return -EFAULT;
2475
2476                 size -= bytes;
2477                 *pos += bytes;
2478                 result += bytes;
2479         }
2480
2481         return result;
2482 }
2483
2484 /**
2485  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2486  *
2487  * This function is used to write memory that has been mapped to the
2488  * GPU and the known addresses are not physical addresses but instead
2489  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2490  */
2491 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2492                                  size_t size, loff_t *pos)
2493 {
2494         struct amdgpu_device *adev = file_inode(f)->i_private;
2495         struct iommu_domain *dom;
2496         ssize_t result = 0;
2497         int r;
2498
2499         dom = iommu_get_domain_for_dev(adev->dev);
2500
2501         while (size) {
2502                 phys_addr_t addr = *pos & PAGE_MASK;
2503                 loff_t off = *pos & ~PAGE_MASK;
2504                 size_t bytes = PAGE_SIZE - off;
2505                 unsigned long pfn;
2506                 struct page *p;
2507                 void *ptr;
2508
2509                 bytes = bytes < size ? bytes : size;
2510
2511                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2512
2513                 pfn = addr >> PAGE_SHIFT;
2514                 if (!pfn_valid(pfn))
2515                         return -EPERM;
2516
2517                 p = pfn_to_page(pfn);
2518                 if (p->mapping != adev->mman.bdev.dev_mapping)
2519                         return -EPERM;
2520
2521                 ptr = kmap(p);
2522                 r = copy_from_user(ptr + off, buf, bytes);
2523                 kunmap(p);
2524                 if (r)
2525                         return -EFAULT;
2526
2527                 size -= bytes;
2528                 *pos += bytes;
2529                 result += bytes;
2530         }
2531
2532         return result;
2533 }
2534
2535 static const struct file_operations amdgpu_ttm_iomem_fops = {
2536         .owner = THIS_MODULE,
2537         .read = amdgpu_iomem_read,
2538         .write = amdgpu_iomem_write,
2539         .llseek = default_llseek
2540 };
2541
2542 static const struct {
2543         char *name;
2544         const struct file_operations *fops;
2545         int domain;
2546 } ttm_debugfs_entries[] = {
2547         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2548 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2549         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2550 #endif
2551         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2552 };
2553
2554 #endif
2555
2556 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2557 {
2558 #if defined(CONFIG_DEBUG_FS)
2559         unsigned count;
2560
2561         struct drm_minor *minor = adev_to_drm(adev)->primary;
2562         struct dentry *ent, *root = minor->debugfs_root;
2563
2564         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2565                 ent = debugfs_create_file(
2566                                 ttm_debugfs_entries[count].name,
2567                                 S_IFREG | S_IRUGO, root,
2568                                 adev,
2569                                 ttm_debugfs_entries[count].fops);
2570                 if (IS_ERR(ent))
2571                         return PTR_ERR(ent);
2572                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2573                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2574                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2575                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2576                 adev->mman.debugfs_entries[count] = ent;
2577         }
2578
2579         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2580
2581 #ifdef CONFIG_SWIOTLB
2582         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2583                 --count;
2584 #endif
2585
2586         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2587 #else
2588         return 0;
2589 #endif
2590 }