drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <[email protected]>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  45                              int usecs)
  46 {
  47         /* paranoia */
  48         if (!adjusted_mode->crtc_htotal)
  49                 return 1;
  50
  51         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  52                             1000 * adjusted_mode->crtc_htotal);
  53 }
  54
  55 /* FIXME: We should instead only take spinlocks once for the entire update
  56  * instead of once per mmio. */
  57 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  58 #define VBLANK_EVASION_TIME_US 250
  59 #else
  60 #define VBLANK_EVASION_TIME_US 100
  61 #endif
  62
  63 /**
  64  * intel_pipe_update_start() - start update of a set of display registers
  65  * @new_crtc_state: the new crtc state
  66  *
  67  * Mark the start of an update to pipe registers that should be updated
  68  * atomically regarding vblank. If the next vblank will happens within
  69  * the next 100 us, this function waits until the vblank passes.
  70  *
  71  * After a successful call to this function, interrupts will be disabled
  72  * until a subsequent call to intel_pipe_update_end(). That is done to
  73  * avoid random delays.
  74  */
  75 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  76 {
  77         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  78         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  79         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  80         long timeout = msecs_to_jiffies_timeout(1);
  81         int scanline, min, max, vblank_start;
  82         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  83         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  84                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  85         DEFINE_WAIT(wait);
  86         u32 psr_status;
  87
  88         vblank_start = adjusted_mode->crtc_vblank_start;
  89         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  90                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  91
  92         /* FIXME needs to be calibrated sensibly */
  93         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
  94                                                       VBLANK_EVASION_TIME_US);
  95         max = vblank_start - 1;
  96
  97         if (min <= 0 || max <= 0)
  98                 goto irq_disable;
  99
 100         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 101                 goto irq_disable;
 102
 103         /*
 104          * Wait for psr to idle out after enabling the VBL interrupts
 105          * VBL interrupts will start the PSR exit and prevent a PSR
 106          * re-entry as well.
 107          */
 108         if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
 109                 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
 110                           psr_status);
 111
 112         local_irq_disable();
 113
 114         crtc->debug.min_vbl = min;
 115         crtc->debug.max_vbl = max;
 116         trace_i915_pipe_update_start(crtc);
 117
 118         for (;;) {
 119                 /*
 120                  * prepare_to_wait() has a memory barrier, which guarantees
 121                  * other CPUs can see the task state update by the time we
 122                  * read the scanline.
 123                  */
 124                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 125
 126                 scanline = intel_get_crtc_scanline(crtc);
 127                 if (scanline < min || scanline > max)
 128                         break;
 129
 130                 if (!timeout) {
 131                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 132                                   pipe_name(crtc->pipe));
 133                         break;
 134                 }
 135
 136                 local_irq_enable();
 137
 138                 timeout = schedule_timeout(timeout);
 139
 140                 local_irq_disable();
 141         }
 142
 143         finish_wait(wq, &wait);
 144
 145         drm_crtc_vblank_put(&crtc->base);
 146
 147         /*
 148          * On VLV/CHV DSI the scanline counter would appear to
 149          * increment approx. 1/3 of a scanline before start of vblank.
 150          * The registers still get latched at start of vblank however.
 151          * This means we must not write any registers on the first
 152          * line of vblank (since not the whole line is actually in
 153          * vblank). And unfortunately we can't use the interrupt to
 154          * wait here since it will fire too soon. We could use the
 155          * frame start interrupt instead since it will fire after the
 156          * critical scanline, but that would require more changes
 157          * in the interrupt code. So for now we'll just do the nasty
 158          * thing and poll for the bad scanline to pass us by.
 159          *
 160          * FIXME figure out if BXT+ DSI suffers from this as well
 161          */
 162         while (need_vlv_dsi_wa && scanline == vblank_start)
 163                 scanline = intel_get_crtc_scanline(crtc);
 164
 165         crtc->debug.scanline_start = scanline;
 166         crtc->debug.start_vbl_time = ktime_get();
 167         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 168
 169         trace_i915_pipe_update_vblank_evaded(crtc);
 170         return;
 171
 172 irq_disable:
 173         local_irq_disable();
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 234 {
 235         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 236         const struct drm_framebuffer *fb = plane_state->base.fb;
 237         unsigned int rotation = plane_state->base.rotation;
 238         u32 stride, max_stride;
 239
 240         /* FIXME other color planes? */
 241         stride = plane_state->color_plane[0].stride;
 242         max_stride = plane->max_stride(plane, fb->format->format,
 243                                        fb->modifier, rotation);
 244
 245         if (stride > max_stride) {
 246                 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
 247                               fb->base.id, stride,
 248                               plane->base.base.id, plane->base.name, max_stride);
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254
 255 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 256 {
 257         const struct drm_framebuffer *fb = plane_state->base.fb;
 258         struct drm_rect *src = &plane_state->base.src;
 259         u32 src_x, src_y, src_w, src_h;
 260
 261         /*
 262          * Hardware doesn't handle subpixel coordinates.
 263          * Adjust to (macro)pixel boundary, but be careful not to
 264          * increase the source viewport size, because that could
 265          * push the downscaling factor out of bounds.
 266          */
 267         src_x = src->x1 >> 16;
 268         src_w = drm_rect_width(src) >> 16;
 269         src_y = src->y1 >> 16;
 270         src_h = drm_rect_height(src) >> 16;
 271
 272         src->x1 = src_x << 16;
 273         src->x2 = (src_x + src_w) << 16;
 274         src->y1 = src_y << 16;
 275         src->y2 = (src_y + src_h) << 16;
 276
 277         if (fb->format->is_yuv &&
 278             (src_x & 1 || src_w & 1)) {
 279                 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
 280                               src_x, src_w);
 281                 return -EINVAL;
 282         }
 283
 284         if (fb->format->is_yuv &&
 285             fb->format->num_planes > 1 &&
 286             (src_y & 1 || src_h & 1)) {
 287                 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of 2 for planar YUV planes\n",
 288                               src_y, src_h);
 289                 return -EINVAL;
 290         }
 291
 292         return 0;
 293 }
 294
 295 unsigned int
 296 skl_plane_max_stride(struct intel_plane *plane,
 297                      u32 pixel_format, u64 modifier,
 298                      unsigned int rotation)
 299 {
 300         int cpp = drm_format_plane_cpp(pixel_format, 0);
 301
 302         /*
 303          * "The stride in bytes must not exceed the
 304          * of the size of 8K pixels and 32K bytes."
 305          */
 306         if (drm_rotation_90_or_270(rotation))
 307                 return min(8192, 32768 / cpp);
 308         else
 309                 return min(8192 * cpp, 32768);
 310 }
 311
 312 static void
 313 skl_program_scaler(struct drm_i915_private *dev_priv,
 314                    struct intel_plane *plane,
 315                    const struct intel_crtc_state *crtc_state,
 316                    const struct intel_plane_state *plane_state)
 317 {
 318         enum plane_id plane_id = plane->id;
 319         enum pipe pipe = plane->pipe;
 320         int scaler_id = plane_state->scaler_id;
 321         const struct intel_scaler *scaler =
 322                 &crtc_state->scaler_state.scalers[scaler_id];
 323         int crtc_x = plane_state->base.dst.x1;
 324         int crtc_y = plane_state->base.dst.y1;
 325         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 326         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 327         u16 y_hphase, uv_rgb_hphase;
 328         u16 y_vphase, uv_rgb_vphase;
 329
 330         /* Sizes are 0 based */
 331         crtc_w--;
 332         crtc_h--;
 333
 334         /* TODO: handle sub-pixel coordinates */
 335         if (plane_state->base.fb->format->format == DRM_FORMAT_NV12) {
 336                 y_hphase = skl_scaler_calc_phase(1, false);
 337                 y_vphase = skl_scaler_calc_phase(1, false);
 338
 339                 /* MPEG2 chroma siting convention */
 340                 uv_rgb_hphase = skl_scaler_calc_phase(2, true);
 341                 uv_rgb_vphase = skl_scaler_calc_phase(2, false);
 342         } else {
 343                 /* not used */
 344                 y_hphase = 0;
 345                 y_vphase = 0;
 346
 347                 uv_rgb_hphase = skl_scaler_calc_phase(1, false);
 348                 uv_rgb_vphase = skl_scaler_calc_phase(1, false);
 349         }
 350
 351         I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 352                       PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 353         I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 354         I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
 355                       PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 356         I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
 357                       PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 358         I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 359         I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 360                       ((crtc_w + 1) << 16)|(crtc_h + 1));
 361 }
 362
 363 void
 364 skl_update_plane(struct intel_plane *plane,
 365                  const struct intel_crtc_state *crtc_state,
 366                  const struct intel_plane_state *plane_state)
 367 {
 368         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 369         enum plane_id plane_id = plane->id;
 370         enum pipe pipe = plane->pipe;
 371         u32 plane_ctl = plane_state->ctl;
 372         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 373         u32 surf_addr = plane_state->color_plane[0].offset;
 374         u32 stride = skl_plane_stride(plane_state, 0);
 375         u32 aux_stride = skl_plane_stride(plane_state, 1);
 376         int crtc_x = plane_state->base.dst.x1;
 377         int crtc_y = plane_state->base.dst.y1;
 378         uint32_t x = plane_state->color_plane[0].x;
 379         uint32_t y = plane_state->color_plane[0].y;
 380         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 381         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 382         unsigned long irqflags;
 383
 384         /* Sizes are 0 based */
 385         src_w--;
 386         src_h--;
 387
 388         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 389
 390         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 391                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 392                               plane_state->color_ctl);
 393
 394         if (key->flags) {
 395                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 396                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 397                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 398         }
 399
 400         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 401         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 402         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 403         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 404                       (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 405         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 406                       (plane_state->color_plane[1].y << 16) |
 407                       plane_state->color_plane[1].x);
 408
 409         /* program plane scaler */
 410         if (plane_state->scaler_id >= 0) {
 411                 skl_program_scaler(dev_priv, plane, crtc_state, plane_state);
 412
 413                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 414         } else {
 415                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 416         }
 417
 418         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 419         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 420                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 421         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 422
 423         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 424 }
 425
 426 void
 427 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 428 {
 429         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 430         enum plane_id plane_id = plane->id;
 431         enum pipe pipe = plane->pipe;
 432         unsigned long irqflags;
 433
 434         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 435
 436         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 437
 438         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 439         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 440
 441         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 442 }
 443
 444 bool
 445 skl_plane_get_hw_state(struct intel_plane *plane,
 446                        enum pipe *pipe)
 447 {
 448         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 449         enum intel_display_power_domain power_domain;
 450         enum plane_id plane_id = plane->id;
 451         bool ret;
 452
 453         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 454         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 455                 return false;
 456
 457         ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 458
 459         *pipe = plane->pipe;
 460
 461         intel_display_power_put(dev_priv, power_domain);
 462
 463         return ret;
 464 }
 465
 466 static void
 467 chv_update_csc(const struct intel_plane_state *plane_state)
 468 {
 469         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 470         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 471         const struct drm_framebuffer *fb = plane_state->base.fb;
 472         enum plane_id plane_id = plane->id;
 473         /*
 474          * |r|   | c0 c1 c2 |   |cr|
 475          * |g| = | c3 c4 c5 | x |y |
 476          * |b|   | c6 c7 c8 |   |cb|
 477          *
 478          * Coefficients are s3.12.
 479          *
 480          * Cb and Cr apparently come in as signed already, and
 481          * we always get full range data in on account of CLRC0/1.
 482          */
 483         static const s16 csc_matrix[][9] = {
 484                 /* BT.601 full range YCbCr -> full range RGB */
 485                 [DRM_COLOR_YCBCR_BT601] = {
 486                          5743, 4096,     0,
 487                         -2925, 4096, -1410,
 488                             0, 4096,  7258,
 489                 },
 490                 /* BT.709 full range YCbCr -> full range RGB */
 491                 [DRM_COLOR_YCBCR_BT709] = {
 492                          6450, 4096,     0,
 493                         -1917, 4096,  -767,
 494                             0, 4096,  7601,
 495                 },
 496         };
 497         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
 498
 499         /* Seems RGB data bypasses the CSC always */
 500         if (!fb->format->is_yuv)
 501                 return;
 502
 503         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 504         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 505         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 506
 507         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 508         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 509         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 510         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 511         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 512
 513         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 514         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 515         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 516
 517         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 518         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 519         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 520 }
 521
 522 #define SIN_0 0
 523 #define COS_0 1
 524
 525 static void
 526 vlv_update_clrc(const struct intel_plane_state *plane_state)
 527 {
 528         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 529         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 530         const struct drm_framebuffer *fb = plane_state->base.fb;
 531         enum pipe pipe = plane->pipe;
 532         enum plane_id plane_id = plane->id;
 533         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 534
 535         if (fb->format->is_yuv &&
 536             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 537                 /*
 538                  * Expand limited range to full range:
 539                  * Contrast is applied first and is used to expand Y range.
 540                  * Brightness is applied second and is used to remove the
 541                  * offset from Y. Saturation/hue is used to expand CbCr range.
 542                  */
 543                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 544                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 545                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 546                 sh_sin = SIN_0 * sh_scale;
 547                 sh_cos = COS_0 * sh_scale;
 548         } else {
 549                 /* Pass-through everything. */
 550                 contrast = 1 << 6;
 551                 brightness = 0;
 552                 sh_scale = 1 << 7;
 553                 sh_sin = SIN_0 * sh_scale;
 554                 sh_cos = COS_0 * sh_scale;
 555         }
 556
 557         /* FIXME these register are single buffered :( */
 558         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 559                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 560         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 561                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 562 }
 563
 564 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 565                           const struct intel_plane_state *plane_state)
 566 {
 567         const struct drm_framebuffer *fb = plane_state->base.fb;
 568         unsigned int rotation = plane_state->base.rotation;
 569         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 570         u32 sprctl;
 571
 572         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 573
 574         switch (fb->format->format) {
 575         case DRM_FORMAT_YUYV:
 576                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 577                 break;
 578         case DRM_FORMAT_YVYU:
 579                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 580                 break;
 581         case DRM_FORMAT_UYVY:
 582                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 583                 break;
 584         case DRM_FORMAT_VYUY:
 585                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 586                 break;
 587         case DRM_FORMAT_RGB565:
 588                 sprctl |= SP_FORMAT_BGR565;
 589                 break;
 590         case DRM_FORMAT_XRGB8888:
 591                 sprctl |= SP_FORMAT_BGRX8888;
 592                 break;
 593         case DRM_FORMAT_ARGB8888:
 594                 sprctl |= SP_FORMAT_BGRA8888;
 595                 break;
 596         case DRM_FORMAT_XBGR2101010:
 597                 sprctl |= SP_FORMAT_RGBX1010102;
 598                 break;
 599         case DRM_FORMAT_ABGR2101010:
 600                 sprctl |= SP_FORMAT_RGBA1010102;
 601                 break;
 602         case DRM_FORMAT_XBGR8888:
 603                 sprctl |= SP_FORMAT_RGBX8888;
 604                 break;
 605         case DRM_FORMAT_ABGR8888:
 606                 sprctl |= SP_FORMAT_RGBA8888;
 607                 break;
 608         default:
 609                 MISSING_CASE(fb->format->format);
 610                 return 0;
 611         }
 612
 613         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 614                 sprctl |= SP_YUV_FORMAT_BT709;
 615
 616         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 617                 sprctl |= SP_TILED;
 618
 619         if (rotation & DRM_MODE_ROTATE_180)
 620                 sprctl |= SP_ROTATE_180;
 621
 622         if (rotation & DRM_MODE_REFLECT_X)
 623                 sprctl |= SP_MIRROR;
 624
 625         if (key->flags & I915_SET_COLORKEY_SOURCE)
 626                 sprctl |= SP_SOURCE_KEY;
 627
 628         return sprctl;
 629 }
 630
 631 static void
 632 vlv_update_plane(struct intel_plane *plane,
 633                  const struct intel_crtc_state *crtc_state,
 634                  const struct intel_plane_state *plane_state)
 635 {
 636         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 637         const struct drm_framebuffer *fb = plane_state->base.fb;
 638         enum pipe pipe = plane->pipe;
 639         enum plane_id plane_id = plane->id;
 640         u32 sprctl = plane_state->ctl;
 641         u32 sprsurf_offset = plane_state->color_plane[0].offset;
 642         u32 linear_offset;
 643         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 644         int crtc_x = plane_state->base.dst.x1;
 645         int crtc_y = plane_state->base.dst.y1;
 646         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 647         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 648         uint32_t x = plane_state->color_plane[0].x;
 649         uint32_t y = plane_state->color_plane[0].y;
 650         unsigned long irqflags;
 651
 652         /* Sizes are 0 based */
 653         crtc_w--;
 654         crtc_h--;
 655
 656         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 657
 658         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 659
 660         vlv_update_clrc(plane_state);
 661
 662         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 663                 chv_update_csc(plane_state);
 664
 665         if (key->flags) {
 666                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 667                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 668                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 669         }
 670         I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
 671                       plane_state->color_plane[0].stride);
 672         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 673
 674         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 675                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 676         else
 677                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 678
 679         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 680
 681         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 682         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 683         I915_WRITE_FW(SPSURF(pipe, plane_id),
 684                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 685         POSTING_READ_FW(SPSURF(pipe, plane_id));
 686
 687         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 688 }
 689
 690 static void
 691 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 692 {
 693         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 694         enum pipe pipe = plane->pipe;
 695         enum plane_id plane_id = plane->id;
 696         unsigned long irqflags;
 697
 698         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 699
 700         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 701
 702         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 703         POSTING_READ_FW(SPSURF(pipe, plane_id));
 704
 705         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 706 }
 707
 708 static bool
 709 vlv_plane_get_hw_state(struct intel_plane *plane,
 710                        enum pipe *pipe)
 711 {
 712         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 713         enum intel_display_power_domain power_domain;
 714         enum plane_id plane_id = plane->id;
 715         bool ret;
 716
 717         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 718         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 719                 return false;
 720
 721         ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
 722
 723         *pipe = plane->pipe;
 724
 725         intel_display_power_put(dev_priv, power_domain);
 726
 727         return ret;
 728 }
 729
 730 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 731                           const struct intel_plane_state *plane_state)
 732 {
 733         struct drm_i915_private *dev_priv =
 734                 to_i915(plane_state->base.plane->dev);
 735         const struct drm_framebuffer *fb = plane_state->base.fb;
 736         unsigned int rotation = plane_state->base.rotation;
 737         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 738         u32 sprctl;
 739
 740         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 741
 742         if (IS_IVYBRIDGE(dev_priv))
 743                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 744
 745         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 746                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 747
 748         switch (fb->format->format) {
 749         case DRM_FORMAT_XBGR8888:
 750                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 751                 break;
 752         case DRM_FORMAT_XRGB8888:
 753                 sprctl |= SPRITE_FORMAT_RGBX888;
 754                 break;
 755         case DRM_FORMAT_YUYV:
 756                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 757                 break;
 758         case DRM_FORMAT_YVYU:
 759                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 760                 break;
 761         case DRM_FORMAT_UYVY:
 762                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 763                 break;
 764         case DRM_FORMAT_VYUY:
 765                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 766                 break;
 767         default:
 768                 MISSING_CASE(fb->format->format);
 769                 return 0;
 770         }
 771
 772         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 773                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 774
 775         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 776                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 777
 778         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 779                 sprctl |= SPRITE_TILED;
 780
 781         if (rotation & DRM_MODE_ROTATE_180)
 782                 sprctl |= SPRITE_ROTATE_180;
 783
 784         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 785                 sprctl |= SPRITE_DEST_KEY;
 786         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 787                 sprctl |= SPRITE_SOURCE_KEY;
 788
 789         return sprctl;
 790 }
 791
 792 static void
 793 ivb_update_plane(struct intel_plane *plane,
 794                  const struct intel_crtc_state *crtc_state,
 795                  const struct intel_plane_state *plane_state)
 796 {
 797         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 798         const struct drm_framebuffer *fb = plane_state->base.fb;
 799         enum pipe pipe = plane->pipe;
 800         u32 sprctl = plane_state->ctl, sprscale = 0;
 801         u32 sprsurf_offset = plane_state->color_plane[0].offset;
 802         u32 linear_offset;
 803         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 804         int crtc_x = plane_state->base.dst.x1;
 805         int crtc_y = plane_state->base.dst.y1;
 806         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 807         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 808         uint32_t x = plane_state->color_plane[0].x;
 809         uint32_t y = plane_state->color_plane[0].y;
 810         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 811         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 812         unsigned long irqflags;
 813
 814         /* Sizes are 0 based */
 815         src_w--;
 816         src_h--;
 817         crtc_w--;
 818         crtc_h--;
 819
 820         if (crtc_w != src_w || crtc_h != src_h)
 821                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 822
 823         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 824
 825         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 826
 827         if (key->flags) {
 828                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 829                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 830                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 831         }
 832
 833         I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
 834         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 835
 836         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 837          * register */
 838         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 839                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 840         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 841                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 842         else
 843                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 844
 845         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 846         if (IS_IVYBRIDGE(dev_priv))
 847                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 848         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 849         I915_WRITE_FW(SPRSURF(pipe),
 850                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 851         POSTING_READ_FW(SPRSURF(pipe));
 852
 853         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 854 }
 855
 856 static void
 857 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 858 {
 859         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 860         enum pipe pipe = plane->pipe;
 861         unsigned long irqflags;
 862
 863         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 864
 865         I915_WRITE_FW(SPRCTL(pipe), 0);
 866         /* Can't leave the scaler enabled... */
 867         if (IS_IVYBRIDGE(dev_priv))
 868                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 869
 870         I915_WRITE_FW(SPRSURF(pipe), 0);
 871         POSTING_READ_FW(SPRSURF(pipe));
 872
 873         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 874 }
 875
 876 static bool
 877 ivb_plane_get_hw_state(struct intel_plane *plane,
 878                        enum pipe *pipe)
 879 {
 880         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 881         enum intel_display_power_domain power_domain;
 882         bool ret;
 883
 884         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 885         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 886                 return false;
 887
 888         ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
 889
 890         *pipe = plane->pipe;
 891
 892         intel_display_power_put(dev_priv, power_domain);
 893
 894         return ret;
 895 }
 896
 897 static unsigned int
 898 g4x_sprite_max_stride(struct intel_plane *plane,
 899                       u32 pixel_format, u64 modifier,
 900                       unsigned int rotation)
 901 {
 902         return 16384;
 903 }
 904
 905 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 906                           const struct intel_plane_state *plane_state)
 907 {
 908         struct drm_i915_private *dev_priv =
 909                 to_i915(plane_state->base.plane->dev);
 910         const struct drm_framebuffer *fb = plane_state->base.fb;
 911         unsigned int rotation = plane_state->base.rotation;
 912         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 913         u32 dvscntr;
 914
 915         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 916
 917         if (IS_GEN6(dev_priv))
 918                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 919
 920         switch (fb->format->format) {
 921         case DRM_FORMAT_XBGR8888:
 922                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 923                 break;
 924         case DRM_FORMAT_XRGB8888:
 925                 dvscntr |= DVS_FORMAT_RGBX888;
 926                 break;
 927         case DRM_FORMAT_YUYV:
 928                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 929                 break;
 930         case DRM_FORMAT_YVYU:
 931                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 932                 break;
 933         case DRM_FORMAT_UYVY:
 934                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 935                 break;
 936         case DRM_FORMAT_VYUY:
 937                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 938                 break;
 939         default:
 940                 MISSING_CASE(fb->format->format);
 941                 return 0;
 942         }
 943
 944         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 945                 dvscntr |= DVS_YUV_FORMAT_BT709;
 946
 947         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 948                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 949
 950         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 951                 dvscntr |= DVS_TILED;
 952
 953         if (rotation & DRM_MODE_ROTATE_180)
 954                 dvscntr |= DVS_ROTATE_180;
 955
 956         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 957                 dvscntr |= DVS_DEST_KEY;
 958         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 959                 dvscntr |= DVS_SOURCE_KEY;
 960
 961         return dvscntr;
 962 }
 963
 964 static void
 965 g4x_update_plane(struct intel_plane *plane,
 966                  const struct intel_crtc_state *crtc_state,
 967                  const struct intel_plane_state *plane_state)
 968 {
 969         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 970         const struct drm_framebuffer *fb = plane_state->base.fb;
 971         enum pipe pipe = plane->pipe;
 972         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 973         u32 dvssurf_offset = plane_state->color_plane[0].offset;
 974         u32 linear_offset;
 975         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 976         int crtc_x = plane_state->base.dst.x1;
 977         int crtc_y = plane_state->base.dst.y1;
 978         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 979         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 980         uint32_t x = plane_state->color_plane[0].x;
 981         uint32_t y = plane_state->color_plane[0].y;
 982         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 983         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 984         unsigned long irqflags;
 985
 986         /* Sizes are 0 based */
 987         src_w--;
 988         src_h--;
 989         crtc_w--;
 990         crtc_h--;
 991
 992         if (crtc_w != src_w || crtc_h != src_h)
 993                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 994
 995         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 996
 997         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 998
 999         if (key->flags) {
1000                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
1001                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
1002                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
1003         }
1004
1005         I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
1006         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1007
1008         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1009                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1010         else
1011                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1012
1013         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1014         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1015         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1016         I915_WRITE_FW(DVSSURF(pipe),
1017                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1018         POSTING_READ_FW(DVSSURF(pipe));
1019
1020         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1021 }
1022
1023 static void
1024 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
1025 {
1026         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1027         enum pipe pipe = plane->pipe;
1028         unsigned long irqflags;
1029
1030         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1031
1032         I915_WRITE_FW(DVSCNTR(pipe), 0);
1033         /* Disable the scaler */
1034         I915_WRITE_FW(DVSSCALE(pipe), 0);
1035
1036         I915_WRITE_FW(DVSSURF(pipe), 0);
1037         POSTING_READ_FW(DVSSURF(pipe));
1038
1039         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1040 }
1041
1042 static bool
1043 g4x_plane_get_hw_state(struct intel_plane *plane,
1044                        enum pipe *pipe)
1045 {
1046         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1047         enum intel_display_power_domain power_domain;
1048         bool ret;
1049
1050         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1051         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1052                 return false;
1053
1054         ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1055
1056         *pipe = plane->pipe;
1057
1058         intel_display_power_put(dev_priv, power_domain);
1059
1060         return ret;
1061 }
1062
1063 static int
1064 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1065                          struct intel_plane_state *plane_state)
1066 {
1067         const struct drm_framebuffer *fb = plane_state->base.fb;
1068         const struct drm_rect *src = &plane_state->base.src;
1069         const struct drm_rect *dst = &plane_state->base.dst;
1070         int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
1071         const struct drm_display_mode *adjusted_mode =
1072                 &crtc_state->base.adjusted_mode;
1073         unsigned int cpp = fb->format->cpp[0];
1074         unsigned int width_bytes;
1075         int min_width, min_height;
1076
1077         crtc_w = drm_rect_width(dst);
1078         crtc_h = drm_rect_height(dst);
1079
1080         src_x = src->x1 >> 16;
1081         src_y = src->y1 >> 16;
1082         src_w = drm_rect_width(src) >> 16;
1083         src_h = drm_rect_height(src) >> 16;
1084
1085         if (src_w == crtc_w && src_h == crtc_h)
1086                 return 0;
1087
1088         min_width = 3;
1089
1090         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1091                 if (src_h & 1) {
1092                         DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1093                         return -EINVAL;
1094                 }
1095                 min_height = 6;
1096         } else {
1097                 min_height = 3;
1098         }
1099
1100         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1101
1102         if (src_w < min_width || src_h < min_height ||
1103             src_w > 2048 || src_h > 2048) {
1104                 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1105                               src_w, src_h, min_width, min_height, 2048, 2048);
1106                 return -EINVAL;
1107         }
1108
1109         if (width_bytes > 4096) {
1110                 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1111                               width_bytes, 4096);
1112                 return -EINVAL;
1113         }
1114
1115         if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1116                 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1117                               fb->pitches[0], 4096);
1118                 return -EINVAL;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int
1125 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1126                  struct intel_plane_state *plane_state)
1127 {
1128         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1129         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1130         int max_scale, min_scale;
1131         int ret;
1132
1133         if (INTEL_GEN(dev_priv) < 7) {
1134                 min_scale = 1;
1135                 max_scale = 16 << 16;
1136         } else if (IS_IVYBRIDGE(dev_priv)) {
1137                 min_scale = 1;
1138                 max_scale = 2 << 16;
1139         } else {
1140                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1141                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
1142         }
1143
1144         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1145                                                   &crtc_state->base,
1146                                                   min_scale, max_scale,
1147                                                   true, true);
1148         if (ret)
1149                 return ret;
1150
1151         if (!plane_state->base.visible)
1152                 return 0;
1153
1154         ret = intel_plane_check_src_coordinates(plane_state);
1155         if (ret)
1156                 return ret;
1157
1158         ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1159         if (ret)
1160                 return ret;
1161
1162         ret = i9xx_check_plane_surface(plane_state);
1163         if (ret)
1164                 return ret;
1165
1166         if (INTEL_GEN(dev_priv) >= 7)
1167                 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1168         else
1169                 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1170
1171         return 0;
1172 }
1173
1174 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1175 {
1176         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1177         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1178         unsigned int rotation = plane_state->base.rotation;
1179
1180         /* CHV ignores the mirror bit when the rotate bit is set :( */
1181         if (IS_CHERRYVIEW(dev_priv) &&
1182             rotation & DRM_MODE_ROTATE_180 &&
1183             rotation & DRM_MODE_REFLECT_X) {
1184                 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1185                 return -EINVAL;
1186         }
1187
1188         return 0;
1189 }
1190
1191 static int
1192 vlv_sprite_check(struct intel_crtc_state *crtc_state,
1193                  struct intel_plane_state *plane_state)
1194 {
1195         int ret;
1196
1197         ret = chv_plane_check_rotation(plane_state);
1198         if (ret)
1199                 return ret;
1200
1201         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1202                                                   &crtc_state->base,
1203                                                   DRM_PLANE_HELPER_NO_SCALING,
1204                                                   DRM_PLANE_HELPER_NO_SCALING,
1205                                                   true, true);
1206         if (ret)
1207                 return ret;
1208
1209         if (!plane_state->base.visible)
1210                 return 0;
1211
1212         ret = intel_plane_check_src_coordinates(plane_state);
1213         if (ret)
1214                 return ret;
1215
1216         ret = i9xx_check_plane_surface(plane_state);
1217         if (ret)
1218                 return ret;
1219
1220         plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1221
1222         return 0;
1223 }
1224
1225 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1226                               const struct intel_plane_state *plane_state)
1227 {
1228         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1229         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1230         const struct drm_framebuffer *fb = plane_state->base.fb;
1231         unsigned int rotation = plane_state->base.rotation;
1232         struct drm_format_name_buf format_name;
1233
1234         if (!fb)
1235                 return 0;
1236
1237         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1238             is_ccs_modifier(fb->modifier)) {
1239                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
1240                               rotation);
1241                 return -EINVAL;
1242         }
1243
1244         if (rotation & DRM_MODE_REFLECT_X &&
1245             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1246                 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
1247                 return -EINVAL;
1248         }
1249
1250         if (drm_rotation_90_or_270(rotation)) {
1251                 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1252                     fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
1253                         DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
1254                         return -EINVAL;
1255                 }
1256
1257                 /*
1258                  * 90/270 is not allowed with RGB64 16:16:16:16 and
1259                  * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1260                  * TBD: Add RGB64 case once its added in supported format
1261                  * list.
1262                  */
1263                 switch (fb->format->format) {
1264                 case DRM_FORMAT_RGB565:
1265                         if (INTEL_GEN(dev_priv) >= 11)
1266                                 break;
1267                         /* fall through */
1268                 case DRM_FORMAT_C8:
1269                         DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
1270                                       drm_get_format_name(fb->format->format,
1271                                                           &format_name));
1272                         return -EINVAL;
1273                 default:
1274                         break;
1275                 }
1276         }
1277
1278         /* Y-tiling is not supported in IF-ID Interlace mode */
1279         if (crtc_state->base.enable &&
1280             crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1281             (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
1282              fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
1283              fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1284              fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
1285                 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
1286                 return -EINVAL;
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1293                                            const struct intel_plane_state *plane_state)
1294 {
1295         struct drm_i915_private *dev_priv =
1296                 to_i915(plane_state->base.plane->dev);
1297         int crtc_x = plane_state->base.dst.x1;
1298         int crtc_w = drm_rect_width(&plane_state->base.dst);
1299         int pipe_src_w = crtc_state->pipe_src_w;
1300
1301         /*
1302          * Display WA #1175: cnl,glk
1303          * Planes other than the cursor may cause FIFO underflow and display
1304          * corruption if starting less than 4 pixels from the right edge of
1305          * the screen.
1306          * Besides the above WA fix the similar problem, where planes other
1307          * than the cursor ending less than 4 pixels from the left edge of the
1308          * screen may cause FIFO underflow and display corruption.
1309          */
1310         if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
1311             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1312                 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
1313                               crtc_x + crtc_w < 4 ? "end" : "start",
1314                               crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1315                               4, pipe_src_w - 4);
1316                 return -ERANGE;
1317         }
1318
1319         return 0;
1320 }
1321
1322 int skl_plane_check(struct intel_crtc_state *crtc_state,
1323                     struct intel_plane_state *plane_state)
1324 {
1325         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1326         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1327         int max_scale, min_scale;
1328         int ret;
1329
1330         ret = skl_plane_check_fb(crtc_state, plane_state);
1331         if (ret)
1332                 return ret;
1333
1334         /* use scaler when colorkey is not required */
1335         if (!plane_state->ckey.flags) {
1336                 const struct drm_framebuffer *fb = plane_state->base.fb;
1337
1338                 min_scale = 1;
1339                 max_scale = skl_max_scale(crtc_state,
1340                                           fb ? fb->format->format : 0);
1341         } else {
1342                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1343                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
1344         }
1345
1346         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1347                                                   &crtc_state->base,
1348                                                   min_scale, max_scale,
1349                                                   true, true);
1350         if (ret)
1351                 return ret;
1352
1353         if (!plane_state->base.visible)
1354                 return 0;
1355
1356         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1357         if (ret)
1358                 return ret;
1359
1360         ret = intel_plane_check_src_coordinates(plane_state);
1361         if (ret)
1362                 return ret;
1363
1364         ret = skl_check_plane_surface(plane_state);
1365         if (ret)
1366                 return ret;
1367
1368         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1369
1370         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1371                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1372                                                              plane_state);
1373
1374         return 0;
1375 }
1376
1377 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1378 {
1379         return INTEL_GEN(dev_priv) >= 9;
1380 }
1381
1382 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1383                                  const struct drm_intel_sprite_colorkey *set)
1384 {
1385         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1386         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1387         struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1388
1389         *key = *set;
1390
1391         /*
1392          * We want src key enabled on the
1393          * sprite and not on the primary.
1394          */
1395         if (plane->id == PLANE_PRIMARY &&
1396             set->flags & I915_SET_COLORKEY_SOURCE)
1397                 key->flags = 0;
1398
1399         /*
1400          * On SKL+ we want dst key enabled on
1401          * the primary and not on the sprite.
1402          */
1403         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1404             set->flags & I915_SET_COLORKEY_DESTINATION)
1405                 key->flags = 0;
1406 }
1407
1408 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1409                                     struct drm_file *file_priv)
1410 {
1411         struct drm_i915_private *dev_priv = to_i915(dev);
1412         struct drm_intel_sprite_colorkey *set = data;
1413         struct drm_plane *plane;
1414         struct drm_plane_state *plane_state;
1415         struct drm_atomic_state *state;
1416         struct drm_modeset_acquire_ctx ctx;
1417         int ret = 0;
1418
1419         /* ignore the pointless "none" flag */
1420         set->flags &= ~I915_SET_COLORKEY_NONE;
1421
1422         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1423                 return -EINVAL;
1424
1425         /* Make sure we don't try to enable both src & dest simultaneously */
1426         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1427                 return -EINVAL;
1428
1429         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1430             set->flags & I915_SET_COLORKEY_DESTINATION)
1431                 return -EINVAL;
1432
1433         plane = drm_plane_find(dev, file_priv, set->plane_id);
1434         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1435                 return -ENOENT;
1436
1437         /*
1438          * SKL+ only plane 2 can do destination keying against plane 1.
1439          * Also multiple planes can't do destination keying on the same
1440          * pipe simultaneously.
1441          */
1442         if (INTEL_GEN(dev_priv) >= 9 &&
1443             to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1444             set->flags & I915_SET_COLORKEY_DESTINATION)
1445                 return -EINVAL;
1446
1447         drm_modeset_acquire_init(&ctx, 0);
1448
1449         state = drm_atomic_state_alloc(plane->dev);
1450         if (!state) {
1451                 ret = -ENOMEM;
1452                 goto out;
1453         }
1454         state->acquire_ctx = &ctx;
1455
1456         while (1) {
1457                 plane_state = drm_atomic_get_plane_state(state, plane);
1458                 ret = PTR_ERR_OR_ZERO(plane_state);
1459                 if (!ret)
1460                         intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1461
1462                 /*
1463                  * On some platforms we have to configure
1464                  * the dst colorkey on the primary plane.
1465                  */
1466                 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1467                         struct intel_crtc *crtc =
1468                                 intel_get_crtc_for_pipe(dev_priv,
1469                                                         to_intel_plane(plane)->pipe);
1470
1471                         plane_state = drm_atomic_get_plane_state(state,
1472                                                                  crtc->base.primary);
1473                         ret = PTR_ERR_OR_ZERO(plane_state);
1474                         if (!ret)
1475                                 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1476                 }
1477
1478                 if (!ret)
1479                         ret = drm_atomic_commit(state);
1480
1481                 if (ret != -EDEADLK)
1482                         break;
1483
1484                 drm_atomic_state_clear(state);
1485                 drm_modeset_backoff(&ctx);
1486         }
1487
1488         drm_atomic_state_put(state);
1489 out:
1490         drm_modeset_drop_locks(&ctx);
1491         drm_modeset_acquire_fini(&ctx);
1492         return ret;
1493 }
1494
1495 static const uint32_t g4x_plane_formats[] = {
1496         DRM_FORMAT_XRGB8888,
1497         DRM_FORMAT_YUYV,
1498         DRM_FORMAT_YVYU,
1499         DRM_FORMAT_UYVY,
1500         DRM_FORMAT_VYUY,
1501 };
1502
1503 static const uint64_t i9xx_plane_format_modifiers[] = {
1504         I915_FORMAT_MOD_X_TILED,
1505         DRM_FORMAT_MOD_LINEAR,
1506         DRM_FORMAT_MOD_INVALID
1507 };
1508
1509 static const uint32_t snb_plane_formats[] = {
1510         DRM_FORMAT_XBGR8888,
1511         DRM_FORMAT_XRGB8888,
1512         DRM_FORMAT_YUYV,
1513         DRM_FORMAT_YVYU,
1514         DRM_FORMAT_UYVY,
1515         DRM_FORMAT_VYUY,
1516 };
1517
1518 static const uint32_t vlv_plane_formats[] = {
1519         DRM_FORMAT_RGB565,
1520         DRM_FORMAT_ABGR8888,
1521         DRM_FORMAT_ARGB8888,
1522         DRM_FORMAT_XBGR8888,
1523         DRM_FORMAT_XRGB8888,
1524         DRM_FORMAT_XBGR2101010,
1525         DRM_FORMAT_ABGR2101010,
1526         DRM_FORMAT_YUYV,
1527         DRM_FORMAT_YVYU,
1528         DRM_FORMAT_UYVY,
1529         DRM_FORMAT_VYUY,
1530 };
1531
1532 static uint32_t skl_plane_formats[] = {
1533         DRM_FORMAT_RGB565,
1534         DRM_FORMAT_ABGR8888,
1535         DRM_FORMAT_ARGB8888,
1536         DRM_FORMAT_XBGR8888,
1537         DRM_FORMAT_XRGB8888,
1538         DRM_FORMAT_YUYV,
1539         DRM_FORMAT_YVYU,
1540         DRM_FORMAT_UYVY,
1541         DRM_FORMAT_VYUY,
1542 };
1543
1544 static uint32_t skl_planar_formats[] = {
1545         DRM_FORMAT_RGB565,
1546         DRM_FORMAT_ABGR8888,
1547         DRM_FORMAT_ARGB8888,
1548         DRM_FORMAT_XBGR8888,
1549         DRM_FORMAT_XRGB8888,
1550         DRM_FORMAT_YUYV,
1551         DRM_FORMAT_YVYU,
1552         DRM_FORMAT_UYVY,
1553         DRM_FORMAT_VYUY,
1554         DRM_FORMAT_NV12,
1555 };
1556
1557 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1558         I915_FORMAT_MOD_Yf_TILED,
1559         I915_FORMAT_MOD_Y_TILED,
1560         I915_FORMAT_MOD_X_TILED,
1561         DRM_FORMAT_MOD_LINEAR,
1562         DRM_FORMAT_MOD_INVALID
1563 };
1564
1565 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1566         I915_FORMAT_MOD_Yf_TILED_CCS,
1567         I915_FORMAT_MOD_Y_TILED_CCS,
1568         I915_FORMAT_MOD_Yf_TILED,
1569         I915_FORMAT_MOD_Y_TILED,
1570         I915_FORMAT_MOD_X_TILED,
1571         DRM_FORMAT_MOD_LINEAR,
1572         DRM_FORMAT_MOD_INVALID
1573 };
1574
1575 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1576                                             u32 format, u64 modifier)
1577 {
1578         switch (modifier) {
1579         case DRM_FORMAT_MOD_LINEAR:
1580         case I915_FORMAT_MOD_X_TILED:
1581                 break;
1582         default:
1583                 return false;
1584         }
1585
1586         switch (format) {
1587         case DRM_FORMAT_XRGB8888:
1588         case DRM_FORMAT_YUYV:
1589         case DRM_FORMAT_YVYU:
1590         case DRM_FORMAT_UYVY:
1591         case DRM_FORMAT_VYUY:
1592                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1593                     modifier == I915_FORMAT_MOD_X_TILED)
1594                         return true;
1595                 /* fall through */
1596         default:
1597                 return false;
1598         }
1599 }
1600
1601 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1602                                             u32 format, u64 modifier)
1603 {
1604         switch (modifier) {
1605         case DRM_FORMAT_MOD_LINEAR:
1606         case I915_FORMAT_MOD_X_TILED:
1607                 break;
1608         default:
1609                 return false;
1610         }
1611
1612         switch (format) {
1613         case DRM_FORMAT_XRGB8888:
1614         case DRM_FORMAT_XBGR8888:
1615         case DRM_FORMAT_YUYV:
1616         case DRM_FORMAT_YVYU:
1617         case DRM_FORMAT_UYVY:
1618         case DRM_FORMAT_VYUY:
1619                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1620                     modifier == I915_FORMAT_MOD_X_TILED)
1621                         return true;
1622                 /* fall through */
1623         default:
1624                 return false;
1625         }
1626 }
1627
1628 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1629                                             u32 format, u64 modifier)
1630 {
1631         switch (modifier) {
1632         case DRM_FORMAT_MOD_LINEAR:
1633         case I915_FORMAT_MOD_X_TILED:
1634                 break;
1635         default:
1636                 return false;
1637         }
1638
1639         switch (format) {
1640         case DRM_FORMAT_RGB565:
1641         case DRM_FORMAT_ABGR8888:
1642         case DRM_FORMAT_ARGB8888:
1643         case DRM_FORMAT_XBGR8888:
1644         case DRM_FORMAT_XRGB8888:
1645         case DRM_FORMAT_XBGR2101010:
1646         case DRM_FORMAT_ABGR2101010:
1647         case DRM_FORMAT_YUYV:
1648         case DRM_FORMAT_YVYU:
1649         case DRM_FORMAT_UYVY:
1650         case DRM_FORMAT_VYUY:
1651                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1652                     modifier == I915_FORMAT_MOD_X_TILED)
1653                         return true;
1654                 /* fall through */
1655         default:
1656                 return false;
1657         }
1658 }
1659
1660 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1661                                            u32 format, u64 modifier)
1662 {
1663         struct intel_plane *plane = to_intel_plane(_plane);
1664
1665         switch (modifier) {
1666         case DRM_FORMAT_MOD_LINEAR:
1667         case I915_FORMAT_MOD_X_TILED:
1668         case I915_FORMAT_MOD_Y_TILED:
1669         case I915_FORMAT_MOD_Yf_TILED:
1670                 break;
1671         case I915_FORMAT_MOD_Y_TILED_CCS:
1672         case I915_FORMAT_MOD_Yf_TILED_CCS:
1673                 if (!plane->has_ccs)
1674                         return false;
1675                 break;
1676         default:
1677                 return false;
1678         }
1679
1680         switch (format) {
1681         case DRM_FORMAT_XRGB8888:
1682         case DRM_FORMAT_XBGR8888:
1683         case DRM_FORMAT_ARGB8888:
1684         case DRM_FORMAT_ABGR8888:
1685                 if (is_ccs_modifier(modifier))
1686                         return true;
1687                 /* fall through */
1688         case DRM_FORMAT_RGB565:
1689         case DRM_FORMAT_XRGB2101010:
1690         case DRM_FORMAT_XBGR2101010:
1691         case DRM_FORMAT_YUYV:
1692         case DRM_FORMAT_YVYU:
1693         case DRM_FORMAT_UYVY:
1694         case DRM_FORMAT_VYUY:
1695         case DRM_FORMAT_NV12:
1696                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1697                         return true;
1698                 /* fall through */
1699         case DRM_FORMAT_C8:
1700                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1701                     modifier == I915_FORMAT_MOD_X_TILED ||
1702                     modifier == I915_FORMAT_MOD_Y_TILED)
1703                         return true;
1704                 /* fall through */
1705         default:
1706                 return false;
1707         }
1708 }
1709
1710 static const struct drm_plane_funcs g4x_sprite_funcs = {
1711         .update_plane = drm_atomic_helper_update_plane,
1712         .disable_plane = drm_atomic_helper_disable_plane,
1713         .destroy = intel_plane_destroy,
1714         .atomic_get_property = intel_plane_atomic_get_property,
1715         .atomic_set_property = intel_plane_atomic_set_property,
1716         .atomic_duplicate_state = intel_plane_duplicate_state,
1717         .atomic_destroy_state = intel_plane_destroy_state,
1718         .format_mod_supported = g4x_sprite_format_mod_supported,
1719 };
1720
1721 static const struct drm_plane_funcs snb_sprite_funcs = {
1722         .update_plane = drm_atomic_helper_update_plane,
1723         .disable_plane = drm_atomic_helper_disable_plane,
1724         .destroy = intel_plane_destroy,
1725         .atomic_get_property = intel_plane_atomic_get_property,
1726         .atomic_set_property = intel_plane_atomic_set_property,
1727         .atomic_duplicate_state = intel_plane_duplicate_state,
1728         .atomic_destroy_state = intel_plane_destroy_state,
1729         .format_mod_supported = snb_sprite_format_mod_supported,
1730 };
1731
1732 static const struct drm_plane_funcs vlv_sprite_funcs = {
1733         .update_plane = drm_atomic_helper_update_plane,
1734         .disable_plane = drm_atomic_helper_disable_plane,
1735         .destroy = intel_plane_destroy,
1736         .atomic_get_property = intel_plane_atomic_get_property,
1737         .atomic_set_property = intel_plane_atomic_set_property,
1738         .atomic_duplicate_state = intel_plane_duplicate_state,
1739         .atomic_destroy_state = intel_plane_destroy_state,
1740         .format_mod_supported = vlv_sprite_format_mod_supported,
1741 };
1742
1743 static const struct drm_plane_funcs skl_plane_funcs = {
1744         .update_plane = drm_atomic_helper_update_plane,
1745         .disable_plane = drm_atomic_helper_disable_plane,
1746         .destroy = intel_plane_destroy,
1747         .atomic_get_property = intel_plane_atomic_get_property,
1748         .atomic_set_property = intel_plane_atomic_set_property,
1749         .atomic_duplicate_state = intel_plane_duplicate_state,
1750         .atomic_destroy_state = intel_plane_destroy_state,
1751         .format_mod_supported = skl_plane_format_mod_supported,
1752 };
1753
1754 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1755                        enum pipe pipe, enum plane_id plane_id)
1756 {
1757         if (plane_id == PLANE_CURSOR)
1758                 return false;
1759
1760         if (INTEL_GEN(dev_priv) >= 10)
1761                 return true;
1762
1763         if (IS_GEMINILAKE(dev_priv))
1764                 return pipe != PIPE_C;
1765
1766         return pipe != PIPE_C &&
1767                 (plane_id == PLANE_PRIMARY ||
1768                  plane_id == PLANE_SPRITE0);
1769 }
1770
1771 struct intel_plane *
1772 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1773                           enum pipe pipe, int plane)
1774 {
1775         struct intel_plane *intel_plane = NULL;
1776         struct intel_plane_state *state = NULL;
1777         const struct drm_plane_funcs *plane_funcs;
1778         unsigned long possible_crtcs;
1779         const uint32_t *plane_formats;
1780         const uint64_t *modifiers;
1781         unsigned int supported_rotations;
1782         int num_plane_formats;
1783         int ret;
1784
1785         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1786         if (!intel_plane) {
1787                 ret = -ENOMEM;
1788                 goto fail;
1789         }
1790
1791         state = intel_create_plane_state(&intel_plane->base);
1792         if (!state) {
1793                 ret = -ENOMEM;
1794                 goto fail;
1795         }
1796         intel_plane->base.state = &state->base;
1797
1798         if (INTEL_GEN(dev_priv) >= 9) {
1799                 state->scaler_id = -1;
1800
1801                 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1802                                                          PLANE_SPRITE0 + plane);
1803
1804                 intel_plane->max_stride = skl_plane_max_stride;
1805                 intel_plane->update_plane = skl_update_plane;
1806                 intel_plane->disable_plane = skl_disable_plane;
1807                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1808                 intel_plane->check_plane = skl_plane_check;
1809
1810                 if (skl_plane_has_planar(dev_priv, pipe,
1811                                          PLANE_SPRITE0 + plane)) {
1812                         plane_formats = skl_planar_formats;
1813                         num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1814                 } else {
1815                         plane_formats = skl_plane_formats;
1816                         num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1817                 }
1818
1819                 if (intel_plane->has_ccs)
1820                         modifiers = skl_plane_format_modifiers_ccs;
1821                 else
1822                         modifiers = skl_plane_format_modifiers_noccs;
1823
1824                 plane_funcs = &skl_plane_funcs;
1825         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1826                 intel_plane->max_stride = i9xx_plane_max_stride;
1827                 intel_plane->update_plane = vlv_update_plane;
1828                 intel_plane->disable_plane = vlv_disable_plane;
1829                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1830                 intel_plane->check_plane = vlv_sprite_check;
1831
1832                 plane_formats = vlv_plane_formats;
1833                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1834                 modifiers = i9xx_plane_format_modifiers;
1835
1836                 plane_funcs = &vlv_sprite_funcs;
1837         } else if (INTEL_GEN(dev_priv) >= 7) {
1838                 intel_plane->max_stride = g4x_sprite_max_stride;
1839                 intel_plane->update_plane = ivb_update_plane;
1840                 intel_plane->disable_plane = ivb_disable_plane;
1841                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1842                 intel_plane->check_plane = g4x_sprite_check;
1843
1844                 plane_formats = snb_plane_formats;
1845                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1846                 modifiers = i9xx_plane_format_modifiers;
1847
1848                 plane_funcs = &snb_sprite_funcs;
1849         } else {
1850                 intel_plane->max_stride = g4x_sprite_max_stride;
1851                 intel_plane->update_plane = g4x_update_plane;
1852                 intel_plane->disable_plane = g4x_disable_plane;
1853                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1854                 intel_plane->check_plane = g4x_sprite_check;
1855
1856                 modifiers = i9xx_plane_format_modifiers;
1857                 if (IS_GEN6(dev_priv)) {
1858                         plane_formats = snb_plane_formats;
1859                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1860
1861                         plane_funcs = &snb_sprite_funcs;
1862                 } else {
1863                         plane_formats = g4x_plane_formats;
1864                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1865
1866                         plane_funcs = &g4x_sprite_funcs;
1867                 }
1868         }
1869
1870         if (INTEL_GEN(dev_priv) >= 9) {
1871                 supported_rotations =
1872                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1873                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1874         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1875                 supported_rotations =
1876                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1877                         DRM_MODE_REFLECT_X;
1878         } else {
1879                 supported_rotations =
1880                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1881         }
1882
1883         intel_plane->pipe = pipe;
1884         intel_plane->i9xx_plane = plane;
1885         intel_plane->id = PLANE_SPRITE0 + plane;
1886         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1887
1888         possible_crtcs = (1 << pipe);
1889
1890         if (INTEL_GEN(dev_priv) >= 9)
1891                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1892                                                possible_crtcs, plane_funcs,
1893                                                plane_formats, num_plane_formats,
1894                                                modifiers,
1895                                                DRM_PLANE_TYPE_OVERLAY,
1896                                                "plane %d%c", plane + 2, pipe_name(pipe));
1897         else
1898                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1899                                                possible_crtcs, plane_funcs,
1900                                                plane_formats, num_plane_formats,
1901                                                modifiers,
1902                                                DRM_PLANE_TYPE_OVERLAY,
1903                                                "sprite %c", sprite_name(pipe, plane));
1904         if (ret)
1905                 goto fail;
1906
1907         drm_plane_create_rotation_property(&intel_plane->base,
1908                                            DRM_MODE_ROTATE_0,
1909                                            supported_rotations);
1910
1911         drm_plane_create_color_properties(&intel_plane->base,
1912                                           BIT(DRM_COLOR_YCBCR_BT601) |
1913                                           BIT(DRM_COLOR_YCBCR_BT709),
1914                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1915                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1916                                           DRM_COLOR_YCBCR_BT709,
1917                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1918
1919         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1920
1921         return intel_plane;
1922
1923 fail:
1924         kfree(state);
1925         kfree(intel_plane);
1926
1927         return ERR_PTR(ret);
1928 }