drivers/gpu/drm/mediatek/mtk_dsi.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_mipi_dsi.h>
  18 #include <drm/drm_panel.h>
  19 #include <linux/clk.h>
  20 #include <linux/component.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/of_graph.h>
  24 #include <linux/phy/phy.h>
  25 #include <linux/platform_device.h>
  26 #include <video/videomode.h>
  27
  28 #include "mtk_drm_ddp_comp.h"
  29
  30 #define DSI_VIDEO_FIFO_DEPTH    (1920 / 4)
  31 #define DSI_HOST_FIFO_DEPTH     64
  32
  33 #define DSI_START               0x00
  34
  35 #define DSI_CON_CTRL            0x10
  36 #define DSI_RESET                       BIT(0)
  37 #define DSI_EN                          BIT(1)
  38
  39 #define DSI_MODE_CTRL           0x14
  40 #define MODE                            (3)
  41 #define CMD_MODE                        0
  42 #define SYNC_PULSE_MODE                 1
  43 #define SYNC_EVENT_MODE                 2
  44 #define BURST_MODE                      3
  45 #define FRM_MODE                        BIT(16)
  46 #define MIX_MODE                        BIT(17)
  47
  48 #define DSI_TXRX_CTRL           0x18
  49 #define VC_NUM                          (2 << 0)
  50 #define LANE_NUM                        (0xf << 2)
  51 #define DIS_EOT                         BIT(6)
  52 #define NULL_EN                         BIT(7)
  53 #define TE_FREERUN                      BIT(8)
  54 #define EXT_TE_EN                       BIT(9)
  55 #define EXT_TE_EDGE                     BIT(10)
  56 #define MAX_RTN_SIZE                    (0xf << 12)
  57 #define HSTX_CKLP_EN                    BIT(16)
  58
  59 #define DSI_PSCTRL              0x1c
  60 #define DSI_PS_WC                       0x3fff
  61 #define DSI_PS_SEL                      (3 << 16)
  62 #define PACKED_PS_16BIT_RGB565          (0 << 16)
  63 #define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  64 #define PACKED_PS_18BIT_RGB666          (2 << 16)
  65 #define PACKED_PS_24BIT_RGB888          (3 << 16)
  66
  67 #define DSI_VSA_NL              0x20
  68 #define DSI_VBP_NL              0x24
  69 #define DSI_VFP_NL              0x28
  70 #define DSI_VACT_NL             0x2C
  71 #define DSI_HSA_WC              0x50
  72 #define DSI_HBP_WC              0x54
  73 #define DSI_HFP_WC              0x58
  74
  75 #define DSI_HSTX_CKL_WC         0x64
  76
  77 #define DSI_PHY_LCCON           0x104
  78 #define LC_HS_TX_EN                     BIT(0)
  79 #define LC_ULPM_EN                      BIT(1)
  80 #define LC_WAKEUP_EN                    BIT(2)
  81
  82 #define DSI_PHY_LD0CON          0x108
  83 #define LD0_HS_TX_EN                    BIT(0)
  84 #define LD0_ULPM_EN                     BIT(1)
  85 #define LD0_WAKEUP_EN                   BIT(2)
  86
  87 #define DSI_PHY_TIMECON0        0x110
  88 #define LPX                             (0xff << 0)
  89 #define HS_PREP                         (0xff << 8)
  90 #define HS_ZERO                         (0xff << 16)
  91 #define HS_TRAIL                        (0xff << 24)
  92
  93 #define DSI_PHY_TIMECON1        0x114
  94 #define TA_GO                           (0xff << 0)
  95 #define TA_SURE                         (0xff << 8)
  96 #define TA_GET                          (0xff << 16)
  97 #define DA_HS_EXIT                      (0xff << 24)
  98
  99 #define DSI_PHY_TIMECON2        0x118
 100 #define CONT_DET                        (0xff << 0)
 101 #define CLK_ZERO                        (0xff << 16)
 102 #define CLK_TRAIL                       (0xff << 24)
 103
 104 #define DSI_PHY_TIMECON3        0x11c
 105 #define CLK_HS_PREP                     (0xff << 0)
 106 #define CLK_HS_POST                     (0xff << 8)
 107 #define CLK_HS_EXIT                     (0xff << 16)
 108
 109 #define T_LPX           5
 110 #define T_HS_PREP       6
 111 #define T_HS_TRAIL      8
 112 #define T_HS_EXIT       7
 113 #define T_HS_ZERO       10
 114
 115 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 116
 117 struct phy;
 118
 119 struct mtk_dsi {
 120         struct mtk_ddp_comp ddp_comp;
 121         struct device *dev;
 122         struct mipi_dsi_host host;
 123         struct drm_encoder encoder;
 124         struct drm_connector conn;
 125         struct drm_panel *panel;
 126         struct drm_bridge *bridge;
 127         struct phy *phy;
 128
 129         void __iomem *regs;
 130
 131         struct clk *engine_clk;
 132         struct clk *digital_clk;
 133         struct clk *hs_clk;
 134
 135         u32 data_rate;
 136
 137         unsigned long mode_flags;
 138         enum mipi_dsi_pixel_format format;
 139         unsigned int lanes;
 140         struct videomode vm;
 141         int refcount;
 142         bool enabled;
 143 };
 144
 145 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
 146 {
 147         return container_of(e, struct mtk_dsi, encoder);
 148 }
 149
 150 static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
 151 {
 152         return container_of(c, struct mtk_dsi, conn);
 153 }
 154
 155 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 156 {
 157         return container_of(h, struct mtk_dsi, host);
 158 }
 159
 160 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 161 {
 162         u32 temp = readl(dsi->regs + offset);
 163
 164         writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 165 }
 166
 167 static void dsi_phy_timconfig(struct mtk_dsi *dsi)
 168 {
 169         u32 timcon0, timcon1, timcon2, timcon3;
 170         u32 ui, cycle_time;
 171
 172         ui = 1000 / dsi->data_rate + 0x01;
 173         cycle_time = 8000 / dsi->data_rate + 0x01;
 174
 175         timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
 176         timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
 177                   T_HS_EXIT << 24;
 178         timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
 179                   (NS_TO_CYCLE(0x150, cycle_time) << 16);
 180         timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
 181                   NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
 182
 183         writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 184         writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 185         writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 186         writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 187 }
 188
 189 static void mtk_dsi_enable(struct mtk_dsi *dsi)
 190 {
 191         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 192 }
 193
 194 static void mtk_dsi_disable(struct mtk_dsi *dsi)
 195 {
 196         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 197 }
 198
 199 static void mtk_dsi_reset(struct mtk_dsi *dsi)
 200 {
 201         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 202         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 203 }
 204
 205 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 206 {
 207         struct device *dev = dsi->dev;
 208         int ret;
 209         u64 pixel_clock, total_bits;
 210         u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
 211
 212         if (++dsi->refcount != 1)
 213                 return 0;
 214
 215         switch (dsi->format) {
 216         case MIPI_DSI_FMT_RGB565:
 217                 bit_per_pixel = 16;
 218                 break;
 219         case MIPI_DSI_FMT_RGB666_PACKED:
 220                 bit_per_pixel = 18;
 221                 break;
 222         case MIPI_DSI_FMT_RGB666:
 223         case MIPI_DSI_FMT_RGB888:
 224         default:
 225                 bit_per_pixel = 24;
 226                 break;
 227         }
 228
 229         /**
 230          * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
 231          * htotal_time = htotal * byte_per_pixel / num_lanes
 232          * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
 233          * mipi_ratio = (htotal_time + overhead_time) / htotal_time
 234          * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
 235          */
 236         pixel_clock = dsi->vm.pixelclock * 1000;
 237         htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
 238                         dsi->vm.hsync_len;
 239         htotal_bits = htotal * bit_per_pixel;
 240
 241         overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
 242                         T_HS_EXIT;
 243         overhead_bits = overhead_cycles * dsi->lanes * 8;
 244         total_bits = htotal_bits + overhead_bits;
 245
 246         dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
 247                                           htotal * dsi->lanes);
 248
 249         ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 250         if (ret < 0) {
 251                 dev_err(dev, "Failed to set data rate: %d\n", ret);
 252                 goto err_refcount;
 253         }
 254
 255         phy_power_on(dsi->phy);
 256
 257         ret = clk_prepare_enable(dsi->engine_clk);
 258         if (ret < 0) {
 259                 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 260                 goto err_phy_power_off;
 261         }
 262
 263         ret = clk_prepare_enable(dsi->digital_clk);
 264         if (ret < 0) {
 265                 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 266                 goto err_disable_engine_clk;
 267         }
 268
 269         mtk_dsi_enable(dsi);
 270         mtk_dsi_reset(dsi);
 271         dsi_phy_timconfig(dsi);
 272
 273         return 0;
 274
 275 err_disable_engine_clk:
 276         clk_disable_unprepare(dsi->engine_clk);
 277 err_phy_power_off:
 278         phy_power_off(dsi->phy);
 279 err_refcount:
 280         dsi->refcount--;
 281         return ret;
 282 }
 283
 284 static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 285 {
 286         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 287         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 288 }
 289
 290 static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 291 {
 292         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 293         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 294         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 295 }
 296
 297 static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 298 {
 299         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 300         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 301 }
 302
 303 static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 304 {
 305         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 306         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 307         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 308 }
 309
 310 static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
 311 {
 312         u32 tmp_reg1;
 313
 314         tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
 315         return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 316 }
 317
 318 static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 319 {
 320         if (enter && !dsi_clk_hs_state(dsi))
 321                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 322         else if (!enter && dsi_clk_hs_state(dsi))
 323                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 324 }
 325
 326 static void dsi_set_mode(struct mtk_dsi *dsi)
 327 {
 328         u32 vid_mode = CMD_MODE;
 329
 330         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 331                 vid_mode = SYNC_PULSE_MODE;
 332
 333                 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
 334                     !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
 335                         vid_mode = BURST_MODE;
 336         }
 337
 338         writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 339 }
 340
 341 static void dsi_ps_control_vact(struct mtk_dsi *dsi)
 342 {
 343         struct videomode *vm = &dsi->vm;
 344         u32 dsi_buf_bpp, ps_wc;
 345         u32 ps_bpp_mode;
 346
 347         if (dsi->format == MIPI_DSI_FMT_RGB565)
 348                 dsi_buf_bpp = 2;
 349         else
 350                 dsi_buf_bpp = 3;
 351
 352         ps_wc = vm->hactive * dsi_buf_bpp;
 353         ps_bpp_mode = ps_wc;
 354
 355         switch (dsi->format) {
 356         case MIPI_DSI_FMT_RGB888:
 357                 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 358                 break;
 359         case MIPI_DSI_FMT_RGB666:
 360                 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 361                 break;
 362         case MIPI_DSI_FMT_RGB666_PACKED:
 363                 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 364                 break;
 365         case MIPI_DSI_FMT_RGB565:
 366                 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 367                 break;
 368         }
 369
 370         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 371         writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 372         writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 373 }
 374
 375 static void dsi_rxtx_control(struct mtk_dsi *dsi)
 376 {
 377         u32 tmp_reg;
 378
 379         switch (dsi->lanes) {
 380         case 1:
 381                 tmp_reg = 1 << 2;
 382                 break;
 383         case 2:
 384                 tmp_reg = 3 << 2;
 385                 break;
 386         case 3:
 387                 tmp_reg = 7 << 2;
 388                 break;
 389         case 4:
 390                 tmp_reg = 0xf << 2;
 391                 break;
 392         default:
 393                 tmp_reg = 0xf << 2;
 394                 break;
 395         }
 396
 397         writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 398 }
 399
 400 static void dsi_ps_control(struct mtk_dsi *dsi)
 401 {
 402         unsigned int dsi_tmp_buf_bpp;
 403         u32 tmp_reg;
 404
 405         switch (dsi->format) {
 406         case MIPI_DSI_FMT_RGB888:
 407                 tmp_reg = PACKED_PS_24BIT_RGB888;
 408                 dsi_tmp_buf_bpp = 3;
 409                 break;
 410         case MIPI_DSI_FMT_RGB666:
 411                 tmp_reg = LOOSELY_PS_18BIT_RGB666;
 412                 dsi_tmp_buf_bpp = 3;
 413                 break;
 414         case MIPI_DSI_FMT_RGB666_PACKED:
 415                 tmp_reg = PACKED_PS_18BIT_RGB666;
 416                 dsi_tmp_buf_bpp = 3;
 417                 break;
 418         case MIPI_DSI_FMT_RGB565:
 419                 tmp_reg = PACKED_PS_16BIT_RGB565;
 420                 dsi_tmp_buf_bpp = 2;
 421                 break;
 422         default:
 423                 tmp_reg = PACKED_PS_24BIT_RGB888;
 424                 dsi_tmp_buf_bpp = 3;
 425                 break;
 426         }
 427
 428         tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 429         writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 430 }
 431
 432 static void dsi_config_vdo_timing(struct mtk_dsi *dsi)
 433 {
 434         unsigned int horizontal_sync_active_byte;
 435         unsigned int horizontal_backporch_byte;
 436         unsigned int horizontal_frontporch_byte;
 437         unsigned int dsi_tmp_buf_bpp;
 438
 439         struct videomode *vm = &dsi->vm;
 440
 441         if (dsi->format == MIPI_DSI_FMT_RGB565)
 442                 dsi_tmp_buf_bpp = 2;
 443         else
 444                 dsi_tmp_buf_bpp = 3;
 445
 446         writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 447         writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 448         writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 449         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 450
 451         horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 452
 453         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 454                 horizontal_backporch_byte =
 455                         (vm->hback_porch * dsi_tmp_buf_bpp - 10);
 456         else
 457                 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
 458                         dsi_tmp_buf_bpp - 10);
 459
 460         horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
 461
 462         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 463         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 464         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 465
 466         dsi_ps_control(dsi);
 467 }
 468
 469 static void mtk_dsi_start(struct mtk_dsi *dsi)
 470 {
 471         writel(0, dsi->regs + DSI_START);
 472         writel(1, dsi->regs + DSI_START);
 473 }
 474
 475 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 476 {
 477         if (WARN_ON(dsi->refcount == 0))
 478                 return;
 479
 480         if (--dsi->refcount != 0)
 481                 return;
 482
 483         dsi_lane0_ulp_mode_enter(dsi);
 484         dsi_clk_ulp_mode_enter(dsi);
 485
 486         mtk_dsi_disable(dsi);
 487
 488         clk_disable_unprepare(dsi->engine_clk);
 489         clk_disable_unprepare(dsi->digital_clk);
 490
 491         phy_power_off(dsi->phy);
 492 }
 493
 494 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 495 {
 496         int ret;
 497
 498         if (dsi->enabled)
 499                 return;
 500
 501         if (dsi->panel) {
 502                 if (drm_panel_prepare(dsi->panel)) {
 503                         DRM_ERROR("failed to setup the panel\n");
 504                         return;
 505                 }
 506         }
 507
 508         ret = mtk_dsi_poweron(dsi);
 509         if (ret < 0) {
 510                 DRM_ERROR("failed to power on dsi\n");
 511                 return;
 512         }
 513
 514         dsi_rxtx_control(dsi);
 515
 516         dsi_clk_ulp_mode_leave(dsi);
 517         dsi_lane0_ulp_mode_leave(dsi);
 518         dsi_clk_hs_mode(dsi, 0);
 519         dsi_set_mode(dsi);
 520
 521         dsi_ps_control_vact(dsi);
 522         dsi_config_vdo_timing(dsi);
 523
 524         dsi_set_mode(dsi);
 525         dsi_clk_hs_mode(dsi, 1);
 526
 527         mtk_dsi_start(dsi);
 528
 529         dsi->enabled = true;
 530 }
 531
 532 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 533 {
 534         if (!dsi->enabled)
 535                 return;
 536
 537         if (dsi->panel) {
 538                 if (drm_panel_disable(dsi->panel)) {
 539                         DRM_ERROR("failed to disable the panel\n");
 540                         return;
 541                 }
 542         }
 543
 544         mtk_dsi_poweroff(dsi);
 545
 546         dsi->enabled = false;
 547 }
 548
 549 static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
 550 {
 551         drm_encoder_cleanup(encoder);
 552 }
 553
 554 static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
 555         .destroy = mtk_dsi_encoder_destroy,
 556 };
 557
 558 static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 559                                        const struct drm_display_mode *mode,
 560                                        struct drm_display_mode *adjusted_mode)
 561 {
 562         return true;
 563 }
 564
 565 static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
 566                                      struct drm_display_mode *mode,
 567                                      struct drm_display_mode *adjusted)
 568 {
 569         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 570
 571         dsi->vm.pixelclock = adjusted->clock;
 572         dsi->vm.hactive = adjusted->hdisplay;
 573         dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
 574         dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
 575         dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
 576
 577         dsi->vm.vactive = adjusted->vdisplay;
 578         dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
 579         dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
 580         dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
 581 }
 582
 583 static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
 584 {
 585         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 586
 587         mtk_output_dsi_disable(dsi);
 588 }
 589
 590 static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
 591 {
 592         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 593
 594         mtk_output_dsi_enable(dsi);
 595 }
 596
 597 static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
 598 {
 599         struct mtk_dsi *dsi = connector_to_dsi(connector);
 600
 601         return drm_panel_get_modes(dsi->panel);
 602 }
 603
 604 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
 605         .mode_fixup = mtk_dsi_encoder_mode_fixup,
 606         .mode_set = mtk_dsi_encoder_mode_set,
 607         .disable = mtk_dsi_encoder_disable,
 608         .enable = mtk_dsi_encoder_enable,
 609 };
 610
 611 static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
 612         .dpms = drm_atomic_helper_connector_dpms,
 613         .fill_modes = drm_helper_probe_single_connector_modes,
 614         .destroy = drm_connector_cleanup,
 615         .reset = drm_atomic_helper_connector_reset,
 616         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 617         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 618 };
 619
 620 static const struct drm_connector_helper_funcs
 621         mtk_dsi_connector_helper_funcs = {
 622         .get_modes = mtk_dsi_connector_get_modes,
 623 };
 624
 625 static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
 626 {
 627         int ret;
 628
 629         ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
 630                                  DRM_MODE_CONNECTOR_DSI);
 631         if (ret) {
 632                 DRM_ERROR("Failed to connector init to drm\n");
 633                 return ret;
 634         }
 635
 636         drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
 637
 638         dsi->conn.dpms = DRM_MODE_DPMS_OFF;
 639         drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
 640
 641         if (dsi->panel) {
 642                 ret = drm_panel_attach(dsi->panel, &dsi->conn);
 643                 if (ret) {
 644                         DRM_ERROR("Failed to attach panel to drm\n");
 645                         goto err_connector_cleanup;
 646                 }
 647         }
 648
 649         return 0;
 650
 651 err_connector_cleanup:
 652         drm_connector_cleanup(&dsi->conn);
 653         return ret;
 654 }
 655
 656 static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
 657 {
 658         int ret;
 659
 660         ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
 661                                DRM_MODE_ENCODER_DSI, NULL);
 662         if (ret) {
 663                 DRM_ERROR("Failed to encoder init to drm\n");
 664                 return ret;
 665         }
 666         drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
 667
 668         /*
 669          * Currently display data paths are statically assigned to a crtc each.
 670          * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
 671          */
 672         dsi->encoder.possible_crtcs = 1;
 673
 674         /* If there's a bridge, attach to it and let it create the connector */
 675         ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
 676         if (ret) {
 677                 DRM_ERROR("Failed to attach bridge to drm\n");
 678
 679                 /* Otherwise create our own connector and attach to a panel */
 680                 ret = mtk_dsi_create_connector(drm, dsi);
 681                 if (ret)
 682                         goto err_encoder_cleanup;
 683         }
 684
 685         return 0;
 686
 687 err_encoder_cleanup:
 688         drm_encoder_cleanup(&dsi->encoder);
 689         return ret;
 690 }
 691
 692 static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
 693 {
 694         drm_encoder_cleanup(&dsi->encoder);
 695         /* Skip connector cleanup if creation was delegated to the bridge */
 696         if (dsi->conn.dev)
 697                 drm_connector_cleanup(&dsi->conn);
 698 }
 699
 700 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
 701 {
 702         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 703
 704         mtk_dsi_poweron(dsi);
 705 }
 706
 707 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
 708 {
 709         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 710
 711         mtk_dsi_poweroff(dsi);
 712 }
 713
 714 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
 715         .start = mtk_dsi_ddp_start,
 716         .stop = mtk_dsi_ddp_stop,
 717 };
 718
 719 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 720                                struct mipi_dsi_device *device)
 721 {
 722         struct mtk_dsi *dsi = host_to_dsi(host);
 723
 724         dsi->lanes = device->lanes;
 725         dsi->format = device->format;
 726         dsi->mode_flags = device->mode_flags;
 727
 728         if (dsi->conn.dev)
 729                 drm_helper_hpd_irq_event(dsi->conn.dev);
 730
 731         return 0;
 732 }
 733
 734 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 735                                struct mipi_dsi_device *device)
 736 {
 737         struct mtk_dsi *dsi = host_to_dsi(host);
 738
 739         if (dsi->conn.dev)
 740                 drm_helper_hpd_irq_event(dsi->conn.dev);
 741
 742         return 0;
 743 }
 744
 745 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
 746         .attach = mtk_dsi_host_attach,
 747         .detach = mtk_dsi_host_detach,
 748 };
 749
 750 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
 751 {
 752         int ret;
 753         struct drm_device *drm = data;
 754         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 755
 756         ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
 757         if (ret < 0) {
 758                 dev_err(dev, "Failed to register component %s: %d\n",
 759                         dev->of_node->full_name, ret);
 760                 return ret;
 761         }
 762
 763         ret = mipi_dsi_host_register(&dsi->host);
 764         if (ret < 0) {
 765                 dev_err(dev, "failed to register DSI host: %d\n", ret);
 766                 goto err_ddp_comp_unregister;
 767         }
 768
 769         ret = mtk_dsi_create_conn_enc(drm, dsi);
 770         if (ret) {
 771                 DRM_ERROR("Encoder create failed with %d\n", ret);
 772                 goto err_unregister;
 773         }
 774
 775         return 0;
 776
 777 err_unregister:
 778         mipi_dsi_host_unregister(&dsi->host);
 779 err_ddp_comp_unregister:
 780         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
 781         return ret;
 782 }
 783
 784 static void mtk_dsi_unbind(struct device *dev, struct device *master,
 785                            void *data)
 786 {
 787         struct drm_device *drm = data;
 788         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 789
 790         mtk_dsi_destroy_conn_enc(dsi);
 791         mipi_dsi_host_unregister(&dsi->host);
 792         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
 793 }
 794
 795 static const struct component_ops mtk_dsi_component_ops = {
 796         .bind = mtk_dsi_bind,
 797         .unbind = mtk_dsi_unbind,
 798 };
 799
 800 static int mtk_dsi_probe(struct platform_device *pdev)
 801 {
 802         struct mtk_dsi *dsi;
 803         struct device *dev = &pdev->dev;
 804         struct device_node *remote_node, *endpoint;
 805         struct resource *regs;
 806         int comp_id;
 807         int ret;
 808
 809         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
 810         if (!dsi)
 811                 return -ENOMEM;
 812
 813         dsi->host.ops = &mtk_dsi_ops;
 814         dsi->host.dev = dev;
 815
 816         endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
 817         if (endpoint) {
 818                 remote_node = of_graph_get_remote_port_parent(endpoint);
 819                 if (!remote_node) {
 820                         dev_err(dev, "No panel connected\n");
 821                         return -ENODEV;
 822                 }
 823
 824                 dsi->bridge = of_drm_find_bridge(remote_node);
 825                 dsi->panel = of_drm_find_panel(remote_node);
 826                 of_node_put(remote_node);
 827                 if (!dsi->bridge && !dsi->panel) {
 828                         dev_info(dev, "Waiting for bridge or panel driver\n");
 829                         return -EPROBE_DEFER;
 830                 }
 831         }
 832
 833         dsi->engine_clk = devm_clk_get(dev, "engine");
 834         if (IS_ERR(dsi->engine_clk)) {
 835                 ret = PTR_ERR(dsi->engine_clk);
 836                 dev_err(dev, "Failed to get engine clock: %d\n", ret);
 837                 return ret;
 838         }
 839
 840         dsi->digital_clk = devm_clk_get(dev, "digital");
 841         if (IS_ERR(dsi->digital_clk)) {
 842                 ret = PTR_ERR(dsi->digital_clk);
 843                 dev_err(dev, "Failed to get digital clock: %d\n", ret);
 844                 return ret;
 845         }
 846
 847         dsi->hs_clk = devm_clk_get(dev, "hs");
 848         if (IS_ERR(dsi->hs_clk)) {
 849                 ret = PTR_ERR(dsi->hs_clk);
 850                 dev_err(dev, "Failed to get hs clock: %d\n", ret);
 851                 return ret;
 852         }
 853
 854         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 855         dsi->regs = devm_ioremap_resource(dev, regs);
 856         if (IS_ERR(dsi->regs)) {
 857                 ret = PTR_ERR(dsi->regs);
 858                 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
 859                 return ret;
 860         }
 861
 862         dsi->phy = devm_phy_get(dev, "dphy");
 863         if (IS_ERR(dsi->phy)) {
 864                 ret = PTR_ERR(dsi->phy);
 865                 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
 866                 return ret;
 867         }
 868
 869         comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
 870         if (comp_id < 0) {
 871                 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
 872                 return comp_id;
 873         }
 874
 875         ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
 876                                 &mtk_dsi_funcs);
 877         if (ret) {
 878                 dev_err(dev, "Failed to initialize component: %d\n", ret);
 879                 return ret;
 880         }
 881
 882         platform_set_drvdata(pdev, dsi);
 883
 884         return component_add(&pdev->dev, &mtk_dsi_component_ops);
 885 }
 886
 887 static int mtk_dsi_remove(struct platform_device *pdev)
 888 {
 889         struct mtk_dsi *dsi = platform_get_drvdata(pdev);
 890
 891         mtk_output_dsi_disable(dsi);
 892         component_del(&pdev->dev, &mtk_dsi_component_ops);
 893
 894         return 0;
 895 }
 896
 897 static const struct of_device_id mtk_dsi_of_match[] = {
 898         { .compatible = "mediatek,mt8173-dsi" },
 899         { },
 900 };
 901
 902 struct platform_driver mtk_dsi_driver = {
 903         .probe = mtk_dsi_probe,
 904         .remove = mtk_dsi_remove,
 905         .driver = {
 906                 .name = "mtk-dsi",
 907                 .of_match_table = mtk_dsi_of_match,
 908         },
 909 };