drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37 #include "dce/dce_10_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET
  75 };
  76
  77 static const struct {
  78         uint32_t        reg;
  79         uint32_t        vblank;
  80         uint32_t        vline;
  81         uint32_t        hpd;
  82
  83 } interrupt_status_offsets[] = { {
  84         .reg = mmDISP_INTERRUPT_STATUS,
  85         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  86         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  87         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  88 }, {
  89         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  90         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 113 } };
 114
 115 static const u32 golden_settings_tonga_a11[] =
 116 {
 117         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x1f311fff, 0x12300000,
 120         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 121 };
 122
 123 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 124 {
 125         switch (adev->asic_type) {
 126         case CHIP_TONGA:
 127                 amdgpu_program_register_sequence(adev,
 128                                                  golden_settings_tonga_a11,
 129                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 130                 break;
 131         default:
 132                 break;
 133         }
 134 }
 135
 136 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 137                                      u32 block_offset, u32 reg)
 138 {
 139         unsigned long flags;
 140         u32 r;
 141
 142         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 143         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 144         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 145         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 146
 147         return r;
 148 }
 149
 150 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 151                                       u32 block_offset, u32 reg, u32 v)
 152 {
 153         unsigned long flags;
 154
 155         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 156         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 157         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 158         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 159 }
 160
 161 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 162 {
 163         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 164                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 165                 return true;
 166         else
 167                 return false;
 168 }
 169
 170 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 171 {
 172         u32 pos1, pos2;
 173
 174         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 175         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 176
 177         if (pos1 != pos2)
 178                 return true;
 179         else
 180                 return false;
 181 }
 182
 183 /**
 184  * dce_v10_0_vblank_wait - vblank wait asic callback.
 185  *
 186  * @adev: amdgpu_device pointer
 187  * @crtc: crtc to wait for vblank on
 188  *
 189  * Wait for vblank on the requested crtc (evergreen+).
 190  */
 191 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 192 {
 193         unsigned i = 0;
 194
 195         if (crtc >= adev->mode_info.num_crtc)
 196                 return;
 197
 198         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 199                 return;
 200
 201         /* depending on when we hit vblank, we may be close to active; if so,
 202          * wait for another frame.
 203          */
 204         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 205                 if (i++ % 100 == 0) {
 206                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 207                                 break;
 208                 }
 209         }
 210
 211         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 212                 if (i++ % 100 == 0) {
 213                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 214                                 break;
 215                 }
 216         }
 217 }
 218
 219 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 220 {
 221         if (crtc >= adev->mode_info.num_crtc)
 222                 return 0;
 223         else
 224                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 225 }
 226
 227 /**
 228  * dce_v10_0_page_flip - pageflip callback.
 229  *
 230  * @adev: amdgpu_device pointer
 231  * @crtc_id: crtc to cleanup pageflip on
 232  * @crtc_base: new address of the crtc (GPU MC address)
 233  *
 234  * Does the actual pageflip (evergreen+).
 235  * During vblank we take the crtc lock and wait for the update_pending
 236  * bit to go high, when it does, we release the lock, and allow the
 237  * double buffered update to take place.
 238  * Returns the current update pending status.
 239  */
 240 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 241                               int crtc_id, u64 crtc_base)
 242 {
 243         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 244         u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
 245         int i;
 246
 247         /* Lock the graphics update lock */
 248         tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 249         WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
 250
 251         /* update the scanout addresses */
 252         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 253                upper_32_bits(crtc_base));
 254         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 255                lower_32_bits(crtc_base));
 256
 257         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 258                upper_32_bits(crtc_base));
 259         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 260                lower_32_bits(crtc_base));
 261
 262         /* Wait for update_pending to go high. */
 263         for (i = 0; i < adev->usec_timeout; i++) {
 264                 if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
 265                                 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
 266                         break;
 267                 udelay(1);
 268         }
 269         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 270
 271         /* Unlock the lock, so double-buffering can take place inside vblank */
 272         tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 273         WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
 274 }
 275
 276 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 277                                         u32 *vbl, u32 *position)
 278 {
 279         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 280                 return -EINVAL;
 281
 282         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 283         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 284
 285         return 0;
 286 }
 287
 288 /**
 289  * dce_v10_0_hpd_sense - hpd sense callback.
 290  *
 291  * @adev: amdgpu_device pointer
 292  * @hpd: hpd (hotplug detect) pin
 293  *
 294  * Checks if a digital monitor is connected (evergreen+).
 295  * Returns true if connected, false if not connected.
 296  */
 297 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 298                                enum amdgpu_hpd_id hpd)
 299 {
 300         int idx;
 301         bool connected = false;
 302
 303         switch (hpd) {
 304         case AMDGPU_HPD_1:
 305                 idx = 0;
 306                 break;
 307         case AMDGPU_HPD_2:
 308                 idx = 1;
 309                 break;
 310         case AMDGPU_HPD_3:
 311                 idx = 2;
 312                 break;
 313         case AMDGPU_HPD_4:
 314                 idx = 3;
 315                 break;
 316         case AMDGPU_HPD_5:
 317                 idx = 4;
 318                 break;
 319         case AMDGPU_HPD_6:
 320                 idx = 5;
 321                 break;
 322         default:
 323                 return connected;
 324         }
 325
 326         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 327             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 328                 connected = true;
 329
 330         return connected;
 331 }
 332
 333 /**
 334  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 335  *
 336  * @adev: amdgpu_device pointer
 337  * @hpd: hpd (hotplug detect) pin
 338  *
 339  * Set the polarity of the hpd pin (evergreen+).
 340  */
 341 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 342                                       enum amdgpu_hpd_id hpd)
 343 {
 344         u32 tmp;
 345         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 346         int idx;
 347
 348         switch (hpd) {
 349         case AMDGPU_HPD_1:
 350                 idx = 0;
 351                 break;
 352         case AMDGPU_HPD_2:
 353                 idx = 1;
 354                 break;
 355         case AMDGPU_HPD_3:
 356                 idx = 2;
 357                 break;
 358         case AMDGPU_HPD_4:
 359                 idx = 3;
 360                 break;
 361         case AMDGPU_HPD_5:
 362                 idx = 4;
 363                 break;
 364         case AMDGPU_HPD_6:
 365                 idx = 5;
 366                 break;
 367         default:
 368                 return;
 369         }
 370
 371         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 372         if (connected)
 373                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 374         else
 375                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 376         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 377 }
 378
 379 /**
 380  * dce_v10_0_hpd_init - hpd setup callback.
 381  *
 382  * @adev: amdgpu_device pointer
 383  *
 384  * Setup the hpd pins used by the card (evergreen+).
 385  * Enable the pin, set the polarity, and enable the hpd interrupts.
 386  */
 387 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 388 {
 389         struct drm_device *dev = adev->ddev;
 390         struct drm_connector *connector;
 391         u32 tmp;
 392         int idx;
 393
 394         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 395                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 396
 397                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 398                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 399                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 400                          * aux dp channel on imac and help (but not completely fix)
 401                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 402                          * also avoid interrupt storms during dpms.
 403                          */
 404                         continue;
 405                 }
 406
 407                 switch (amdgpu_connector->hpd.hpd) {
 408                 case AMDGPU_HPD_1:
 409                         idx = 0;
 410                         break;
 411                 case AMDGPU_HPD_2:
 412                         idx = 1;
 413                         break;
 414                 case AMDGPU_HPD_3:
 415                         idx = 2;
 416                         break;
 417                 case AMDGPU_HPD_4:
 418                         idx = 3;
 419                         break;
 420                 case AMDGPU_HPD_5:
 421                         idx = 4;
 422                         break;
 423                 case AMDGPU_HPD_6:
 424                         idx = 5;
 425                         break;
 426                 default:
 427                         continue;
 428                 }
 429
 430                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 431                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 432                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 433
 434                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 435                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 436                                     DC_HPD_CONNECT_INT_DELAY,
 437                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 438                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 439                                     DC_HPD_DISCONNECT_INT_DELAY,
 440                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 441                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 442
 443                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 444                 amdgpu_irq_get(adev, &adev->hpd_irq,
 445                                amdgpu_connector->hpd.hpd);
 446         }
 447 }
 448
 449 /**
 450  * dce_v10_0_hpd_fini - hpd tear down callback.
 451  *
 452  * @adev: amdgpu_device pointer
 453  *
 454  * Tear down the hpd pins used by the card (evergreen+).
 455  * Disable the hpd interrupts.
 456  */
 457 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 458 {
 459         struct drm_device *dev = adev->ddev;
 460         struct drm_connector *connector;
 461         u32 tmp;
 462         int idx;
 463
 464         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 465                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 466
 467                 switch (amdgpu_connector->hpd.hpd) {
 468                 case AMDGPU_HPD_1:
 469                         idx = 0;
 470                         break;
 471                 case AMDGPU_HPD_2:
 472                         idx = 1;
 473                         break;
 474                 case AMDGPU_HPD_3:
 475                         idx = 2;
 476                         break;
 477                 case AMDGPU_HPD_4:
 478                         idx = 3;
 479                         break;
 480                 case AMDGPU_HPD_5:
 481                         idx = 4;
 482                         break;
 483                 case AMDGPU_HPD_6:
 484                         idx = 5;
 485                         break;
 486                 default:
 487                         continue;
 488                 }
 489
 490                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 491                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 492                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 493
 494                 amdgpu_irq_put(adev, &adev->hpd_irq,
 495                                amdgpu_connector->hpd.hpd);
 496         }
 497 }
 498
 499 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 500 {
 501         return mmDC_GPIO_HPD_A;
 502 }
 503
 504 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 505 {
 506         u32 crtc_hung = 0;
 507         u32 crtc_status[6];
 508         u32 i, j, tmp;
 509
 510         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 511                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 512                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 513                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 514                         crtc_hung |= (1 << i);
 515                 }
 516         }
 517
 518         for (j = 0; j < 10; j++) {
 519                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 520                         if (crtc_hung & (1 << i)) {
 521                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 522                                 if (tmp != crtc_status[i])
 523                                         crtc_hung &= ~(1 << i);
 524                         }
 525                 }
 526                 if (crtc_hung == 0)
 527                         return false;
 528                 udelay(100);
 529         }
 530
 531         return true;
 532 }
 533
 534 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
 535                                      struct amdgpu_mode_mc_save *save)
 536 {
 537         u32 crtc_enabled, tmp;
 538         int i;
 539
 540         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 541         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 542
 543         /* disable VGA render */
 544         tmp = RREG32(mmVGA_RENDER_CONTROL);
 545         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 546         WREG32(mmVGA_RENDER_CONTROL, tmp);
 547
 548         /* blank the display controllers */
 549         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 550                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 551                                              CRTC_CONTROL, CRTC_MASTER_EN);
 552                 if (crtc_enabled) {
 553 #if 0
 554                         u32 frame_count;
 555                         int j;
 556
 557                         save->crtc_enabled[i] = true;
 558                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 559                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 560                                 amdgpu_display_vblank_wait(adev, i);
 561                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 562                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 563                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 564                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 565                         }
 566                         /* wait for the next frame */
 567                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 568                         for (j = 0; j < adev->usec_timeout; j++) {
 569                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 570                                         break;
 571                                 udelay(1);
 572                         }
 573                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 574                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 575                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 576                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 577                         }
 578                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 579                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 580                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 581                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 582                         }
 583 #else
 584                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 585                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 586                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 587                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 588                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 589                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 590                         save->crtc_enabled[i] = false;
 591                         /* ***** */
 592 #endif
 593                 } else {
 594                         save->crtc_enabled[i] = false;
 595                 }
 596         }
 597 }
 598
 599 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
 600                                        struct amdgpu_mode_mc_save *save)
 601 {
 602         u32 tmp, frame_count;
 603         int i, j;
 604
 605         /* update crtc base addresses */
 606         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 607                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 608                        upper_32_bits(adev->mc.vram_start));
 609                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 610                        upper_32_bits(adev->mc.vram_start));
 611                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 612                        (u32)adev->mc.vram_start);
 613                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 614                        (u32)adev->mc.vram_start);
 615
 616                 if (save->crtc_enabled[i]) {
 617                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 618                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 619                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 620                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 621                         }
 622                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 623                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 624                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 625                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 626                         }
 627                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 628                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 629                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 630                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 631                         }
 632                         for (j = 0; j < adev->usec_timeout; j++) {
 633                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 634                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 635                                         break;
 636                                 udelay(1);
 637                         }
 638                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 639                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 640                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 641                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 642                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 643                         /* wait for the next frame */
 644                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 645                         for (j = 0; j < adev->usec_timeout; j++) {
 646                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 647                                         break;
 648                                 udelay(1);
 649                         }
 650                 }
 651         }
 652
 653         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 654         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 655
 656         /* Unlock vga access */
 657         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 658         mdelay(1);
 659         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 660 }
 661
 662 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 663                                            bool render)
 664 {
 665         u32 tmp;
 666
 667         /* Lockout access through VGA aperture*/
 668         tmp = RREG32(mmVGA_HDP_CONTROL);
 669         if (render)
 670                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 671         else
 672                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 673         WREG32(mmVGA_HDP_CONTROL, tmp);
 674
 675         /* disable VGA render */
 676         tmp = RREG32(mmVGA_RENDER_CONTROL);
 677         if (render)
 678                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 679         else
 680                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 681         WREG32(mmVGA_RENDER_CONTROL, tmp);
 682 }
 683
 684 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 685 {
 686         struct drm_device *dev = encoder->dev;
 687         struct amdgpu_device *adev = dev->dev_private;
 688         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 689         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 690         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 691         int bpc = 0;
 692         u32 tmp = 0;
 693         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 694
 695         if (connector) {
 696                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 697                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 698                 dither = amdgpu_connector->dither;
 699         }
 700
 701         /* LVDS/eDP FMT is set up by atom */
 702         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 703                 return;
 704
 705         /* not needed for analog */
 706         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 707             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 708                 return;
 709
 710         if (bpc == 0)
 711                 return;
 712
 713         switch (bpc) {
 714         case 6:
 715                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 716                         /* XXX sort out optimal dither settings */
 717                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 718                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 719                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 720                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 721                 } else {
 722                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 723                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 724                 }
 725                 break;
 726         case 8:
 727                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 728                         /* XXX sort out optimal dither settings */
 729                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 730                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 731                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 732                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 733                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 734                 } else {
 735                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 737                 }
 738                 break;
 739         case 10:
 740                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 741                         /* XXX sort out optimal dither settings */
 742                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 743                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 744                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 745                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 746                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 747                 } else {
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 749                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 750                 }
 751                 break;
 752         default:
 753                 /* not needed */
 754                 break;
 755         }
 756
 757         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 758 }
 759
 760
 761 /* display watermark setup */
 762 /**
 763  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 764  *
 765  * @adev: amdgpu_device pointer
 766  * @amdgpu_crtc: the selected display controller
 767  * @mode: the current display mode on the selected display
 768  * controller
 769  *
 770  * Setup up the line buffer allocation for
 771  * the selected display controller (CIK).
 772  * Returns the line buffer size in pixels.
 773  */
 774 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 775                                        struct amdgpu_crtc *amdgpu_crtc,
 776                                        struct drm_display_mode *mode)
 777 {
 778         u32 tmp, buffer_alloc, i, mem_cfg;
 779         u32 pipe_offset = amdgpu_crtc->crtc_id;
 780         /*
 781          * Line Buffer Setup
 782          * There are 6 line buffers, one for each display controllers.
 783          * There are 3 partitions per LB. Select the number of partitions
 784          * to enable based on the display width.  For display widths larger
 785          * than 4096, you need use to use 2 display controllers and combine
 786          * them using the stereo blender.
 787          */
 788         if (amdgpu_crtc->base.enabled && mode) {
 789                 if (mode->crtc_hdisplay < 1920) {
 790                         mem_cfg = 1;
 791                         buffer_alloc = 2;
 792                 } else if (mode->crtc_hdisplay < 2560) {
 793                         mem_cfg = 2;
 794                         buffer_alloc = 2;
 795                 } else if (mode->crtc_hdisplay < 4096) {
 796                         mem_cfg = 0;
 797                         buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
 798                 } else {
 799                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 800                         mem_cfg = 0;
 801                         buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
 802                 }
 803         } else {
 804                 mem_cfg = 1;
 805                 buffer_alloc = 0;
 806         }
 807
 808         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 809         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 810         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 811
 812         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 813         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 814         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 815
 816         for (i = 0; i < adev->usec_timeout; i++) {
 817                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 818                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 819                         break;
 820                 udelay(1);
 821         }
 822
 823         if (amdgpu_crtc->base.enabled && mode) {
 824                 switch (mem_cfg) {
 825                 case 0:
 826                 default:
 827                         return 4096 * 2;
 828                 case 1:
 829                         return 1920 * 2;
 830                 case 2:
 831                         return 2560 * 2;
 832                 }
 833         }
 834
 835         /* controller not enabled, so no lb used */
 836         return 0;
 837 }
 838
 839 /**
 840  * cik_get_number_of_dram_channels - get the number of dram channels
 841  *
 842  * @adev: amdgpu_device pointer
 843  *
 844  * Look up the number of video ram channels (CIK).
 845  * Used for display watermark bandwidth calculations
 846  * Returns the number of dram channels
 847  */
 848 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 849 {
 850         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 851
 852         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 853         case 0:
 854         default:
 855                 return 1;
 856         case 1:
 857                 return 2;
 858         case 2:
 859                 return 4;
 860         case 3:
 861                 return 8;
 862         case 4:
 863                 return 3;
 864         case 5:
 865                 return 6;
 866         case 6:
 867                 return 10;
 868         case 7:
 869                 return 12;
 870         case 8:
 871                 return 16;
 872         }
 873 }
 874
 875 struct dce10_wm_params {
 876         u32 dram_channels; /* number of dram channels */
 877         u32 yclk;          /* bandwidth per dram data pin in kHz */
 878         u32 sclk;          /* engine clock in kHz */
 879         u32 disp_clk;      /* display clock in kHz */
 880         u32 src_width;     /* viewport width */
 881         u32 active_time;   /* active display time in ns */
 882         u32 blank_time;    /* blank time in ns */
 883         bool interlaced;    /* mode is interlaced */
 884         fixed20_12 vsc;    /* vertical scale ratio */
 885         u32 num_heads;     /* number of active crtcs */
 886         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 887         u32 lb_size;       /* line buffer allocated to pipe */
 888         u32 vtaps;         /* vertical scaler taps */
 889 };
 890
 891 /**
 892  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 893  *
 894  * @wm: watermark calculation data
 895  *
 896  * Calculate the raw dram bandwidth (CIK).
 897  * Used for display watermark bandwidth calculations
 898  * Returns the dram bandwidth in MBytes/s
 899  */
 900 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 901 {
 902         /* Calculate raw DRAM Bandwidth */
 903         fixed20_12 dram_efficiency; /* 0.7 */
 904         fixed20_12 yclk, dram_channels, bandwidth;
 905         fixed20_12 a;
 906
 907         a.full = dfixed_const(1000);
 908         yclk.full = dfixed_const(wm->yclk);
 909         yclk.full = dfixed_div(yclk, a);
 910         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 911         a.full = dfixed_const(10);
 912         dram_efficiency.full = dfixed_const(7);
 913         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 914         bandwidth.full = dfixed_mul(dram_channels, yclk);
 915         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 916
 917         return dfixed_trunc(bandwidth);
 918 }
 919
 920 /**
 921  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 922  *
 923  * @wm: watermark calculation data
 924  *
 925  * Calculate the dram bandwidth used for display (CIK).
 926  * Used for display watermark bandwidth calculations
 927  * Returns the dram bandwidth for display in MBytes/s
 928  */
 929 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 930 {
 931         /* Calculate DRAM Bandwidth and the part allocated to display. */
 932         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 933         fixed20_12 yclk, dram_channels, bandwidth;
 934         fixed20_12 a;
 935
 936         a.full = dfixed_const(1000);
 937         yclk.full = dfixed_const(wm->yclk);
 938         yclk.full = dfixed_div(yclk, a);
 939         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 940         a.full = dfixed_const(10);
 941         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 942         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 943         bandwidth.full = dfixed_mul(dram_channels, yclk);
 944         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 945
 946         return dfixed_trunc(bandwidth);
 947 }
 948
 949 /**
 950  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 951  *
 952  * @wm: watermark calculation data
 953  *
 954  * Calculate the data return bandwidth used for display (CIK).
 955  * Used for display watermark bandwidth calculations
 956  * Returns the data return bandwidth in MBytes/s
 957  */
 958 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 959 {
 960         /* Calculate the display Data return Bandwidth */
 961         fixed20_12 return_efficiency; /* 0.8 */
 962         fixed20_12 sclk, bandwidth;
 963         fixed20_12 a;
 964
 965         a.full = dfixed_const(1000);
 966         sclk.full = dfixed_const(wm->sclk);
 967         sclk.full = dfixed_div(sclk, a);
 968         a.full = dfixed_const(10);
 969         return_efficiency.full = dfixed_const(8);
 970         return_efficiency.full = dfixed_div(return_efficiency, a);
 971         a.full = dfixed_const(32);
 972         bandwidth.full = dfixed_mul(a, sclk);
 973         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 974
 975         return dfixed_trunc(bandwidth);
 976 }
 977
 978 /**
 979  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
 980  *
 981  * @wm: watermark calculation data
 982  *
 983  * Calculate the dmif bandwidth used for display (CIK).
 984  * Used for display watermark bandwidth calculations
 985  * Returns the dmif bandwidth in MBytes/s
 986  */
 987 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 988 {
 989         /* Calculate the DMIF Request Bandwidth */
 990         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 991         fixed20_12 disp_clk, bandwidth;
 992         fixed20_12 a, b;
 993
 994         a.full = dfixed_const(1000);
 995         disp_clk.full = dfixed_const(wm->disp_clk);
 996         disp_clk.full = dfixed_div(disp_clk, a);
 997         a.full = dfixed_const(32);
 998         b.full = dfixed_mul(a, disp_clk);
 999
1000         a.full = dfixed_const(10);
1001         disp_clk_request_efficiency.full = dfixed_const(8);
1002         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1003
1004         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1005
1006         return dfixed_trunc(bandwidth);
1007 }
1008
1009 /**
1010  * dce_v10_0_available_bandwidth - get the min available bandwidth
1011  *
1012  * @wm: watermark calculation data
1013  *
1014  * Calculate the min available bandwidth used for display (CIK).
1015  * Used for display watermark bandwidth calculations
1016  * Returns the min available bandwidth in MBytes/s
1017  */
1018 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1019 {
1020         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1021         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1022         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1023         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1024
1025         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1026 }
1027
1028 /**
1029  * dce_v10_0_average_bandwidth - get the average available bandwidth
1030  *
1031  * @wm: watermark calculation data
1032  *
1033  * Calculate the average available bandwidth used for display (CIK).
1034  * Used for display watermark bandwidth calculations
1035  * Returns the average available bandwidth in MBytes/s
1036  */
1037 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1038 {
1039         /* Calculate the display mode Average Bandwidth
1040          * DisplayMode should contain the source and destination dimensions,
1041          * timing, etc.
1042          */
1043         fixed20_12 bpp;
1044         fixed20_12 line_time;
1045         fixed20_12 src_width;
1046         fixed20_12 bandwidth;
1047         fixed20_12 a;
1048
1049         a.full = dfixed_const(1000);
1050         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1051         line_time.full = dfixed_div(line_time, a);
1052         bpp.full = dfixed_const(wm->bytes_per_pixel);
1053         src_width.full = dfixed_const(wm->src_width);
1054         bandwidth.full = dfixed_mul(src_width, bpp);
1055         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1056         bandwidth.full = dfixed_div(bandwidth, line_time);
1057
1058         return dfixed_trunc(bandwidth);
1059 }
1060
1061 /**
1062  * dce_v10_0_latency_watermark - get the latency watermark
1063  *
1064  * @wm: watermark calculation data
1065  *
1066  * Calculate the latency watermark (CIK).
1067  * Used for display watermark bandwidth calculations
1068  * Returns the latency watermark in ns
1069  */
1070 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1071 {
1072         /* First calculate the latency in ns */
1073         u32 mc_latency = 2000; /* 2000 ns. */
1074         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1075         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1076         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1077         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1078         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1079                 (wm->num_heads * cursor_line_pair_return_time);
1080         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1081         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1082         u32 tmp, dmif_size = 12288;
1083         fixed20_12 a, b, c;
1084
1085         if (wm->num_heads == 0)
1086                 return 0;
1087
1088         a.full = dfixed_const(2);
1089         b.full = dfixed_const(1);
1090         if ((wm->vsc.full > a.full) ||
1091             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1092             (wm->vtaps >= 5) ||
1093             ((wm->vsc.full >= a.full) && wm->interlaced))
1094                 max_src_lines_per_dst_line = 4;
1095         else
1096                 max_src_lines_per_dst_line = 2;
1097
1098         a.full = dfixed_const(available_bandwidth);
1099         b.full = dfixed_const(wm->num_heads);
1100         a.full = dfixed_div(a, b);
1101
1102         b.full = dfixed_const(mc_latency + 512);
1103         c.full = dfixed_const(wm->disp_clk);
1104         b.full = dfixed_div(b, c);
1105
1106         c.full = dfixed_const(dmif_size);
1107         b.full = dfixed_div(c, b);
1108
1109         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1110
1111         b.full = dfixed_const(1000);
1112         c.full = dfixed_const(wm->disp_clk);
1113         b.full = dfixed_div(c, b);
1114         c.full = dfixed_const(wm->bytes_per_pixel);
1115         b.full = dfixed_mul(b, c);
1116
1117         lb_fill_bw = min(tmp, dfixed_trunc(b));
1118
1119         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1120         b.full = dfixed_const(1000);
1121         c.full = dfixed_const(lb_fill_bw);
1122         b.full = dfixed_div(c, b);
1123         a.full = dfixed_div(a, b);
1124         line_fill_time = dfixed_trunc(a);
1125
1126         if (line_fill_time < wm->active_time)
1127                 return latency;
1128         else
1129                 return latency + (line_fill_time - wm->active_time);
1130
1131 }
1132
1133 /**
1134  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1135  * average and available dram bandwidth
1136  *
1137  * @wm: watermark calculation data
1138  *
1139  * Check if the display average bandwidth fits in the display
1140  * dram bandwidth (CIK).
1141  * Used for display watermark bandwidth calculations
1142  * Returns true if the display fits, false if not.
1143  */
1144 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1145 {
1146         if (dce_v10_0_average_bandwidth(wm) <=
1147             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1148                 return true;
1149         else
1150                 return false;
1151 }
1152
1153 /**
1154  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1155  * average and available bandwidth
1156  *
1157  * @wm: watermark calculation data
1158  *
1159  * Check if the display average bandwidth fits in the display
1160  * available bandwidth (CIK).
1161  * Used for display watermark bandwidth calculations
1162  * Returns true if the display fits, false if not.
1163  */
1164 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1165 {
1166         if (dce_v10_0_average_bandwidth(wm) <=
1167             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1168                 return true;
1169         else
1170                 return false;
1171 }
1172
1173 /**
1174  * dce_v10_0_check_latency_hiding - check latency hiding
1175  *
1176  * @wm: watermark calculation data
1177  *
1178  * Check latency hiding (CIK).
1179  * Used for display watermark bandwidth calculations
1180  * Returns true if the display fits, false if not.
1181  */
1182 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1183 {
1184         u32 lb_partitions = wm->lb_size / wm->src_width;
1185         u32 line_time = wm->active_time + wm->blank_time;
1186         u32 latency_tolerant_lines;
1187         u32 latency_hiding;
1188         fixed20_12 a;
1189
1190         a.full = dfixed_const(1);
1191         if (wm->vsc.full > a.full)
1192                 latency_tolerant_lines = 1;
1193         else {
1194                 if (lb_partitions <= (wm->vtaps + 1))
1195                         latency_tolerant_lines = 1;
1196                 else
1197                         latency_tolerant_lines = 2;
1198         }
1199
1200         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1201
1202         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1203                 return true;
1204         else
1205                 return false;
1206 }
1207
1208 /**
1209  * dce_v10_0_program_watermarks - program display watermarks
1210  *
1211  * @adev: amdgpu_device pointer
1212  * @amdgpu_crtc: the selected display controller
1213  * @lb_size: line buffer size
1214  * @num_heads: number of display controllers in use
1215  *
1216  * Calculate and program the display watermarks for the
1217  * selected display controller (CIK).
1218  */
1219 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1220                                         struct amdgpu_crtc *amdgpu_crtc,
1221                                         u32 lb_size, u32 num_heads)
1222 {
1223         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1224         struct dce10_wm_params wm_low, wm_high;
1225         u32 pixel_period;
1226         u32 line_time = 0;
1227         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1228         u32 tmp, wm_mask;
1229
1230         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1231                 pixel_period = 1000000 / (u32)mode->clock;
1232                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1233
1234                 /* watermark for high clocks */
1235                 if (adev->pm.dpm_enabled) {
1236                         wm_high.yclk =
1237                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1238                         wm_high.sclk =
1239                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1240                 } else {
1241                         wm_high.yclk = adev->pm.current_mclk * 10;
1242                         wm_high.sclk = adev->pm.current_sclk * 10;
1243                 }
1244
1245                 wm_high.disp_clk = mode->clock;
1246                 wm_high.src_width = mode->crtc_hdisplay;
1247                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1248                 wm_high.blank_time = line_time - wm_high.active_time;
1249                 wm_high.interlaced = false;
1250                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1251                         wm_high.interlaced = true;
1252                 wm_high.vsc = amdgpu_crtc->vsc;
1253                 wm_high.vtaps = 1;
1254                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1255                         wm_high.vtaps = 2;
1256                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1257                 wm_high.lb_size = lb_size;
1258                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1259                 wm_high.num_heads = num_heads;
1260
1261                 /* set for high clocks */
1262                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1263
1264                 /* possibly force display priority to high */
1265                 /* should really do this at mode validation time... */
1266                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1267                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1268                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1269                     (adev->mode_info.disp_priority == 2)) {
1270                         DRM_DEBUG_KMS("force priority to high\n");
1271                 }
1272
1273                 /* watermark for low clocks */
1274                 if (adev->pm.dpm_enabled) {
1275                         wm_low.yclk =
1276                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1277                         wm_low.sclk =
1278                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1279                 } else {
1280                         wm_low.yclk = adev->pm.current_mclk * 10;
1281                         wm_low.sclk = adev->pm.current_sclk * 10;
1282                 }
1283
1284                 wm_low.disp_clk = mode->clock;
1285                 wm_low.src_width = mode->crtc_hdisplay;
1286                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1287                 wm_low.blank_time = line_time - wm_low.active_time;
1288                 wm_low.interlaced = false;
1289                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1290                         wm_low.interlaced = true;
1291                 wm_low.vsc = amdgpu_crtc->vsc;
1292                 wm_low.vtaps = 1;
1293                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1294                         wm_low.vtaps = 2;
1295                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1296                 wm_low.lb_size = lb_size;
1297                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1298                 wm_low.num_heads = num_heads;
1299
1300                 /* set for low clocks */
1301                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1302
1303                 /* possibly force display priority to high */
1304                 /* should really do this at mode validation time... */
1305                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1306                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1307                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1308                     (adev->mode_info.disp_priority == 2)) {
1309                         DRM_DEBUG_KMS("force priority to high\n");
1310                 }
1311         }
1312
1313         /* select wm A */
1314         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1315         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1316         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1317         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1318         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1319         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1320         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1321         /* select wm B */
1322         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1323         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1324         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1325         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1326         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1327         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1328         /* restore original selection */
1329         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1330
1331         /* save values for DPM */
1332         amdgpu_crtc->line_time = line_time;
1333         amdgpu_crtc->wm_high = latency_watermark_a;
1334         amdgpu_crtc->wm_low = latency_watermark_b;
1335 }
1336
1337 /**
1338  * dce_v10_0_bandwidth_update - program display watermarks
1339  *
1340  * @adev: amdgpu_device pointer
1341  *
1342  * Calculate and program the display watermarks and line
1343  * buffer allocation (CIK).
1344  */
1345 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1346 {
1347         struct drm_display_mode *mode = NULL;
1348         u32 num_heads = 0, lb_size;
1349         int i;
1350
1351         amdgpu_update_display_priority(adev);
1352
1353         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1354                 if (adev->mode_info.crtcs[i]->base.enabled)
1355                         num_heads++;
1356         }
1357         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1358                 mode = &adev->mode_info.crtcs[i]->base.mode;
1359                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1360                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1361                                             lb_size, num_heads);
1362         }
1363 }
1364
1365 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1366 {
1367         int i;
1368         u32 offset, tmp;
1369
1370         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1371                 offset = adev->mode_info.audio.pin[i].offset;
1372                 tmp = RREG32_AUDIO_ENDPT(offset,
1373                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1374                 if (((tmp &
1375                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1376                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1377                         adev->mode_info.audio.pin[i].connected = false;
1378                 else
1379                         adev->mode_info.audio.pin[i].connected = true;
1380         }
1381 }
1382
1383 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1384 {
1385         int i;
1386
1387         dce_v10_0_audio_get_connected_pins(adev);
1388
1389         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1390                 if (adev->mode_info.audio.pin[i].connected)
1391                         return &adev->mode_info.audio.pin[i];
1392         }
1393         DRM_ERROR("No connected audio pins found!\n");
1394         return NULL;
1395 }
1396
1397 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1398 {
1399         struct amdgpu_device *adev = encoder->dev->dev_private;
1400         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1401         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1402         u32 tmp;
1403
1404         if (!dig || !dig->afmt || !dig->afmt->pin)
1405                 return;
1406
1407         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1408         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1409         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1410 }
1411
1412 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1413                                                 struct drm_display_mode *mode)
1414 {
1415         struct amdgpu_device *adev = encoder->dev->dev_private;
1416         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1417         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1418         struct drm_connector *connector;
1419         struct amdgpu_connector *amdgpu_connector = NULL;
1420         u32 tmp;
1421         int interlace = 0;
1422
1423         if (!dig || !dig->afmt || !dig->afmt->pin)
1424                 return;
1425
1426         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1427                 if (connector->encoder == encoder) {
1428                         amdgpu_connector = to_amdgpu_connector(connector);
1429                         break;
1430                 }
1431         }
1432
1433         if (!amdgpu_connector) {
1434                 DRM_ERROR("Couldn't find encoder's connector\n");
1435                 return;
1436         }
1437
1438         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1439                 interlace = 1;
1440         if (connector->latency_present[interlace]) {
1441                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1442                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1443                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1444                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1445         } else {
1446                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1447                                     VIDEO_LIPSYNC, 0);
1448                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1449                                     AUDIO_LIPSYNC, 0);
1450         }
1451         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1452                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1453 }
1454
1455 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1456 {
1457         struct amdgpu_device *adev = encoder->dev->dev_private;
1458         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1459         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1460         struct drm_connector *connector;
1461         struct amdgpu_connector *amdgpu_connector = NULL;
1462         u32 tmp;
1463         u8 *sadb = NULL;
1464         int sad_count;
1465
1466         if (!dig || !dig->afmt || !dig->afmt->pin)
1467                 return;
1468
1469         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1470                 if (connector->encoder == encoder) {
1471                         amdgpu_connector = to_amdgpu_connector(connector);
1472                         break;
1473                 }
1474         }
1475
1476         if (!amdgpu_connector) {
1477                 DRM_ERROR("Couldn't find encoder's connector\n");
1478                 return;
1479         }
1480
1481         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1482         if (sad_count < 0) {
1483                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1484                 sad_count = 0;
1485         }
1486
1487         /* program the speaker allocation */
1488         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1489                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1490         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1491                             DP_CONNECTION, 0);
1492         /* set HDMI mode */
1493         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1494                             HDMI_CONNECTION, 1);
1495         if (sad_count)
1496                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1497                                     SPEAKER_ALLOCATION, sadb[0]);
1498         else
1499                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1500                                     SPEAKER_ALLOCATION, 5); /* stereo */
1501         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1502                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1503
1504         kfree(sadb);
1505 }
1506
1507 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1508 {
1509         struct amdgpu_device *adev = encoder->dev->dev_private;
1510         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1511         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1512         struct drm_connector *connector;
1513         struct amdgpu_connector *amdgpu_connector = NULL;
1514         struct cea_sad *sads;
1515         int i, sad_count;
1516
1517         static const u16 eld_reg_to_type[][2] = {
1518                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1519                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1520                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1521                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1522                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1523                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1524                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1525                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1526                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1527                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1528                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1529                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1530         };
1531
1532         if (!dig || !dig->afmt || !dig->afmt->pin)
1533                 return;
1534
1535         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1536                 if (connector->encoder == encoder) {
1537                         amdgpu_connector = to_amdgpu_connector(connector);
1538                         break;
1539                 }
1540         }
1541
1542         if (!amdgpu_connector) {
1543                 DRM_ERROR("Couldn't find encoder's connector\n");
1544                 return;
1545         }
1546
1547         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1548         if (sad_count <= 0) {
1549                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1550                 return;
1551         }
1552         BUG_ON(!sads);
1553
1554         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1555                 u32 tmp = 0;
1556                 u8 stereo_freqs = 0;
1557                 int max_channels = -1;
1558                 int j;
1559
1560                 for (j = 0; j < sad_count; j++) {
1561                         struct cea_sad *sad = &sads[j];
1562
1563                         if (sad->format == eld_reg_to_type[i][1]) {
1564                                 if (sad->channels > max_channels) {
1565                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1566                                                             MAX_CHANNELS, sad->channels);
1567                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1568                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1569                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1570                                                             SUPPORTED_FREQUENCIES, sad->freq);
1571                                         max_channels = sad->channels;
1572                                 }
1573
1574                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1575                                         stereo_freqs |= sad->freq;
1576                                 else
1577                                         break;
1578                         }
1579                 }
1580
1581                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1582                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1583                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1584         }
1585
1586         kfree(sads);
1587 }
1588
1589 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1590                                   struct amdgpu_audio_pin *pin,
1591                                   bool enable)
1592 {
1593         if (!pin)
1594                 return;
1595
1596         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1597                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1598 }
1599
1600 static const u32 pin_offsets[] =
1601 {
1602         AUD0_REGISTER_OFFSET,
1603         AUD1_REGISTER_OFFSET,
1604         AUD2_REGISTER_OFFSET,
1605         AUD3_REGISTER_OFFSET,
1606         AUD4_REGISTER_OFFSET,
1607         AUD5_REGISTER_OFFSET,
1608         AUD6_REGISTER_OFFSET,
1609 };
1610
1611 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1612 {
1613         int i;
1614
1615         if (!amdgpu_audio)
1616                 return 0;
1617
1618         adev->mode_info.audio.enabled = true;
1619
1620         adev->mode_info.audio.num_pins = 7;
1621
1622         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1623                 adev->mode_info.audio.pin[i].channels = -1;
1624                 adev->mode_info.audio.pin[i].rate = -1;
1625                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1626                 adev->mode_info.audio.pin[i].status_bits = 0;
1627                 adev->mode_info.audio.pin[i].category_code = 0;
1628                 adev->mode_info.audio.pin[i].connected = false;
1629                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1630                 adev->mode_info.audio.pin[i].id = i;
1631                 /* disable audio.  it will be set up later */
1632                 /* XXX remove once we switch to ip funcs */
1633                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1634         }
1635
1636         return 0;
1637 }
1638
1639 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1640 {
1641         int i;
1642
1643         if (!adev->mode_info.audio.enabled)
1644                 return;
1645
1646         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1647                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1648
1649         adev->mode_info.audio.enabled = false;
1650 }
1651
1652 /*
1653  * update the N and CTS parameters for a given pixel clock rate
1654  */
1655 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1656 {
1657         struct drm_device *dev = encoder->dev;
1658         struct amdgpu_device *adev = dev->dev_private;
1659         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1660         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1661         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1662         u32 tmp;
1663
1664         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1665         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1666         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1667         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1668         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1669         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1670
1671         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1672         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1673         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1674         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1675         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1676         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1677
1678         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1679         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1680         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1681         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1682         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1683         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1684
1685 }
1686
1687 /*
1688  * build a HDMI Video Info Frame
1689  */
1690 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1691                                                void *buffer, size_t size)
1692 {
1693         struct drm_device *dev = encoder->dev;
1694         struct amdgpu_device *adev = dev->dev_private;
1695         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1696         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1697         uint8_t *frame = buffer + 3;
1698         uint8_t *header = buffer;
1699
1700         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1701                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1702         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1703                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1704         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1705                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1706         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1707                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1708 }
1709
1710 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1711 {
1712         struct drm_device *dev = encoder->dev;
1713         struct amdgpu_device *adev = dev->dev_private;
1714         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1715         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1716         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1717         u32 dto_phase = 24 * 1000;
1718         u32 dto_modulo = clock;
1719         u32 tmp;
1720
1721         if (!dig || !dig->afmt)
1722                 return;
1723
1724         /* XXX two dtos; generally use dto0 for hdmi */
1725         /* Express [24MHz / target pixel clock] as an exact rational
1726          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1727          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1728          */
1729         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1730         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1731                             amdgpu_crtc->crtc_id);
1732         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1733         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1734         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1735 }
1736
1737 /*
1738  * update the info frames with the data from the current display mode
1739  */
1740 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1741                                   struct drm_display_mode *mode)
1742 {
1743         struct drm_device *dev = encoder->dev;
1744         struct amdgpu_device *adev = dev->dev_private;
1745         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1746         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1747         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1748         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1749         struct hdmi_avi_infoframe frame;
1750         ssize_t err;
1751         u32 tmp;
1752         int bpc = 8;
1753
1754         if (!dig || !dig->afmt)
1755                 return;
1756
1757         /* Silent, r600_hdmi_enable will raise WARN for us */
1758         if (!dig->afmt->enabled)
1759                 return;
1760
1761         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1762         if (encoder->crtc) {
1763                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1764                 bpc = amdgpu_crtc->bpc;
1765         }
1766
1767         /* disable audio prior to setting up hw */
1768         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1769         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1770
1771         dce_v10_0_audio_set_dto(encoder, mode->clock);
1772
1773         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1774         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1775         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1776
1777         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1778
1779         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1780         switch (bpc) {
1781         case 0:
1782         case 6:
1783         case 8:
1784         case 16:
1785         default:
1786                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1787                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1788                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1789                           connector->name, bpc);
1790                 break;
1791         case 10:
1792                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1793                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1794                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1795                           connector->name);
1796                 break;
1797         case 12:
1798                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1799                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1800                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1801                           connector->name);
1802                 break;
1803         }
1804         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1805
1806         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1807         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1808         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1809         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1810         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1811
1812         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1813         /* enable audio info frames (frames won't be set until audio is enabled) */
1814         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1815         /* required for audio info values to be updated */
1816         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1817         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1818
1819         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1820         /* required for audio info values to be updated */
1821         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1822         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1823
1824         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1825         /* anything other than 0 */
1826         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1827         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1828
1829         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1830
1831         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1832         /* set the default audio delay */
1833         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1834         /* should be suffient for all audio modes and small enough for all hblanks */
1835         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1836         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1837
1838         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1839         /* allow 60958 channel status fields to be updated */
1840         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1841         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1842
1843         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1844         if (bpc > 8)
1845                 /* clear SW CTS value */
1846                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1847         else
1848                 /* select SW CTS value */
1849                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1850         /* allow hw to sent ACR packets when required */
1851         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1852         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1853
1854         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1855
1856         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1857         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1858         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1859
1860         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1861         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1862         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1863
1864         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1865         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1866         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1867         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1868         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1869         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1870         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1871         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1872
1873         dce_v10_0_audio_write_speaker_allocation(encoder);
1874
1875         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1876                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1877
1878         dce_v10_0_afmt_audio_select_pin(encoder);
1879         dce_v10_0_audio_write_sad_regs(encoder);
1880         dce_v10_0_audio_write_latency_fields(encoder, mode);
1881
1882         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1883         if (err < 0) {
1884                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1885                 return;
1886         }
1887
1888         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1889         if (err < 0) {
1890                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1891                 return;
1892         }
1893
1894         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1895
1896         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1897         /* enable AVI info frames */
1898         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1899         /* required for audio info values to be updated */
1900         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1901         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1902
1903         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1904         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1905         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1906
1907         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1908         /* send audio packets */
1909         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1910         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1911
1912         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1913         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1914         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1915         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1916
1917         /* enable audio after to setting up hw */
1918         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1919 }
1920
1921 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1922 {
1923         struct drm_device *dev = encoder->dev;
1924         struct amdgpu_device *adev = dev->dev_private;
1925         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1926         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1927
1928         if (!dig || !dig->afmt)
1929                 return;
1930
1931         /* Silent, r600_hdmi_enable will raise WARN for us */
1932         if (enable && dig->afmt->enabled)
1933                 return;
1934         if (!enable && !dig->afmt->enabled)
1935                 return;
1936
1937         if (!enable && dig->afmt->pin) {
1938                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1939                 dig->afmt->pin = NULL;
1940         }
1941
1942         dig->afmt->enabled = enable;
1943
1944         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1945                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1946 }
1947
1948 static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
1949 {
1950         int i;
1951
1952         for (i = 0; i < adev->mode_info.num_dig; i++)
1953                 adev->mode_info.afmt[i] = NULL;
1954
1955         /* DCE10 has audio blocks tied to DIG encoders */
1956         for (i = 0; i < adev->mode_info.num_dig; i++) {
1957                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1958                 if (adev->mode_info.afmt[i]) {
1959                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1960                         adev->mode_info.afmt[i]->id = i;
1961                 }
1962         }
1963 }
1964
1965 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1966 {
1967         int i;
1968
1969         for (i = 0; i < adev->mode_info.num_dig; i++) {
1970                 kfree(adev->mode_info.afmt[i]);
1971                 adev->mode_info.afmt[i] = NULL;
1972         }
1973 }
1974
1975 static const u32 vga_control_regs[6] =
1976 {
1977         mmD1VGA_CONTROL,
1978         mmD2VGA_CONTROL,
1979         mmD3VGA_CONTROL,
1980         mmD4VGA_CONTROL,
1981         mmD5VGA_CONTROL,
1982         mmD6VGA_CONTROL,
1983 };
1984
1985 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1986 {
1987         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1988         struct drm_device *dev = crtc->dev;
1989         struct amdgpu_device *adev = dev->dev_private;
1990         u32 vga_control;
1991
1992         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1993         if (enable)
1994                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1995         else
1996                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1997 }
1998
1999 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2000 {
2001         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2002         struct drm_device *dev = crtc->dev;
2003         struct amdgpu_device *adev = dev->dev_private;
2004
2005         if (enable)
2006                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2007         else
2008                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2009 }
2010
2011 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2012                                      struct drm_framebuffer *fb,
2013                                      int x, int y, int atomic)
2014 {
2015         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2016         struct drm_device *dev = crtc->dev;
2017         struct amdgpu_device *adev = dev->dev_private;
2018         struct amdgpu_framebuffer *amdgpu_fb;
2019         struct drm_framebuffer *target_fb;
2020         struct drm_gem_object *obj;
2021         struct amdgpu_bo *rbo;
2022         uint64_t fb_location, tiling_flags;
2023         uint32_t fb_format, fb_pitch_pixels;
2024         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2025         u32 pipe_config;
2026         u32 tmp, viewport_w, viewport_h;
2027         int r;
2028         bool bypass_lut = false;
2029
2030         /* no fb bound */
2031         if (!atomic && !crtc->primary->fb) {
2032                 DRM_DEBUG_KMS("No FB bound\n");
2033                 return 0;
2034         }
2035
2036         if (atomic) {
2037                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2038                 target_fb = fb;
2039         }
2040         else {
2041                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2042                 target_fb = crtc->primary->fb;
2043         }
2044
2045         /* If atomic, assume fb object is pinned & idle & fenced and
2046          * just update base pointers
2047          */
2048         obj = amdgpu_fb->obj;
2049         rbo = gem_to_amdgpu_bo(obj);
2050         r = amdgpu_bo_reserve(rbo, false);
2051         if (unlikely(r != 0))
2052                 return r;
2053
2054         if (atomic)
2055                 fb_location = amdgpu_bo_gpu_offset(rbo);
2056         else {
2057                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2058                 if (unlikely(r != 0)) {
2059                         amdgpu_bo_unreserve(rbo);
2060                         return -EINVAL;
2061                 }
2062         }
2063
2064         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2065         amdgpu_bo_unreserve(rbo);
2066
2067         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2068
2069         switch (target_fb->pixel_format) {
2070         case DRM_FORMAT_C8:
2071                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2072                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2073                 break;
2074         case DRM_FORMAT_XRGB4444:
2075         case DRM_FORMAT_ARGB4444:
2076                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2077                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2078 #ifdef __BIG_ENDIAN
2079                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2080                                         ENDIAN_8IN16);
2081 #endif
2082                 break;
2083         case DRM_FORMAT_XRGB1555:
2084         case DRM_FORMAT_ARGB1555:
2085                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2086                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2087 #ifdef __BIG_ENDIAN
2088                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2089                                         ENDIAN_8IN16);
2090 #endif
2091                 break;
2092         case DRM_FORMAT_BGRX5551:
2093         case DRM_FORMAT_BGRA5551:
2094                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2095                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2096 #ifdef __BIG_ENDIAN
2097                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2098                                         ENDIAN_8IN16);
2099 #endif
2100                 break;
2101         case DRM_FORMAT_RGB565:
2102                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2103                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2104 #ifdef __BIG_ENDIAN
2105                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2106                                         ENDIAN_8IN16);
2107 #endif
2108                 break;
2109         case DRM_FORMAT_XRGB8888:
2110         case DRM_FORMAT_ARGB8888:
2111                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2112                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2113 #ifdef __BIG_ENDIAN
2114                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2115                                         ENDIAN_8IN32);
2116 #endif
2117                 break;
2118         case DRM_FORMAT_XRGB2101010:
2119         case DRM_FORMAT_ARGB2101010:
2120                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2121                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2122 #ifdef __BIG_ENDIAN
2123                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2124                                         ENDIAN_8IN32);
2125 #endif
2126                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2127                 bypass_lut = true;
2128                 break;
2129         case DRM_FORMAT_BGRX1010102:
2130         case DRM_FORMAT_BGRA1010102:
2131                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2132                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2133 #ifdef __BIG_ENDIAN
2134                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2135                                         ENDIAN_8IN32);
2136 #endif
2137                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2138                 bypass_lut = true;
2139                 break;
2140         default:
2141                 DRM_ERROR("Unsupported screen format %s\n",
2142                         drm_get_format_name(target_fb->pixel_format));
2143                 return -EINVAL;
2144         }
2145
2146         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2147                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2148
2149                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2150                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2151                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2152                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2153                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2154
2155                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2156                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2157                                           ARRAY_2D_TILED_THIN1);
2158                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2159                                           tile_split);
2160                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2161                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2162                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2163                                           mtaspect);
2164                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2165                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2166         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2167                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2168                                           ARRAY_1D_TILED_THIN1);
2169         }
2170
2171         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2172                                   pipe_config);
2173
2174         dce_v10_0_vga_enable(crtc, false);
2175
2176         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2177                upper_32_bits(fb_location));
2178         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2179                upper_32_bits(fb_location));
2180         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2181                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2182         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2183                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2184         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2185         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2186
2187         /*
2188          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2189          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2190          * retain the full precision throughout the pipeline.
2191          */
2192         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2193         if (bypass_lut)
2194                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2195         else
2196                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2197         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2198
2199         if (bypass_lut)
2200                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2201
2202         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2203         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2204         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2205         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2206         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2207         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2208
2209         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2210         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2211
2212         dce_v10_0_grph_enable(crtc, true);
2213
2214         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2215                target_fb->height);
2216
2217         x &= ~3;
2218         y &= ~1;
2219         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2220                (x << 16) | y);
2221         viewport_w = crtc->mode.hdisplay;
2222         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2223         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2224                (viewport_w << 16) | viewport_h);
2225
2226         /* pageflip setup */
2227         /* make sure flip is at vb rather than hb */
2228         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2229         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2230                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2231         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2232
2233         /* set pageflip to happen only at start of vblank interval (front porch) */
2234         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2235
2236         if (!atomic && fb && fb != crtc->primary->fb) {
2237                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2238                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2239                 r = amdgpu_bo_reserve(rbo, false);
2240                 if (unlikely(r != 0))
2241                         return r;
2242                 amdgpu_bo_unpin(rbo);
2243                 amdgpu_bo_unreserve(rbo);
2244         }
2245
2246         /* Bytes per pixel may have changed */
2247         dce_v10_0_bandwidth_update(adev);
2248
2249         return 0;
2250 }
2251
2252 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2253                                      struct drm_display_mode *mode)
2254 {
2255         struct drm_device *dev = crtc->dev;
2256         struct amdgpu_device *adev = dev->dev_private;
2257         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2258         u32 tmp;
2259
2260         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2261         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2262                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2263         else
2264                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2265         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2266 }
2267
2268 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2269 {
2270         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2271         struct drm_device *dev = crtc->dev;
2272         struct amdgpu_device *adev = dev->dev_private;
2273         int i;
2274         u32 tmp;
2275
2276         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2277
2278         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2279         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2280         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2281         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2282
2283         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2284         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2285         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2286
2287         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2288         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2289         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2290
2291         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2292         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2293         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2294         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2295
2296         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2297
2298         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2299         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2300         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2301
2302         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2303         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2304         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2305
2306         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2307         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2308
2309         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2310         for (i = 0; i < 256; i++) {
2311                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2312                        (amdgpu_crtc->lut_r[i] << 20) |
2313                        (amdgpu_crtc->lut_g[i] << 10) |
2314                        (amdgpu_crtc->lut_b[i] << 0));
2315         }
2316
2317         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2318         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2319         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2320         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2321         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2322
2323         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2324         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2325         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2326         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2327
2328         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2329         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2330         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2331         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2332
2333         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2334         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2335         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2336         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2337
2338         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2339         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2340         /* XXX this only needs to be programmed once per crtc at startup,
2341          * not sure where the best place for it is
2342          */
2343         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2344         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2345         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2346 }
2347
2348 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2349 {
2350         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2351         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2352
2353         switch (amdgpu_encoder->encoder_id) {
2354         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2355                 if (dig->linkb)
2356                         return 1;
2357                 else
2358                         return 0;
2359                 break;
2360         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2361                 if (dig->linkb)
2362                         return 3;
2363                 else
2364                         return 2;
2365                 break;
2366         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2367                 if (dig->linkb)
2368                         return 5;
2369                 else
2370                         return 4;
2371                 break;
2372         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2373                 return 6;
2374                 break;
2375         default:
2376                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2377                 return 0;
2378         }
2379 }
2380
2381 /**
2382  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2383  *
2384  * @crtc: drm crtc
2385  *
2386  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2387  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2388  * monitors a dedicated PPLL must be used.  If a particular board has
2389  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2390  * as there is no need to program the PLL itself.  If we are not able to
2391  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2392  * avoid messing up an existing monitor.
2393  *
2394  * Asic specific PLL information
2395  *
2396  * DCE 10.x
2397  * Tonga
2398  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2399  * CI
2400  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2401  *
2402  */
2403 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2404 {
2405         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2406         struct drm_device *dev = crtc->dev;
2407         struct amdgpu_device *adev = dev->dev_private;
2408         u32 pll_in_use;
2409         int pll;
2410
2411         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2412                 if (adev->clock.dp_extclk)
2413                         /* skip PPLL programming if using ext clock */
2414                         return ATOM_PPLL_INVALID;
2415                 else {
2416                         /* use the same PPLL for all DP monitors */
2417                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2418                         if (pll != ATOM_PPLL_INVALID)
2419                                 return pll;
2420                 }
2421         } else {
2422                 /* use the same PPLL for all monitors with the same clock */
2423                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2424                 if (pll != ATOM_PPLL_INVALID)
2425                         return pll;
2426         }
2427
2428         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2429         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2430         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2431                 return ATOM_PPLL2;
2432         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2433                 return ATOM_PPLL1;
2434         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2435                 return ATOM_PPLL0;
2436         DRM_ERROR("unable to allocate a PPLL\n");
2437         return ATOM_PPLL_INVALID;
2438 }
2439
2440 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2441 {
2442         struct amdgpu_device *adev = crtc->dev->dev_private;
2443         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2444         uint32_t cur_lock;
2445
2446         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2447         if (lock)
2448                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2449         else
2450                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2451         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2452 }
2453
2454 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2455 {
2456         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2457         struct amdgpu_device *adev = crtc->dev->dev_private;
2458         u32 tmp;
2459
2460         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2461         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2462         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2463 }
2464
2465 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2466 {
2467         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2468         struct amdgpu_device *adev = crtc->dev->dev_private;
2469         u32 tmp;
2470
2471         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2472         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2473         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2474         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2475 }
2476
2477 static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
2478                               uint64_t gpu_addr)
2479 {
2480         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2481         struct amdgpu_device *adev = crtc->dev->dev_private;
2482
2483         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2484                upper_32_bits(gpu_addr));
2485         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2486                lower_32_bits(gpu_addr));
2487 }
2488
2489 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2490                                      int x, int y)
2491 {
2492         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2493         struct amdgpu_device *adev = crtc->dev->dev_private;
2494         int xorigin = 0, yorigin = 0;
2495
2496         /* avivo cursor are offset into the total surface */
2497         x += crtc->x;
2498         y += crtc->y;
2499         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2500
2501         if (x < 0) {
2502                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2503                 x = 0;
2504         }
2505         if (y < 0) {
2506                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2507                 y = 0;
2508         }
2509
2510         dce_v10_0_lock_cursor(crtc, true);
2511         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2512         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2513         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2514                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2515         dce_v10_0_lock_cursor(crtc, false);
2516
2517         return 0;
2518 }
2519
2520 static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc,
2521                                     struct drm_file *file_priv,
2522                                     uint32_t handle,
2523                                     uint32_t width,
2524                                     uint32_t height)
2525 {
2526         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2527         struct drm_gem_object *obj;
2528         struct amdgpu_bo *robj;
2529         uint64_t gpu_addr;
2530         int ret;
2531
2532         if (!handle) {
2533                 /* turn off cursor */
2534                 dce_v10_0_hide_cursor(crtc);
2535                 obj = NULL;
2536                 goto unpin;
2537         }
2538
2539         if ((width > amdgpu_crtc->max_cursor_width) ||
2540             (height > amdgpu_crtc->max_cursor_height)) {
2541                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2542                 return -EINVAL;
2543         }
2544
2545         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2546         if (!obj) {
2547                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2548                 return -ENOENT;
2549         }
2550
2551         robj = gem_to_amdgpu_bo(obj);
2552         ret = amdgpu_bo_reserve(robj, false);
2553         if (unlikely(ret != 0))
2554                 goto fail;
2555         ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
2556                                        0, &gpu_addr);
2557         amdgpu_bo_unreserve(robj);
2558         if (ret)
2559                 goto fail;
2560
2561         amdgpu_crtc->cursor_width = width;
2562         amdgpu_crtc->cursor_height = height;
2563
2564         dce_v10_0_lock_cursor(crtc, true);
2565         dce_v10_0_set_cursor(crtc, obj, gpu_addr);
2566         dce_v10_0_show_cursor(crtc);
2567         dce_v10_0_lock_cursor(crtc, false);
2568
2569 unpin:
2570         if (amdgpu_crtc->cursor_bo) {
2571                 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2572                 ret = amdgpu_bo_reserve(robj, false);
2573                 if (likely(ret == 0)) {
2574                         amdgpu_bo_unpin(robj);
2575                         amdgpu_bo_unreserve(robj);
2576                 }
2577                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2578         }
2579
2580         amdgpu_crtc->cursor_bo = obj;
2581         return 0;
2582 fail:
2583         drm_gem_object_unreference_unlocked(obj);
2584
2585         return ret;
2586 }
2587
2588 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2589                                     u16 *blue, uint32_t start, uint32_t size)
2590 {
2591         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2592         int end = (start + size > 256) ? 256 : start + size, i;
2593
2594         /* userspace palettes are always correct as is */
2595         for (i = start; i < end; i++) {
2596                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2597                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2598                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2599         }
2600         dce_v10_0_crtc_load_lut(crtc);
2601 }
2602
2603 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2604 {
2605         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2606
2607         drm_crtc_cleanup(crtc);
2608         destroy_workqueue(amdgpu_crtc->pflip_queue);
2609         kfree(amdgpu_crtc);
2610 }
2611
2612 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2613         .cursor_set = dce_v10_0_crtc_cursor_set,
2614         .cursor_move = dce_v10_0_crtc_cursor_move,
2615         .gamma_set = dce_v10_0_crtc_gamma_set,
2616         .set_config = amdgpu_crtc_set_config,
2617         .destroy = dce_v10_0_crtc_destroy,
2618         .page_flip = amdgpu_crtc_page_flip,
2619 };
2620
2621 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2622 {
2623         struct drm_device *dev = crtc->dev;
2624         struct amdgpu_device *adev = dev->dev_private;
2625         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2626
2627         switch (mode) {
2628         case DRM_MODE_DPMS_ON:
2629                 amdgpu_crtc->enabled = true;
2630                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2631                 dce_v10_0_vga_enable(crtc, true);
2632                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2633                 dce_v10_0_vga_enable(crtc, false);
2634                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2635                 dce_v10_0_crtc_load_lut(crtc);
2636                 break;
2637         case DRM_MODE_DPMS_STANDBY:
2638         case DRM_MODE_DPMS_SUSPEND:
2639         case DRM_MODE_DPMS_OFF:
2640                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2641                 if (amdgpu_crtc->enabled) {
2642                         dce_v10_0_vga_enable(crtc, true);
2643                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2644                         dce_v10_0_vga_enable(crtc, false);
2645                 }
2646                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2647                 amdgpu_crtc->enabled = false;
2648                 break;
2649         }
2650         /* adjust pm to dpms */
2651         amdgpu_pm_compute_clocks(adev);
2652 }
2653
2654 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2655 {
2656         /* disable crtc pair power gating before programming */
2657         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2658         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2659         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2660 }
2661
2662 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2663 {
2664         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2665         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2666 }
2667
2668 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2669 {
2670         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2671         struct drm_device *dev = crtc->dev;
2672         struct amdgpu_device *adev = dev->dev_private;
2673         struct amdgpu_atom_ss ss;
2674         int i;
2675
2676         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2677         if (crtc->primary->fb) {
2678                 int r;
2679                 struct amdgpu_framebuffer *amdgpu_fb;
2680                 struct amdgpu_bo *rbo;
2681
2682                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2683                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2684                 r = amdgpu_bo_reserve(rbo, false);
2685                 if (unlikely(r))
2686                         DRM_ERROR("failed to reserve rbo before unpin\n");
2687                 else {
2688                         amdgpu_bo_unpin(rbo);
2689                         amdgpu_bo_unreserve(rbo);
2690                 }
2691         }
2692         /* disable the GRPH */
2693         dce_v10_0_grph_enable(crtc, false);
2694
2695         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2696
2697         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2698                 if (adev->mode_info.crtcs[i] &&
2699                     adev->mode_info.crtcs[i]->enabled &&
2700                     i != amdgpu_crtc->crtc_id &&
2701                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2702                         /* one other crtc is using this pll don't turn
2703                          * off the pll
2704                          */
2705                         goto done;
2706                 }
2707         }
2708
2709         switch (amdgpu_crtc->pll_id) {
2710         case ATOM_PPLL0:
2711         case ATOM_PPLL1:
2712         case ATOM_PPLL2:
2713                 /* disable the ppll */
2714                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2715                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2716                 break;
2717         default:
2718                 break;
2719         }
2720 done:
2721         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2722         amdgpu_crtc->adjusted_clock = 0;
2723         amdgpu_crtc->encoder = NULL;
2724         amdgpu_crtc->connector = NULL;
2725 }
2726
2727 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2728                                   struct drm_display_mode *mode,
2729                                   struct drm_display_mode *adjusted_mode,
2730                                   int x, int y, struct drm_framebuffer *old_fb)
2731 {
2732         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2733
2734         if (!amdgpu_crtc->adjusted_clock)
2735                 return -EINVAL;
2736
2737         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2738         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2739         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2740         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2741         amdgpu_atombios_crtc_scaler_setup(crtc);
2742         /* update the hw version fpr dpm */
2743         amdgpu_crtc->hw_mode = *adjusted_mode;
2744
2745         return 0;
2746 }
2747
2748 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2749                                      const struct drm_display_mode *mode,
2750                                      struct drm_display_mode *adjusted_mode)
2751 {
2752         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_encoder *encoder;
2755
2756         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2757         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2758                 if (encoder->crtc == crtc) {
2759                         amdgpu_crtc->encoder = encoder;
2760                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2761                         break;
2762                 }
2763         }
2764         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2765                 amdgpu_crtc->encoder = NULL;
2766                 amdgpu_crtc->connector = NULL;
2767                 return false;
2768         }
2769         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2770                 return false;
2771         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2772                 return false;
2773         /* pick pll */
2774         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2775         /* if we can't get a PPLL for a non-DP encoder, fail */
2776         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2777             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2778                 return false;
2779
2780         return true;
2781 }
2782
2783 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2784                                   struct drm_framebuffer *old_fb)
2785 {
2786         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2787 }
2788
2789 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2790                                          struct drm_framebuffer *fb,
2791                                          int x, int y, enum mode_set_atomic state)
2792 {
2793        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2794 }
2795
2796 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2797         .dpms = dce_v10_0_crtc_dpms,
2798         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2799         .mode_set = dce_v10_0_crtc_mode_set,
2800         .mode_set_base = dce_v10_0_crtc_set_base,
2801         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2802         .prepare = dce_v10_0_crtc_prepare,
2803         .commit = dce_v10_0_crtc_commit,
2804         .load_lut = dce_v10_0_crtc_load_lut,
2805         .disable = dce_v10_0_crtc_disable,
2806 };
2807
2808 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2809 {
2810         struct amdgpu_crtc *amdgpu_crtc;
2811         int i;
2812
2813         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2814                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2815         if (amdgpu_crtc == NULL)
2816                 return -ENOMEM;
2817
2818         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2819
2820         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2821         amdgpu_crtc->crtc_id = index;
2822         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2823         adev->mode_info.crtcs[index] = amdgpu_crtc;
2824
2825         amdgpu_crtc->max_cursor_width = 128;
2826         amdgpu_crtc->max_cursor_height = 128;
2827         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2828         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2829
2830         for (i = 0; i < 256; i++) {
2831                 amdgpu_crtc->lut_r[i] = i << 2;
2832                 amdgpu_crtc->lut_g[i] = i << 2;
2833                 amdgpu_crtc->lut_b[i] = i << 2;
2834         }
2835
2836         switch (amdgpu_crtc->crtc_id) {
2837         case 0:
2838         default:
2839                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2840                 break;
2841         case 1:
2842                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2843                 break;
2844         case 2:
2845                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2846                 break;
2847         case 3:
2848                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2849                 break;
2850         case 4:
2851                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2852                 break;
2853         case 5:
2854                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2855                 break;
2856         }
2857
2858         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2859         amdgpu_crtc->adjusted_clock = 0;
2860         amdgpu_crtc->encoder = NULL;
2861         amdgpu_crtc->connector = NULL;
2862         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2863
2864         return 0;
2865 }
2866
2867 static int dce_v10_0_early_init(struct amdgpu_device *adev)
2868 {
2869         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2870         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2871
2872         dce_v10_0_set_display_funcs(adev);
2873         dce_v10_0_set_irq_funcs(adev);
2874
2875         switch (adev->asic_type) {
2876         case CHIP_TONGA:
2877                 adev->mode_info.num_crtc = 6; /* XXX 7??? */
2878                 adev->mode_info.num_hpd = 6;
2879                 adev->mode_info.num_dig = 7;
2880                 break;
2881         default:
2882                 /* FIXME: not supported yet */
2883                 return -EINVAL;
2884         }
2885
2886         return 0;
2887 }
2888
2889 static int dce_v10_0_sw_init(struct amdgpu_device *adev)
2890 {
2891         int r, i;
2892
2893         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2894                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2895                 if (r)
2896                         return r;
2897         }
2898
2899         for (i = 8; i < 20; i += 2) {
2900                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2901                 if (r)
2902                         return r;
2903         }
2904
2905         /* HPD hotplug */
2906         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2907         if (r)
2908                 return r;
2909
2910         adev->mode_info.mode_config_initialized = true;
2911
2912         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2913
2914         adev->ddev->mode_config.max_width = 16384;
2915         adev->ddev->mode_config.max_height = 16384;
2916
2917         adev->ddev->mode_config.preferred_depth = 24;
2918         adev->ddev->mode_config.prefer_shadow = 1;
2919
2920         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2921
2922         r = amdgpu_modeset_create_props(adev);
2923         if (r)
2924                 return r;
2925
2926         adev->ddev->mode_config.max_width = 16384;
2927         adev->ddev->mode_config.max_height = 16384;
2928
2929         /* allocate crtcs */
2930         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2931                 r = dce_v10_0_crtc_init(adev, i);
2932                 if (r)
2933                         return r;
2934         }
2935
2936         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2937                 amdgpu_print_display_setup(adev->ddev);
2938         else
2939                 return -EINVAL;
2940
2941         /* setup afmt */
2942         dce_v10_0_afmt_init(adev);
2943
2944         r = dce_v10_0_audio_init(adev);
2945         if (r)
2946                 return r;
2947
2948         drm_kms_helper_poll_init(adev->ddev);
2949
2950         return r;
2951 }
2952
2953 static int dce_v10_0_sw_fini(struct amdgpu_device *adev)
2954 {
2955         kfree(adev->mode_info.bios_hardcoded_edid);
2956
2957         drm_kms_helper_poll_fini(adev->ddev);
2958
2959         dce_v10_0_audio_fini(adev);
2960
2961         dce_v10_0_afmt_fini(adev);
2962
2963         drm_mode_config_cleanup(adev->ddev);
2964         adev->mode_info.mode_config_initialized = false;
2965
2966         return 0;
2967 }
2968
2969 static int dce_v10_0_hw_init(struct amdgpu_device *adev)
2970 {
2971         int i;
2972
2973         dce_v10_0_init_golden_registers(adev);
2974
2975         /* init dig PHYs, disp eng pll */
2976         amdgpu_atombios_encoder_init_dig(adev);
2977         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2978
2979         /* initialize hpd */
2980         dce_v10_0_hpd_init(adev);
2981
2982         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2983                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2984         }
2985
2986         return 0;
2987 }
2988
2989 static int dce_v10_0_hw_fini(struct amdgpu_device *adev)
2990 {
2991         int i;
2992
2993         dce_v10_0_hpd_fini(adev);
2994
2995         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2996                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2997         }
2998
2999         return 0;
3000 }
3001
3002 static int dce_v10_0_suspend(struct amdgpu_device *adev)
3003 {
3004         struct drm_connector *connector;
3005
3006         drm_kms_helper_poll_disable(adev->ddev);
3007
3008         /* turn off display hw */
3009         list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
3010                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
3011         }
3012
3013         amdgpu_atombios_scratch_regs_save(adev);
3014
3015         dce_v10_0_hpd_fini(adev);
3016
3017         return 0;
3018 }
3019
3020 static int dce_v10_0_resume(struct amdgpu_device *adev)
3021 {
3022         struct drm_connector *connector;
3023
3024         dce_v10_0_init_golden_registers(adev);
3025
3026         amdgpu_atombios_scratch_regs_restore(adev);
3027
3028         /* init dig PHYs, disp eng pll */
3029         amdgpu_atombios_encoder_init_dig(adev);
3030         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3031         /* turn on the BL */
3032         if (adev->mode_info.bl_encoder) {
3033                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3034                                                                   adev->mode_info.bl_encoder);
3035                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3036                                                     bl_level);
3037         }
3038
3039         /* initialize hpd */
3040         dce_v10_0_hpd_init(adev);
3041
3042         /* blat the mode back in */
3043         drm_helper_resume_force_mode(adev->ddev);
3044         /* turn on display hw */
3045         list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
3046                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3047         }
3048
3049         drm_kms_helper_poll_enable(adev->ddev);
3050
3051         return 0;
3052 }
3053
3054 static bool dce_v10_0_is_idle(struct amdgpu_device *adev)
3055 {
3056         /* XXX todo */
3057         return true;
3058 }
3059
3060 static int dce_v10_0_wait_for_idle(struct amdgpu_device *adev)
3061 {
3062         /* XXX todo */
3063         return 0;
3064 }
3065
3066 static void dce_v10_0_print_status(struct amdgpu_device *adev)
3067 {
3068         dev_info(adev->dev, "DCE 10.x registers\n");
3069         /* XXX todo */
3070 }
3071
3072 static int dce_v10_0_soft_reset(struct amdgpu_device *adev)
3073 {
3074         u32 srbm_soft_reset = 0, tmp;
3075
3076         if (dce_v10_0_is_display_hung(adev))
3077                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3078
3079         if (srbm_soft_reset) {
3080                 dce_v10_0_print_status(adev);
3081
3082                 tmp = RREG32(mmSRBM_SOFT_RESET);
3083                 tmp |= srbm_soft_reset;
3084                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3085                 WREG32(mmSRBM_SOFT_RESET, tmp);
3086                 tmp = RREG32(mmSRBM_SOFT_RESET);
3087
3088                 udelay(50);
3089
3090                 tmp &= ~srbm_soft_reset;
3091                 WREG32(mmSRBM_SOFT_RESET, tmp);
3092                 tmp = RREG32(mmSRBM_SOFT_RESET);
3093
3094                 /* Wait a little for things to settle down */
3095                 udelay(50);
3096                 dce_v10_0_print_status(adev);
3097         }
3098         return 0;
3099 }
3100
3101 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3102                                                      int crtc,
3103                                                      enum amdgpu_interrupt_state state)
3104 {
3105         u32 lb_interrupt_mask;
3106
3107         if (crtc >= adev->mode_info.num_crtc) {
3108                 DRM_DEBUG("invalid crtc %d\n", crtc);
3109                 return;
3110         }
3111
3112         switch (state) {
3113         case AMDGPU_IRQ_STATE_DISABLE:
3114                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3115                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3116                                                   VBLANK_INTERRUPT_MASK, 0);
3117                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3118                 break;
3119         case AMDGPU_IRQ_STATE_ENABLE:
3120                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3121                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3122                                                   VBLANK_INTERRUPT_MASK, 1);
3123                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3124                 break;
3125         default:
3126                 break;
3127         }
3128 }
3129
3130 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3131                                                     int crtc,
3132                                                     enum amdgpu_interrupt_state state)
3133 {
3134         u32 lb_interrupt_mask;
3135
3136         if (crtc >= adev->mode_info.num_crtc) {
3137                 DRM_DEBUG("invalid crtc %d\n", crtc);
3138                 return;
3139         }
3140
3141         switch (state) {
3142         case AMDGPU_IRQ_STATE_DISABLE:
3143                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3144                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3145                                                   VLINE_INTERRUPT_MASK, 0);
3146                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3147                 break;
3148         case AMDGPU_IRQ_STATE_ENABLE:
3149                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3150                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3151                                                   VLINE_INTERRUPT_MASK, 1);
3152                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3153                 break;
3154         default:
3155                 break;
3156         }
3157 }
3158
3159 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3160                                        struct amdgpu_irq_src *source,
3161                                        unsigned hpd,
3162                                        enum amdgpu_interrupt_state state)
3163 {
3164         u32 tmp;
3165
3166         if (hpd >= adev->mode_info.num_hpd) {
3167                 DRM_DEBUG("invalid hdp %d\n", hpd);
3168                 return 0;
3169         }
3170
3171         switch (state) {
3172         case AMDGPU_IRQ_STATE_DISABLE:
3173                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3174                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3175                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3176                 break;
3177         case AMDGPU_IRQ_STATE_ENABLE:
3178                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3179                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3180                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3181                 break;
3182         default:
3183                 break;
3184         }
3185
3186         return 0;
3187 }
3188
3189 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3190                                         struct amdgpu_irq_src *source,
3191                                         unsigned type,
3192                                         enum amdgpu_interrupt_state state)
3193 {
3194         switch (type) {
3195         case AMDGPU_CRTC_IRQ_VBLANK1:
3196                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3197                 break;
3198         case AMDGPU_CRTC_IRQ_VBLANK2:
3199                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3200                 break;
3201         case AMDGPU_CRTC_IRQ_VBLANK3:
3202                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3203                 break;
3204         case AMDGPU_CRTC_IRQ_VBLANK4:
3205                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3206                 break;
3207         case AMDGPU_CRTC_IRQ_VBLANK5:
3208                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3209                 break;
3210         case AMDGPU_CRTC_IRQ_VBLANK6:
3211                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3212                 break;
3213         case AMDGPU_CRTC_IRQ_VLINE1:
3214                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3215                 break;
3216         case AMDGPU_CRTC_IRQ_VLINE2:
3217                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3218                 break;
3219         case AMDGPU_CRTC_IRQ_VLINE3:
3220                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3221                 break;
3222         case AMDGPU_CRTC_IRQ_VLINE4:
3223                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3224                 break;
3225         case AMDGPU_CRTC_IRQ_VLINE5:
3226                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3227                 break;
3228         case AMDGPU_CRTC_IRQ_VLINE6:
3229                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3230                 break;
3231         default:
3232                 break;
3233         }
3234         return 0;
3235 }
3236
3237 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3238                                             struct amdgpu_irq_src *src,
3239                                             unsigned type,
3240                                             enum amdgpu_interrupt_state state)
3241 {
3242         u32 reg, reg_block;
3243         /* now deal with page flip IRQ */
3244         switch (type) {
3245                 case AMDGPU_PAGEFLIP_IRQ_D1:
3246                         reg_block = CRTC0_REGISTER_OFFSET;
3247                         break;
3248                 case AMDGPU_PAGEFLIP_IRQ_D2:
3249                         reg_block = CRTC1_REGISTER_OFFSET;
3250                         break;
3251                 case AMDGPU_PAGEFLIP_IRQ_D3:
3252                         reg_block = CRTC2_REGISTER_OFFSET;
3253                         break;
3254                 case AMDGPU_PAGEFLIP_IRQ_D4:
3255                         reg_block = CRTC3_REGISTER_OFFSET;
3256                         break;
3257                 case AMDGPU_PAGEFLIP_IRQ_D5:
3258                         reg_block = CRTC4_REGISTER_OFFSET;
3259                         break;
3260                 case AMDGPU_PAGEFLIP_IRQ_D6:
3261                         reg_block = CRTC5_REGISTER_OFFSET;
3262                         break;
3263                 default:
3264                         DRM_ERROR("invalid pageflip crtc %d\n", type);
3265                         return -EINVAL;
3266         }
3267
3268         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
3269         if (state == AMDGPU_IRQ_STATE_DISABLE)
3270                 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3271         else
3272                 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3273
3274         return 0;
3275 }
3276
3277 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3278                                   struct amdgpu_irq_src *source,
3279                                   struct amdgpu_iv_entry *entry)
3280 {
3281         int reg_block;
3282         unsigned long flags;
3283         unsigned crtc_id;
3284         struct amdgpu_crtc *amdgpu_crtc;
3285         struct amdgpu_flip_work *works;
3286
3287         crtc_id = (entry->src_id - 8) >> 1;
3288         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3289
3290         /* ack the interrupt */
3291         switch(crtc_id){
3292                 case AMDGPU_PAGEFLIP_IRQ_D1:
3293                         reg_block = CRTC0_REGISTER_OFFSET;
3294                         break;
3295                 case AMDGPU_PAGEFLIP_IRQ_D2:
3296                         reg_block = CRTC1_REGISTER_OFFSET;
3297                         break;
3298                 case AMDGPU_PAGEFLIP_IRQ_D3:
3299                         reg_block = CRTC2_REGISTER_OFFSET;
3300                         break;
3301                 case AMDGPU_PAGEFLIP_IRQ_D4:
3302                         reg_block = CRTC3_REGISTER_OFFSET;
3303                         break;
3304                 case AMDGPU_PAGEFLIP_IRQ_D5:
3305                         reg_block = CRTC4_REGISTER_OFFSET;
3306                         break;
3307                 case AMDGPU_PAGEFLIP_IRQ_D6:
3308                         reg_block = CRTC5_REGISTER_OFFSET;
3309                         break;
3310                 default:
3311                         DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3312                         return -EINVAL;
3313         }
3314
3315         if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3316                 WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3317
3318         /* IRQ could occur when in initial stage */
3319         if (amdgpu_crtc == NULL)
3320                 return 0;
3321
3322         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3323         works = amdgpu_crtc->pflip_works;
3324         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3325                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3326                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3327                                                  amdgpu_crtc->pflip_status,
3328                                                  AMDGPU_FLIP_SUBMITTED);
3329                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3330                 return 0;
3331         }
3332
3333         /* page flip completed. clean up */
3334         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3335         amdgpu_crtc->pflip_works = NULL;
3336
3337         /* wakeup usersapce */
3338         if (works->event)
3339                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3340
3341         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3342
3343         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3344         amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
3345         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3346
3347         return 0;
3348 }
3349
3350 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3351                                   int hpd)
3352 {
3353         u32 tmp;
3354
3355         if (hpd >= adev->mode_info.num_hpd) {
3356                 DRM_DEBUG("invalid hdp %d\n", hpd);
3357                 return;
3358         }
3359
3360         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3361         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3362         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3363 }
3364
3365 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3366                                           int crtc)
3367 {
3368         u32 tmp;
3369
3370         if (crtc >= adev->mode_info.num_crtc) {
3371                 DRM_DEBUG("invalid crtc %d\n", crtc);
3372                 return;
3373         }
3374
3375         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3376         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3377         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3378 }
3379
3380 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3381                                          int crtc)
3382 {
3383         u32 tmp;
3384
3385         if (crtc >= adev->mode_info.num_crtc) {
3386                 DRM_DEBUG("invalid crtc %d\n", crtc);
3387                 return;
3388         }
3389
3390         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3391         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3392         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3393 }
3394
3395 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3396                               struct amdgpu_irq_src *source,
3397                               struct amdgpu_iv_entry *entry)
3398 {
3399         unsigned crtc = entry->src_id - 1;
3400         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3401         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3402
3403         switch (entry->src_data) {
3404         case 0: /* vblank */
3405                 if (disp_int & interrupt_status_offsets[crtc].vblank) {
3406                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3407                         if (amdgpu_irq_enabled(adev, source, irq_type)) {
3408                                 drm_handle_vblank(adev->ddev, crtc);
3409                         }
3410                         DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3411                 }
3412                 break;
3413         case 1: /* vline */
3414                 if (disp_int & interrupt_status_offsets[crtc].vline) {
3415                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3416                         DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3417                 }
3418                 break;
3419         default:
3420                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3421                 break;
3422         }
3423
3424         return 0;
3425 }
3426
3427 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3428                              struct amdgpu_irq_src *source,
3429                              struct amdgpu_iv_entry *entry)
3430 {
3431         uint32_t disp_int, mask;
3432         unsigned hpd;
3433
3434         if (entry->src_data >= adev->mode_info.num_hpd) {
3435                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3436                 return 0;
3437         }
3438
3439         hpd = entry->src_data;
3440         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3441         mask = interrupt_status_offsets[hpd].hpd;
3442
3443         if (disp_int & mask) {
3444                 dce_v10_0_hpd_int_ack(adev, hpd);
3445                 schedule_work(&adev->hotplug_work);
3446                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3447         }
3448
3449         return 0;
3450 }
3451
3452 static int dce_v10_0_set_clockgating_state(struct amdgpu_device *adev,
3453                                           enum amdgpu_clockgating_state state)
3454 {
3455         return 0;
3456 }
3457
3458 static int dce_v10_0_set_powergating_state(struct amdgpu_device *adev,
3459                                           enum amdgpu_powergating_state state)
3460 {
3461         return 0;
3462 }
3463
3464 const struct amdgpu_ip_funcs dce_v10_0_ip_funcs = {
3465         .early_init = dce_v10_0_early_init,
3466         .late_init = NULL,
3467         .sw_init = dce_v10_0_sw_init,
3468         .sw_fini = dce_v10_0_sw_fini,
3469         .hw_init = dce_v10_0_hw_init,
3470         .hw_fini = dce_v10_0_hw_fini,
3471         .suspend = dce_v10_0_suspend,
3472         .resume = dce_v10_0_resume,
3473         .is_idle = dce_v10_0_is_idle,
3474         .wait_for_idle = dce_v10_0_wait_for_idle,
3475         .soft_reset = dce_v10_0_soft_reset,
3476         .print_status = dce_v10_0_print_status,
3477         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3478         .set_powergating_state = dce_v10_0_set_powergating_state,
3479 };
3480
3481 static void
3482 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3483                           struct drm_display_mode *mode,
3484                           struct drm_display_mode *adjusted_mode)
3485 {
3486         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3487
3488         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3489
3490         /* need to call this here rather than in prepare() since we need some crtc info */
3491         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3492
3493         /* set scaler clears this on some chips */
3494         dce_v10_0_set_interleave(encoder->crtc, mode);
3495
3496         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3497                 dce_v10_0_afmt_enable(encoder, true);
3498                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3499         }
3500 }
3501
3502 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3503 {
3504         struct amdgpu_device *adev = encoder->dev->dev_private;
3505         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3506         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3507
3508         if ((amdgpu_encoder->active_device &
3509              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3510             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3511              ENCODER_OBJECT_ID_NONE)) {
3512                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3513                 if (dig) {
3514                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3515                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3516                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3517                 }
3518         }
3519
3520         amdgpu_atombios_scratch_regs_lock(adev, true);
3521
3522         if (connector) {
3523                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3524
3525                 /* select the clock/data port if it uses a router */
3526                 if (amdgpu_connector->router.cd_valid)
3527                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3528
3529                 /* turn eDP panel on for mode set */
3530                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3531                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3532                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3533         }
3534
3535         /* this is needed for the pll/ss setup to work correctly in some cases */
3536         amdgpu_atombios_encoder_set_crtc_source(encoder);
3537         /* set up the FMT blocks */
3538         dce_v10_0_program_fmt(encoder);
3539 }
3540
3541 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3542 {
3543         struct drm_device *dev = encoder->dev;
3544         struct amdgpu_device *adev = dev->dev_private;
3545
3546         /* need to call this here as we need the crtc set up */
3547         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3548         amdgpu_atombios_scratch_regs_lock(adev, false);
3549 }
3550
3551 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3552 {
3553         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3554         struct amdgpu_encoder_atom_dig *dig;
3555
3556         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3557
3558         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3559                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3560                         dce_v10_0_afmt_enable(encoder, false);
3561                 dig = amdgpu_encoder->enc_priv;
3562                 dig->dig_encoder = -1;
3563         }
3564         amdgpu_encoder->active_device = 0;
3565 }
3566
3567 /* these are handled by the primary encoders */
3568 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3569 {
3570
3571 }
3572
3573 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3574 {
3575
3576 }
3577
3578 static void
3579 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3580                       struct drm_display_mode *mode,
3581                       struct drm_display_mode *adjusted_mode)
3582 {
3583
3584 }
3585
3586 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3587 {
3588
3589 }
3590
3591 static void
3592 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3593 {
3594
3595 }
3596
3597 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder,
3598                                     const struct drm_display_mode *mode,
3599                                     struct drm_display_mode *adjusted_mode)
3600 {
3601         return true;
3602 }
3603
3604 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3605         .dpms = dce_v10_0_ext_dpms,
3606         .mode_fixup = dce_v10_0_ext_mode_fixup,
3607         .prepare = dce_v10_0_ext_prepare,
3608         .mode_set = dce_v10_0_ext_mode_set,
3609         .commit = dce_v10_0_ext_commit,
3610         .disable = dce_v10_0_ext_disable,
3611         /* no detect for TMDS/LVDS yet */
3612 };
3613
3614 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3615         .dpms = amdgpu_atombios_encoder_dpms,
3616         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3617         .prepare = dce_v10_0_encoder_prepare,
3618         .mode_set = dce_v10_0_encoder_mode_set,
3619         .commit = dce_v10_0_encoder_commit,
3620         .disable = dce_v10_0_encoder_disable,
3621         .detect = amdgpu_atombios_encoder_dig_detect,
3622 };
3623
3624 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3625         .dpms = amdgpu_atombios_encoder_dpms,
3626         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3627         .prepare = dce_v10_0_encoder_prepare,
3628         .mode_set = dce_v10_0_encoder_mode_set,
3629         .commit = dce_v10_0_encoder_commit,
3630         .detect = amdgpu_atombios_encoder_dac_detect,
3631 };
3632
3633 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3634 {
3635         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3636         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3637                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3638         kfree(amdgpu_encoder->enc_priv);
3639         drm_encoder_cleanup(encoder);
3640         kfree(amdgpu_encoder);
3641 }
3642
3643 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3644         .destroy = dce_v10_0_encoder_destroy,
3645 };
3646
3647 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3648                                  uint32_t encoder_enum,
3649                                  uint32_t supported_device,
3650                                  u16 caps)
3651 {
3652         struct drm_device *dev = adev->ddev;
3653         struct drm_encoder *encoder;
3654         struct amdgpu_encoder *amdgpu_encoder;
3655
3656         /* see if we already added it */
3657         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3658                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3659                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3660                         amdgpu_encoder->devices |= supported_device;
3661                         return;
3662                 }
3663
3664         }
3665
3666         /* add a new one */
3667         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3668         if (!amdgpu_encoder)
3669                 return;
3670
3671         encoder = &amdgpu_encoder->base;
3672         switch (adev->mode_info.num_crtc) {
3673         case 1:
3674                 encoder->possible_crtcs = 0x1;
3675                 break;
3676         case 2:
3677         default:
3678                 encoder->possible_crtcs = 0x3;
3679                 break;
3680         case 4:
3681                 encoder->possible_crtcs = 0xf;
3682                 break;
3683         case 6:
3684                 encoder->possible_crtcs = 0x3f;
3685                 break;
3686         }
3687
3688         amdgpu_encoder->enc_priv = NULL;
3689
3690         amdgpu_encoder->encoder_enum = encoder_enum;
3691         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3692         amdgpu_encoder->devices = supported_device;
3693         amdgpu_encoder->rmx_type = RMX_OFF;
3694         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3695         amdgpu_encoder->is_ext_encoder = false;
3696         amdgpu_encoder->caps = caps;
3697
3698         switch (amdgpu_encoder->encoder_id) {
3699         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3700         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3701                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3702                                  DRM_MODE_ENCODER_DAC);
3703                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3704                 break;
3705         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3706         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3707         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3708         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3709         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3710                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3711                         amdgpu_encoder->rmx_type = RMX_FULL;
3712                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3713                                          DRM_MODE_ENCODER_LVDS);
3714                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3715                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3716                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3717                                          DRM_MODE_ENCODER_DAC);
3718                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3719                 } else {
3720                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3721                                          DRM_MODE_ENCODER_TMDS);
3722                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3723                 }
3724                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3725                 break;
3726         case ENCODER_OBJECT_ID_SI170B:
3727         case ENCODER_OBJECT_ID_CH7303:
3728         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3729         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3730         case ENCODER_OBJECT_ID_TITFP513:
3731         case ENCODER_OBJECT_ID_VT1623:
3732         case ENCODER_OBJECT_ID_HDMI_SI1930:
3733         case ENCODER_OBJECT_ID_TRAVIS:
3734         case ENCODER_OBJECT_ID_NUTMEG:
3735                 /* these are handled by the primary encoders */
3736                 amdgpu_encoder->is_ext_encoder = true;
3737                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3738                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3739                                          DRM_MODE_ENCODER_LVDS);
3740                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3741                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3742                                          DRM_MODE_ENCODER_DAC);
3743                 else
3744                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3745                                          DRM_MODE_ENCODER_TMDS);
3746                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3747                 break;
3748         }
3749 }
3750
3751 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3752         .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3753         .bandwidth_update = &dce_v10_0_bandwidth_update,
3754         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3755         .vblank_wait = &dce_v10_0_vblank_wait,
3756         .is_display_hung = &dce_v10_0_is_display_hung,
3757         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3758         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3759         .hpd_sense = &dce_v10_0_hpd_sense,
3760         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3761         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3762         .page_flip = &dce_v10_0_page_flip,
3763         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3764         .add_encoder = &dce_v10_0_encoder_add,
3765         .add_connector = &amdgpu_connector_add,
3766         .stop_mc_access = &dce_v10_0_stop_mc_access,
3767         .resume_mc_access = &dce_v10_0_resume_mc_access,
3768 };
3769
3770 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3771 {
3772         if (adev->mode_info.funcs == NULL)
3773                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3774 }
3775
3776 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3777         .set = dce_v10_0_set_crtc_irq_state,
3778         .process = dce_v10_0_crtc_irq,
3779 };
3780
3781 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3782         .set = dce_v10_0_set_pageflip_irq_state,
3783         .process = dce_v10_0_pageflip_irq,
3784 };
3785
3786 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3787         .set = dce_v10_0_set_hpd_irq_state,
3788         .process = dce_v10_0_hpd_irq,
3789 };
3790
3791 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3792 {
3793         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3794         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3795
3796         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3797         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3798
3799         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3800         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3801 }