1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 #include <linux/regulator/consumer.h>
5 #include <linux/reset.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/platform_device.h>
10 #include "lima_device.h"
15 #include "lima_l2_cache.h"
16 #include "lima_dlbu.h"
17 #include "lima_bcast.h"
23 bool must_have[lima_gpu_num];
24 int offset[lima_gpu_num];
26 int (*init)(struct lima_ip *ip);
27 void (*fini)(struct lima_ip *ip);
30 #define LIMA_IP_DESC(ipname, mst0, mst1, off0, off1, func, irq) \
31 [lima_ip_##ipname] = { \
35 [lima_gpu_mali400] = mst0, \
36 [lima_gpu_mali450] = mst1, \
39 [lima_gpu_mali400] = off0, \
40 [lima_gpu_mali450] = off1, \
42 .init = lima_##func##_init, \
43 .fini = lima_##func##_fini, \
46 static struct lima_ip_desc lima_ip_desc[lima_ip_num] = {
47 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
48 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
49 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
50 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
51 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
52 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
53 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
54 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
55 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
56 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
57 LIMA_IP_DESC(pp5, false, false, -1, 0x2A000, pp, "pp5"),
58 LIMA_IP_DESC(pp6, false, false, -1, 0x2C000, pp, "pp6"),
59 LIMA_IP_DESC(pp7, false, false, -1, 0x2E000, pp, "pp7"),
60 LIMA_IP_DESC(gpmmu, true, true, 0x03000, 0x03000, mmu, "gpmmu"),
61 LIMA_IP_DESC(ppmmu0, true, true, 0x04000, 0x04000, mmu, "ppmmu0"),
62 LIMA_IP_DESC(ppmmu1, false, false, 0x05000, 0x05000, mmu, "ppmmu1"),
63 LIMA_IP_DESC(ppmmu2, false, false, 0x06000, 0x06000, mmu, "ppmmu2"),
64 LIMA_IP_DESC(ppmmu3, false, false, 0x07000, 0x07000, mmu, "ppmmu3"),
65 LIMA_IP_DESC(ppmmu4, false, false, -1, 0x1C000, mmu, "ppmmu4"),
66 LIMA_IP_DESC(ppmmu5, false, false, -1, 0x1D000, mmu, "ppmmu5"),
67 LIMA_IP_DESC(ppmmu6, false, false, -1, 0x1E000, mmu, "ppmmu6"),
68 LIMA_IP_DESC(ppmmu7, false, false, -1, 0x1F000, mmu, "ppmmu7"),
69 LIMA_IP_DESC(dlbu, false, true, -1, 0x14000, dlbu, NULL),
70 LIMA_IP_DESC(bcast, false, true, -1, 0x13000, bcast, NULL),
71 LIMA_IP_DESC(pp_bcast, false, true, -1, 0x16000, pp_bcast, "pp"),
72 LIMA_IP_DESC(ppmmu_bcast, false, true, -1, 0x15000, mmu, NULL),
75 const char *lima_ip_name(struct lima_ip *ip)
77 return lima_ip_desc[ip->id].name;
80 static int lima_clk_init(struct lima_device *dev)
84 dev->clk_bus = devm_clk_get(dev->dev, "bus");
85 if (IS_ERR(dev->clk_bus)) {
86 err = PTR_ERR(dev->clk_bus);
87 if (err != -EPROBE_DEFER)
88 dev_err(dev->dev, "get bus clk failed %d\n", err);
92 dev->clk_gpu = devm_clk_get(dev->dev, "core");
93 if (IS_ERR(dev->clk_gpu)) {
94 err = PTR_ERR(dev->clk_gpu);
95 if (err != -EPROBE_DEFER)
96 dev_err(dev->dev, "get core clk failed %d\n", err);
100 err = clk_prepare_enable(dev->clk_bus);
104 err = clk_prepare_enable(dev->clk_gpu);
108 dev->reset = devm_reset_control_get_optional(dev->dev, NULL);
109 if (IS_ERR(dev->reset)) {
110 err = PTR_ERR(dev->reset);
111 if (err != -EPROBE_DEFER)
112 dev_err(dev->dev, "get reset controller failed %d\n",
115 } else if (dev->reset != NULL) {
116 err = reset_control_deassert(dev->reset);
119 "reset controller deassert failed %d\n", err);
127 clk_disable_unprepare(dev->clk_gpu);
129 clk_disable_unprepare(dev->clk_bus);
133 static void lima_clk_fini(struct lima_device *dev)
135 if (dev->reset != NULL)
136 reset_control_assert(dev->reset);
137 clk_disable_unprepare(dev->clk_gpu);
138 clk_disable_unprepare(dev->clk_bus);
141 static int lima_regulator_init(struct lima_device *dev)
145 dev->regulator = devm_regulator_get_optional(dev->dev, "mali");
146 if (IS_ERR(dev->regulator)) {
147 ret = PTR_ERR(dev->regulator);
148 dev->regulator = NULL;
151 if (ret != -EPROBE_DEFER)
152 dev_err(dev->dev, "failed to get regulator: %d\n", ret);
156 ret = regulator_enable(dev->regulator);
158 dev_err(dev->dev, "failed to enable regulator: %d\n", ret);
165 static void lima_regulator_fini(struct lima_device *dev)
168 regulator_disable(dev->regulator);
171 static int lima_init_ip(struct lima_device *dev, int index)
173 struct lima_ip_desc *desc = lima_ip_desc + index;
174 struct lima_ip *ip = dev->ip + index;
175 int offset = desc->offset[dev->id];
176 bool must = desc->must_have[dev->id];
184 ip->iomem = dev->iomem + offset;
185 if (desc->irq_name) {
186 err = platform_get_irq_byname(dev->pdev, desc->irq_name);
192 err = desc->init(ip);
199 return must ? err : 0;
202 static void lima_fini_ip(struct lima_device *ldev, int index)
204 struct lima_ip_desc *desc = lima_ip_desc + index;
205 struct lima_ip *ip = ldev->ip + index;
211 static int lima_init_gp_pipe(struct lima_device *dev)
213 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
216 err = lima_sched_pipe_init(pipe, "gp");
220 pipe->l2_cache[pipe->num_l2_cache++] = dev->ip + lima_ip_l2_cache0;
221 pipe->mmu[pipe->num_mmu++] = dev->ip + lima_ip_gpmmu;
222 pipe->processor[pipe->num_processor++] = dev->ip + lima_ip_gp;
224 err = lima_gp_pipe_init(dev);
226 lima_sched_pipe_fini(pipe);
233 static void lima_fini_gp_pipe(struct lima_device *dev)
235 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
237 lima_gp_pipe_fini(dev);
238 lima_sched_pipe_fini(pipe);
241 static int lima_init_pp_pipe(struct lima_device *dev)
243 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
246 err = lima_sched_pipe_init(pipe, "pp");
250 for (i = 0; i < LIMA_SCHED_PIPE_MAX_PROCESSOR; i++) {
251 struct lima_ip *pp = dev->ip + lima_ip_pp0 + i;
252 struct lima_ip *ppmmu = dev->ip + lima_ip_ppmmu0 + i;
253 struct lima_ip *l2_cache;
255 if (dev->id == lima_gpu_mali400)
256 l2_cache = dev->ip + lima_ip_l2_cache0;
258 l2_cache = dev->ip + lima_ip_l2_cache1 + (i >> 2);
260 if (pp->present && ppmmu->present && l2_cache->present) {
261 pipe->mmu[pipe->num_mmu++] = ppmmu;
262 pipe->processor[pipe->num_processor++] = pp;
263 if (!pipe->l2_cache[i >> 2])
264 pipe->l2_cache[pipe->num_l2_cache++] = l2_cache;
268 if (dev->ip[lima_ip_bcast].present) {
269 pipe->bcast_processor = dev->ip + lima_ip_pp_bcast;
270 pipe->bcast_mmu = dev->ip + lima_ip_ppmmu_bcast;
273 err = lima_pp_pipe_init(dev);
275 lima_sched_pipe_fini(pipe);
282 static void lima_fini_pp_pipe(struct lima_device *dev)
284 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
286 lima_pp_pipe_fini(dev);
287 lima_sched_pipe_fini(pipe);
290 int lima_device_init(struct lima_device *ldev)
293 struct resource *res;
295 dma_set_coherent_mask(ldev->dev, DMA_BIT_MASK(32));
297 err = lima_clk_init(ldev);
301 err = lima_regulator_init(ldev);
305 ldev->empty_vm = lima_vm_create(ldev);
306 if (!ldev->empty_vm) {
312 if (ldev->id == lima_gpu_mali450) {
313 ldev->va_end = LIMA_VA_RESERVE_START;
314 ldev->dlbu_cpu = dma_alloc_wc(
315 ldev->dev, LIMA_PAGE_SIZE,
316 &ldev->dlbu_dma, GFP_KERNEL);
317 if (!ldev->dlbu_cpu) {
322 ldev->va_end = LIMA_VA_RESERVE_END;
324 res = platform_get_resource(ldev->pdev, IORESOURCE_MEM, 0);
325 ldev->iomem = devm_ioremap_resource(ldev->dev, res);
326 if (IS_ERR(ldev->iomem)) {
327 dev_err(ldev->dev, "fail to ioremap iomem\n");
328 err = PTR_ERR(ldev->iomem);
332 for (i = 0; i < lima_ip_num; i++) {
333 err = lima_init_ip(ldev, i);
338 err = lima_init_gp_pipe(ldev);
342 err = lima_init_pp_pipe(ldev);
346 dev_info(ldev->dev, "bus rate = %lu\n", clk_get_rate(ldev->clk_bus));
347 dev_info(ldev->dev, "mod rate = %lu", clk_get_rate(ldev->clk_gpu));
352 lima_fini_gp_pipe(ldev);
355 lima_fini_ip(ldev, i);
358 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE,
359 ldev->dlbu_cpu, ldev->dlbu_dma);
361 lima_vm_put(ldev->empty_vm);
363 lima_regulator_fini(ldev);
369 void lima_device_fini(struct lima_device *ldev)
373 lima_fini_pp_pipe(ldev);
374 lima_fini_gp_pipe(ldev);
376 for (i = lima_ip_num - 1; i >= 0; i--)
377 lima_fini_ip(ldev, i);
380 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE,
381 ldev->dlbu_cpu, ldev->dlbu_dma);
383 lima_vm_put(ldev->empty_vm);
385 lima_regulator_fini(ldev);