drivers/dma/stm32-mdma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Author(s): M'boumba Cedric Madianga <[email protected]>
   6  *            Pierre-Yves Mordret <[email protected]>
   7  *
   8  * Driver for STM32 MDMA controller
   9  *
  10  * Inspired by stm32-dma.c and dma-jz4780.c
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/list.h>
  24 #include <linux/log2.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_dma.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/reset.h>
  31 #include <linux/slab.h>
  32
  33 #include "virt-dma.h"
  34
  35 #define STM32_MDMA_GISR0                0x0000 /* MDMA Int Status Reg 1 */
  36
  37 /* MDMA Channel x interrupt/status register */
  38 #define STM32_MDMA_CISR(x)              (0x40 + 0x40 * (x)) /* x = 0..62 */
  39 #define STM32_MDMA_CISR_CRQA            BIT(16)
  40 #define STM32_MDMA_CISR_TCIF            BIT(4)
  41 #define STM32_MDMA_CISR_BTIF            BIT(3)
  42 #define STM32_MDMA_CISR_BRTIF           BIT(2)
  43 #define STM32_MDMA_CISR_CTCIF           BIT(1)
  44 #define STM32_MDMA_CISR_TEIF            BIT(0)
  45
  46 /* MDMA Channel x interrupt flag clear register */
  47 #define STM32_MDMA_CIFCR(x)             (0x44 + 0x40 * (x))
  48 #define STM32_MDMA_CIFCR_CLTCIF         BIT(4)
  49 #define STM32_MDMA_CIFCR_CBTIF          BIT(3)
  50 #define STM32_MDMA_CIFCR_CBRTIF         BIT(2)
  51 #define STM32_MDMA_CIFCR_CCTCIF         BIT(1)
  52 #define STM32_MDMA_CIFCR_CTEIF          BIT(0)
  53 #define STM32_MDMA_CIFCR_CLEAR_ALL      (STM32_MDMA_CIFCR_CLTCIF \
  54                                         | STM32_MDMA_CIFCR_CBTIF \
  55                                         | STM32_MDMA_CIFCR_CBRTIF \
  56                                         | STM32_MDMA_CIFCR_CCTCIF \
  57                                         | STM32_MDMA_CIFCR_CTEIF)
  58
  59 /* MDMA Channel x error status register */
  60 #define STM32_MDMA_CESR(x)              (0x48 + 0x40 * (x))
  61 #define STM32_MDMA_CESR_BSE             BIT(11)
  62 #define STM32_MDMA_CESR_ASR             BIT(10)
  63 #define STM32_MDMA_CESR_TEMD            BIT(9)
  64 #define STM32_MDMA_CESR_TELD            BIT(8)
  65 #define STM32_MDMA_CESR_TED             BIT(7)
  66 #define STM32_MDMA_CESR_TEA_MASK        GENMASK(6, 0)
  67
  68 /* MDMA Channel x control register */
  69 #define STM32_MDMA_CCR(x)               (0x4C + 0x40 * (x))
  70 #define STM32_MDMA_CCR_SWRQ             BIT(16)
  71 #define STM32_MDMA_CCR_WEX              BIT(14)
  72 #define STM32_MDMA_CCR_HEX              BIT(13)
  73 #define STM32_MDMA_CCR_BEX              BIT(12)
  74 #define STM32_MDMA_CCR_SM               BIT(8)
  75 #define STM32_MDMA_CCR_PL_MASK          GENMASK(7, 6)
  76 #define STM32_MDMA_CCR_PL(n)            FIELD_PREP(STM32_MDMA_CCR_PL_MASK, (n))
  77 #define STM32_MDMA_CCR_TCIE             BIT(5)
  78 #define STM32_MDMA_CCR_BTIE             BIT(4)
  79 #define STM32_MDMA_CCR_BRTIE            BIT(3)
  80 #define STM32_MDMA_CCR_CTCIE            BIT(2)
  81 #define STM32_MDMA_CCR_TEIE             BIT(1)
  82 #define STM32_MDMA_CCR_EN               BIT(0)
  83 #define STM32_MDMA_CCR_IRQ_MASK         (STM32_MDMA_CCR_TCIE \
  84                                         | STM32_MDMA_CCR_BTIE \
  85                                         | STM32_MDMA_CCR_BRTIE \
  86                                         | STM32_MDMA_CCR_CTCIE \
  87                                         | STM32_MDMA_CCR_TEIE)
  88
  89 /* MDMA Channel x transfer configuration register */
  90 #define STM32_MDMA_CTCR(x)              (0x50 + 0x40 * (x))
  91 #define STM32_MDMA_CTCR_BWM             BIT(31)
  92 #define STM32_MDMA_CTCR_SWRM            BIT(30)
  93 #define STM32_MDMA_CTCR_TRGM_MSK        GENMASK(29, 28)
  94 #define STM32_MDMA_CTCR_TRGM(n)         FIELD_PREP(STM32_MDMA_CTCR_TRGM_MSK, (n))
  95 #define STM32_MDMA_CTCR_TRGM_GET(n)     FIELD_GET(STM32_MDMA_CTCR_TRGM_MSK, (n))
  96 #define STM32_MDMA_CTCR_PAM_MASK        GENMASK(27, 26)
  97 #define STM32_MDMA_CTCR_PAM(n)          FIELD_PREP(STM32_MDMA_CTCR_PAM_MASK, (n))
  98 #define STM32_MDMA_CTCR_PKE             BIT(25)
  99 #define STM32_MDMA_CTCR_TLEN_MSK        GENMASK(24, 18)
 100 #define STM32_MDMA_CTCR_TLEN(n)         FIELD_PREP(STM32_MDMA_CTCR_TLEN_MSK, (n))
 101 #define STM32_MDMA_CTCR_TLEN_GET(n)     FIELD_GET(STM32_MDMA_CTCR_TLEN_MSK, (n))
 102 #define STM32_MDMA_CTCR_LEN2_MSK        GENMASK(25, 18)
 103 #define STM32_MDMA_CTCR_LEN2(n)         FIELD_PREP(STM32_MDMA_CTCR_LEN2_MSK, (n))
 104 #define STM32_MDMA_CTCR_LEN2_GET(n)     FIELD_GET(STM32_MDMA_CTCR_LEN2_MSK, (n))
 105 #define STM32_MDMA_CTCR_DBURST_MASK     GENMASK(17, 15)
 106 #define STM32_MDMA_CTCR_DBURST(n)       FIELD_PREP(STM32_MDMA_CTCR_DBURST_MASK, (n))
 107 #define STM32_MDMA_CTCR_SBURST_MASK     GENMASK(14, 12)
 108 #define STM32_MDMA_CTCR_SBURST(n)       FIELD_PREP(STM32_MDMA_CTCR_SBURST_MASK, (n))
 109 #define STM32_MDMA_CTCR_DINCOS_MASK     GENMASK(11, 10)
 110 #define STM32_MDMA_CTCR_DINCOS(n)       FIELD_PREP(STM32_MDMA_CTCR_DINCOS_MASK, (n))
 111 #define STM32_MDMA_CTCR_SINCOS_MASK     GENMASK(9, 8)
 112 #define STM32_MDMA_CTCR_SINCOS(n)       FIELD_PREP(STM32_MDMA_CTCR_SINCOS_MASK, (n))
 113 #define STM32_MDMA_CTCR_DSIZE_MASK      GENMASK(7, 6)
 114 #define STM32_MDMA_CTCR_DSIZE(n)        FIELD_PREP(STM32_MDMA_CTCR_DSIZE_MASK, (n))
 115 #define STM32_MDMA_CTCR_SSIZE_MASK      GENMASK(5, 4)
 116 #define STM32_MDMA_CTCR_SSIZE(n)        FIELD_PREP(STM32_MDMA_CTCR_SSIZE_MASK, (n))
 117 #define STM32_MDMA_CTCR_DINC_MASK       GENMASK(3, 2)
 118 #define STM32_MDMA_CTCR_DINC(n)         FIELD_PREP(STM32_MDMA_CTCR_DINC_MASK, (n))
 119 #define STM32_MDMA_CTCR_SINC_MASK       GENMASK(1, 0)
 120 #define STM32_MDMA_CTCR_SINC(n)         FIELD_PREP(STM32_MDMA_CTCR_SINC_MASK, (n))
 121 #define STM32_MDMA_CTCR_CFG_MASK        (STM32_MDMA_CTCR_SINC_MASK \
 122                                         | STM32_MDMA_CTCR_DINC_MASK \
 123                                         | STM32_MDMA_CTCR_SINCOS_MASK \
 124                                         | STM32_MDMA_CTCR_DINCOS_MASK \
 125                                         | STM32_MDMA_CTCR_LEN2_MSK \
 126                                         | STM32_MDMA_CTCR_TRGM_MSK)
 127
 128 /* MDMA Channel x block number of data register */
 129 #define STM32_MDMA_CBNDTR(x)            (0x54 + 0x40 * (x))
 130 #define STM32_MDMA_CBNDTR_BRC_MK        GENMASK(31, 20)
 131 #define STM32_MDMA_CBNDTR_BRC(n)        FIELD_PREP(STM32_MDMA_CBNDTR_BRC_MK, (n))
 132 #define STM32_MDMA_CBNDTR_BRC_GET(n)    FIELD_GET(STM32_MDMA_CBNDTR_BRC_MK, (n))
 133
 134 #define STM32_MDMA_CBNDTR_BRDUM         BIT(19)
 135 #define STM32_MDMA_CBNDTR_BRSUM         BIT(18)
 136 #define STM32_MDMA_CBNDTR_BNDT_MASK     GENMASK(16, 0)
 137 #define STM32_MDMA_CBNDTR_BNDT(n)       FIELD_PREP(STM32_MDMA_CBNDTR_BNDT_MASK, (n))
 138
 139 /* MDMA Channel x source address register */
 140 #define STM32_MDMA_CSAR(x)              (0x58 + 0x40 * (x))
 141
 142 /* MDMA Channel x destination address register */
 143 #define STM32_MDMA_CDAR(x)              (0x5C + 0x40 * (x))
 144
 145 /* MDMA Channel x block repeat address update register */
 146 #define STM32_MDMA_CBRUR(x)             (0x60 + 0x40 * (x))
 147 #define STM32_MDMA_CBRUR_DUV_MASK       GENMASK(31, 16)
 148 #define STM32_MDMA_CBRUR_DUV(n)         FIELD_PREP(STM32_MDMA_CBRUR_DUV_MASK, (n))
 149 #define STM32_MDMA_CBRUR_SUV_MASK       GENMASK(15, 0)
 150 #define STM32_MDMA_CBRUR_SUV(n)         FIELD_PREP(STM32_MDMA_CBRUR_SUV_MASK, (n))
 151
 152 /* MDMA Channel x link address register */
 153 #define STM32_MDMA_CLAR(x)              (0x64 + 0x40 * (x))
 154
 155 /* MDMA Channel x trigger and bus selection register */
 156 #define STM32_MDMA_CTBR(x)              (0x68 + 0x40 * (x))
 157 #define STM32_MDMA_CTBR_DBUS            BIT(17)
 158 #define STM32_MDMA_CTBR_SBUS            BIT(16)
 159 #define STM32_MDMA_CTBR_TSEL_MASK       GENMASK(5, 0)
 160 #define STM32_MDMA_CTBR_TSEL(n)         FIELD_PREP(STM32_MDMA_CTBR_TSEL_MASK, (n))
 161
 162 /* MDMA Channel x mask address register */
 163 #define STM32_MDMA_CMAR(x)              (0x70 + 0x40 * (x))
 164
 165 /* MDMA Channel x mask data register */
 166 #define STM32_MDMA_CMDR(x)              (0x74 + 0x40 * (x))
 167
 168 #define STM32_MDMA_MAX_BUF_LEN          128
 169 #define STM32_MDMA_MAX_BLOCK_LEN        65536
 170 #define STM32_MDMA_MAX_CHANNELS         32
 171 #define STM32_MDMA_MAX_REQUESTS         256
 172 #define STM32_MDMA_MAX_BURST            128
 173 #define STM32_MDMA_VERY_HIGH_PRIORITY   0x3
 174
 175 enum stm32_mdma_trigger_mode {
 176         STM32_MDMA_BUFFER,
 177         STM32_MDMA_BLOCK,
 178         STM32_MDMA_BLOCK_REP,
 179         STM32_MDMA_LINKED_LIST,
 180 };
 181
 182 enum stm32_mdma_width {
 183         STM32_MDMA_BYTE,
 184         STM32_MDMA_HALF_WORD,
 185         STM32_MDMA_WORD,
 186         STM32_MDMA_DOUBLE_WORD,
 187 };
 188
 189 enum stm32_mdma_inc_mode {
 190         STM32_MDMA_FIXED = 0,
 191         STM32_MDMA_INC = 2,
 192         STM32_MDMA_DEC = 3,
 193 };
 194
 195 struct stm32_mdma_chan_config {
 196         u32 request;
 197         u32 priority_level;
 198         u32 transfer_config;
 199         u32 mask_addr;
 200         u32 mask_data;
 201         bool m2m_hw; /* True when MDMA is triggered by STM32 DMA */
 202 };
 203
 204 struct stm32_mdma_hwdesc {
 205         u32 ctcr;
 206         u32 cbndtr;
 207         u32 csar;
 208         u32 cdar;
 209         u32 cbrur;
 210         u32 clar;
 211         u32 ctbr;
 212         u32 dummy;
 213         u32 cmar;
 214         u32 cmdr;
 215 } __aligned(64);
 216
 217 struct stm32_mdma_desc_node {
 218         struct stm32_mdma_hwdesc *hwdesc;
 219         dma_addr_t hwdesc_phys;
 220 };
 221
 222 struct stm32_mdma_desc {
 223         struct virt_dma_desc vdesc;
 224         u32 ccr;
 225         bool cyclic;
 226         u32 count;
 227         struct stm32_mdma_desc_node node[];
 228 };
 229
 230 struct stm32_mdma_dma_config {
 231         u32 request;    /* STM32 DMA channel stream id, triggering MDMA */
 232         u32 cmar;       /* STM32 DMA interrupt flag clear register address */
 233         u32 cmdr;       /* STM32 DMA Transfer Complete flag */
 234 };
 235
 236 struct stm32_mdma_chan {
 237         struct virt_dma_chan vchan;
 238         struct dma_pool *desc_pool;
 239         u32 id;
 240         struct stm32_mdma_desc *desc;
 241         u32 curr_hwdesc;
 242         struct dma_slave_config dma_config;
 243         struct stm32_mdma_chan_config chan_config;
 244         bool busy;
 245         u32 mem_burst;
 246         u32 mem_width;
 247 };
 248
 249 struct stm32_mdma_device {
 250         struct dma_device ddev;
 251         void __iomem *base;
 252         struct clk *clk;
 253         int irq;
 254         u32 nr_channels;
 255         u32 nr_requests;
 256         u32 nr_ahb_addr_masks;
 257         u32 chan_reserved;
 258         struct stm32_mdma_chan chan[STM32_MDMA_MAX_CHANNELS];
 259         u32 ahb_addr_masks[];
 260 };
 261
 262 static struct stm32_mdma_device *stm32_mdma_get_dev(
 263         struct stm32_mdma_chan *chan)
 264 {
 265         return container_of(chan->vchan.chan.device, struct stm32_mdma_device,
 266                             ddev);
 267 }
 268
 269 static struct stm32_mdma_chan *to_stm32_mdma_chan(struct dma_chan *c)
 270 {
 271         return container_of(c, struct stm32_mdma_chan, vchan.chan);
 272 }
 273
 274 static struct stm32_mdma_desc *to_stm32_mdma_desc(struct virt_dma_desc *vdesc)
 275 {
 276         return container_of(vdesc, struct stm32_mdma_desc, vdesc);
 277 }
 278
 279 static struct device *chan2dev(struct stm32_mdma_chan *chan)
 280 {
 281         return &chan->vchan.chan.dev->device;
 282 }
 283
 284 static struct device *mdma2dev(struct stm32_mdma_device *mdma_dev)
 285 {
 286         return mdma_dev->ddev.dev;
 287 }
 288
 289 static u32 stm32_mdma_read(struct stm32_mdma_device *dmadev, u32 reg)
 290 {
 291         return readl_relaxed(dmadev->base + reg);
 292 }
 293
 294 static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val)
 295 {
 296         writel_relaxed(val, dmadev->base + reg);
 297 }
 298
 299 static void stm32_mdma_set_bits(struct stm32_mdma_device *dmadev, u32 reg,
 300                                 u32 mask)
 301 {
 302         void __iomem *addr = dmadev->base + reg;
 303
 304         writel_relaxed(readl_relaxed(addr) | mask, addr);
 305 }
 306
 307 static void stm32_mdma_clr_bits(struct stm32_mdma_device *dmadev, u32 reg,
 308                                 u32 mask)
 309 {
 310         void __iomem *addr = dmadev->base + reg;
 311
 312         writel_relaxed(readl_relaxed(addr) & ~mask, addr);
 313 }
 314
 315 static struct stm32_mdma_desc *stm32_mdma_alloc_desc(
 316                 struct stm32_mdma_chan *chan, u32 count)
 317 {
 318         struct stm32_mdma_desc *desc;
 319         int i;
 320
 321         desc = kzalloc(struct_size(desc, node, count), GFP_NOWAIT);
 322         if (!desc)
 323                 return NULL;
 324
 325         for (i = 0; i < count; i++) {
 326                 desc->node[i].hwdesc =
 327                         dma_pool_alloc(chan->desc_pool, GFP_NOWAIT,
 328                                        &desc->node[i].hwdesc_phys);
 329                 if (!desc->node[i].hwdesc)
 330                         goto err;
 331         }
 332
 333         desc->count = count;
 334
 335         return desc;
 336
 337 err:
 338         dev_err(chan2dev(chan), "Failed to allocate descriptor\n");
 339         while (--i >= 0)
 340                 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
 341                               desc->node[i].hwdesc_phys);
 342         kfree(desc);
 343         return NULL;
 344 }
 345
 346 static void stm32_mdma_desc_free(struct virt_dma_desc *vdesc)
 347 {
 348         struct stm32_mdma_desc *desc = to_stm32_mdma_desc(vdesc);
 349         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(vdesc->tx.chan);
 350         int i;
 351
 352         for (i = 0; i < desc->count; i++)
 353                 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
 354                               desc->node[i].hwdesc_phys);
 355         kfree(desc);
 356 }
 357
 358 static int stm32_mdma_get_width(struct stm32_mdma_chan *chan,
 359                                 enum dma_slave_buswidth width)
 360 {
 361         switch (width) {
 362         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 363         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 364         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 365         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 366                 return ffs(width) - 1;
 367         default:
 368                 dev_err(chan2dev(chan), "Dma bus width %i not supported\n",
 369                         width);
 370                 return -EINVAL;
 371         }
 372 }
 373
 374 static enum dma_slave_buswidth stm32_mdma_get_max_width(dma_addr_t addr,
 375                                                         u32 buf_len, u32 tlen)
 376 {
 377         enum dma_slave_buswidth max_width = DMA_SLAVE_BUSWIDTH_8_BYTES;
 378
 379         for (max_width = DMA_SLAVE_BUSWIDTH_8_BYTES;
 380              max_width > DMA_SLAVE_BUSWIDTH_1_BYTE;
 381              max_width >>= 1) {
 382                 /*
 383                  * Address and buffer length both have to be aligned on
 384                  * bus width
 385                  */
 386                 if ((((buf_len | addr) & (max_width - 1)) == 0) &&
 387                     tlen >= max_width)
 388                         break;
 389         }
 390
 391         return max_width;
 392 }
 393
 394 static u32 stm32_mdma_get_best_burst(u32 buf_len, u32 tlen, u32 max_burst,
 395                                      enum dma_slave_buswidth width)
 396 {
 397         u32 best_burst;
 398
 399         best_burst = min((u32)1 << __ffs(tlen | buf_len),
 400                          max_burst * width) / width;
 401
 402         return (best_burst > 0) ? best_burst : 1;
 403 }
 404
 405 static int stm32_mdma_disable_chan(struct stm32_mdma_chan *chan)
 406 {
 407         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
 408         u32 ccr, cisr, id, reg;
 409         int ret;
 410
 411         id = chan->id;
 412         reg = STM32_MDMA_CCR(id);
 413
 414         /* Disable interrupts */
 415         stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_IRQ_MASK);
 416
 417         ccr = stm32_mdma_read(dmadev, reg);
 418         if (ccr & STM32_MDMA_CCR_EN) {
 419                 stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_EN);
 420
 421                 /* Ensure that any ongoing transfer has been completed */
 422                 ret = readl_relaxed_poll_timeout_atomic(
 423                                 dmadev->base + STM32_MDMA_CISR(id), cisr,
 424                                 (cisr & STM32_MDMA_CISR_CTCIF), 10, 1000);
 425                 if (ret) {
 426                         dev_err(chan2dev(chan), "%s: timeout!\n", __func__);
 427                         return -EBUSY;
 428                 }
 429         }
 430
 431         return 0;
 432 }
 433
 434 static void stm32_mdma_stop(struct stm32_mdma_chan *chan)
 435 {
 436         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
 437         u32 status;
 438         int ret;
 439
 440         /* Disable DMA */
 441         ret = stm32_mdma_disable_chan(chan);
 442         if (ret < 0)
 443                 return;
 444
 445         /* Clear interrupt status if it is there */
 446         status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
 447         if (status) {
 448                 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 449                         __func__, status);
 450                 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status);
 451         }
 452
 453         chan->busy = false;
 454 }
 455
 456 static void stm32_mdma_set_bus(struct stm32_mdma_device *dmadev, u32 *ctbr,
 457                                u32 ctbr_mask, u32 src_addr)
 458 {
 459         u32 mask;
 460         int i;
 461
 462         /* Check if memory device is on AHB or AXI */
 463         *ctbr &= ~ctbr_mask;
 464         mask = src_addr & 0xF0000000;
 465         for (i = 0; i < dmadev->nr_ahb_addr_masks; i++) {
 466                 if (mask == dmadev->ahb_addr_masks[i]) {
 467                         *ctbr |= ctbr_mask;
 468                         break;
 469                 }
 470         }
 471 }
 472
 473 static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
 474                                      enum dma_transfer_direction direction,
 475                                      u32 *mdma_ccr, u32 *mdma_ctcr,
 476                                      u32 *mdma_ctbr, dma_addr_t addr,
 477                                      u32 buf_len)
 478 {
 479         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
 480         struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
 481         enum dma_slave_buswidth src_addr_width, dst_addr_width;
 482         phys_addr_t src_addr, dst_addr;
 483         int src_bus_width, dst_bus_width;
 484         u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
 485         u32 ccr, ctcr, ctbr, tlen;
 486
 487         src_addr_width = chan->dma_config.src_addr_width;
 488         dst_addr_width = chan->dma_config.dst_addr_width;
 489         src_maxburst = chan->dma_config.src_maxburst;
 490         dst_maxburst = chan->dma_config.dst_maxburst;
 491
 492         ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id));
 493         ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id));
 494         ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id));
 495
 496         /* Enable HW request mode */
 497         ctcr &= ~STM32_MDMA_CTCR_SWRM;
 498
 499         /* Set DINC, SINC, DINCOS, SINCOS, TRGM and TLEN retrieve from DT */
 500         ctcr &= ~STM32_MDMA_CTCR_CFG_MASK;
 501         ctcr |= chan_config->transfer_config & STM32_MDMA_CTCR_CFG_MASK;
 502
 503         /*
 504          * For buffer transfer length (TLEN) we have to set
 505          * the number of bytes - 1 in CTCR register
 506          */
 507         tlen = STM32_MDMA_CTCR_LEN2_GET(ctcr);
 508         ctcr &= ~STM32_MDMA_CTCR_LEN2_MSK;
 509         ctcr |= STM32_MDMA_CTCR_TLEN((tlen - 1));
 510
 511         /* Disable Pack Enable */
 512         ctcr &= ~STM32_MDMA_CTCR_PKE;
 513
 514         /* Check burst size constraints */
 515         if (src_maxburst * src_addr_width > STM32_MDMA_MAX_BURST ||
 516             dst_maxburst * dst_addr_width > STM32_MDMA_MAX_BURST) {
 517                 dev_err(chan2dev(chan),
 518                         "burst size * bus width higher than %d bytes\n",
 519                         STM32_MDMA_MAX_BURST);
 520                 return -EINVAL;
 521         }
 522
 523         if ((!is_power_of_2(src_maxburst) && src_maxburst > 0) ||
 524             (!is_power_of_2(dst_maxburst) && dst_maxburst > 0)) {
 525                 dev_err(chan2dev(chan), "burst size must be a power of 2\n");
 526                 return -EINVAL;
 527         }
 528
 529         /*
 530          * Configure channel control:
 531          * - Clear SW request as in this case this is a HW one
 532          * - Clear WEX, HEX and BEX bits
 533          * - Set priority level
 534          */
 535         ccr &= ~(STM32_MDMA_CCR_SWRQ | STM32_MDMA_CCR_WEX | STM32_MDMA_CCR_HEX |
 536                  STM32_MDMA_CCR_BEX | STM32_MDMA_CCR_PL_MASK);
 537         ccr |= STM32_MDMA_CCR_PL(chan_config->priority_level);
 538
 539         /* Configure Trigger selection */
 540         ctbr &= ~STM32_MDMA_CTBR_TSEL_MASK;
 541         ctbr |= STM32_MDMA_CTBR_TSEL(chan_config->request);
 542
 543         switch (direction) {
 544         case DMA_MEM_TO_DEV:
 545                 dst_addr = chan->dma_config.dst_addr;
 546
 547                 /* Set device data size */
 548                 if (chan_config->m2m_hw)
 549                         dst_addr_width = stm32_mdma_get_max_width(dst_addr, buf_len,
 550                                                                   STM32_MDMA_MAX_BUF_LEN);
 551                 dst_bus_width = stm32_mdma_get_width(chan, dst_addr_width);
 552                 if (dst_bus_width < 0)
 553                         return dst_bus_width;
 554                 ctcr &= ~STM32_MDMA_CTCR_DSIZE_MASK;
 555                 ctcr |= STM32_MDMA_CTCR_DSIZE(dst_bus_width);
 556                 if (chan_config->m2m_hw) {
 557                         ctcr &= ~STM32_MDMA_CTCR_DINCOS_MASK;
 558                         ctcr |= STM32_MDMA_CTCR_DINCOS(dst_bus_width);
 559                 }
 560
 561                 /* Set device burst value */
 562                 if (chan_config->m2m_hw)
 563                         dst_maxburst = STM32_MDMA_MAX_BUF_LEN / dst_addr_width;
 564
 565                 dst_best_burst = stm32_mdma_get_best_burst(buf_len, tlen,
 566                                                            dst_maxburst,
 567                                                            dst_addr_width);
 568                 chan->mem_burst = dst_best_burst;
 569                 ctcr &= ~STM32_MDMA_CTCR_DBURST_MASK;
 570                 ctcr |= STM32_MDMA_CTCR_DBURST((ilog2(dst_best_burst)));
 571
 572                 /* Set memory data size */
 573                 src_addr_width = stm32_mdma_get_max_width(addr, buf_len, tlen);
 574                 chan->mem_width = src_addr_width;
 575                 src_bus_width = stm32_mdma_get_width(chan, src_addr_width);
 576                 if (src_bus_width < 0)
 577                         return src_bus_width;
 578                 ctcr &= ~STM32_MDMA_CTCR_SSIZE_MASK |
 579                         STM32_MDMA_CTCR_SINCOS_MASK;
 580                 ctcr |= STM32_MDMA_CTCR_SSIZE(src_bus_width) |
 581                         STM32_MDMA_CTCR_SINCOS(src_bus_width);
 582
 583                 /* Set memory burst value */
 584                 src_maxburst = STM32_MDMA_MAX_BUF_LEN / src_addr_width;
 585                 src_best_burst = stm32_mdma_get_best_burst(buf_len, tlen,
 586                                                            src_maxburst,
 587                                                            src_addr_width);
 588                 chan->mem_burst = src_best_burst;
 589                 ctcr &= ~STM32_MDMA_CTCR_SBURST_MASK;
 590                 ctcr |= STM32_MDMA_CTCR_SBURST((ilog2(src_best_burst)));
 591
 592                 /* Select bus */
 593                 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
 594                                    dst_addr);
 595
 596                 if (dst_bus_width != src_bus_width)
 597                         ctcr |= STM32_MDMA_CTCR_PKE;
 598
 599                 /* Set destination address */
 600                 stm32_mdma_write(dmadev, STM32_MDMA_CDAR(chan->id), dst_addr);
 601                 break;
 602
 603         case DMA_DEV_TO_MEM:
 604                 src_addr = chan->dma_config.src_addr;
 605
 606                 /* Set device data size */
 607                 if (chan_config->m2m_hw)
 608                         src_addr_width = stm32_mdma_get_max_width(src_addr, buf_len,
 609                                                                   STM32_MDMA_MAX_BUF_LEN);
 610
 611                 src_bus_width = stm32_mdma_get_width(chan, src_addr_width);
 612                 if (src_bus_width < 0)
 613                         return src_bus_width;
 614                 ctcr &= ~STM32_MDMA_CTCR_SSIZE_MASK;
 615                 ctcr |= STM32_MDMA_CTCR_SSIZE(src_bus_width);
 616                 if (chan_config->m2m_hw) {
 617                         ctcr &= ~STM32_MDMA_CTCR_SINCOS_MASK;
 618                         ctcr |= STM32_MDMA_CTCR_SINCOS(src_bus_width);
 619                 }
 620
 621                 /* Set device burst value */
 622                 if (chan_config->m2m_hw)
 623                         src_maxburst = STM32_MDMA_MAX_BUF_LEN / src_addr_width;
 624
 625                 src_best_burst = stm32_mdma_get_best_burst(buf_len, tlen,
 626                                                            src_maxburst,
 627                                                            src_addr_width);
 628                 ctcr &= ~STM32_MDMA_CTCR_SBURST_MASK;
 629                 ctcr |= STM32_MDMA_CTCR_SBURST((ilog2(src_best_burst)));
 630
 631                 /* Set memory data size */
 632                 dst_addr_width = stm32_mdma_get_max_width(addr, buf_len, tlen);
 633                 chan->mem_width = dst_addr_width;
 634                 dst_bus_width = stm32_mdma_get_width(chan, dst_addr_width);
 635                 if (dst_bus_width < 0)
 636                         return dst_bus_width;
 637                 ctcr &= ~(STM32_MDMA_CTCR_DSIZE_MASK |
 638                         STM32_MDMA_CTCR_DINCOS_MASK);
 639                 ctcr |= STM32_MDMA_CTCR_DSIZE(dst_bus_width) |
 640                         STM32_MDMA_CTCR_DINCOS(dst_bus_width);
 641
 642                 /* Set memory burst value */
 643                 dst_maxburst = STM32_MDMA_MAX_BUF_LEN / dst_addr_width;
 644                 dst_best_burst = stm32_mdma_get_best_burst(buf_len, tlen,
 645                                                            dst_maxburst,
 646                                                            dst_addr_width);
 647                 ctcr &= ~STM32_MDMA_CTCR_DBURST_MASK;
 648                 ctcr |= STM32_MDMA_CTCR_DBURST((ilog2(dst_best_burst)));
 649
 650                 /* Select bus */
 651                 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
 652                                    src_addr);
 653
 654                 if (dst_bus_width != src_bus_width)
 655                         ctcr |= STM32_MDMA_CTCR_PKE;
 656
 657                 /* Set source address */
 658                 stm32_mdma_write(dmadev, STM32_MDMA_CSAR(chan->id), src_addr);
 659                 break;
 660
 661         default:
 662                 dev_err(chan2dev(chan), "Dma direction is not supported\n");
 663                 return -EINVAL;
 664         }
 665
 666         *mdma_ccr = ccr;
 667         *mdma_ctcr = ctcr;
 668         *mdma_ctbr = ctbr;
 669
 670         return 0;
 671 }
 672
 673 static void stm32_mdma_dump_hwdesc(struct stm32_mdma_chan *chan,
 674                                    struct stm32_mdma_desc_node *node)
 675 {
 676         dev_dbg(chan2dev(chan), "hwdesc:  %pad\n", &node->hwdesc_phys);
 677         dev_dbg(chan2dev(chan), "CTCR:    0x%08x\n", node->hwdesc->ctcr);
 678         dev_dbg(chan2dev(chan), "CBNDTR:  0x%08x\n", node->hwdesc->cbndtr);
 679         dev_dbg(chan2dev(chan), "CSAR:    0x%08x\n", node->hwdesc->csar);
 680         dev_dbg(chan2dev(chan), "CDAR:    0x%08x\n", node->hwdesc->cdar);
 681         dev_dbg(chan2dev(chan), "CBRUR:   0x%08x\n", node->hwdesc->cbrur);
 682         dev_dbg(chan2dev(chan), "CLAR:    0x%08x\n", node->hwdesc->clar);
 683         dev_dbg(chan2dev(chan), "CTBR:    0x%08x\n", node->hwdesc->ctbr);
 684         dev_dbg(chan2dev(chan), "CMAR:    0x%08x\n", node->hwdesc->cmar);
 685         dev_dbg(chan2dev(chan), "CMDR:    0x%08x\n\n", node->hwdesc->cmdr);
 686 }
 687
 688 static void stm32_mdma_setup_hwdesc(struct stm32_mdma_chan *chan,
 689                                     struct stm32_mdma_desc *desc,
 690                                     enum dma_transfer_direction dir, u32 count,
 691                                     dma_addr_t src_addr, dma_addr_t dst_addr,
 692                                     u32 len, u32 ctcr, u32 ctbr, bool is_last,
 693                                     bool is_first, bool is_cyclic)
 694 {
 695         struct stm32_mdma_chan_config *config = &chan->chan_config;
 696         struct stm32_mdma_hwdesc *hwdesc;
 697         u32 next = count + 1;
 698
 699         hwdesc = desc->node[count].hwdesc;
 700         hwdesc->ctcr = ctcr;
 701         hwdesc->cbndtr &= ~(STM32_MDMA_CBNDTR_BRC_MK |
 702                         STM32_MDMA_CBNDTR_BRDUM |
 703                         STM32_MDMA_CBNDTR_BRSUM |
 704                         STM32_MDMA_CBNDTR_BNDT_MASK);
 705         hwdesc->cbndtr |= STM32_MDMA_CBNDTR_BNDT(len);
 706         hwdesc->csar = src_addr;
 707         hwdesc->cdar = dst_addr;
 708         hwdesc->cbrur = 0;
 709         hwdesc->ctbr = ctbr;
 710         hwdesc->cmar = config->mask_addr;
 711         hwdesc->cmdr = config->mask_data;
 712
 713         if (is_last) {
 714                 if (is_cyclic)
 715                         hwdesc->clar = desc->node[0].hwdesc_phys;
 716                 else
 717                         hwdesc->clar = 0;
 718         } else {
 719                 hwdesc->clar = desc->node[next].hwdesc_phys;
 720         }
 721
 722         stm32_mdma_dump_hwdesc(chan, &desc->node[count]);
 723 }
 724
 725 static int stm32_mdma_setup_xfer(struct stm32_mdma_chan *chan,
 726                                  struct stm32_mdma_desc *desc,
 727                                  struct scatterlist *sgl, u32 sg_len,
 728                                  enum dma_transfer_direction direction)
 729 {
 730         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
 731         struct dma_slave_config *dma_config = &chan->dma_config;
 732         struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
 733         struct scatterlist *sg;
 734         dma_addr_t src_addr, dst_addr;
 735         u32 m2m_hw_period, ccr, ctcr, ctbr;
 736         int i, ret = 0;
 737
 738         if (chan_config->m2m_hw)
 739                 m2m_hw_period = sg_dma_len(sgl);
 740
 741         for_each_sg(sgl, sg, sg_len, i) {
 742                 if (sg_dma_len(sg) > STM32_MDMA_MAX_BLOCK_LEN) {
 743                         dev_err(chan2dev(chan), "Invalid block len\n");
 744                         return -EINVAL;
 745                 }
 746
 747                 if (direction == DMA_MEM_TO_DEV) {
 748                         src_addr = sg_dma_address(sg);
 749                         dst_addr = dma_config->dst_addr;
 750                         if (chan_config->m2m_hw && (i & 1))
 751                                 dst_addr += m2m_hw_period;
 752                         ret = stm32_mdma_set_xfer_param(chan, direction, &ccr,
 753                                                         &ctcr, &ctbr, src_addr,
 754                                                         sg_dma_len(sg));
 755                         stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
 756                                            src_addr);
 757                 } else {
 758                         src_addr = dma_config->src_addr;
 759                         if (chan_config->m2m_hw && (i & 1))
 760                                 src_addr += m2m_hw_period;
 761                         dst_addr = sg_dma_address(sg);
 762                         ret = stm32_mdma_set_xfer_param(chan, direction, &ccr,
 763                                                         &ctcr, &ctbr, dst_addr,
 764                                                         sg_dma_len(sg));
 765                         stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
 766                                            dst_addr);
 767                 }
 768
 769                 if (ret < 0)
 770                         return ret;
 771
 772                 stm32_mdma_setup_hwdesc(chan, desc, direction, i, src_addr,
 773                                         dst_addr, sg_dma_len(sg), ctcr, ctbr,
 774                                         i == sg_len - 1, i == 0, false);
 775         }
 776
 777         /* Enable interrupts */
 778         ccr &= ~STM32_MDMA_CCR_IRQ_MASK;
 779         ccr |= STM32_MDMA_CCR_TEIE | STM32_MDMA_CCR_CTCIE;
 780         if (sg_len > 1)
 781                 ccr |= STM32_MDMA_CCR_BTIE;
 782         desc->ccr = ccr;
 783
 784         return 0;
 785 }
 786
 787 static struct dma_async_tx_descriptor *
 788 stm32_mdma_prep_slave_sg(struct dma_chan *c, struct scatterlist *sgl,
 789                          u32 sg_len, enum dma_transfer_direction direction,
 790                          unsigned long flags, void *context)
 791 {
 792         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
 793         struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
 794         struct stm32_mdma_desc *desc;
 795         int i, ret;
 796
 797         /*
 798          * Once DMA is in setup cyclic mode the channel we cannot assign this
 799          * channel anymore. The DMA channel needs to be aborted or terminated
 800          * for allowing another request.
 801          */
 802         if (chan->desc && chan->desc->cyclic) {
 803                 dev_err(chan2dev(chan),
 804                         "Request not allowed when dma in cyclic mode\n");
 805                 return NULL;
 806         }
 807
 808         desc = stm32_mdma_alloc_desc(chan, sg_len);
 809         if (!desc)
 810                 return NULL;
 811
 812         ret = stm32_mdma_setup_xfer(chan, desc, sgl, sg_len, direction);
 813         if (ret < 0)
 814                 goto xfer_setup_err;
 815
 816         /*
 817          * In case of M2M HW transfer triggered by STM32 DMA, we do not have to clear the
 818          * transfer complete flag by hardware in order to let the CPU rearm the STM32 DMA
 819          * with the next sg element and update some data in dmaengine framework.
 820          */
 821         if (chan_config->m2m_hw && direction == DMA_MEM_TO_DEV) {
 822                 struct stm32_mdma_hwdesc *hwdesc;
 823
 824                 for (i = 0; i < sg_len; i++) {
 825                         hwdesc = desc->node[i].hwdesc;
 826                         hwdesc->cmar = 0;
 827                         hwdesc->cmdr = 0;
 828                 }
 829         }
 830
 831         desc->cyclic = false;
 832
 833         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 834
 835 xfer_setup_err:
 836         for (i = 0; i < desc->count; i++)
 837                 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
 838                               desc->node[i].hwdesc_phys);
 839         kfree(desc);
 840         return NULL;
 841 }
 842
 843 static struct dma_async_tx_descriptor *
 844 stm32_mdma_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr,
 845                            size_t buf_len, size_t period_len,
 846                            enum dma_transfer_direction direction,
 847                            unsigned long flags)
 848 {
 849         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
 850         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
 851         struct dma_slave_config *dma_config = &chan->dma_config;
 852         struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
 853         struct stm32_mdma_desc *desc;
 854         dma_addr_t src_addr, dst_addr;
 855         u32 ccr, ctcr, ctbr, count;
 856         int i, ret;
 857
 858         /*
 859          * Once DMA is in setup cyclic mode the channel we cannot assign this
 860          * channel anymore. The DMA channel needs to be aborted or terminated
 861          * for allowing another request.
 862          */
 863         if (chan->desc && chan->desc->cyclic) {
 864                 dev_err(chan2dev(chan),
 865                         "Request not allowed when dma in cyclic mode\n");
 866                 return NULL;
 867         }
 868
 869         if (!buf_len || !period_len || period_len > STM32_MDMA_MAX_BLOCK_LEN) {
 870                 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 871                 return NULL;
 872         }
 873
 874         if (buf_len % period_len) {
 875                 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 876                 return NULL;
 877         }
 878
 879         count = buf_len / period_len;
 880
 881         desc = stm32_mdma_alloc_desc(chan, count);
 882         if (!desc)
 883                 return NULL;
 884
 885         /* Select bus */
 886         if (direction == DMA_MEM_TO_DEV) {
 887                 src_addr = buf_addr;
 888                 ret = stm32_mdma_set_xfer_param(chan, direction, &ccr, &ctcr,
 889                                                 &ctbr, src_addr, period_len);
 890                 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
 891                                    src_addr);
 892         } else {
 893                 dst_addr = buf_addr;
 894                 ret = stm32_mdma_set_xfer_param(chan, direction, &ccr, &ctcr,
 895                                                 &ctbr, dst_addr, period_len);
 896                 stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
 897                                    dst_addr);
 898         }
 899
 900         if (ret < 0)
 901                 goto xfer_setup_err;
 902
 903         /* Enable interrupts */
 904         ccr &= ~STM32_MDMA_CCR_IRQ_MASK;
 905         ccr |= STM32_MDMA_CCR_TEIE | STM32_MDMA_CCR_CTCIE | STM32_MDMA_CCR_BTIE;
 906         desc->ccr = ccr;
 907
 908         /* Configure hwdesc list */
 909         for (i = 0; i < count; i++) {
 910                 if (direction == DMA_MEM_TO_DEV) {
 911                         src_addr = buf_addr + i * period_len;
 912                         dst_addr = dma_config->dst_addr;
 913                         if (chan_config->m2m_hw && (i & 1))
 914                                 dst_addr += period_len;
 915                 } else {
 916                         src_addr = dma_config->src_addr;
 917                         if (chan_config->m2m_hw && (i & 1))
 918                                 src_addr += period_len;
 919                         dst_addr = buf_addr + i * period_len;
 920                 }
 921
 922                 stm32_mdma_setup_hwdesc(chan, desc, direction, i, src_addr,
 923                                         dst_addr, period_len, ctcr, ctbr,
 924                                         i == count - 1, i == 0, true);
 925         }
 926
 927         desc->cyclic = true;
 928
 929         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 930
 931 xfer_setup_err:
 932         for (i = 0; i < desc->count; i++)
 933                 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
 934                               desc->node[i].hwdesc_phys);
 935         kfree(desc);
 936         return NULL;
 937 }
 938
 939 static struct dma_async_tx_descriptor *
 940 stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
 941                            size_t len, unsigned long flags)
 942 {
 943         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
 944         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
 945         enum dma_slave_buswidth max_width;
 946         struct stm32_mdma_desc *desc;
 947         struct stm32_mdma_hwdesc *hwdesc;
 948         u32 ccr, ctcr, ctbr, cbndtr, count, max_burst, mdma_burst;
 949         u32 best_burst, tlen;
 950         size_t xfer_count, offset;
 951         int src_bus_width, dst_bus_width;
 952         int i;
 953
 954         /*
 955          * Once DMA is in setup cyclic mode the channel we cannot assign this
 956          * channel anymore. The DMA channel needs to be aborted or terminated
 957          * to allow another request
 958          */
 959         if (chan->desc && chan->desc->cyclic) {
 960                 dev_err(chan2dev(chan),
 961                         "Request not allowed when dma in cyclic mode\n");
 962                 return NULL;
 963         }
 964
 965         count = DIV_ROUND_UP(len, STM32_MDMA_MAX_BLOCK_LEN);
 966         desc = stm32_mdma_alloc_desc(chan, count);
 967         if (!desc)
 968                 return NULL;
 969
 970         ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id));
 971         ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id));
 972         ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id));
 973         cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
 974
 975         /* Enable sw req, some interrupts and clear other bits */
 976         ccr &= ~(STM32_MDMA_CCR_WEX | STM32_MDMA_CCR_HEX |
 977                  STM32_MDMA_CCR_BEX | STM32_MDMA_CCR_PL_MASK |
 978                  STM32_MDMA_CCR_IRQ_MASK);
 979         ccr |= STM32_MDMA_CCR_TEIE;
 980
 981         /* Enable SW request mode, dest/src inc and clear other bits */
 982         ctcr &= ~(STM32_MDMA_CTCR_BWM | STM32_MDMA_CTCR_TRGM_MSK |
 983                   STM32_MDMA_CTCR_PAM_MASK | STM32_MDMA_CTCR_PKE |
 984                   STM32_MDMA_CTCR_TLEN_MSK | STM32_MDMA_CTCR_DBURST_MASK |
 985                   STM32_MDMA_CTCR_SBURST_MASK | STM32_MDMA_CTCR_DINCOS_MASK |
 986                   STM32_MDMA_CTCR_SINCOS_MASK | STM32_MDMA_CTCR_DSIZE_MASK |
 987                   STM32_MDMA_CTCR_SSIZE_MASK | STM32_MDMA_CTCR_DINC_MASK |
 988                   STM32_MDMA_CTCR_SINC_MASK);
 989         ctcr |= STM32_MDMA_CTCR_SWRM | STM32_MDMA_CTCR_SINC(STM32_MDMA_INC) |
 990                 STM32_MDMA_CTCR_DINC(STM32_MDMA_INC);
 991
 992         /* Reset HW request */
 993         ctbr &= ~STM32_MDMA_CTBR_TSEL_MASK;
 994
 995         /* Select bus */
 996         stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS, src);
 997         stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS, dest);
 998
 999         /* Clear CBNDTR registers */
1000         cbndtr &= ~(STM32_MDMA_CBNDTR_BRC_MK | STM32_MDMA_CBNDTR_BRDUM |
1001                         STM32_MDMA_CBNDTR_BRSUM | STM32_MDMA_CBNDTR_BNDT_MASK);
1002
1003         if (len <= STM32_MDMA_MAX_BLOCK_LEN) {
1004                 cbndtr |= STM32_MDMA_CBNDTR_BNDT(len);
1005                 if (len <= STM32_MDMA_MAX_BUF_LEN) {
1006                         /* Setup a buffer transfer */
1007                         ccr |= STM32_MDMA_CCR_TCIE | STM32_MDMA_CCR_CTCIE;
1008                         ctcr |= STM32_MDMA_CTCR_TRGM(STM32_MDMA_BUFFER);
1009                 } else {
1010                         /* Setup a block transfer */
1011                         ccr |= STM32_MDMA_CCR_BTIE | STM32_MDMA_CCR_CTCIE;
1012                         ctcr |= STM32_MDMA_CTCR_TRGM(STM32_MDMA_BLOCK);
1013                 }
1014
1015                 tlen = STM32_MDMA_MAX_BUF_LEN;
1016                 ctcr |= STM32_MDMA_CTCR_TLEN((tlen - 1));
1017
1018                 /* Set source best burst size */
1019                 max_width = stm32_mdma_get_max_width(src, len, tlen);
1020                 src_bus_width = stm32_mdma_get_width(chan, max_width);
1021
1022                 max_burst = tlen / max_width;
1023                 best_burst = stm32_mdma_get_best_burst(len, tlen, max_burst,
1024                                                        max_width);
1025                 mdma_burst = ilog2(best_burst);
1026
1027                 ctcr |= STM32_MDMA_CTCR_SBURST(mdma_burst) |
1028                         STM32_MDMA_CTCR_SSIZE(src_bus_width) |
1029                         STM32_MDMA_CTCR_SINCOS(src_bus_width);
1030
1031                 /* Set destination best burst size */
1032                 max_width = stm32_mdma_get_max_width(dest, len, tlen);
1033                 dst_bus_width = stm32_mdma_get_width(chan, max_width);
1034
1035                 max_burst = tlen / max_width;
1036                 best_burst = stm32_mdma_get_best_burst(len, tlen, max_burst,
1037                                                        max_width);
1038                 mdma_burst = ilog2(best_burst);
1039
1040                 ctcr |= STM32_MDMA_CTCR_DBURST(mdma_burst) |
1041                         STM32_MDMA_CTCR_DSIZE(dst_bus_width) |
1042                         STM32_MDMA_CTCR_DINCOS(dst_bus_width);
1043
1044                 if (dst_bus_width != src_bus_width)
1045                         ctcr |= STM32_MDMA_CTCR_PKE;
1046
1047                 /* Prepare hardware descriptor */
1048                 hwdesc = desc->node[0].hwdesc;
1049                 hwdesc->ctcr = ctcr;
1050                 hwdesc->cbndtr = cbndtr;
1051                 hwdesc->csar = src;
1052                 hwdesc->cdar = dest;
1053                 hwdesc->cbrur = 0;
1054                 hwdesc->clar = 0;
1055                 hwdesc->ctbr = ctbr;
1056                 hwdesc->cmar = 0;
1057                 hwdesc->cmdr = 0;
1058
1059                 stm32_mdma_dump_hwdesc(chan, &desc->node[0]);
1060         } else {
1061                 /* Setup a LLI transfer */
1062                 ctcr |= STM32_MDMA_CTCR_TRGM(STM32_MDMA_LINKED_LIST) |
1063                         STM32_MDMA_CTCR_TLEN((STM32_MDMA_MAX_BUF_LEN - 1));
1064                 ccr |= STM32_MDMA_CCR_BTIE | STM32_MDMA_CCR_CTCIE;
1065                 tlen = STM32_MDMA_MAX_BUF_LEN;
1066
1067                 for (i = 0, offset = 0; offset < len;
1068                      i++, offset += xfer_count) {
1069                         xfer_count = min_t(size_t, len - offset,
1070                                            STM32_MDMA_MAX_BLOCK_LEN);
1071
1072                         /* Set source best burst size */
1073                         max_width = stm32_mdma_get_max_width(src, len, tlen);
1074                         src_bus_width = stm32_mdma_get_width(chan, max_width);
1075
1076                         max_burst = tlen / max_width;
1077                         best_burst = stm32_mdma_get_best_burst(len, tlen,
1078                                                                max_burst,
1079                                                                max_width);
1080                         mdma_burst = ilog2(best_burst);
1081
1082                         ctcr |= STM32_MDMA_CTCR_SBURST(mdma_burst) |
1083                                 STM32_MDMA_CTCR_SSIZE(src_bus_width) |
1084                                 STM32_MDMA_CTCR_SINCOS(src_bus_width);
1085
1086                         /* Set destination best burst size */
1087                         max_width = stm32_mdma_get_max_width(dest, len, tlen);
1088                         dst_bus_width = stm32_mdma_get_width(chan, max_width);
1089
1090                         max_burst = tlen / max_width;
1091                         best_burst = stm32_mdma_get_best_burst(len, tlen,
1092                                                                max_burst,
1093                                                                max_width);
1094                         mdma_burst = ilog2(best_burst);
1095
1096                         ctcr |= STM32_MDMA_CTCR_DBURST(mdma_burst) |
1097                                 STM32_MDMA_CTCR_DSIZE(dst_bus_width) |
1098                                 STM32_MDMA_CTCR_DINCOS(dst_bus_width);
1099
1100                         if (dst_bus_width != src_bus_width)
1101                                 ctcr |= STM32_MDMA_CTCR_PKE;
1102
1103                         /* Prepare hardware descriptor */
1104                         stm32_mdma_setup_hwdesc(chan, desc, DMA_MEM_TO_MEM, i,
1105                                                 src + offset, dest + offset,
1106                                                 xfer_count, ctcr, ctbr,
1107                                                 i == count - 1, i == 0, false);
1108                 }
1109         }
1110
1111         desc->ccr = ccr;
1112
1113         desc->cyclic = false;
1114
1115         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1116 }
1117
1118 static void stm32_mdma_dump_reg(struct stm32_mdma_chan *chan)
1119 {
1120         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1121
1122         dev_dbg(chan2dev(chan), "CCR:     0x%08x\n",
1123                 stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)));
1124         dev_dbg(chan2dev(chan), "CTCR:    0x%08x\n",
1125                 stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)));
1126         dev_dbg(chan2dev(chan), "CBNDTR:  0x%08x\n",
1127                 stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)));
1128         dev_dbg(chan2dev(chan), "CSAR:    0x%08x\n",
1129                 stm32_mdma_read(dmadev, STM32_MDMA_CSAR(chan->id)));
1130         dev_dbg(chan2dev(chan), "CDAR:    0x%08x\n",
1131                 stm32_mdma_read(dmadev, STM32_MDMA_CDAR(chan->id)));
1132         dev_dbg(chan2dev(chan), "CBRUR:   0x%08x\n",
1133                 stm32_mdma_read(dmadev, STM32_MDMA_CBRUR(chan->id)));
1134         dev_dbg(chan2dev(chan), "CLAR:    0x%08x\n",
1135                 stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id)));
1136         dev_dbg(chan2dev(chan), "CTBR:    0x%08x\n",
1137                 stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)));
1138         dev_dbg(chan2dev(chan), "CMAR:    0x%08x\n",
1139                 stm32_mdma_read(dmadev, STM32_MDMA_CMAR(chan->id)));
1140         dev_dbg(chan2dev(chan), "CMDR:    0x%08x\n",
1141                 stm32_mdma_read(dmadev, STM32_MDMA_CMDR(chan->id)));
1142 }
1143
1144 static void stm32_mdma_start_transfer(struct stm32_mdma_chan *chan)
1145 {
1146         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1147         struct virt_dma_desc *vdesc;
1148         struct stm32_mdma_hwdesc *hwdesc;
1149         u32 id = chan->id;
1150         u32 status, reg;
1151
1152         vdesc = vchan_next_desc(&chan->vchan);
1153         if (!vdesc) {
1154                 chan->desc = NULL;
1155                 return;
1156         }
1157
1158         list_del(&vdesc->node);
1159
1160         chan->desc = to_stm32_mdma_desc(vdesc);
1161         hwdesc = chan->desc->node[0].hwdesc;
1162         chan->curr_hwdesc = 0;
1163
1164         stm32_mdma_write(dmadev, STM32_MDMA_CCR(id), chan->desc->ccr);
1165         stm32_mdma_write(dmadev, STM32_MDMA_CTCR(id), hwdesc->ctcr);
1166         stm32_mdma_write(dmadev, STM32_MDMA_CBNDTR(id), hwdesc->cbndtr);
1167         stm32_mdma_write(dmadev, STM32_MDMA_CSAR(id), hwdesc->csar);
1168         stm32_mdma_write(dmadev, STM32_MDMA_CDAR(id), hwdesc->cdar);
1169         stm32_mdma_write(dmadev, STM32_MDMA_CBRUR(id), hwdesc->cbrur);
1170         stm32_mdma_write(dmadev, STM32_MDMA_CLAR(id), hwdesc->clar);
1171         stm32_mdma_write(dmadev, STM32_MDMA_CTBR(id), hwdesc->ctbr);
1172         stm32_mdma_write(dmadev, STM32_MDMA_CMAR(id), hwdesc->cmar);
1173         stm32_mdma_write(dmadev, STM32_MDMA_CMDR(id), hwdesc->cmdr);
1174
1175         /* Clear interrupt status if it is there */
1176         status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1177         if (status)
1178                 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(id), status);
1179
1180         stm32_mdma_dump_reg(chan);
1181
1182         /* Start DMA */
1183         stm32_mdma_set_bits(dmadev, STM32_MDMA_CCR(id), STM32_MDMA_CCR_EN);
1184
1185         /* Set SW request in case of MEM2MEM transfer */
1186         if (hwdesc->ctcr & STM32_MDMA_CTCR_SWRM) {
1187                 reg = STM32_MDMA_CCR(id);
1188                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ);
1189         }
1190
1191         chan->busy = true;
1192
1193         dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
1194 }
1195
1196 static void stm32_mdma_issue_pending(struct dma_chan *c)
1197 {
1198         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1199         unsigned long flags;
1200
1201         spin_lock_irqsave(&chan->vchan.lock, flags);
1202
1203         if (!vchan_issue_pending(&chan->vchan))
1204                 goto end;
1205
1206         dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
1207
1208         if (!chan->desc && !chan->busy)
1209                 stm32_mdma_start_transfer(chan);
1210
1211 end:
1212         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1213 }
1214
1215 static int stm32_mdma_pause(struct dma_chan *c)
1216 {
1217         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1218         unsigned long flags;
1219         int ret;
1220
1221         spin_lock_irqsave(&chan->vchan.lock, flags);
1222         ret = stm32_mdma_disable_chan(chan);
1223         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1224
1225         if (!ret)
1226                 dev_dbg(chan2dev(chan), "vchan %pK: pause\n", &chan->vchan);
1227
1228         return ret;
1229 }
1230
1231 static int stm32_mdma_resume(struct dma_chan *c)
1232 {
1233         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1234         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1235         struct stm32_mdma_hwdesc *hwdesc;
1236         unsigned long flags;
1237         u32 status, reg;
1238
1239         hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc;
1240
1241         spin_lock_irqsave(&chan->vchan.lock, flags);
1242
1243         /* Re-configure control register */
1244         stm32_mdma_write(dmadev, STM32_MDMA_CCR(chan->id), chan->desc->ccr);
1245
1246         /* Clear interrupt status if it is there */
1247         status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1248         if (status)
1249                 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status);
1250
1251         stm32_mdma_dump_reg(chan);
1252
1253         /* Re-start DMA */
1254         reg = STM32_MDMA_CCR(chan->id);
1255         stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_EN);
1256
1257         /* Set SW request in case of MEM2MEM transfer */
1258         if (hwdesc->ctcr & STM32_MDMA_CTCR_SWRM)
1259                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ);
1260
1261         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1262
1263         dev_dbg(chan2dev(chan), "vchan %pK: resume\n", &chan->vchan);
1264
1265         return 0;
1266 }
1267
1268 static int stm32_mdma_terminate_all(struct dma_chan *c)
1269 {
1270         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1271         unsigned long flags;
1272         LIST_HEAD(head);
1273
1274         spin_lock_irqsave(&chan->vchan.lock, flags);
1275         if (chan->desc) {
1276                 vchan_terminate_vdesc(&chan->desc->vdesc);
1277                 if (chan->busy)
1278                         stm32_mdma_stop(chan);
1279                 chan->desc = NULL;
1280         }
1281         vchan_get_all_descriptors(&chan->vchan, &head);
1282         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1283
1284         vchan_dma_desc_free_list(&chan->vchan, &head);
1285
1286         return 0;
1287 }
1288
1289 static void stm32_mdma_synchronize(struct dma_chan *c)
1290 {
1291         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1292
1293         vchan_synchronize(&chan->vchan);
1294 }
1295
1296 static int stm32_mdma_slave_config(struct dma_chan *c,
1297                                    struct dma_slave_config *config)
1298 {
1299         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1300
1301         memcpy(&chan->dma_config, config, sizeof(*config));
1302
1303         /* Check if user is requesting STM32 DMA to trigger MDMA */
1304         if (config->peripheral_size) {
1305                 struct stm32_mdma_dma_config *mdma_config;
1306
1307                 mdma_config = (struct stm32_mdma_dma_config *)chan->dma_config.peripheral_config;
1308                 chan->chan_config.request = mdma_config->request;
1309                 chan->chan_config.mask_addr = mdma_config->cmar;
1310                 chan->chan_config.mask_data = mdma_config->cmdr;
1311                 chan->chan_config.m2m_hw = true;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static size_t stm32_mdma_desc_residue(struct stm32_mdma_chan *chan,
1318                                       struct stm32_mdma_desc *desc,
1319                                       u32 curr_hwdesc)
1320 {
1321         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1322         struct stm32_mdma_hwdesc *hwdesc;
1323         u32 cbndtr, residue, modulo, burst_size;
1324         int i;
1325
1326         residue = 0;
1327         for (i = curr_hwdesc + 1; i < desc->count; i++) {
1328                 hwdesc = desc->node[i].hwdesc;
1329                 residue += STM32_MDMA_CBNDTR_BNDT(hwdesc->cbndtr);
1330         }
1331         cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
1332         residue += cbndtr & STM32_MDMA_CBNDTR_BNDT_MASK;
1333
1334         if (!chan->mem_burst)
1335                 return residue;
1336
1337         burst_size = chan->mem_burst * chan->mem_width;
1338         modulo = residue % burst_size;
1339         if (modulo)
1340                 residue = residue - modulo + burst_size;
1341
1342         return residue;
1343 }
1344
1345 static enum dma_status stm32_mdma_tx_status(struct dma_chan *c,
1346                                             dma_cookie_t cookie,
1347                                             struct dma_tx_state *state)
1348 {
1349         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1350         struct virt_dma_desc *vdesc;
1351         enum dma_status status;
1352         unsigned long flags;
1353         u32 residue = 0;
1354
1355         status = dma_cookie_status(c, cookie, state);
1356         if ((status == DMA_COMPLETE) || (!state))
1357                 return status;
1358
1359         spin_lock_irqsave(&chan->vchan.lock, flags);
1360
1361         vdesc = vchan_find_desc(&chan->vchan, cookie);
1362         if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1363                 residue = stm32_mdma_desc_residue(chan, chan->desc,
1364                                                   chan->curr_hwdesc);
1365         else if (vdesc)
1366                 residue = stm32_mdma_desc_residue(chan,
1367                                                   to_stm32_mdma_desc(vdesc), 0);
1368         dma_set_residue(state, residue);
1369
1370         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1371
1372         return status;
1373 }
1374
1375 static void stm32_mdma_xfer_end(struct stm32_mdma_chan *chan)
1376 {
1377         vchan_cookie_complete(&chan->desc->vdesc);
1378         chan->desc = NULL;
1379         chan->busy = false;
1380
1381         /* Start the next transfer if this driver has a next desc */
1382         stm32_mdma_start_transfer(chan);
1383 }
1384
1385 static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid)
1386 {
1387         struct stm32_mdma_device *dmadev = devid;
1388         struct stm32_mdma_chan *chan;
1389         u32 reg, id, ccr, ien, status;
1390
1391         /* Find out which channel generates the interrupt */
1392         status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
1393         if (!status) {
1394                 dev_dbg(mdma2dev(dmadev), "spurious it\n");
1395                 return IRQ_NONE;
1396         }
1397         id = __ffs(status);
1398         chan = &dmadev->chan[id];
1399
1400         /* Handle interrupt for the channel */
1401         spin_lock(&chan->vchan.lock);
1402         status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1403         /* Mask Channel ReQuest Active bit which can be set in case of MEM2MEM */
1404         status &= ~STM32_MDMA_CISR_CRQA;
1405         ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
1406         ien = (ccr & STM32_MDMA_CCR_IRQ_MASK) >> 1;
1407
1408         if (!(status & ien)) {
1409                 spin_unlock(&chan->vchan.lock);
1410                 if (chan->busy)
1411                         dev_warn(chan2dev(chan),
1412                                  "spurious it (status=0x%04x, ien=0x%04x)\n", status, ien);
1413                 else
1414                         dev_dbg(chan2dev(chan),
1415                                 "spurious it (status=0x%04x, ien=0x%04x)\n", status, ien);
1416                 return IRQ_NONE;
1417         }
1418
1419         reg = STM32_MDMA_CIFCR(id);
1420
1421         if (status & STM32_MDMA_CISR_TEIF) {
1422                 dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n",
1423                         readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)));
1424                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF);
1425                 status &= ~STM32_MDMA_CISR_TEIF;
1426         }
1427
1428         if (status & STM32_MDMA_CISR_CTCIF) {
1429                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CCTCIF);
1430                 status &= ~STM32_MDMA_CISR_CTCIF;
1431                 stm32_mdma_xfer_end(chan);
1432         }
1433
1434         if (status & STM32_MDMA_CISR_BRTIF) {
1435                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBRTIF);
1436                 status &= ~STM32_MDMA_CISR_BRTIF;
1437         }
1438
1439         if (status & STM32_MDMA_CISR_BTIF) {
1440                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBTIF);
1441                 status &= ~STM32_MDMA_CISR_BTIF;
1442                 chan->curr_hwdesc++;
1443                 if (chan->desc && chan->desc->cyclic) {
1444                         if (chan->curr_hwdesc == chan->desc->count)
1445                                 chan->curr_hwdesc = 0;
1446                         vchan_cyclic_callback(&chan->desc->vdesc);
1447                 }
1448         }
1449
1450         if (status & STM32_MDMA_CISR_TCIF) {
1451                 stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CLTCIF);
1452                 status &= ~STM32_MDMA_CISR_TCIF;
1453         }
1454
1455         if (status) {
1456                 stm32_mdma_set_bits(dmadev, reg, status);
1457                 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
1458                 if (!(ccr & STM32_MDMA_CCR_EN))
1459                         dev_err(chan2dev(chan), "chan disabled by HW\n");
1460         }
1461
1462         spin_unlock(&chan->vchan.lock);
1463
1464         return IRQ_HANDLED;
1465 }
1466
1467 static int stm32_mdma_alloc_chan_resources(struct dma_chan *c)
1468 {
1469         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1470         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1471         int ret;
1472
1473         chan->desc_pool = dmam_pool_create(dev_name(&c->dev->device),
1474                                            c->device->dev,
1475                                            sizeof(struct stm32_mdma_hwdesc),
1476                                           __alignof__(struct stm32_mdma_hwdesc),
1477                                            0);
1478         if (!chan->desc_pool) {
1479                 dev_err(chan2dev(chan), "failed to allocate descriptor pool\n");
1480                 return -ENOMEM;
1481         }
1482
1483         ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1484         if (ret < 0)
1485                 return ret;
1486
1487         ret = stm32_mdma_disable_chan(chan);
1488         if (ret < 0)
1489                 pm_runtime_put(dmadev->ddev.dev);
1490
1491         return ret;
1492 }
1493
1494 static void stm32_mdma_free_chan_resources(struct dma_chan *c)
1495 {
1496         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1497         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1498         unsigned long flags;
1499
1500         dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1501
1502         if (chan->busy) {
1503                 spin_lock_irqsave(&chan->vchan.lock, flags);
1504                 stm32_mdma_stop(chan);
1505                 chan->desc = NULL;
1506                 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1507         }
1508
1509         pm_runtime_put(dmadev->ddev.dev);
1510         vchan_free_chan_resources(to_virt_chan(c));
1511         dmam_pool_destroy(chan->desc_pool);
1512         chan->desc_pool = NULL;
1513 }
1514
1515 static bool stm32_mdma_filter_fn(struct dma_chan *c, void *fn_param)
1516 {
1517         struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
1518         struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1519
1520         /* Check if chan is marked Secure */
1521         if (dmadev->chan_reserved & BIT(chan->id))
1522                 return false;
1523
1524         return true;
1525 }
1526
1527 static struct dma_chan *stm32_mdma_of_xlate(struct of_phandle_args *dma_spec,
1528                                             struct of_dma *ofdma)
1529 {
1530         struct stm32_mdma_device *dmadev = ofdma->of_dma_data;
1531         dma_cap_mask_t mask = dmadev->ddev.cap_mask;
1532         struct stm32_mdma_chan *chan;
1533         struct dma_chan *c;
1534         struct stm32_mdma_chan_config config;
1535
1536         if (dma_spec->args_count < 5) {
1537                 dev_err(mdma2dev(dmadev), "Bad number of args\n");
1538                 return NULL;
1539         }
1540
1541         memset(&config, 0, sizeof(config));
1542         config.request = dma_spec->args[0];
1543         config.priority_level = dma_spec->args[1];
1544         config.transfer_config = dma_spec->args[2];
1545         config.mask_addr = dma_spec->args[3];
1546         config.mask_data = dma_spec->args[4];
1547
1548         if (config.request >= dmadev->nr_requests) {
1549                 dev_err(mdma2dev(dmadev), "Bad request line\n");
1550                 return NULL;
1551         }
1552
1553         if (config.priority_level > STM32_MDMA_VERY_HIGH_PRIORITY) {
1554                 dev_err(mdma2dev(dmadev), "Priority level not supported\n");
1555                 return NULL;
1556         }
1557
1558         c = __dma_request_channel(&mask, stm32_mdma_filter_fn, &config, ofdma->of_node);
1559         if (!c) {
1560                 dev_err(mdma2dev(dmadev), "No more channels available\n");
1561                 return NULL;
1562         }
1563
1564         chan = to_stm32_mdma_chan(c);
1565         chan->chan_config = config;
1566
1567         return c;
1568 }
1569
1570 static const struct of_device_id stm32_mdma_of_match[] = {
1571         { .compatible = "st,stm32h7-mdma", },
1572         { /* sentinel */ },
1573 };
1574 MODULE_DEVICE_TABLE(of, stm32_mdma_of_match);
1575
1576 static int stm32_mdma_probe(struct platform_device *pdev)
1577 {
1578         struct stm32_mdma_chan *chan;
1579         struct stm32_mdma_device *dmadev;
1580         struct dma_device *dd;
1581         struct device_node *of_node;
1582         struct reset_control *rst;
1583         u32 nr_channels, nr_requests;
1584         int i, count, ret;
1585
1586         of_node = pdev->dev.of_node;
1587         if (!of_node)
1588                 return -ENODEV;
1589
1590         ret = device_property_read_u32(&pdev->dev, "dma-channels",
1591                                        &nr_channels);
1592         if (ret) {
1593                 nr_channels = STM32_MDMA_MAX_CHANNELS;
1594                 dev_warn(&pdev->dev, "MDMA defaulting on %i channels\n",
1595                          nr_channels);
1596         }
1597
1598         ret = device_property_read_u32(&pdev->dev, "dma-requests",
1599                                        &nr_requests);
1600         if (ret) {
1601                 nr_requests = STM32_MDMA_MAX_REQUESTS;
1602                 dev_warn(&pdev->dev, "MDMA defaulting on %i request lines\n",
1603                          nr_requests);
1604         }
1605
1606         count = device_property_count_u32(&pdev->dev, "st,ahb-addr-masks");
1607         if (count < 0)
1608                 count = 0;
1609
1610         dmadev = devm_kzalloc(&pdev->dev,
1611                               struct_size(dmadev, ahb_addr_masks, count),
1612                               GFP_KERNEL);
1613         if (!dmadev)
1614                 return -ENOMEM;
1615
1616         dmadev->nr_channels = nr_channels;
1617         dmadev->nr_requests = nr_requests;
1618         device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
1619                                        dmadev->ahb_addr_masks,
1620                                        count);
1621         dmadev->nr_ahb_addr_masks = count;
1622
1623         dmadev->base = devm_platform_ioremap_resource(pdev, 0);
1624         if (IS_ERR(dmadev->base))
1625                 return PTR_ERR(dmadev->base);
1626
1627         dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1628         if (IS_ERR(dmadev->clk))
1629                 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk),
1630                                      "Missing clock controller\n");
1631
1632         ret = clk_prepare_enable(dmadev->clk);
1633         if (ret < 0) {
1634                 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
1635                 return ret;
1636         }
1637
1638         rst = devm_reset_control_get(&pdev->dev, NULL);
1639         if (IS_ERR(rst)) {
1640                 ret = PTR_ERR(rst);
1641                 if (ret == -EPROBE_DEFER)
1642                         goto err_clk;
1643         } else {
1644                 reset_control_assert(rst);
1645                 udelay(2);
1646                 reset_control_deassert(rst);
1647         }
1648
1649         dd = &dmadev->ddev;
1650         dma_cap_set(DMA_SLAVE, dd->cap_mask);
1651         dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1652         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1653         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1654         dd->device_alloc_chan_resources = stm32_mdma_alloc_chan_resources;
1655         dd->device_free_chan_resources = stm32_mdma_free_chan_resources;
1656         dd->device_tx_status = stm32_mdma_tx_status;
1657         dd->device_issue_pending = stm32_mdma_issue_pending;
1658         dd->device_prep_slave_sg = stm32_mdma_prep_slave_sg;
1659         dd->device_prep_dma_cyclic = stm32_mdma_prep_dma_cyclic;
1660         dd->device_prep_dma_memcpy = stm32_mdma_prep_dma_memcpy;
1661         dd->device_config = stm32_mdma_slave_config;
1662         dd->device_pause = stm32_mdma_pause;
1663         dd->device_resume = stm32_mdma_resume;
1664         dd->device_terminate_all = stm32_mdma_terminate_all;
1665         dd->device_synchronize = stm32_mdma_synchronize;
1666         dd->descriptor_reuse = true;
1667
1668         dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1669                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1670                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1671                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1672         dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1673                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1674                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1675                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1676         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1677                 BIT(DMA_MEM_TO_MEM);
1678         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1679         dd->max_burst = STM32_MDMA_MAX_BURST;
1680         dd->dev = &pdev->dev;
1681         INIT_LIST_HEAD(&dd->channels);
1682
1683         for (i = 0; i < dmadev->nr_channels; i++) {
1684                 chan = &dmadev->chan[i];
1685                 chan->id = i;
1686
1687                 if (stm32_mdma_read(dmadev, STM32_MDMA_CCR(i)) & STM32_MDMA_CCR_SM)
1688                         dmadev->chan_reserved |= BIT(i);
1689
1690                 chan->vchan.desc_free = stm32_mdma_desc_free;
1691                 vchan_init(&chan->vchan, dd);
1692         }
1693
1694         dmadev->irq = platform_get_irq(pdev, 0);
1695         if (dmadev->irq < 0) {
1696                 ret = dmadev->irq;
1697                 goto err_clk;
1698         }
1699
1700         ret = devm_request_irq(&pdev->dev, dmadev->irq, stm32_mdma_irq_handler,
1701                                0, dev_name(&pdev->dev), dmadev);
1702         if (ret) {
1703                 dev_err(&pdev->dev, "failed to request IRQ\n");
1704                 goto err_clk;
1705         }
1706
1707         ret = dmaenginem_async_device_register(dd);
1708         if (ret)
1709                 goto err_clk;
1710
1711         ret = of_dma_controller_register(of_node, stm32_mdma_of_xlate, dmadev);
1712         if (ret < 0) {
1713                 dev_err(&pdev->dev,
1714                         "STM32 MDMA DMA OF registration failed %d\n", ret);
1715                 goto err_clk;
1716         }
1717
1718         platform_set_drvdata(pdev, dmadev);
1719         pm_runtime_set_active(&pdev->dev);
1720         pm_runtime_enable(&pdev->dev);
1721         pm_runtime_get_noresume(&pdev->dev);
1722         pm_runtime_put(&pdev->dev);
1723
1724         dev_info(&pdev->dev, "STM32 MDMA driver registered\n");
1725
1726         return 0;
1727
1728 err_clk:
1729         clk_disable_unprepare(dmadev->clk);
1730
1731         return ret;
1732 }
1733
1734 #ifdef CONFIG_PM
1735 static int stm32_mdma_runtime_suspend(struct device *dev)
1736 {
1737         struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1738
1739         clk_disable_unprepare(dmadev->clk);
1740
1741         return 0;
1742 }
1743
1744 static int stm32_mdma_runtime_resume(struct device *dev)
1745 {
1746         struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1747         int ret;
1748
1749         ret = clk_prepare_enable(dmadev->clk);
1750         if (ret) {
1751                 dev_err(dev, "failed to prepare_enable clock\n");
1752                 return ret;
1753         }
1754
1755         return 0;
1756 }
1757 #endif
1758
1759 #ifdef CONFIG_PM_SLEEP
1760 static int stm32_mdma_pm_suspend(struct device *dev)
1761 {
1762         struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1763         u32 ccr, id;
1764         int ret;
1765
1766         ret = pm_runtime_resume_and_get(dev);
1767         if (ret < 0)
1768                 return ret;
1769
1770         for (id = 0; id < dmadev->nr_channels; id++) {
1771                 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
1772                 if (ccr & STM32_MDMA_CCR_EN) {
1773                         dev_warn(dev, "Suspend is prevented by Chan %i\n", id);
1774                         return -EBUSY;
1775                 }
1776         }
1777
1778         pm_runtime_put_sync(dev);
1779
1780         pm_runtime_force_suspend(dev);
1781
1782         return 0;
1783 }
1784
1785 static int stm32_mdma_pm_resume(struct device *dev)
1786 {
1787         return pm_runtime_force_resume(dev);
1788 }
1789 #endif
1790
1791 static const struct dev_pm_ops stm32_mdma_pm_ops = {
1792         SET_SYSTEM_SLEEP_PM_OPS(stm32_mdma_pm_suspend, stm32_mdma_pm_resume)
1793         SET_RUNTIME_PM_OPS(stm32_mdma_runtime_suspend,
1794                            stm32_mdma_runtime_resume, NULL)
1795 };
1796
1797 static struct platform_driver stm32_mdma_driver = {
1798         .probe = stm32_mdma_probe,
1799         .driver = {
1800                 .name = "stm32-mdma",
1801                 .of_match_table = stm32_mdma_of_match,
1802                 .pm = &stm32_mdma_pm_ops,
1803         },
1804 };
1805
1806 static int __init stm32_mdma_init(void)
1807 {
1808         return platform_driver_register(&stm32_mdma_driver);
1809 }
1810
1811 subsys_initcall(stm32_mdma_init);
1812
1813 MODULE_DESCRIPTION("Driver for STM32 MDMA controller");
1814 MODULE_AUTHOR("M'boumba Cedric Madianga <[email protected]>");
1815 MODULE_AUTHOR("Pierre-Yves Mordret <[email protected]>");