drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

   1 /****************************************************************************\
   2 *
   3 *  File Name      ta_ras_if.h
   4 *  Project        AMD PSP SW IP Module
   5 *
   6 *  Description    Interface to the RAS Trusted Application
   7 *
   8 *  Copyright 2019 Advanced Micro Devices, Inc.
   9 *
  10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
  11 * and associated documentation files (the "Software"), to deal in the Software without restriction,
  12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
  14 * subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in all copies or substantial
  17 * portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25 * OTHER DEALINGS IN THE SOFTWARE.
  26 */
  27 #ifndef _TA_RAS_IF_H
  28 #define _TA_RAS_IF_H
  29
  30 /* Responses have bit 31 set */
  31 #define RSP_ID_MASK (1U << 31)
  32 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
  33
  34 #define TA_NUM_BLOCK_MAX                14
  35
  36 enum ras_command {
  37         TA_RAS_COMMAND__ENABLE_FEATURES = 0,
  38         TA_RAS_COMMAND__DISABLE_FEATURES,
  39         TA_RAS_COMMAND__TRIGGER_ERROR,
  40 };
  41
  42 enum ta_ras_status {
  43         TA_RAS_STATUS__SUCCESS                          = 0x00,
  44         TA_RAS_STATUS__RESET_NEEDED                     = 0x01,
  45         TA_RAS_STATUS__ERROR_INVALID_PARAMETER          = 0x02,
  46         TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE          = 0x03,
  47         TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD          = 0x04,
  48         TA_RAS_STATUS__ERROR_INJECTION_FAILED           = 0x05
  49 };
  50
  51 enum ta_ras_block {
  52         TA_RAS_BLOCK__UMC = 0,
  53         TA_RAS_BLOCK__SDMA,
  54         TA_RAS_BLOCK__GFX,
  55         TA_RAS_BLOCK__MMHUB,
  56         TA_RAS_BLOCK__ATHUB,
  57         TA_RAS_BLOCK__PCIE_BIF,
  58         TA_RAS_BLOCK__HDP,
  59         TA_RAS_BLOCK__XGMI_WAFL,
  60         TA_RAS_BLOCK__DF,
  61         TA_RAS_BLOCK__SMN,
  62         TA_RAS_BLOCK__SEM,
  63         TA_RAS_BLOCK__MP0,
  64         TA_RAS_BLOCK__MP1,
  65         TA_RAS_BLOCK__FUSE = (TA_NUM_BLOCK_MAX - 1),
  66 };
  67
  68 enum ta_ras_error_type {
  69         TA_RAS_ERROR__NONE                              = 0,
  70         TA_RAS_ERROR__PARITY                            = 1,
  71         TA_RAS_ERROR__SINGLE_CORRECTABLE                = 2,
  72         TA_RAS_ERROR__MULTI_UNCORRECTABLE               = 4,
  73         TA_RAS_ERROR__POISON                            = 8
  74 };
  75
  76 struct ta_ras_enable_features_input {
  77         enum ta_ras_block       block_id;
  78         enum ta_ras_error_type  error_type;
  79 };
  80
  81 struct ta_ras_disable_features_input {
  82         enum ta_ras_block       block_id;
  83         enum ta_ras_error_type  error_type;
  84 };
  85
  86 struct ta_ras_trigger_error_input {
  87         enum ta_ras_block               block_id;
  88         enum ta_ras_error_type          inject_error_type;
  89         uint32_t                        sub_block_index;
  90         uint64_t                        address;
  91         uint64_t                        value;
  92 };
  93
  94 union ta_ras_cmd_input {
  95         struct ta_ras_enable_features_input     enable_features;
  96         struct ta_ras_disable_features_input    disable_features;
  97         struct ta_ras_trigger_error_input       trigger_error;
  98 };
  99
 100 struct ta_ras_shared_memory {
 101         uint32_t                        cmd_id;
 102         uint32_t                        resp_id;
 103         enum ta_ras_status              ras_status;
 104         uint32_t                        reserved;
 105         union ta_ras_cmd_input          ras_in_message;
 106 };
 107
 108 #endif // TL_RAS_IF_H_