2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
45 #include "drm_crtc_internal.h"
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
102 static const struct edid_quirk {
106 } edid_quirk_list[] = {
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
162 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
163 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
165 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
166 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
168 /* Valve Index Headset */
169 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
170 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
171 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
172 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
187 /* HTC Vive and Vive Pro VR Headsets */
188 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
189 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
191 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
192 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
193 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
194 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
196 /* Windows Mixed Reality Headsets */
197 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
198 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
199 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
200 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
201 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
202 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
203 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
204 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
206 /* Sony PlayStation VR Headset */
207 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
209 /* Sensics VR Headsets */
210 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
212 /* OSVR HDK and HDK2 VR Headsets */
213 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
217 * Autogenerated from the DMT spec.
218 * This table is copied from xfree86/modes/xf86EdidModes.c.
220 static const struct drm_display_mode drm_dmt_modes[] = {
221 /* 0x01 - 640x350@85Hz */
222 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
223 736, 832, 0, 350, 382, 385, 445, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
225 /* 0x02 - 640x400@85Hz */
226 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 400, 401, 404, 445, 0,
228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 0x03 - 720x400@85Hz */
230 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
231 828, 936, 0, 400, 401, 404, 446, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x04 - 640x480@60Hz */
234 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
235 752, 800, 0, 480, 490, 492, 525, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x05 - 640x480@72Hz */
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
239 704, 832, 0, 480, 489, 492, 520, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x06 - 640x480@75Hz */
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
243 720, 840, 0, 480, 481, 484, 500, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x07 - 640x480@85Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
247 752, 832, 0, 480, 481, 484, 509, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x08 - 800x600@56Hz */
250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
251 896, 1024, 0, 600, 601, 603, 625, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x09 - 800x600@60Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
255 968, 1056, 0, 600, 601, 605, 628, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x0a - 800x600@72Hz */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
259 976, 1040, 0, 600, 637, 643, 666, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x0b - 800x600@75Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
263 896, 1056, 0, 600, 601, 604, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0c - 800x600@85Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
267 896, 1048, 0, 600, 601, 604, 631, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0d - 800x600@120Hz RB */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
271 880, 960, 0, 600, 603, 607, 636, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
273 /* 0x0e - 848x480@60Hz */
274 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
275 976, 1088, 0, 480, 486, 494, 517, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0f - 1024x768@43Hz, interlace */
278 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
279 1208, 1264, 0, 768, 768, 776, 817, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
281 DRM_MODE_FLAG_INTERLACE) },
282 /* 0x10 - 1024x768@60Hz */
283 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
284 1184, 1344, 0, 768, 771, 777, 806, 0,
285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
286 /* 0x11 - 1024x768@70Hz */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
288 1184, 1328, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x12 - 1024x768@75Hz */
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
292 1136, 1312, 0, 768, 769, 772, 800, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x13 - 1024x768@85Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
296 1168, 1376, 0, 768, 769, 772, 808, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x14 - 1024x768@120Hz RB */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
300 1104, 1184, 0, 768, 771, 775, 813, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x15 - 1152x864@75Hz */
303 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
304 1344, 1600, 0, 864, 865, 868, 900, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x55 - 1280x720@60Hz */
307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
308 1430, 1650, 0, 720, 725, 730, 750, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x16 - 1280x768@60Hz RB */
311 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
312 1360, 1440, 0, 768, 771, 778, 790, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x17 - 1280x768@60Hz */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
316 1472, 1664, 0, 768, 771, 778, 798, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x18 - 1280x768@75Hz */
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
320 1488, 1696, 0, 768, 771, 778, 805, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x19 - 1280x768@85Hz */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
324 1496, 1712, 0, 768, 771, 778, 809, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x1a - 1280x768@120Hz RB */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
328 1360, 1440, 0, 768, 771, 778, 813, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
330 /* 0x1b - 1280x800@60Hz RB */
331 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
332 1360, 1440, 0, 800, 803, 809, 823, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x1c - 1280x800@60Hz */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
336 1480, 1680, 0, 800, 803, 809, 831, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x1d - 1280x800@75Hz */
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
340 1488, 1696, 0, 800, 803, 809, 838, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1e - 1280x800@85Hz */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
344 1496, 1712, 0, 800, 803, 809, 843, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1f - 1280x800@120Hz RB */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
348 1360, 1440, 0, 800, 803, 809, 847, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x20 - 1280x960@60Hz */
351 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
352 1488, 1800, 0, 960, 961, 964, 1000, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x21 - 1280x960@85Hz */
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
356 1504, 1728, 0, 960, 961, 964, 1011, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x22 - 1280x960@120Hz RB */
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
360 1360, 1440, 0, 960, 963, 967, 1017, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x23 - 1280x1024@60Hz */
363 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
364 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x24 - 1280x1024@75Hz */
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x25 - 1280x1024@85Hz */
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
372 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x26 - 1280x1024@120Hz RB */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
376 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
378 /* 0x27 - 1360x768@60Hz */
379 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
380 1536, 1792, 0, 768, 771, 777, 795, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x28 - 1360x768@120Hz RB */
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
384 1440, 1520, 0, 768, 771, 776, 813, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386 /* 0x51 - 1366x768@60Hz */
387 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
388 1579, 1792, 0, 768, 771, 774, 798, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x56 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
392 1436, 1500, 0, 768, 769, 772, 800, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x29 - 1400x1050@60Hz RB */
395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
396 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x2a - 1400x1050@60Hz */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
400 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x2b - 1400x1050@75Hz */
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
404 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x2c - 1400x1050@85Hz */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
408 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x2d - 1400x1050@120Hz RB */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
412 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
414 /* 0x2e - 1440x900@60Hz RB */
415 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
416 1520, 1600, 0, 900, 903, 909, 926, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2f - 1440x900@60Hz */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
420 1672, 1904, 0, 900, 903, 909, 934, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x30 - 1440x900@75Hz */
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
424 1688, 1936, 0, 900, 903, 909, 942, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x31 - 1440x900@85Hz */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
428 1696, 1952, 0, 900, 903, 909, 948, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x32 - 1440x900@120Hz RB */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
432 1520, 1600, 0, 900, 903, 909, 953, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x53 - 1600x900@60Hz */
435 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
436 1704, 1800, 0, 900, 901, 904, 1000, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x33 - 1600x1200@60Hz */
439 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
440 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x34 - 1600x1200@65Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x35 - 1600x1200@70Hz */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x36 - 1600x1200@75Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x37 - 1600x1200@85Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x38 - 1600x1200@120Hz RB */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
460 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
462 /* 0x39 - 1680x1050@60Hz RB */
463 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
464 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x3a - 1680x1050@60Hz */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
468 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x3b - 1680x1050@75Hz */
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
472 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3c - 1680x1050@85Hz */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
476 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x3d - 1680x1050@120Hz RB */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
480 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x3e - 1792x1344@60Hz */
483 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
484 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3f - 1792x1344@75Hz */
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
488 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x40 - 1792x1344@120Hz RB */
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
492 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x41 - 1856x1392@60Hz */
495 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
496 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x42 - 1856x1392@75Hz */
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
500 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x43 - 1856x1392@120Hz RB */
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
504 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x52 - 1920x1080@60Hz */
507 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
508 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x44 - 1920x1200@60Hz RB */
511 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
512 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x45 - 1920x1200@60Hz */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
516 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
518 /* 0x46 - 1920x1200@75Hz */
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
520 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x47 - 1920x1200@85Hz */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
524 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x48 - 1920x1200@120Hz RB */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
528 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x49 - 1920x1440@60Hz */
531 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
532 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x4a - 1920x1440@75Hz */
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
536 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x4b - 1920x1440@120Hz RB */
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
540 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x54 - 2048x1152@60Hz */
543 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
544 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4c - 2560x1600@60Hz RB */
547 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
548 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
550 /* 0x4d - 2560x1600@60Hz */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
552 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554 /* 0x4e - 2560x1600@75Hz */
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
556 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4f - 2560x1600@85Hz */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x50 - 2560x1600@120Hz RB */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
564 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
566 /* 0x57 - 4096x2160@60Hz RB */
567 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
568 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
577 * These more or less come from the DMT spec. The 720x400 modes are
578 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
579 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
580 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
583 * The DMT modes have been fact-checked; the rest are mild guesses.
585 static const struct drm_display_mode edid_est_modes[] = {
586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
587 968, 1056, 0, 600, 601, 605, 628, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
590 896, 1024, 0, 600, 601, 603, 625, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
593 720, 840, 0, 480, 481, 484, 500, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
596 704, 832, 0, 480, 489, 492, 520, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
599 768, 864, 0, 480, 483, 486, 525, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
602 752, 800, 0, 480, 490, 492, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
605 846, 900, 0, 400, 421, 423, 449, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
608 846, 900, 0, 400, 412, 414, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
610 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
611 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
614 1136, 1312, 0, 768, 769, 772, 800, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
617 1184, 1328, 0, 768, 771, 777, 806, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
620 1184, 1344, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
622 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
623 1208, 1264, 0, 768, 768, 776, 817, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
625 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
626 928, 1152, 0, 624, 625, 628, 667, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
629 896, 1056, 0, 600, 601, 604, 625, 0,
630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
632 976, 1040, 0, 600, 637, 643, 666, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
634 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
635 1344, 1600, 0, 864, 865, 868, 900, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
646 static const struct minimode est3_modes[] = {
654 { 1024, 768, 85, 0 },
655 { 1152, 864, 75, 0 },
657 { 1280, 768, 60, 1 },
658 { 1280, 768, 60, 0 },
659 { 1280, 768, 75, 0 },
660 { 1280, 768, 85, 0 },
661 { 1280, 960, 60, 0 },
662 { 1280, 960, 85, 0 },
663 { 1280, 1024, 60, 0 },
664 { 1280, 1024, 85, 0 },
666 { 1360, 768, 60, 0 },
667 { 1440, 900, 60, 1 },
668 { 1440, 900, 60, 0 },
669 { 1440, 900, 75, 0 },
670 { 1440, 900, 85, 0 },
671 { 1400, 1050, 60, 1 },
672 { 1400, 1050, 60, 0 },
673 { 1400, 1050, 75, 0 },
675 { 1400, 1050, 85, 0 },
676 { 1680, 1050, 60, 1 },
677 { 1680, 1050, 60, 0 },
678 { 1680, 1050, 75, 0 },
679 { 1680, 1050, 85, 0 },
680 { 1600, 1200, 60, 0 },
681 { 1600, 1200, 65, 0 },
682 { 1600, 1200, 70, 0 },
684 { 1600, 1200, 75, 0 },
685 { 1600, 1200, 85, 0 },
686 { 1792, 1344, 60, 0 },
687 { 1792, 1344, 75, 0 },
688 { 1856, 1392, 60, 0 },
689 { 1856, 1392, 75, 0 },
690 { 1920, 1200, 60, 1 },
691 { 1920, 1200, 60, 0 },
693 { 1920, 1200, 75, 0 },
694 { 1920, 1200, 85, 0 },
695 { 1920, 1440, 60, 0 },
696 { 1920, 1440, 75, 0 },
699 static const struct minimode extra_modes[] = {
700 { 1024, 576, 60, 0 },
701 { 1366, 768, 60, 0 },
702 { 1600, 900, 60, 0 },
703 { 1680, 945, 60, 0 },
704 { 1920, 1080, 60, 0 },
705 { 2048, 1152, 60, 0 },
706 { 2048, 1536, 60, 0 },
710 * Probably taken from CEA-861 spec.
711 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
713 * Index using the VIC.
715 static const struct drm_display_mode edid_cea_modes[] = {
716 /* 0 - dummy, VICs start at 1 */
718 /* 1 - 640x480@60Hz 4:3 */
719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
720 752, 800, 0, 480, 490, 492, 525, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
723 /* 2 - 720x480@60Hz 4:3 */
724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
725 798, 858, 0, 480, 489, 495, 525, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
728 /* 3 - 720x480@60Hz 16:9 */
729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
730 798, 858, 0, 480, 489, 495, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
733 /* 4 - 1280x720@60Hz 16:9 */
734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
735 1430, 1650, 0, 720, 725, 730, 750, 0,
736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738 /* 5 - 1920x1080i@60Hz 16:9 */
739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
742 DRM_MODE_FLAG_INTERLACE),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 6 - 720(1440)x480i@60Hz 4:3 */
745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 480, 488, 494, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 7 - 720(1440)x480i@60Hz 16:9 */
751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 480, 488, 494, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 8 - 720(1440)x240@60Hz 4:3 */
757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
758 801, 858, 0, 240, 244, 247, 262, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
760 DRM_MODE_FLAG_DBLCLK),
761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
762 /* 9 - 720(1440)x240@60Hz 16:9 */
763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 240, 244, 247, 262, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_DBLCLK),
767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 10 - 2880x480i@60Hz 4:3 */
769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE),
773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
774 /* 11 - 2880x480i@60Hz 16:9 */
775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
776 3204, 3432, 0, 480, 488, 494, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_INTERLACE),
779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
780 /* 12 - 2880x240@60Hz 4:3 */
781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
782 3204, 3432, 0, 240, 244, 247, 262, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 13 - 2880x240@60Hz 16:9 */
786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
790 /* 14 - 1440x480@60Hz 4:3 */
791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
792 1596, 1716, 0, 480, 489, 495, 525, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795 /* 15 - 1440x480@60Hz 16:9 */
796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
797 1596, 1716, 0, 480, 489, 495, 525, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 16 - 1920x1080@60Hz 16:9 */
801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
805 /* 17 - 720x576@50Hz 4:3 */
806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
807 796, 864, 0, 576, 581, 586, 625, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
810 /* 18 - 720x576@50Hz 16:9 */
811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
812 796, 864, 0, 576, 581, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
815 /* 19 - 1280x720@50Hz 16:9 */
816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
817 1760, 1980, 0, 720, 725, 730, 750, 0,
818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 20 - 1920x1080i@50Hz 16:9 */
821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
824 DRM_MODE_FLAG_INTERLACE),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 21 - 720(1440)x576i@50Hz 4:3 */
827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 576, 580, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
832 /* 22 - 720(1440)x576i@50Hz 16:9 */
833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 576, 580, 586, 625, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 23 - 720(1440)x288@50Hz 4:3 */
839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
840 795, 864, 0, 288, 290, 293, 312, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
842 DRM_MODE_FLAG_DBLCLK),
843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
844 /* 24 - 720(1440)x288@50Hz 16:9 */
845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 288, 290, 293, 312, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_DBLCLK),
849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
850 /* 25 - 2880x576i@50Hz 4:3 */
851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
854 DRM_MODE_FLAG_INTERLACE),
855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
856 /* 26 - 2880x576i@50Hz 16:9 */
857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
858 3180, 3456, 0, 576, 580, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
860 DRM_MODE_FLAG_INTERLACE),
861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862 /* 27 - 2880x288@50Hz 4:3 */
863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
864 3180, 3456, 0, 288, 290, 293, 312, 0,
865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867 /* 28 - 2880x288@50Hz 16:9 */
868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
872 /* 29 - 1440x576@50Hz 4:3 */
873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
874 1592, 1728, 0, 576, 581, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877 /* 30 - 1440x576@50Hz 16:9 */
878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
879 1592, 1728, 0, 576, 581, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 31 - 1920x1080@50Hz 16:9 */
883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
887 /* 32 - 1920x1080@24Hz 16:9 */
888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892 /* 33 - 1920x1080@25Hz 16:9 */
893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
897 /* 34 - 1920x1080@30Hz 16:9 */
898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 35 - 2880x480@60Hz 4:3 */
903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
904 3192, 3432, 0, 480, 489, 495, 525, 0,
905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
907 /* 36 - 2880x480@60Hz 16:9 */
908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
909 3192, 3432, 0, 480, 489, 495, 525, 0,
910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 37 - 2880x576@50Hz 4:3 */
913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
914 3184, 3456, 0, 576, 581, 586, 625, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917 /* 38 - 2880x576@50Hz 16:9 */
918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
919 3184, 3456, 0, 576, 581, 586, 625, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 39 - 1920x1080i@50Hz 16:9 */
923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
926 DRM_MODE_FLAG_INTERLACE),
927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 40 - 1920x1080i@100Hz 16:9 */
929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
932 DRM_MODE_FLAG_INTERLACE),
933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 41 - 1280x720@100Hz 16:9 */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
936 1760, 1980, 0, 720, 725, 730, 750, 0,
937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 42 - 720x576@100Hz 4:3 */
940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
944 /* 43 - 720x576@100Hz 16:9 */
945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 796, 864, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 44 - 720(1440)x576i@100Hz 4:3 */
950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
951 795, 864, 0, 576, 580, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
955 /* 45 - 720(1440)x576i@100Hz 16:9 */
956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
961 /* 46 - 1920x1080i@120Hz 16:9 */
962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
965 DRM_MODE_FLAG_INTERLACE),
966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 47 - 1280x720@120Hz 16:9 */
968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
969 1430, 1650, 0, 720, 725, 730, 750, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 48 - 720x480@120Hz 4:3 */
973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
977 /* 49 - 720x480@120Hz 16:9 */
978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 50 - 720(1440)x480i@120Hz 4:3 */
983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
984 801, 858, 0, 480, 488, 494, 525, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
988 /* 51 - 720(1440)x480i@120Hz 16:9 */
989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
990 801, 858, 0, 480, 488, 494, 525, 0,
991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 52 - 720x576@200Hz 4:3 */
995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
996 796, 864, 0, 576, 581, 586, 625, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
999 /* 53 - 720x576@200Hz 16:9 */
1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1001 796, 864, 0, 576, 581, 586, 625, 0,
1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 54 - 720(1440)x576i@200Hz 4:3 */
1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1006 795, 864, 0, 576, 580, 586, 625, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1010 /* 55 - 720(1440)x576i@200Hz 16:9 */
1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1012 795, 864, 0, 576, 580, 586, 625, 0,
1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1016 /* 56 - 720x480@240Hz 4:3 */
1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1018 798, 858, 0, 480, 489, 495, 525, 0,
1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1021 /* 57 - 720x480@240Hz 16:9 */
1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1023 798, 858, 0, 480, 489, 495, 525, 0,
1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 58 - 720(1440)x480i@240Hz 4:3 */
1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1028 801, 858, 0, 480, 488, 494, 525, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1032 /* 59 - 720(1440)x480i@240Hz 16:9 */
1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1034 801, 858, 0, 480, 488, 494, 525, 0,
1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1038 /* 60 - 1280x720@24Hz 16:9 */
1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1040 3080, 3300, 0, 720, 725, 730, 750, 0,
1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1043 /* 61 - 1280x720@25Hz 16:9 */
1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1045 3740, 3960, 0, 720, 725, 730, 750, 0,
1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 62 - 1280x720@30Hz 16:9 */
1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1050 3080, 3300, 0, 720, 725, 730, 750, 0,
1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1053 /* 63 - 1920x1080@120Hz 16:9 */
1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 64 - 1920x1080@100Hz 16:9 */
1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 65 - 1280x720@24Hz 64:27 */
1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1065 3080, 3300, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1068 /* 66 - 1280x720@25Hz 64:27 */
1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1070 3740, 3960, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1073 /* 67 - 1280x720@30Hz 64:27 */
1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1075 3080, 3300, 0, 720, 725, 730, 750, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1078 /* 68 - 1280x720@50Hz 64:27 */
1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1080 1760, 1980, 0, 720, 725, 730, 750, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1083 /* 69 - 1280x720@60Hz 64:27 */
1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1085 1430, 1650, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1088 /* 70 - 1280x720@100Hz 64:27 */
1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1090 1760, 1980, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1093 /* 71 - 1280x720@120Hz 64:27 */
1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1095 1430, 1650, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1098 /* 72 - 1920x1080@24Hz 64:27 */
1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1103 /* 73 - 1920x1080@25Hz 64:27 */
1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1108 /* 74 - 1920x1080@30Hz 64:27 */
1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1113 /* 75 - 1920x1080@50Hz 64:27 */
1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1118 /* 76 - 1920x1080@60Hz 64:27 */
1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1123 /* 77 - 1920x1080@100Hz 64:27 */
1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1128 /* 78 - 1920x1080@120Hz 64:27 */
1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1133 /* 79 - 1680x720@24Hz 64:27 */
1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1135 3080, 3300, 0, 720, 725, 730, 750, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1138 /* 80 - 1680x720@25Hz 64:27 */
1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1140 2948, 3168, 0, 720, 725, 730, 750, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1143 /* 81 - 1680x720@30Hz 64:27 */
1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1145 2420, 2640, 0, 720, 725, 730, 750, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1148 /* 82 - 1680x720@50Hz 64:27 */
1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1150 1980, 2200, 0, 720, 725, 730, 750, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1153 /* 83 - 1680x720@60Hz 64:27 */
1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1155 1980, 2200, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1158 /* 84 - 1680x720@100Hz 64:27 */
1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1160 1780, 2000, 0, 720, 725, 730, 825, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1163 /* 85 - 1680x720@120Hz 64:27 */
1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1165 1780, 2000, 0, 720, 725, 730, 825, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1168 /* 86 - 2560x1080@24Hz 64:27 */
1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1173 /* 87 - 2560x1080@25Hz 64:27 */
1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1178 /* 88 - 2560x1080@30Hz 64:27 */
1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1183 /* 89 - 2560x1080@50Hz 64:27 */
1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1188 /* 90 - 2560x1080@60Hz 64:27 */
1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1193 /* 91 - 2560x1080@100Hz 64:27 */
1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1198 /* 92 - 2560x1080@120Hz 64:27 */
1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1203 /* 93 - 3840x2160@24Hz 16:9 */
1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1208 /* 94 - 3840x2160@25Hz 16:9 */
1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1213 /* 95 - 3840x2160@30Hz 16:9 */
1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1218 /* 96 - 3840x2160@50Hz 16:9 */
1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1223 /* 97 - 3840x2160@60Hz 16:9 */
1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1228 /* 98 - 4096x2160@24Hz 256:135 */
1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1233 /* 99 - 4096x2160@25Hz 256:135 */
1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1238 /* 100 - 4096x2160@30Hz 256:135 */
1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1243 /* 101 - 4096x2160@50Hz 256:135 */
1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1248 /* 102 - 4096x2160@60Hz 256:135 */
1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1253 /* 103 - 3840x2160@24Hz 64:27 */
1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1258 /* 104 - 3840x2160@25Hz 64:27 */
1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1263 /* 105 - 3840x2160@30Hz 64:27 */
1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1268 /* 106 - 3840x2160@50Hz 64:27 */
1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1273 /* 107 - 3840x2160@60Hz 64:27 */
1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1278 /* 108 - 1280x720@48Hz 16:9 */
1279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1280 2280, 2500, 0, 720, 725, 730, 750, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1283 /* 109 - 1280x720@48Hz 64:27 */
1284 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1285 2280, 2500, 0, 720, 725, 730, 750, 0,
1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1287 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1288 /* 110 - 1680x720@48Hz 64:27 */
1289 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1290 2530, 2750, 0, 720, 725, 730, 750, 0,
1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1293 /* 111 - 1920x1080@48Hz 16:9 */
1294 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1295 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1298 /* 112 - 1920x1080@48Hz 64:27 */
1299 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1300 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1302 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1303 /* 113 - 2560x1080@48Hz 64:27 */
1304 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1305 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1308 /* 114 - 3840x2160@48Hz 16:9 */
1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1310 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1313 /* 115 - 4096x2160@48Hz 256:135 */
1314 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1315 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1317 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1318 /* 116 - 3840x2160@48Hz 64:27 */
1319 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1320 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1322 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1323 /* 117 - 3840x2160@100Hz 16:9 */
1324 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1325 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1327 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1328 /* 118 - 3840x2160@120Hz 16:9 */
1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1330 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1332 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1333 /* 119 - 3840x2160@100Hz 64:27 */
1334 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1335 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1337 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1338 /* 120 - 3840x2160@120Hz 64:27 */
1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1340 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1343 /* 121 - 5120x2160@24Hz 64:27 */
1344 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1345 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1347 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1348 /* 122 - 5120x2160@25Hz 64:27 */
1349 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1350 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1352 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1353 /* 123 - 5120x2160@30Hz 64:27 */
1354 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1355 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1357 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1358 /* 124 - 5120x2160@48Hz 64:27 */
1359 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1360 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1362 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1363 /* 125 - 5120x2160@50Hz 64:27 */
1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1365 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1367 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1368 /* 126 - 5120x2160@60Hz 64:27 */
1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1370 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1372 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1373 /* 127 - 5120x2160@100Hz 64:27 */
1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1375 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1377 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 * HDMI 1.4 4k modes. Index using the VIC.
1383 static const struct drm_display_mode edid_4k_modes[] = {
1384 /* 0 - dummy, VICs start at 1 */
1386 /* 1 - 3840x2160@30Hz */
1387 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1388 3840, 4016, 4104, 4400, 0,
1389 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1392 /* 2 - 3840x2160@25Hz */
1393 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1394 3840, 4896, 4984, 5280, 0,
1395 2160, 2168, 2178, 2250, 0,
1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1398 /* 3 - 3840x2160@24Hz */
1399 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1400 3840, 5116, 5204, 5500, 0,
1401 2160, 2168, 2178, 2250, 0,
1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 /* 4 - 4096x2160@24Hz (SMPTE) */
1405 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1406 4096, 5116, 5204, 5500, 0,
1407 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1412 /*** DDC fetch and block validation ***/
1414 static const u8 edid_header[] = {
1415 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1419 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1420 * @raw_edid: pointer to raw base EDID block
1422 * Sanity check the header of the base EDID block.
1424 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1426 int drm_edid_header_is_valid(const u8 *raw_edid)
1430 for (i = 0; i < sizeof(edid_header); i++)
1431 if (raw_edid[i] == edid_header[i])
1436 EXPORT_SYMBOL(drm_edid_header_is_valid);
1438 static int edid_fixup __read_mostly = 6;
1439 module_param_named(edid_fixup, edid_fixup, int, 0400);
1440 MODULE_PARM_DESC(edid_fixup,
1441 "Minimum number of valid EDID header bytes (0-8, default 6)");
1443 static void drm_get_displayid(struct drm_connector *connector,
1445 static int validate_displayid(u8 *displayid, int length, int idx);
1447 static int drm_edid_block_checksum(const u8 *raw_edid)
1451 for (i = 0; i < EDID_LENGTH; i++)
1452 csum += raw_edid[i];
1457 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1459 if (memchr_inv(in_edid, 0, length))
1466 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1467 * @raw_edid: pointer to raw EDID block
1468 * @block: type of block to validate (0 for base, extension otherwise)
1469 * @print_bad_edid: if true, dump bad EDID blocks to the console
1470 * @edid_corrupt: if true, the header or checksum is invalid
1472 * Validate a base or extension EDID block and optionally dump bad blocks to
1475 * Return: True if the block is valid, false otherwise.
1477 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1481 struct edid *edid = (struct edid *)raw_edid;
1483 if (WARN_ON(!raw_edid))
1486 if (edid_fixup > 8 || edid_fixup < 0)
1490 int score = drm_edid_header_is_valid(raw_edid);
1493 *edid_corrupt = false;
1494 } else if (score >= edid_fixup) {
1495 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1496 * The corrupt flag needs to be set here otherwise, the
1497 * fix-up code here will correct the problem, the
1498 * checksum is correct and the test fails
1501 *edid_corrupt = true;
1502 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1503 memcpy(raw_edid, edid_header, sizeof(edid_header));
1506 *edid_corrupt = true;
1511 csum = drm_edid_block_checksum(raw_edid);
1514 *edid_corrupt = true;
1516 /* allow CEA to slide through, switches mangle this */
1517 if (raw_edid[0] == CEA_EXT) {
1518 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1519 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1522 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1528 /* per-block-type checks */
1529 switch (raw_edid[0]) {
1531 if (edid->version != 1) {
1532 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1536 if (edid->revision > 4)
1537 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1547 if (print_bad_edid) {
1548 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1549 pr_notice("EDID block is all zeroes\n");
1551 pr_notice("Raw EDID:\n");
1552 print_hex_dump(KERN_NOTICE,
1553 " \t", DUMP_PREFIX_NONE, 16, 1,
1554 raw_edid, EDID_LENGTH, false);
1559 EXPORT_SYMBOL(drm_edid_block_valid);
1562 * drm_edid_is_valid - sanity check EDID data
1565 * Sanity-check an entire EDID record (including extensions)
1567 * Return: True if the EDID data is valid, false otherwise.
1569 bool drm_edid_is_valid(struct edid *edid)
1572 u8 *raw = (u8 *)edid;
1577 for (i = 0; i <= edid->extensions; i++)
1578 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1583 EXPORT_SYMBOL(drm_edid_is_valid);
1585 #define DDC_SEGMENT_ADDR 0x30
1587 * drm_do_probe_ddc_edid() - get EDID information via I2C
1588 * @data: I2C device adapter
1589 * @buf: EDID data buffer to be filled
1590 * @block: 128 byte EDID block to start fetching from
1591 * @len: EDID data buffer length to fetch
1593 * Try to fetch EDID information by calling I2C driver functions.
1595 * Return: 0 on success or -1 on failure.
1598 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1600 struct i2c_adapter *adapter = data;
1601 unsigned char start = block * EDID_LENGTH;
1602 unsigned char segment = block >> 1;
1603 unsigned char xfers = segment ? 3 : 2;
1604 int ret, retries = 5;
1607 * The core I2C driver will automatically retry the transfer if the
1608 * adapter reports EAGAIN. However, we find that bit-banging transfers
1609 * are susceptible to errors under a heavily loaded machine and
1610 * generate spurious NAKs and timeouts. Retrying the transfer
1611 * of the individual block a few times seems to overcome this.
1614 struct i2c_msg msgs[] = {
1616 .addr = DDC_SEGMENT_ADDR,
1634 * Avoid sending the segment addr to not upset non-compliant
1637 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1639 if (ret == -ENXIO) {
1640 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1644 } while (ret != xfers && --retries);
1646 return ret == xfers ? 0 : -1;
1649 static void connector_bad_edid(struct drm_connector *connector,
1650 u8 *edid, int num_blocks)
1654 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1657 dev_warn(connector->dev->dev,
1658 "%s: EDID is invalid:\n",
1660 for (i = 0; i < num_blocks; i++) {
1661 u8 *block = edid + i * EDID_LENGTH;
1664 if (drm_edid_is_zero(block, EDID_LENGTH))
1665 sprintf(prefix, "\t[%02x] ZERO ", i);
1666 else if (!drm_edid_block_valid(block, i, false, NULL))
1667 sprintf(prefix, "\t[%02x] BAD ", i);
1669 sprintf(prefix, "\t[%02x] GOOD ", i);
1671 print_hex_dump(KERN_WARNING,
1672 prefix, DUMP_PREFIX_NONE, 16, 1,
1673 block, EDID_LENGTH, false);
1677 /* Get override or firmware EDID */
1678 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1680 struct edid *override = NULL;
1682 if (connector->override_edid)
1683 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1686 override = drm_load_edid_firmware(connector);
1688 return IS_ERR(override) ? NULL : override;
1692 * drm_add_override_edid_modes - add modes from override/firmware EDID
1693 * @connector: connector we're probing
1695 * Add modes from the override/firmware EDID, if available. Only to be used from
1696 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1697 * failed during drm_get_edid() and caused the override/firmware EDID to be
1700 * Return: The number of modes added or 0 if we couldn't find any.
1702 int drm_add_override_edid_modes(struct drm_connector *connector)
1704 struct edid *override;
1707 override = drm_get_override_edid(connector);
1709 drm_connector_update_edid_property(connector, override);
1710 num_modes = drm_add_edid_modes(connector, override);
1713 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1714 connector->base.id, connector->name, num_modes);
1719 EXPORT_SYMBOL(drm_add_override_edid_modes);
1722 * drm_do_get_edid - get EDID data using a custom EDID block read function
1723 * @connector: connector we're probing
1724 * @get_edid_block: EDID block read function
1725 * @data: private data passed to the block read function
1727 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1728 * exposes a different interface to read EDID blocks this function can be used
1729 * to get EDID data using a custom block read function.
1731 * As in the general case the DDC bus is accessible by the kernel at the I2C
1732 * level, drivers must make all reasonable efforts to expose it as an I2C
1733 * adapter and use drm_get_edid() instead of abusing this function.
1735 * The EDID may be overridden using debugfs override_edid or firmare EDID
1736 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1737 * order. Having either of them bypasses actual EDID reads.
1739 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1741 struct edid *drm_do_get_edid(struct drm_connector *connector,
1742 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1746 int i, j = 0, valid_extensions = 0;
1748 struct edid *override;
1750 override = drm_get_override_edid(connector);
1754 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1757 /* base block fetch */
1758 for (i = 0; i < 4; i++) {
1759 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1761 if (drm_edid_block_valid(edid, 0, false,
1762 &connector->edid_corrupt))
1764 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1765 connector->null_edid_counter++;
1772 /* if there's no extensions, we're done */
1773 valid_extensions = edid[0x7e];
1774 if (valid_extensions == 0)
1775 return (struct edid *)edid;
1777 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1782 for (j = 1; j <= edid[0x7e]; j++) {
1783 u8 *block = edid + j * EDID_LENGTH;
1785 for (i = 0; i < 4; i++) {
1786 if (get_edid_block(data, block, j, EDID_LENGTH))
1788 if (drm_edid_block_valid(block, j, false, NULL))
1796 if (valid_extensions != edid[0x7e]) {
1799 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1801 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1802 edid[0x7e] = valid_extensions;
1804 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1810 for (i = 0; i <= edid[0x7e]; i++) {
1811 u8 *block = edid + i * EDID_LENGTH;
1813 if (!drm_edid_block_valid(block, i, false, NULL))
1816 memcpy(base, block, EDID_LENGTH);
1817 base += EDID_LENGTH;
1824 return (struct edid *)edid;
1827 connector_bad_edid(connector, edid, 1);
1832 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1835 * drm_probe_ddc() - probe DDC presence
1836 * @adapter: I2C adapter to probe
1838 * Return: True on success, false on failure.
1841 drm_probe_ddc(struct i2c_adapter *adapter)
1845 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1847 EXPORT_SYMBOL(drm_probe_ddc);
1850 * drm_get_edid - get EDID data, if available
1851 * @connector: connector we're probing
1852 * @adapter: I2C adapter to use for DDC
1854 * Poke the given I2C channel to grab EDID data if possible. If found,
1855 * attach it to the connector.
1857 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1859 struct edid *drm_get_edid(struct drm_connector *connector,
1860 struct i2c_adapter *adapter)
1864 if (connector->force == DRM_FORCE_OFF)
1867 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1870 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1872 drm_get_displayid(connector, edid);
1875 EXPORT_SYMBOL(drm_get_edid);
1878 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1879 * @connector: connector we're probing
1880 * @adapter: I2C adapter to use for DDC
1882 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1883 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1884 * switch DDC to the GPU which is retrieving EDID.
1886 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1888 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1889 struct i2c_adapter *adapter)
1891 struct pci_dev *pdev = connector->dev->pdev;
1894 vga_switcheroo_lock_ddc(pdev);
1895 edid = drm_get_edid(connector, adapter);
1896 vga_switcheroo_unlock_ddc(pdev);
1900 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1903 * drm_edid_duplicate - duplicate an EDID and the extensions
1904 * @edid: EDID to duplicate
1906 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1908 struct edid *drm_edid_duplicate(const struct edid *edid)
1910 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1912 EXPORT_SYMBOL(drm_edid_duplicate);
1914 /*** EDID parsing ***/
1917 * edid_vendor - match a string against EDID's obfuscated vendor field
1918 * @edid: EDID to match
1919 * @vendor: vendor string
1921 * Returns true if @vendor is in @edid, false otherwise
1923 static bool edid_vendor(const struct edid *edid, const char *vendor)
1925 char edid_vendor[3];
1927 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1928 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1929 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1930 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1932 return !strncmp(edid_vendor, vendor, 3);
1936 * edid_get_quirks - return quirk flags for a given EDID
1937 * @edid: EDID to process
1939 * This tells subsequent routines what fixes they need to apply.
1941 static u32 edid_get_quirks(const struct edid *edid)
1943 const struct edid_quirk *quirk;
1946 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1947 quirk = &edid_quirk_list[i];
1949 if (edid_vendor(edid, quirk->vendor) &&
1950 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1951 return quirk->quirks;
1957 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1958 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1961 * edid_fixup_preferred - set preferred modes based on quirk list
1962 * @connector: has mode list to fix up
1963 * @quirks: quirks list
1965 * Walk the mode list for @connector, clearing the preferred status
1966 * on existing modes and setting it anew for the right mode ala @quirks.
1968 static void edid_fixup_preferred(struct drm_connector *connector,
1971 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1972 int target_refresh = 0;
1973 int cur_vrefresh, preferred_vrefresh;
1975 if (list_empty(&connector->probed_modes))
1978 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1979 target_refresh = 60;
1980 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1981 target_refresh = 75;
1983 preferred_mode = list_first_entry(&connector->probed_modes,
1984 struct drm_display_mode, head);
1986 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1987 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1989 if (cur_mode == preferred_mode)
1992 /* Largest mode is preferred */
1993 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1994 preferred_mode = cur_mode;
1996 cur_vrefresh = cur_mode->vrefresh ?
1997 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1998 preferred_vrefresh = preferred_mode->vrefresh ?
1999 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
2000 /* At a given size, try to get closest to target refresh */
2001 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2002 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2003 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2004 preferred_mode = cur_mode;
2008 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2012 mode_is_rb(const struct drm_display_mode *mode)
2014 return (mode->htotal - mode->hdisplay == 160) &&
2015 (mode->hsync_end - mode->hdisplay == 80) &&
2016 (mode->hsync_end - mode->hsync_start == 32) &&
2017 (mode->vsync_start - mode->vdisplay == 3);
2021 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2022 * @dev: Device to duplicate against
2023 * @hsize: Mode width
2024 * @vsize: Mode height
2025 * @fresh: Mode refresh rate
2026 * @rb: Mode reduced-blanking-ness
2028 * Walk the DMT mode list looking for a match for the given parameters.
2030 * Return: A newly allocated copy of the mode, or NULL if not found.
2032 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2033 int hsize, int vsize, int fresh,
2038 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2039 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2040 if (hsize != ptr->hdisplay)
2042 if (vsize != ptr->vdisplay)
2044 if (fresh != drm_mode_vrefresh(ptr))
2046 if (rb != mode_is_rb(ptr))
2049 return drm_mode_duplicate(dev, ptr);
2054 EXPORT_SYMBOL(drm_mode_find_dmt);
2056 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2059 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2063 u8 *det_base = ext + d;
2066 for (i = 0; i < n; i++)
2067 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2071 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2073 unsigned int i, n = min((int)ext[0x02], 6);
2074 u8 *det_base = ext + 5;
2077 return; /* unknown version */
2079 for (i = 0; i < n; i++)
2080 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2084 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2087 struct edid *edid = (struct edid *)raw_edid;
2092 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2093 cb(&(edid->detailed_timings[i]), closure);
2095 for (i = 1; i <= raw_edid[0x7e]; i++) {
2096 u8 *ext = raw_edid + (i * EDID_LENGTH);
2099 cea_for_each_detailed_block(ext, cb, closure);
2102 vtb_for_each_detailed_block(ext, cb, closure);
2111 is_rb(struct detailed_timing *t, void *data)
2114 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2116 *(bool *)data = true;
2119 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2121 drm_monitor_supports_rb(struct edid *edid)
2123 if (edid->revision >= 4) {
2125 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2129 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2133 find_gtf2(struct detailed_timing *t, void *data)
2136 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2140 /* Secondary GTF curve kicks in above some break frequency */
2142 drm_gtf2_hbreak(struct edid *edid)
2145 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2146 return r ? (r[12] * 2) : 0;
2150 drm_gtf2_2c(struct edid *edid)
2153 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2154 return r ? r[13] : 0;
2158 drm_gtf2_m(struct edid *edid)
2161 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2162 return r ? (r[15] << 8) + r[14] : 0;
2166 drm_gtf2_k(struct edid *edid)
2169 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2170 return r ? r[16] : 0;
2174 drm_gtf2_2j(struct edid *edid)
2177 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2178 return r ? r[17] : 0;
2182 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2183 * @edid: EDID block to scan
2185 static int standard_timing_level(struct edid *edid)
2187 if (edid->revision >= 2) {
2188 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2190 if (drm_gtf2_hbreak(edid))
2198 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2199 * monitors fill with ascii space (0x20) instead.
2202 bad_std_timing(u8 a, u8 b)
2204 return (a == 0x00 && b == 0x00) ||
2205 (a == 0x01 && b == 0x01) ||
2206 (a == 0x20 && b == 0x20);
2210 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2211 * @connector: connector of for the EDID block
2212 * @edid: EDID block to scan
2213 * @t: standard timing params
2215 * Take the standard timing params (in this case width, aspect, and refresh)
2216 * and convert them into a real mode using CVT/GTF/DMT.
2218 static struct drm_display_mode *
2219 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2220 struct std_timing *t)
2222 struct drm_device *dev = connector->dev;
2223 struct drm_display_mode *m, *mode = NULL;
2226 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2227 >> EDID_TIMING_ASPECT_SHIFT;
2228 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2229 >> EDID_TIMING_VFREQ_SHIFT;
2230 int timing_level = standard_timing_level(edid);
2232 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2235 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2236 hsize = t->hsize * 8 + 248;
2237 /* vrefresh_rate = vfreq + 60 */
2238 vrefresh_rate = vfreq + 60;
2239 /* the vdisplay is calculated based on the aspect ratio */
2240 if (aspect_ratio == 0) {
2241 if (edid->revision < 3)
2244 vsize = (hsize * 10) / 16;
2245 } else if (aspect_ratio == 1)
2246 vsize = (hsize * 3) / 4;
2247 else if (aspect_ratio == 2)
2248 vsize = (hsize * 4) / 5;
2250 vsize = (hsize * 9) / 16;
2252 /* HDTV hack, part 1 */
2253 if (vrefresh_rate == 60 &&
2254 ((hsize == 1360 && vsize == 765) ||
2255 (hsize == 1368 && vsize == 769))) {
2261 * If this connector already has a mode for this size and refresh
2262 * rate (because it came from detailed or CVT info), use that
2263 * instead. This way we don't have to guess at interlace or
2266 list_for_each_entry(m, &connector->probed_modes, head)
2267 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2268 drm_mode_vrefresh(m) == vrefresh_rate)
2271 /* HDTV hack, part 2 */
2272 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2273 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2277 mode->hdisplay = 1366;
2278 mode->hsync_start = mode->hsync_start - 1;
2279 mode->hsync_end = mode->hsync_end - 1;
2283 /* check whether it can be found in default mode table */
2284 if (drm_monitor_supports_rb(edid)) {
2285 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2290 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2294 /* okay, generate it */
2295 switch (timing_level) {
2299 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2303 * This is potentially wrong if there's ever a monitor with
2304 * more than one ranges section, each claiming a different
2305 * secondary GTF curve. Please don't do that.
2307 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2310 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2311 drm_mode_destroy(dev, mode);
2312 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2313 vrefresh_rate, 0, 0,
2321 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2329 * EDID is delightfully ambiguous about how interlaced modes are to be
2330 * encoded. Our internal representation is of frame height, but some
2331 * HDTV detailed timings are encoded as field height.
2333 * The format list here is from CEA, in frame size. Technically we
2334 * should be checking refresh rate too. Whatever.
2337 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2338 struct detailed_pixel_timing *pt)
2341 static const struct {
2343 } cea_interlaced[] = {
2353 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2356 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2357 if ((mode->hdisplay == cea_interlaced[i].w) &&
2358 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2359 mode->vdisplay *= 2;
2360 mode->vsync_start *= 2;
2361 mode->vsync_end *= 2;
2367 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2371 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2372 * @dev: DRM device (needed to create new mode)
2374 * @timing: EDID detailed timing info
2375 * @quirks: quirks to apply
2377 * An EDID detailed timing block contains enough info for us to create and
2378 * return a new struct drm_display_mode.
2380 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2382 struct detailed_timing *timing,
2385 struct drm_display_mode *mode;
2386 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2387 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2388 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2389 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2390 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2391 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2392 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2393 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2394 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2396 /* ignore tiny modes */
2397 if (hactive < 64 || vactive < 64)
2400 if (pt->misc & DRM_EDID_PT_STEREO) {
2401 DRM_DEBUG_KMS("stereo mode not supported\n");
2404 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2405 DRM_DEBUG_KMS("composite sync not supported\n");
2408 /* it is incorrect if hsync/vsync width is zero */
2409 if (!hsync_pulse_width || !vsync_pulse_width) {
2410 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2411 "Wrong Hsync/Vsync pulse width\n");
2415 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2416 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2423 mode = drm_mode_create(dev);
2427 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2428 timing->pixel_clock = cpu_to_le16(1088);
2430 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2432 mode->hdisplay = hactive;
2433 mode->hsync_start = mode->hdisplay + hsync_offset;
2434 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2435 mode->htotal = mode->hdisplay + hblank;
2437 mode->vdisplay = vactive;
2438 mode->vsync_start = mode->vdisplay + vsync_offset;
2439 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2440 mode->vtotal = mode->vdisplay + vblank;
2442 /* Some EDIDs have bogus h/vtotal values */
2443 if (mode->hsync_end > mode->htotal)
2444 mode->htotal = mode->hsync_end + 1;
2445 if (mode->vsync_end > mode->vtotal)
2446 mode->vtotal = mode->vsync_end + 1;
2448 drm_mode_do_interlace_quirk(mode, pt);
2450 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2451 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2454 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2455 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2456 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2457 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2460 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2461 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2463 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2464 mode->width_mm *= 10;
2465 mode->height_mm *= 10;
2468 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2469 mode->width_mm = edid->width_cm * 10;
2470 mode->height_mm = edid->height_cm * 10;
2473 mode->type = DRM_MODE_TYPE_DRIVER;
2474 mode->vrefresh = drm_mode_vrefresh(mode);
2475 drm_mode_set_name(mode);
2481 mode_in_hsync_range(const struct drm_display_mode *mode,
2482 struct edid *edid, u8 *t)
2484 int hsync, hmin, hmax;
2487 if (edid->revision >= 4)
2488 hmin += ((t[4] & 0x04) ? 255 : 0);
2490 if (edid->revision >= 4)
2491 hmax += ((t[4] & 0x08) ? 255 : 0);
2492 hsync = drm_mode_hsync(mode);
2494 return (hsync <= hmax && hsync >= hmin);
2498 mode_in_vsync_range(const struct drm_display_mode *mode,
2499 struct edid *edid, u8 *t)
2501 int vsync, vmin, vmax;
2504 if (edid->revision >= 4)
2505 vmin += ((t[4] & 0x01) ? 255 : 0);
2507 if (edid->revision >= 4)
2508 vmax += ((t[4] & 0x02) ? 255 : 0);
2509 vsync = drm_mode_vrefresh(mode);
2511 return (vsync <= vmax && vsync >= vmin);
2515 range_pixel_clock(struct edid *edid, u8 *t)
2518 if (t[9] == 0 || t[9] == 255)
2521 /* 1.4 with CVT support gives us real precision, yay */
2522 if (edid->revision >= 4 && t[10] == 0x04)
2523 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2525 /* 1.3 is pathetic, so fuzz up a bit */
2526 return t[9] * 10000 + 5001;
2530 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2531 struct detailed_timing *timing)
2534 u8 *t = (u8 *)timing;
2536 if (!mode_in_hsync_range(mode, edid, t))
2539 if (!mode_in_vsync_range(mode, edid, t))
2542 if ((max_clock = range_pixel_clock(edid, t)))
2543 if (mode->clock > max_clock)
2546 /* 1.4 max horizontal check */
2547 if (edid->revision >= 4 && t[10] == 0x04)
2548 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2551 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2557 static bool valid_inferred_mode(const struct drm_connector *connector,
2558 const struct drm_display_mode *mode)
2560 const struct drm_display_mode *m;
2563 list_for_each_entry(m, &connector->probed_modes, head) {
2564 if (mode->hdisplay == m->hdisplay &&
2565 mode->vdisplay == m->vdisplay &&
2566 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2567 return false; /* duplicated */
2568 if (mode->hdisplay <= m->hdisplay &&
2569 mode->vdisplay <= m->vdisplay)
2576 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2577 struct detailed_timing *timing)
2580 struct drm_display_mode *newmode;
2581 struct drm_device *dev = connector->dev;
2583 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2584 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2585 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2586 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2588 drm_mode_probed_add(connector, newmode);
2597 /* fix up 1366x768 mode from 1368x768;
2598 * GFT/CVT can't express 1366 width which isn't dividable by 8
2600 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2602 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2603 mode->hdisplay = 1366;
2604 mode->hsync_start--;
2606 drm_mode_set_name(mode);
2611 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2612 struct detailed_timing *timing)
2615 struct drm_display_mode *newmode;
2616 struct drm_device *dev = connector->dev;
2618 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2619 const struct minimode *m = &extra_modes[i];
2620 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2624 drm_mode_fixup_1366x768(newmode);
2625 if (!mode_in_range(newmode, edid, timing) ||
2626 !valid_inferred_mode(connector, newmode)) {
2627 drm_mode_destroy(dev, newmode);
2631 drm_mode_probed_add(connector, newmode);
2639 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2640 struct detailed_timing *timing)
2643 struct drm_display_mode *newmode;
2644 struct drm_device *dev = connector->dev;
2645 bool rb = drm_monitor_supports_rb(edid);
2647 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2648 const struct minimode *m = &extra_modes[i];
2649 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2653 drm_mode_fixup_1366x768(newmode);
2654 if (!mode_in_range(newmode, edid, timing) ||
2655 !valid_inferred_mode(connector, newmode)) {
2656 drm_mode_destroy(dev, newmode);
2660 drm_mode_probed_add(connector, newmode);
2668 do_inferred_modes(struct detailed_timing *timing, void *c)
2670 struct detailed_mode_closure *closure = c;
2671 struct detailed_non_pixel *data = &timing->data.other_data;
2672 struct detailed_data_monitor_range *range = &data->data.range;
2674 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2677 closure->modes += drm_dmt_modes_for_range(closure->connector,
2681 if (!version_greater(closure->edid, 1, 1))
2682 return; /* GTF not defined yet */
2684 switch (range->flags) {
2685 case 0x02: /* secondary gtf, XXX could do more */
2686 case 0x00: /* default gtf */
2687 closure->modes += drm_gtf_modes_for_range(closure->connector,
2691 case 0x04: /* cvt, only in 1.4+ */
2692 if (!version_greater(closure->edid, 1, 3))
2695 closure->modes += drm_cvt_modes_for_range(closure->connector,
2699 case 0x01: /* just the ranges, no formula */
2706 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2708 struct detailed_mode_closure closure = {
2709 .connector = connector,
2713 if (version_greater(edid, 1, 0))
2714 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2717 return closure.modes;
2721 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2723 int i, j, m, modes = 0;
2724 struct drm_display_mode *mode;
2725 u8 *est = ((u8 *)timing) + 6;
2727 for (i = 0; i < 6; i++) {
2728 for (j = 7; j >= 0; j--) {
2729 m = (i * 8) + (7 - j);
2730 if (m >= ARRAY_SIZE(est3_modes))
2732 if (est[i] & (1 << j)) {
2733 mode = drm_mode_find_dmt(connector->dev,
2739 drm_mode_probed_add(connector, mode);
2750 do_established_modes(struct detailed_timing *timing, void *c)
2752 struct detailed_mode_closure *closure = c;
2753 struct detailed_non_pixel *data = &timing->data.other_data;
2755 if (data->type == EDID_DETAIL_EST_TIMINGS)
2756 closure->modes += drm_est3_modes(closure->connector, timing);
2760 * add_established_modes - get est. modes from EDID and add them
2761 * @connector: connector to add mode(s) to
2762 * @edid: EDID block to scan
2764 * Each EDID block contains a bitmap of the supported "established modes" list
2765 * (defined above). Tease them out and add them to the global modes list.
2768 add_established_modes(struct drm_connector *connector, struct edid *edid)
2770 struct drm_device *dev = connector->dev;
2771 unsigned long est_bits = edid->established_timings.t1 |
2772 (edid->established_timings.t2 << 8) |
2773 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2775 struct detailed_mode_closure closure = {
2776 .connector = connector,
2780 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2781 if (est_bits & (1<<i)) {
2782 struct drm_display_mode *newmode;
2783 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2785 drm_mode_probed_add(connector, newmode);
2791 if (version_greater(edid, 1, 0))
2792 drm_for_each_detailed_block((u8 *)edid,
2793 do_established_modes, &closure);
2795 return modes + closure.modes;
2799 do_standard_modes(struct detailed_timing *timing, void *c)
2801 struct detailed_mode_closure *closure = c;
2802 struct detailed_non_pixel *data = &timing->data.other_data;
2803 struct drm_connector *connector = closure->connector;
2804 struct edid *edid = closure->edid;
2806 if (data->type == EDID_DETAIL_STD_MODES) {
2808 for (i = 0; i < 6; i++) {
2809 struct std_timing *std;
2810 struct drm_display_mode *newmode;
2812 std = &data->data.timings[i];
2813 newmode = drm_mode_std(connector, edid, std);
2815 drm_mode_probed_add(connector, newmode);
2823 * add_standard_modes - get std. modes from EDID and add them
2824 * @connector: connector to add mode(s) to
2825 * @edid: EDID block to scan
2827 * Standard modes can be calculated using the appropriate standard (DMT,
2828 * GTF or CVT. Grab them from @edid and add them to the list.
2831 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2834 struct detailed_mode_closure closure = {
2835 .connector = connector,
2839 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2840 struct drm_display_mode *newmode;
2842 newmode = drm_mode_std(connector, edid,
2843 &edid->standard_timings[i]);
2845 drm_mode_probed_add(connector, newmode);
2850 if (version_greater(edid, 1, 0))
2851 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2854 /* XXX should also look for standard codes in VTB blocks */
2856 return modes + closure.modes;
2859 static int drm_cvt_modes(struct drm_connector *connector,
2860 struct detailed_timing *timing)
2862 int i, j, modes = 0;
2863 struct drm_display_mode *newmode;
2864 struct drm_device *dev = connector->dev;
2865 struct cvt_timing *cvt;
2866 const int rates[] = { 60, 85, 75, 60, 50 };
2867 const u8 empty[3] = { 0, 0, 0 };
2869 for (i = 0; i < 4; i++) {
2870 int uninitialized_var(width), height;
2871 cvt = &(timing->data.other_data.data.cvt[i]);
2873 if (!memcmp(cvt->code, empty, 3))
2876 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2877 switch (cvt->code[1] & 0x0c) {
2879 width = height * 4 / 3;
2882 width = height * 16 / 9;
2885 width = height * 16 / 10;
2888 width = height * 15 / 9;
2892 for (j = 1; j < 5; j++) {
2893 if (cvt->code[2] & (1 << j)) {
2894 newmode = drm_cvt_mode(dev, width, height,
2898 drm_mode_probed_add(connector, newmode);
2909 do_cvt_mode(struct detailed_timing *timing, void *c)
2911 struct detailed_mode_closure *closure = c;
2912 struct detailed_non_pixel *data = &timing->data.other_data;
2914 if (data->type == EDID_DETAIL_CVT_3BYTE)
2915 closure->modes += drm_cvt_modes(closure->connector, timing);
2919 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2921 struct detailed_mode_closure closure = {
2922 .connector = connector,
2926 if (version_greater(edid, 1, 2))
2927 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2929 /* XXX should also look for CVT codes in VTB blocks */
2931 return closure.modes;
2934 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2937 do_detailed_mode(struct detailed_timing *timing, void *c)
2939 struct detailed_mode_closure *closure = c;
2940 struct drm_display_mode *newmode;
2942 if (timing->pixel_clock) {
2943 newmode = drm_mode_detailed(closure->connector->dev,
2944 closure->edid, timing,
2949 if (closure->preferred)
2950 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2953 * Detailed modes are limited to 10kHz pixel clock resolution,
2954 * so fix up anything that looks like CEA/HDMI mode, but the clock
2955 * is just slightly off.
2957 fixup_detailed_cea_mode_clock(newmode);
2959 drm_mode_probed_add(closure->connector, newmode);
2961 closure->preferred = false;
2966 * add_detailed_modes - Add modes from detailed timings
2967 * @connector: attached connector
2968 * @edid: EDID block to scan
2969 * @quirks: quirks to apply
2972 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2975 struct detailed_mode_closure closure = {
2976 .connector = connector,
2982 if (closure.preferred && !version_greater(edid, 1, 3))
2984 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2986 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2988 return closure.modes;
2991 #define AUDIO_BLOCK 0x01
2992 #define VIDEO_BLOCK 0x02
2993 #define VENDOR_BLOCK 0x03
2994 #define SPEAKER_BLOCK 0x04
2995 #define HDR_STATIC_METADATA_BLOCK 0x6
2996 #define USE_EXTENDED_TAG 0x07
2997 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2998 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2999 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3000 #define EDID_BASIC_AUDIO (1 << 6)
3001 #define EDID_CEA_YCRCB444 (1 << 5)
3002 #define EDID_CEA_YCRCB422 (1 << 4)
3003 #define EDID_CEA_VCDB_QS (1 << 6)
3006 * Search EDID for CEA extension block.
3008 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
3010 u8 *edid_ext = NULL;
3013 /* No EDID or EDID extensions */
3014 if (edid == NULL || edid->extensions == 0)
3017 /* Find CEA extension */
3018 for (i = 0; i < edid->extensions; i++) {
3019 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3020 if (edid_ext[0] == ext_id)
3024 if (i == edid->extensions)
3031 static u8 *drm_find_displayid_extension(const struct edid *edid)
3033 return drm_find_edid_extension(edid, DISPLAYID_EXT);
3036 static u8 *drm_find_cea_extension(const struct edid *edid)
3040 int length = EDID_LENGTH;
3041 struct displayid_block *block;
3045 /* Look for a top level CEA extension block */
3046 cea = drm_find_edid_extension(edid, CEA_EXT);
3050 /* CEA blocks can also be found embedded in a DisplayID block */
3051 displayid = drm_find_displayid_extension(edid);
3055 ret = validate_displayid(displayid, length, idx);
3059 idx += sizeof(struct displayid_hdr);
3060 for_each_displayid_db(displayid, block, idx, length) {
3061 if (block->tag == DATA_BLOCK_CTA) {
3071 * Calculate the alternate clock for the CEA mode
3072 * (60Hz vs. 59.94Hz etc.)
3075 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3077 unsigned int clock = cea_mode->clock;
3079 if (cea_mode->vrefresh % 6 != 0)
3083 * edid_cea_modes contains the 59.94Hz
3084 * variant for 240 and 480 line modes,
3085 * and the 60Hz variant otherwise.
3087 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3088 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3090 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3096 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3099 * For certain VICs the spec allows the vertical
3100 * front porch to vary by one or two lines.
3102 * cea_modes[] stores the variant with the shortest
3103 * vertical front porch. We can adjust the mode to
3104 * get the other variants by simply increasing the
3105 * vertical front porch length.
3107 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
3108 edid_cea_modes[9].vtotal != 262 ||
3109 edid_cea_modes[12].vtotal != 262 ||
3110 edid_cea_modes[13].vtotal != 262 ||
3111 edid_cea_modes[23].vtotal != 312 ||
3112 edid_cea_modes[24].vtotal != 312 ||
3113 edid_cea_modes[27].vtotal != 312 ||
3114 edid_cea_modes[28].vtotal != 312);
3116 if (((vic == 8 || vic == 9 ||
3117 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3118 ((vic == 23 || vic == 24 ||
3119 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3120 mode->vsync_start++;
3130 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3131 unsigned int clock_tolerance)
3133 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3136 if (!to_match->clock)
3139 if (to_match->picture_aspect_ratio)
3140 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3142 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3143 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3144 unsigned int clock1, clock2;
3146 /* Check both 60Hz and 59.94Hz */
3147 clock1 = cea_mode.clock;
3148 clock2 = cea_mode_alternate_clock(&cea_mode);
3150 if (abs(to_match->clock - clock1) > clock_tolerance &&
3151 abs(to_match->clock - clock2) > clock_tolerance)
3155 if (drm_mode_match(to_match, &cea_mode, match_flags))
3157 } while (cea_mode_alternate_timings(vic, &cea_mode));
3164 * drm_match_cea_mode - look for a CEA mode matching given mode
3165 * @to_match: display mode
3167 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3170 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3172 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3175 if (!to_match->clock)
3178 if (to_match->picture_aspect_ratio)
3179 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3181 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3182 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3183 unsigned int clock1, clock2;
3185 /* Check both 60Hz and 59.94Hz */
3186 clock1 = cea_mode.clock;
3187 clock2 = cea_mode_alternate_clock(&cea_mode);
3189 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3190 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3194 if (drm_mode_match(to_match, &cea_mode, match_flags))
3196 } while (cea_mode_alternate_timings(vic, &cea_mode));
3201 EXPORT_SYMBOL(drm_match_cea_mode);
3203 static bool drm_valid_cea_vic(u8 vic)
3205 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3209 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3210 * the input VIC from the CEA mode list
3211 * @video_code: ID given to each of the CEA modes
3213 * Returns picture aspect ratio
3215 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3217 return edid_cea_modes[video_code].picture_aspect_ratio;
3219 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3222 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3225 * It's almost like cea_mode_alternate_clock(), we just need to add an
3226 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3230 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3232 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3233 return hdmi_mode->clock;
3235 return cea_mode_alternate_clock(hdmi_mode);
3238 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3239 unsigned int clock_tolerance)
3241 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3244 if (!to_match->clock)
3247 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3248 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3249 unsigned int clock1, clock2;
3251 /* Make sure to also match alternate clocks */
3252 clock1 = hdmi_mode->clock;
3253 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3255 if (abs(to_match->clock - clock1) > clock_tolerance &&
3256 abs(to_match->clock - clock2) > clock_tolerance)
3259 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3267 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3268 * @to_match: display mode
3270 * An HDMI mode is one defined in the HDMI vendor specific block.
3272 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3274 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3276 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3279 if (!to_match->clock)
3282 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3283 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3284 unsigned int clock1, clock2;
3286 /* Make sure to also match alternate clocks */
3287 clock1 = hdmi_mode->clock;
3288 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3290 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3291 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3292 drm_mode_match(to_match, hdmi_mode, match_flags))
3298 static bool drm_valid_hdmi_vic(u8 vic)
3300 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3304 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3306 struct drm_device *dev = connector->dev;
3307 struct drm_display_mode *mode, *tmp;
3311 /* Don't add CEA modes if the CEA extension block is missing */
3312 if (!drm_find_cea_extension(edid))
3316 * Go through all probed modes and create a new mode
3317 * with the alternate clock for certain CEA modes.
3319 list_for_each_entry(mode, &connector->probed_modes, head) {
3320 const struct drm_display_mode *cea_mode = NULL;
3321 struct drm_display_mode *newmode;
3322 u8 vic = drm_match_cea_mode(mode);
3323 unsigned int clock1, clock2;
3325 if (drm_valid_cea_vic(vic)) {
3326 cea_mode = &edid_cea_modes[vic];
3327 clock2 = cea_mode_alternate_clock(cea_mode);
3329 vic = drm_match_hdmi_mode(mode);
3330 if (drm_valid_hdmi_vic(vic)) {
3331 cea_mode = &edid_4k_modes[vic];
3332 clock2 = hdmi_mode_alternate_clock(cea_mode);
3339 clock1 = cea_mode->clock;
3341 if (clock1 == clock2)
3344 if (mode->clock != clock1 && mode->clock != clock2)
3347 newmode = drm_mode_duplicate(dev, cea_mode);
3351 /* Carry over the stereo flags */
3352 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3355 * The current mode could be either variant. Make
3356 * sure to pick the "other" clock for the new mode.
3358 if (mode->clock != clock1)
3359 newmode->clock = clock1;
3361 newmode->clock = clock2;
3363 list_add_tail(&newmode->head, &list);
3366 list_for_each_entry_safe(mode, tmp, &list, head) {
3367 list_del(&mode->head);
3368 drm_mode_probed_add(connector, mode);
3375 static u8 svd_to_vic(u8 svd)
3377 /* 0-6 bit vic, 7th bit native mode indicator */
3378 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3384 static struct drm_display_mode *
3385 drm_display_mode_from_vic_index(struct drm_connector *connector,
3386 const u8 *video_db, u8 video_len,
3389 struct drm_device *dev = connector->dev;
3390 struct drm_display_mode *newmode;
3393 if (video_db == NULL || video_index >= video_len)
3396 /* CEA modes are numbered 1..127 */
3397 vic = svd_to_vic(video_db[video_index]);
3398 if (!drm_valid_cea_vic(vic))
3401 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3405 newmode->vrefresh = 0;
3411 * do_y420vdb_modes - Parse YCBCR 420 only modes
3412 * @connector: connector corresponding to the HDMI sink
3413 * @svds: start of the data block of CEA YCBCR 420 VDB
3414 * @len: length of the CEA YCBCR 420 VDB
3416 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3417 * which contains modes which can be supported in YCBCR 420
3418 * output format only.
3420 static int do_y420vdb_modes(struct drm_connector *connector,
3421 const u8 *svds, u8 svds_len)
3424 struct drm_device *dev = connector->dev;
3425 struct drm_display_info *info = &connector->display_info;
3426 struct drm_hdmi_info *hdmi = &info->hdmi;
3428 for (i = 0; i < svds_len; i++) {
3429 u8 vic = svd_to_vic(svds[i]);
3430 struct drm_display_mode *newmode;
3432 if (!drm_valid_cea_vic(vic))
3435 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3438 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3439 drm_mode_probed_add(connector, newmode);
3444 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3449 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3450 * @connector: connector corresponding to the HDMI sink
3451 * @vic: CEA vic for the video mode to be added in the map
3453 * Makes an entry for a videomode in the YCBCR 420 bitmap
3456 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3458 u8 vic = svd_to_vic(svd);
3459 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3461 if (!drm_valid_cea_vic(vic))
3464 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3468 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3471 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3473 for (i = 0; i < len; i++) {
3474 struct drm_display_mode *mode;
3475 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3478 * YCBCR420 capability block contains a bitmap which
3479 * gives the index of CEA modes from CEA VDB, which
3480 * can support YCBCR 420 sampling output also (apart
3481 * from RGB/YCBCR444 etc).
3482 * For example, if the bit 0 in bitmap is set,
3483 * first mode in VDB can support YCBCR420 output too.
3484 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3486 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3487 drm_add_cmdb_modes(connector, db[i]);
3489 drm_mode_probed_add(connector, mode);
3497 struct stereo_mandatory_mode {
3498 int width, height, vrefresh;
3502 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3503 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3504 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3506 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3508 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3509 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3510 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3511 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3512 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3516 stereo_match_mandatory(const struct drm_display_mode *mode,
3517 const struct stereo_mandatory_mode *stereo_mode)
3519 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3521 return mode->hdisplay == stereo_mode->width &&
3522 mode->vdisplay == stereo_mode->height &&
3523 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3524 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3527 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3529 struct drm_device *dev = connector->dev;
3530 const struct drm_display_mode *mode;
3531 struct list_head stereo_modes;
3534 INIT_LIST_HEAD(&stereo_modes);
3536 list_for_each_entry(mode, &connector->probed_modes, head) {
3537 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3538 const struct stereo_mandatory_mode *mandatory;
3539 struct drm_display_mode *new_mode;
3541 if (!stereo_match_mandatory(mode,
3542 &stereo_mandatory_modes[i]))
3545 mandatory = &stereo_mandatory_modes[i];
3546 new_mode = drm_mode_duplicate(dev, mode);
3550 new_mode->flags |= mandatory->flags;
3551 list_add_tail(&new_mode->head, &stereo_modes);
3556 list_splice_tail(&stereo_modes, &connector->probed_modes);
3561 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3563 struct drm_device *dev = connector->dev;
3564 struct drm_display_mode *newmode;
3566 if (!drm_valid_hdmi_vic(vic)) {
3567 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3571 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3575 drm_mode_probed_add(connector, newmode);
3580 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3581 const u8 *video_db, u8 video_len, u8 video_index)
3583 struct drm_display_mode *newmode;
3586 if (structure & (1 << 0)) {
3587 newmode = drm_display_mode_from_vic_index(connector, video_db,
3591 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3592 drm_mode_probed_add(connector, newmode);
3596 if (structure & (1 << 6)) {
3597 newmode = drm_display_mode_from_vic_index(connector, video_db,
3601 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3602 drm_mode_probed_add(connector, newmode);
3606 if (structure & (1 << 8)) {
3607 newmode = drm_display_mode_from_vic_index(connector, video_db,
3611 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3612 drm_mode_probed_add(connector, newmode);
3621 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3622 * @connector: connector corresponding to the HDMI sink
3623 * @db: start of the CEA vendor specific block
3624 * @len: length of the CEA block payload, ie. one can access up to db[len]
3626 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3627 * also adds the stereo 3d modes when applicable.
3630 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3631 const u8 *video_db, u8 video_len)
3633 struct drm_display_info *info = &connector->display_info;
3634 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3635 u8 vic_len, hdmi_3d_len = 0;
3642 /* no HDMI_Video_Present */
3643 if (!(db[8] & (1 << 5)))
3646 /* Latency_Fields_Present */
3647 if (db[8] & (1 << 7))
3650 /* I_Latency_Fields_Present */
3651 if (db[8] & (1 << 6))
3654 /* the declared length is not long enough for the 2 first bytes
3655 * of additional video format capabilities */
3656 if (len < (8 + offset + 2))
3661 if (db[8 + offset] & (1 << 7)) {
3662 modes += add_hdmi_mandatory_stereo_modes(connector);
3664 /* 3D_Multi_present */
3665 multi_present = (db[8 + offset] & 0x60) >> 5;
3669 vic_len = db[8 + offset] >> 5;
3670 hdmi_3d_len = db[8 + offset] & 0x1f;
3672 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3675 vic = db[9 + offset + i];
3676 modes += add_hdmi_mode(connector, vic);
3678 offset += 1 + vic_len;
3680 if (multi_present == 1)
3682 else if (multi_present == 2)
3687 if (len < (8 + offset + hdmi_3d_len - 1))
3690 if (hdmi_3d_len < multi_len)
3693 if (multi_present == 1 || multi_present == 2) {
3694 /* 3D_Structure_ALL */
3695 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3697 /* check if 3D_MASK is present */
3698 if (multi_present == 2)
3699 mask = (db[10 + offset] << 8) | db[11 + offset];
3703 for (i = 0; i < 16; i++) {
3704 if (mask & (1 << i))
3705 modes += add_3d_struct_modes(connector,
3712 offset += multi_len;
3714 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3716 struct drm_display_mode *newmode = NULL;
3717 unsigned int newflag = 0;
3718 bool detail_present;
3720 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3722 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3725 /* 2D_VIC_order_X */
3726 vic_index = db[8 + offset + i] >> 4;
3728 /* 3D_Structure_X */
3729 switch (db[8 + offset + i] & 0x0f) {
3731 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3734 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3738 if ((db[9 + offset + i] >> 4) == 1)
3739 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3744 newmode = drm_display_mode_from_vic_index(connector,
3750 newmode->flags |= newflag;
3751 drm_mode_probed_add(connector, newmode);
3762 info->has_hdmi_infoframe = true;
3767 cea_db_payload_len(const u8 *db)
3769 return db[0] & 0x1f;
3773 cea_db_extended_tag(const u8 *db)
3779 cea_db_tag(const u8 *db)
3785 cea_revision(const u8 *cea)
3791 cea_db_offsets(const u8 *cea, int *start, int *end)
3793 /* DisplayID CTA extension blocks and top-level CEA EDID
3794 * block header definitions differ in the following bytes:
3795 * 1) Byte 2 of the header specifies length differently,
3796 * 2) Byte 3 is only present in the CEA top level block.
3798 * The different definitions for byte 2 follow.
3800 * DisplayID CTA extension block defines byte 2 as:
3801 * Number of payload bytes
3803 * CEA EDID block defines byte 2 as:
3804 * Byte number (decimal) within this block where the 18-byte
3805 * DTDs begin. If no non-DTD data is present in this extension
3806 * block, the value should be set to 04h (the byte after next).
3807 * If set to 00h, there are no DTDs present in this block and
3810 if (cea[0] == DATA_BLOCK_CTA) {
3812 *end = *start + cea[2];
3813 } else if (cea[0] == CEA_EXT) {
3814 /* Data block offset in CEA extension block */
3819 if (*end < 4 || *end > 127)
3828 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3832 if (cea_db_tag(db) != VENDOR_BLOCK)
3835 if (cea_db_payload_len(db) < 5)
3838 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3840 return hdmi_id == HDMI_IEEE_OUI;
3843 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3847 if (cea_db_tag(db) != VENDOR_BLOCK)
3850 if (cea_db_payload_len(db) < 7)
3853 oui = db[3] << 16 | db[2] << 8 | db[1];
3855 return oui == HDMI_FORUM_IEEE_OUI;
3858 static bool cea_db_is_vcdb(const u8 *db)
3860 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3863 if (cea_db_payload_len(db) != 2)
3866 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3872 static bool cea_db_is_y420cmdb(const u8 *db)
3874 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3877 if (!cea_db_payload_len(db))
3880 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3886 static bool cea_db_is_y420vdb(const u8 *db)
3888 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3891 if (!cea_db_payload_len(db))
3894 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3900 #define for_each_cea_db(cea, i, start, end) \
3901 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3903 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3906 struct drm_display_info *info = &connector->display_info;
3907 struct drm_hdmi_info *hdmi = &info->hdmi;
3908 u8 map_len = cea_db_payload_len(db) - 1;
3913 /* All CEA modes support ycbcr420 sampling also.*/
3914 hdmi->y420_cmdb_map = U64_MAX;
3915 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3920 * This map indicates which of the existing CEA block modes
3921 * from VDB can support YCBCR420 output too. So if bit=0 is
3922 * set, first mode from VDB can support YCBCR420 output too.
3923 * We will parse and keep this map, before parsing VDB itself
3924 * to avoid going through the same block again and again.
3926 * Spec is not clear about max possible size of this block.
3927 * Clamping max bitmap block size at 8 bytes. Every byte can
3928 * address 8 CEA modes, in this way this map can address
3929 * 8*8 = first 64 SVDs.
3931 if (WARN_ON_ONCE(map_len > 8))
3934 for (count = 0; count < map_len; count++)
3935 map |= (u64)db[2 + count] << (8 * count);
3938 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3940 hdmi->y420_cmdb_map = map;
3944 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3946 const u8 *cea = drm_find_cea_extension(edid);
3947 const u8 *db, *hdmi = NULL, *video = NULL;
3948 u8 dbl, hdmi_len, video_len = 0;
3951 if (cea && cea_revision(cea) >= 3) {
3954 if (cea_db_offsets(cea, &start, &end))
3957 for_each_cea_db(cea, i, start, end) {
3959 dbl = cea_db_payload_len(db);
3961 if (cea_db_tag(db) == VIDEO_BLOCK) {
3964 modes += do_cea_modes(connector, video, dbl);
3965 } else if (cea_db_is_hdmi_vsdb(db)) {
3968 } else if (cea_db_is_y420vdb(db)) {
3969 const u8 *vdb420 = &db[2];
3971 /* Add 4:2:0(only) modes present in EDID */
3972 modes += do_y420vdb_modes(connector,
3980 * We parse the HDMI VSDB after having added the cea modes as we will
3981 * be patching their flags when the sink supports stereo 3D.
3984 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3990 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3992 const struct drm_display_mode *cea_mode;
3993 int clock1, clock2, clock;
3998 * allow 5kHz clock difference either way to account for
3999 * the 10kHz clock resolution limit of detailed timings.
4001 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4002 if (drm_valid_cea_vic(vic)) {
4004 cea_mode = &edid_cea_modes[vic];
4005 clock1 = cea_mode->clock;
4006 clock2 = cea_mode_alternate_clock(cea_mode);
4008 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4009 if (drm_valid_hdmi_vic(vic)) {
4011 cea_mode = &edid_4k_modes[vic];
4012 clock1 = cea_mode->clock;
4013 clock2 = hdmi_mode_alternate_clock(cea_mode);
4019 /* pick whichever is closest */
4020 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4025 if (mode->clock == clock)
4028 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4029 type, vic, mode->clock, clock);
4030 mode->clock = clock;
4033 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4035 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4038 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4041 if (cea_db_payload_len(db) < 3)
4047 static uint8_t eotf_supported(const u8 *edid_ext)
4049 return edid_ext[2] &
4050 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4051 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4052 BIT(HDMI_EOTF_SMPTE_ST2084) |
4053 BIT(HDMI_EOTF_BT_2100_HLG));
4056 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4058 return edid_ext[3] &
4059 BIT(HDMI_STATIC_METADATA_TYPE1);
4063 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4067 len = cea_db_payload_len(db);
4069 connector->hdr_sink_metadata.hdmi_type1.eotf =
4071 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4072 hdr_metadata_type(db);
4075 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4077 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4079 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4083 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4085 u8 len = cea_db_payload_len(db);
4087 if (len >= 6 && (db[6] & (1 << 7)))
4088 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4090 connector->latency_present[0] = db[8] >> 7;
4091 connector->latency_present[1] = (db[8] >> 6) & 1;
4094 connector->video_latency[0] = db[9];
4096 connector->audio_latency[0] = db[10];
4098 connector->video_latency[1] = db[11];
4100 connector->audio_latency[1] = db[12];
4102 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4103 "video latency %d %d, "
4104 "audio latency %d %d\n",
4105 connector->latency_present[0],
4106 connector->latency_present[1],
4107 connector->video_latency[0],
4108 connector->video_latency[1],
4109 connector->audio_latency[0],
4110 connector->audio_latency[1]);
4114 monitor_name(struct detailed_timing *t, void *data)
4116 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4117 *(u8 **)data = t->data.other_data.data.str.str;
4120 static int get_monitor_name(struct edid *edid, char name[13])
4122 char *edid_name = NULL;
4128 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4129 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4130 if (edid_name[mnl] == 0x0a)
4133 name[mnl] = edid_name[mnl];
4140 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4141 * @edid: monitor EDID information
4142 * @name: pointer to a character array to hold the name of the monitor
4143 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4146 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4154 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4155 memcpy(name, buf, name_length);
4156 name[name_length] = '\0';
4158 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4160 static void clear_eld(struct drm_connector *connector)
4162 memset(connector->eld, 0, sizeof(connector->eld));
4164 connector->latency_present[0] = false;
4165 connector->latency_present[1] = false;
4166 connector->video_latency[0] = 0;
4167 connector->audio_latency[0] = 0;
4168 connector->video_latency[1] = 0;
4169 connector->audio_latency[1] = 0;
4173 * drm_edid_to_eld - build ELD from EDID
4174 * @connector: connector corresponding to the HDMI/DP sink
4175 * @edid: EDID to parse
4177 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4178 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4180 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4182 uint8_t *eld = connector->eld;
4185 int total_sad_count = 0;
4189 clear_eld(connector);
4194 cea = drm_find_cea_extension(edid);
4196 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4200 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4201 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4203 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4204 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4206 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4208 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4209 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4210 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4211 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4213 if (cea_revision(cea) >= 3) {
4216 if (cea_db_offsets(cea, &start, &end)) {
4221 for_each_cea_db(cea, i, start, end) {
4223 dbl = cea_db_payload_len(db);
4225 switch (cea_db_tag(db)) {
4229 /* Audio Data Block, contains SADs */
4230 sad_count = min(dbl / 3, 15 - total_sad_count);
4232 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4233 &db[1], sad_count * 3);
4234 total_sad_count += sad_count;
4237 /* Speaker Allocation Data Block */
4239 eld[DRM_ELD_SPEAKER] = db[1];
4242 /* HDMI Vendor-Specific Data Block */
4243 if (cea_db_is_hdmi_vsdb(db))
4244 drm_parse_hdmi_vsdb_audio(connector, db);
4251 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4253 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4254 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4255 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4257 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4259 eld[DRM_ELD_BASELINE_ELD_LEN] =
4260 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4262 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4263 drm_eld_size(eld), total_sad_count);
4267 * drm_edid_to_sad - extracts SADs from EDID
4268 * @edid: EDID to parse
4269 * @sads: pointer that will be set to the extracted SADs
4271 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4273 * Note: The returned pointer needs to be freed using kfree().
4275 * Return: The number of found SADs or negative number on error.
4277 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4280 int i, start, end, dbl;
4283 cea = drm_find_cea_extension(edid);
4285 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4289 if (cea_revision(cea) < 3) {
4290 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4294 if (cea_db_offsets(cea, &start, &end)) {
4295 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4299 for_each_cea_db(cea, i, start, end) {
4302 if (cea_db_tag(db) == AUDIO_BLOCK) {
4304 dbl = cea_db_payload_len(db);
4306 count = dbl / 3; /* SAD is 3B */
4307 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4310 for (j = 0; j < count; j++) {
4311 u8 *sad = &db[1 + j * 3];
4313 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4314 (*sads)[j].channels = sad[0] & 0x7;
4315 (*sads)[j].freq = sad[1] & 0x7F;
4316 (*sads)[j].byte2 = sad[2];
4324 EXPORT_SYMBOL(drm_edid_to_sad);
4327 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4328 * @edid: EDID to parse
4329 * @sadb: pointer to the speaker block
4331 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4333 * Note: The returned pointer needs to be freed using kfree().
4335 * Return: The number of found Speaker Allocation Blocks or negative number on
4338 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4341 int i, start, end, dbl;
4344 cea = drm_find_cea_extension(edid);
4346 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4350 if (cea_revision(cea) < 3) {
4351 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4355 if (cea_db_offsets(cea, &start, &end)) {
4356 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4360 for_each_cea_db(cea, i, start, end) {
4361 const u8 *db = &cea[i];
4363 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4364 dbl = cea_db_payload_len(db);
4366 /* Speaker Allocation Data Block */
4368 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4379 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4382 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4383 * @connector: connector associated with the HDMI/DP sink
4384 * @mode: the display mode
4386 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4387 * the sink doesn't support audio or video.
4389 int drm_av_sync_delay(struct drm_connector *connector,
4390 const struct drm_display_mode *mode)
4392 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4395 if (!connector->latency_present[0])
4397 if (!connector->latency_present[1])
4400 a = connector->audio_latency[i];
4401 v = connector->video_latency[i];
4404 * HDMI/DP sink doesn't support audio or video?
4406 if (a == 255 || v == 255)
4410 * Convert raw EDID values to millisecond.
4411 * Treat unknown latency as 0ms.
4414 a = min(2 * (a - 1), 500);
4416 v = min(2 * (v - 1), 500);
4418 return max(v - a, 0);
4420 EXPORT_SYMBOL(drm_av_sync_delay);
4423 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4424 * @edid: monitor EDID information
4426 * Parse the CEA extension according to CEA-861-B.
4428 * Return: True if the monitor is HDMI, false if not or unknown.
4430 bool drm_detect_hdmi_monitor(struct edid *edid)
4434 int start_offset, end_offset;
4436 edid_ext = drm_find_cea_extension(edid);
4440 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4444 * Because HDMI identifier is in Vendor Specific Block,
4445 * search it from all data blocks of CEA extension.
4447 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4448 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4454 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4457 * drm_detect_monitor_audio - check monitor audio capability
4458 * @edid: EDID block to scan
4460 * Monitor should have CEA extension block.
4461 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4462 * audio' only. If there is any audio extension block and supported
4463 * audio format, assume at least 'basic audio' support, even if 'basic
4464 * audio' is not defined in EDID.
4466 * Return: True if the monitor supports audio, false otherwise.
4468 bool drm_detect_monitor_audio(struct edid *edid)
4472 bool has_audio = false;
4473 int start_offset, end_offset;
4475 edid_ext = drm_find_cea_extension(edid);
4479 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4482 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4486 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4489 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4490 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4492 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4493 DRM_DEBUG_KMS("CEA audio format %d\n",
4494 (edid_ext[i + j] >> 3) & 0xf);
4501 EXPORT_SYMBOL(drm_detect_monitor_audio);
4505 * drm_default_rgb_quant_range - default RGB quantization range
4506 * @mode: display mode
4508 * Determine the default RGB quantization range for the mode,
4509 * as specified in CEA-861.
4511 * Return: The default RGB quantization range for the mode
4513 enum hdmi_quantization_range
4514 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4516 /* All CEA modes other than VIC 1 use limited quantization range. */
4517 return drm_match_cea_mode(mode) > 1 ?
4518 HDMI_QUANTIZATION_RANGE_LIMITED :
4519 HDMI_QUANTIZATION_RANGE_FULL;
4521 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4523 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4525 struct drm_display_info *info = &connector->display_info;
4527 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4529 if (db[2] & EDID_CEA_VCDB_QS)
4530 info->rgb_quant_range_selectable = true;
4533 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4537 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4539 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4540 hdmi->y420_dc_modes = dc_mask;
4543 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4546 struct drm_display_info *display = &connector->display_info;
4547 struct drm_hdmi_info *hdmi = &display->hdmi;
4549 display->has_hdmi_infoframe = true;
4551 if (hf_vsdb[6] & 0x80) {
4552 hdmi->scdc.supported = true;
4553 if (hf_vsdb[6] & 0x40)
4554 hdmi->scdc.read_request = true;
4558 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4559 * And as per the spec, three factors confirm this:
4560 * * Availability of a HF-VSDB block in EDID (check)
4561 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4562 * * SCDC support available (let's check)
4563 * Lets check it out.
4567 /* max clock is 5000 KHz times block value */
4568 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4569 struct drm_scdc *scdc = &hdmi->scdc;
4571 if (max_tmds_clock > 340000) {
4572 display->max_tmds_clock = max_tmds_clock;
4573 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4574 display->max_tmds_clock);
4577 if (scdc->supported) {
4578 scdc->scrambling.supported = true;
4580 /* Few sinks support scrambling for cloks < 340M */
4581 if ((hf_vsdb[6] & 0x8))
4582 scdc->scrambling.low_rates = true;
4586 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4589 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4592 struct drm_display_info *info = &connector->display_info;
4593 unsigned int dc_bpc = 0;
4595 /* HDMI supports at least 8 bpc */
4598 if (cea_db_payload_len(hdmi) < 6)
4601 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4603 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4604 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4608 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4610 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4611 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4615 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4617 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4618 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4623 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4628 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4629 connector->name, dc_bpc);
4633 * Deep color support mandates RGB444 support for all video
4634 * modes and forbids YCRCB422 support for all video modes per
4637 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4639 /* YCRCB444 is optional according to spec. */
4640 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4641 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4642 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4647 * Spec says that if any deep color mode is supported at all,
4648 * then deep color 36 bit must be supported.
4650 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4651 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4657 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4659 struct drm_display_info *info = &connector->display_info;
4660 u8 len = cea_db_payload_len(db);
4663 info->dvi_dual = db[6] & 1;
4665 info->max_tmds_clock = db[7] * 5000;
4667 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4668 "max TMDS clock %d kHz\n",
4670 info->max_tmds_clock);
4672 drm_parse_hdmi_deep_color_info(connector, db);
4675 static void drm_parse_cea_ext(struct drm_connector *connector,
4676 const struct edid *edid)
4678 struct drm_display_info *info = &connector->display_info;
4682 edid_ext = drm_find_cea_extension(edid);
4686 info->cea_rev = edid_ext[1];
4688 /* The existence of a CEA block should imply RGB support */
4689 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4690 if (edid_ext[3] & EDID_CEA_YCRCB444)
4691 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4692 if (edid_ext[3] & EDID_CEA_YCRCB422)
4693 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4695 if (cea_db_offsets(edid_ext, &start, &end))
4698 for_each_cea_db(edid_ext, i, start, end) {
4699 const u8 *db = &edid_ext[i];
4701 if (cea_db_is_hdmi_vsdb(db))
4702 drm_parse_hdmi_vsdb_video(connector, db);
4703 if (cea_db_is_hdmi_forum_vsdb(db))
4704 drm_parse_hdmi_forum_vsdb(connector, db);
4705 if (cea_db_is_y420cmdb(db))
4706 drm_parse_y420cmdb_bitmap(connector, db);
4707 if (cea_db_is_vcdb(db))
4708 drm_parse_vcdb(connector, db);
4709 if (cea_db_is_hdmi_hdr_metadata_block(db))
4710 drm_parse_hdr_metadata_block(connector, db);
4714 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4715 * all of the values which would have been set from EDID
4718 drm_reset_display_info(struct drm_connector *connector)
4720 struct drm_display_info *info = &connector->display_info;
4723 info->height_mm = 0;
4726 info->color_formats = 0;
4728 info->max_tmds_clock = 0;
4729 info->dvi_dual = false;
4730 info->has_hdmi_infoframe = false;
4731 info->rgb_quant_range_selectable = false;
4732 memset(&info->hdmi, 0, sizeof(info->hdmi));
4734 info->non_desktop = 0;
4737 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4739 struct drm_display_info *info = &connector->display_info;
4741 u32 quirks = edid_get_quirks(edid);
4743 drm_reset_display_info(connector);
4745 info->width_mm = edid->width_cm * 10;
4746 info->height_mm = edid->height_cm * 10;
4748 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4750 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4752 if (edid->revision < 3)
4755 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4758 drm_parse_cea_ext(connector, edid);
4761 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4763 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4764 * tells us to assume 8 bpc color depth if the EDID doesn't have
4765 * extensions which tell otherwise.
4767 if (info->bpc == 0 && edid->revision == 3 &&
4768 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4770 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4771 connector->name, info->bpc);
4774 /* Only defined for 1.4 with digital displays */
4775 if (edid->revision < 4)
4778 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4779 case DRM_EDID_DIGITAL_DEPTH_6:
4782 case DRM_EDID_DIGITAL_DEPTH_8:
4785 case DRM_EDID_DIGITAL_DEPTH_10:
4788 case DRM_EDID_DIGITAL_DEPTH_12:
4791 case DRM_EDID_DIGITAL_DEPTH_14:
4794 case DRM_EDID_DIGITAL_DEPTH_16:
4797 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4803 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4804 connector->name, info->bpc);
4806 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4807 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4808 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4809 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4810 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4814 static int validate_displayid(u8 *displayid, int length, int idx)
4818 struct displayid_hdr *base;
4820 base = (struct displayid_hdr *)&displayid[idx];
4822 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4823 base->rev, base->bytes, base->prod_id, base->ext_count);
4825 if (base->bytes + 5 > length - idx)
4827 for (i = idx; i <= base->bytes + 5; i++) {
4828 csum += displayid[i];
4831 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4837 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4838 struct displayid_detailed_timings_1 *timings)
4840 struct drm_display_mode *mode;
4841 unsigned pixel_clock = (timings->pixel_clock[0] |
4842 (timings->pixel_clock[1] << 8) |
4843 (timings->pixel_clock[2] << 16));
4844 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4845 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4846 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4847 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4848 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4849 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4850 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4851 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4852 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4853 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4854 mode = drm_mode_create(dev);
4858 mode->clock = pixel_clock * 10;
4859 mode->hdisplay = hactive;
4860 mode->hsync_start = mode->hdisplay + hsync;
4861 mode->hsync_end = mode->hsync_start + hsync_width;
4862 mode->htotal = mode->hdisplay + hblank;
4864 mode->vdisplay = vactive;
4865 mode->vsync_start = mode->vdisplay + vsync;
4866 mode->vsync_end = mode->vsync_start + vsync_width;
4867 mode->vtotal = mode->vdisplay + vblank;
4870 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4871 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4872 mode->type = DRM_MODE_TYPE_DRIVER;
4874 if (timings->flags & 0x80)
4875 mode->type |= DRM_MODE_TYPE_PREFERRED;
4876 mode->vrefresh = drm_mode_vrefresh(mode);
4877 drm_mode_set_name(mode);
4882 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4883 struct displayid_block *block)
4885 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4888 struct drm_display_mode *newmode;
4890 /* blocks must be multiple of 20 bytes length */
4891 if (block->num_bytes % 20)
4894 num_timings = block->num_bytes / 20;
4895 for (i = 0; i < num_timings; i++) {
4896 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4898 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4902 drm_mode_probed_add(connector, newmode);
4908 static int add_displayid_detailed_modes(struct drm_connector *connector,
4914 int length = EDID_LENGTH;
4915 struct displayid_block *block;
4918 displayid = drm_find_displayid_extension(edid);
4922 ret = validate_displayid(displayid, length, idx);
4926 idx += sizeof(struct displayid_hdr);
4927 for_each_displayid_db(displayid, block, idx, length) {
4928 switch (block->tag) {
4929 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4930 num_modes += add_displayid_detailed_1_modes(connector, block);
4938 * drm_add_edid_modes - add modes from EDID data, if available
4939 * @connector: connector we're probing
4942 * Add the specified modes to the connector's mode list. Also fills out the
4943 * &drm_display_info structure and ELD in @connector with any information which
4944 * can be derived from the edid.
4946 * Return: The number of modes added or 0 if we couldn't find any.
4948 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4954 clear_eld(connector);
4957 if (!drm_edid_is_valid(edid)) {
4958 clear_eld(connector);
4959 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4964 drm_edid_to_eld(connector, edid);
4967 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4968 * To avoid multiple parsing of same block, lets parse that map
4969 * from sink info, before parsing CEA modes.
4971 quirks = drm_add_display_info(connector, edid);
4974 * EDID spec says modes should be preferred in this order:
4975 * - preferred detailed mode
4976 * - other detailed modes from base block
4977 * - detailed modes from extension blocks
4978 * - CVT 3-byte code modes
4979 * - standard timing codes
4980 * - established timing codes
4981 * - modes inferred from GTF or CVT range information
4983 * We get this pretty much right.
4985 * XXX order for additional mode types in extension blocks?
4987 num_modes += add_detailed_modes(connector, edid, quirks);
4988 num_modes += add_cvt_modes(connector, edid);
4989 num_modes += add_standard_modes(connector, edid);
4990 num_modes += add_established_modes(connector, edid);
4991 num_modes += add_cea_modes(connector, edid);
4992 num_modes += add_alternate_cea_modes(connector, edid);
4993 num_modes += add_displayid_detailed_modes(connector, edid);
4994 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4995 num_modes += add_inferred_modes(connector, edid);
4997 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4998 edid_fixup_preferred(connector, quirks);
5000 if (quirks & EDID_QUIRK_FORCE_6BPC)
5001 connector->display_info.bpc = 6;
5003 if (quirks & EDID_QUIRK_FORCE_8BPC)
5004 connector->display_info.bpc = 8;
5006 if (quirks & EDID_QUIRK_FORCE_10BPC)
5007 connector->display_info.bpc = 10;
5009 if (quirks & EDID_QUIRK_FORCE_12BPC)
5010 connector->display_info.bpc = 12;
5014 EXPORT_SYMBOL(drm_add_edid_modes);
5017 * drm_add_modes_noedid - add modes for the connectors without EDID
5018 * @connector: connector we're probing
5019 * @hdisplay: the horizontal display limit
5020 * @vdisplay: the vertical display limit
5022 * Add the specified modes to the connector's mode list. Only when the
5023 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5025 * Return: The number of modes added or 0 if we couldn't find any.
5027 int drm_add_modes_noedid(struct drm_connector *connector,
5028 int hdisplay, int vdisplay)
5030 int i, count, num_modes = 0;
5031 struct drm_display_mode *mode;
5032 struct drm_device *dev = connector->dev;
5034 count = ARRAY_SIZE(drm_dmt_modes);
5040 for (i = 0; i < count; i++) {
5041 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5042 if (hdisplay && vdisplay) {
5044 * Only when two are valid, they will be used to check
5045 * whether the mode should be added to the mode list of
5048 if (ptr->hdisplay > hdisplay ||
5049 ptr->vdisplay > vdisplay)
5052 if (drm_mode_vrefresh(ptr) > 61)
5054 mode = drm_mode_duplicate(dev, ptr);
5056 drm_mode_probed_add(connector, mode);
5062 EXPORT_SYMBOL(drm_add_modes_noedid);
5065 * drm_set_preferred_mode - Sets the preferred mode of a connector
5066 * @connector: connector whose mode list should be processed
5067 * @hpref: horizontal resolution of preferred mode
5068 * @vpref: vertical resolution of preferred mode
5070 * Marks a mode as preferred if it matches the resolution specified by @hpref
5073 void drm_set_preferred_mode(struct drm_connector *connector,
5074 int hpref, int vpref)
5076 struct drm_display_mode *mode;
5078 list_for_each_entry(mode, &connector->probed_modes, head) {
5079 if (mode->hdisplay == hpref &&
5080 mode->vdisplay == vpref)
5081 mode->type |= DRM_MODE_TYPE_PREFERRED;
5084 EXPORT_SYMBOL(drm_set_preferred_mode);
5086 static bool is_hdmi2_sink(struct drm_connector *connector)
5089 * FIXME: sil-sii8620 doesn't have a connector around when
5090 * we need one, so we have to be prepared for a NULL connector.
5095 return connector->display_info.hdmi.scdc.supported ||
5096 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5099 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5101 return sink_eotf & BIT(output_eotf);
5105 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5106 * HDR metadata from userspace
5107 * @frame: HDMI DRM infoframe
5108 * @conn_state: Connector state containing HDR metadata
5110 * Return: 0 on success or a negative error code on failure.
5113 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5114 const struct drm_connector_state *conn_state)
5116 struct drm_connector *connector;
5117 struct hdr_output_metadata *hdr_metadata;
5120 if (!frame || !conn_state)
5123 connector = conn_state->connector;
5125 if (!conn_state->hdr_output_metadata)
5128 hdr_metadata = conn_state->hdr_output_metadata->data;
5130 if (!hdr_metadata || !connector)
5133 /* Sink EOTF is Bit map while infoframe is absolute values */
5134 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5135 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5136 DRM_DEBUG_KMS("EOTF Not Supported\n");
5140 err = hdmi_drm_infoframe_init(frame);
5144 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5145 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5147 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5148 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5149 BUILD_BUG_ON(sizeof(frame->white_point) !=
5150 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5152 memcpy(&frame->display_primaries,
5153 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5154 sizeof(frame->display_primaries));
5156 memcpy(&frame->white_point,
5157 &hdr_metadata->hdmi_metadata_type1.white_point,
5158 sizeof(frame->white_point));
5160 frame->max_display_mastering_luminance =
5161 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5162 frame->min_display_mastering_luminance =
5163 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5164 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5165 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5169 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5172 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5173 * data from a DRM display mode
5174 * @frame: HDMI AVI infoframe
5175 * @connector: the connector
5176 * @mode: DRM display mode
5178 * Return: 0 on success or a negative error code on failure.
5181 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5182 struct drm_connector *connector,
5183 const struct drm_display_mode *mode)
5185 enum hdmi_picture_aspect picture_aspect;
5188 if (!frame || !mode)
5191 err = hdmi_avi_infoframe_init(frame);
5195 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5196 frame->pixel_repeat = 1;
5198 frame->video_code = drm_match_cea_mode(mode);
5201 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5202 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5203 * have to make sure we dont break HDMI 1.4 sinks.
5205 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
5206 frame->video_code = 0;
5209 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5210 * we should send its VIC in vendor infoframes, else send the
5211 * VIC in AVI infoframes. Lets check if this mode is present in
5212 * HDMI 1.4b 4K modes
5214 if (frame->video_code) {
5215 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
5216 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
5218 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
5219 frame->video_code = 0;
5222 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5225 * As some drivers don't support atomic, we can't use connector state.
5226 * So just initialize the frame with default values, just the same way
5227 * as it's done with other properties here.
5229 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5233 * Populate picture aspect ratio from either
5234 * user input (if specified) or from the CEA mode list.
5236 picture_aspect = mode->picture_aspect_ratio;
5237 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
5238 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
5241 * The infoframe can't convey anything but none, 4:3
5242 * and 16:9, so if the user has asked for anything else
5243 * we can only satisfy it by specifying the right VIC.
5245 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5246 if (picture_aspect !=
5247 drm_get_cea_aspect_ratio(frame->video_code))
5249 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5252 frame->picture_aspect = picture_aspect;
5253 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5254 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5258 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5260 /* HDMI Colorspace Spec Definitions */
5261 #define FULL_COLORIMETRY_MASK 0x1FF
5262 #define NORMAL_COLORIMETRY_MASK 0x3
5263 #define EXTENDED_COLORIMETRY_MASK 0x7
5264 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5266 #define C(x) ((x) << 0)
5267 #define EC(x) ((x) << 2)
5268 #define ACE(x) ((x) << 5)
5270 #define HDMI_COLORIMETRY_NO_DATA 0x0
5271 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5272 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5273 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5274 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5275 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5276 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5277 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5278 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5279 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5280 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5281 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5282 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5284 static const u32 hdmi_colorimetry_val[] = {
5285 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5286 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5287 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5288 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5289 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5290 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5291 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5292 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5293 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5294 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5295 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5303 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5304 * colorspace information
5305 * @frame: HDMI AVI infoframe
5306 * @conn_state: connector state
5309 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5310 const struct drm_connector_state *conn_state)
5312 u32 colorimetry_val;
5313 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5315 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5316 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5318 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5320 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5322 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5323 * structure and extend it in drivers/video/hdmi
5325 frame->extended_colorimetry = (colorimetry_val >> 2) &
5326 EXTENDED_COLORIMETRY_MASK;
5328 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5331 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5332 * quantization range information
5333 * @frame: HDMI AVI infoframe
5334 * @connector: the connector
5335 * @mode: DRM display mode
5336 * @rgb_quant_range: RGB quantization range (Q)
5339 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5340 struct drm_connector *connector,
5341 const struct drm_display_mode *mode,
5342 enum hdmi_quantization_range rgb_quant_range)
5344 const struct drm_display_info *info = &connector->display_info;
5348 * "A Source shall not send a non-zero Q value that does not correspond
5349 * to the default RGB Quantization Range for the transmitted Picture
5350 * unless the Sink indicates support for the Q bit in a Video
5351 * Capabilities Data Block."
5353 * HDMI 2.0 recommends sending non-zero Q when it does match the
5354 * default RGB quantization range for the mode, even when QS=0.
5356 if (info->rgb_quant_range_selectable ||
5357 rgb_quant_range == drm_default_rgb_quant_range(mode))
5358 frame->quantization_range = rgb_quant_range;
5360 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5364 * "When transmitting any RGB colorimetry, the Source should set the
5365 * YQ-field to match the RGB Quantization Range being transmitted
5366 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5367 * set YQ=1) and the Sink shall ignore the YQ-field."
5369 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5370 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5371 * good way to tell which version of CEA-861 the sink supports, so
5372 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5375 if (!is_hdmi2_sink(connector) ||
5376 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5377 frame->ycc_quantization_range =
5378 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5380 frame->ycc_quantization_range =
5381 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5383 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5385 static enum hdmi_3d_structure
5386 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5388 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5391 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5392 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5393 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5394 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5395 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5396 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5397 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5398 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5399 case DRM_MODE_FLAG_3D_L_DEPTH:
5400 return HDMI_3D_STRUCTURE_L_DEPTH;
5401 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5402 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5403 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5404 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5405 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5406 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5408 return HDMI_3D_STRUCTURE_INVALID;
5413 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5414 * data from a DRM display mode
5415 * @frame: HDMI vendor infoframe
5416 * @connector: the connector
5417 * @mode: DRM display mode
5419 * Note that there's is a need to send HDMI vendor infoframes only when using a
5420 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5421 * function will return -EINVAL, error that can be safely ignored.
5423 * Return: 0 on success or a negative error code on failure.
5426 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5427 struct drm_connector *connector,
5428 const struct drm_display_mode *mode)
5431 * FIXME: sil-sii8620 doesn't have a connector around when
5432 * we need one, so we have to be prepared for a NULL connector.
5434 bool has_hdmi_infoframe = connector ?
5435 connector->display_info.has_hdmi_infoframe : false;
5440 if (!frame || !mode)
5443 if (!has_hdmi_infoframe)
5446 vic = drm_match_hdmi_mode(mode);
5447 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5450 * Even if it's not absolutely necessary to send the infoframe
5451 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5452 * know that the sink can handle it. This is based on a
5453 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5454 * have trouble realizing that they shuld switch from 3D to 2D
5455 * mode if the source simply stops sending the infoframe when
5456 * it wants to switch from 3D to 2D.
5459 if (vic && s3d_flags)
5462 err = hdmi_vendor_infoframe_init(frame);
5467 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5471 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5473 static int drm_parse_tiled_block(struct drm_connector *connector,
5474 struct displayid_block *block)
5476 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5478 u8 tile_v_loc, tile_h_loc;
5479 u8 num_v_tile, num_h_tile;
5480 struct drm_tile_group *tg;
5482 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5483 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5485 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5486 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5487 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5488 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5490 connector->has_tile = true;
5491 if (tile->tile_cap & 0x80)
5492 connector->tile_is_single_monitor = true;
5494 connector->num_h_tile = num_h_tile + 1;
5495 connector->num_v_tile = num_v_tile + 1;
5496 connector->tile_h_loc = tile_h_loc;
5497 connector->tile_v_loc = tile_v_loc;
5498 connector->tile_h_size = w + 1;
5499 connector->tile_v_size = h + 1;
5501 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5502 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5503 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5504 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5505 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5507 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5509 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5514 if (connector->tile_group != tg) {
5515 /* if we haven't got a pointer,
5516 take the reference, drop ref to old tile group */
5517 if (connector->tile_group) {
5518 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5520 connector->tile_group = tg;
5522 /* if same tile group, then release the ref we just took. */
5523 drm_mode_put_tile_group(connector->dev, tg);
5527 static int drm_parse_display_id(struct drm_connector *connector,
5528 u8 *displayid, int length,
5529 bool is_edid_extension)
5531 /* if this is an EDID extension the first byte will be 0x70 */
5533 struct displayid_block *block;
5536 if (is_edid_extension)
5539 ret = validate_displayid(displayid, length, idx);
5543 idx += sizeof(struct displayid_hdr);
5544 for_each_displayid_db(displayid, block, idx, length) {
5545 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5546 block->tag, block->rev, block->num_bytes);
5548 switch (block->tag) {
5549 case DATA_BLOCK_TILED_DISPLAY:
5550 ret = drm_parse_tiled_block(connector, block);
5554 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5555 /* handled in mode gathering code. */
5557 case DATA_BLOCK_CTA:
5558 /* handled in the cea parser code. */
5561 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5568 static void drm_get_displayid(struct drm_connector *connector,
5571 void *displayid = NULL;
5573 connector->has_tile = false;
5574 displayid = drm_find_displayid_extension(edid);
5576 /* drop reference to any tile group we had */
5580 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5583 if (!connector->has_tile)
5587 if (connector->tile_group) {
5588 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5589 connector->tile_group = NULL;
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