drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
  43
  44 #define mmUVD_PG0_CC_UVD_HARVESTING                                                                    0x00c7
  45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX                                                           1
  46 //UVD_PG0_CC_UVD_HARVESTING
  47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                         0x1
  48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                           0x00000002L
  49
  50 #define UVD7_MAX_HW_INSTANCES_VEGA20                    2
  51
  52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int uvd_v7_0_start(struct amdgpu_device *adev);
  56 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  58
  59 static int amdgpu_ih_clientid_uvds[] = {
  60         SOC15_IH_CLIENTID_UVD,
  61         SOC15_IH_CLIENTID_UVD1
  62 };
  63
  64 /**
  65  * uvd_v7_0_ring_get_rptr - get read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware read pointer
  70  */
  71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  76 }
  77
  78 /**
  79  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Returns the current hardware enc read pointer
  84  */
  85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  90                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  91         else
  92                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  93 }
  94
  95 /**
  96  * uvd_v7_0_ring_get_wptr - get write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware write pointer
 101  */
 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 107 }
 108
 109 /**
 110  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
 111  *
 112  * @ring: amdgpu_ring pointer
 113  *
 114  * Returns the current hardware enc write pointer
 115  */
 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         if (ring->use_doorbell)
 121                 return adev->wb.wb[ring->wptr_offs];
 122
 123         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 124                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 125         else
 126                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 127 }
 128
 129 /**
 130  * uvd_v7_0_ring_set_wptr - set write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the write pointer to the hardware
 135  */
 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 141 }
 142
 143 /**
 144  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 145  *
 146  * @ring: amdgpu_ring pointer
 147  *
 148  * Commits the enc write pointer to the hardware
 149  */
 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 151 {
 152         struct amdgpu_device *adev = ring->adev;
 153
 154         if (ring->use_doorbell) {
 155                 /* XXX check if swapping is necessary on BE */
 156                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 157                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 158                 return;
 159         }
 160
 161         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 162                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 163                         lower_32_bits(ring->wptr));
 164         else
 165                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 166                         lower_32_bits(ring->wptr));
 167 }
 168
 169 /**
 170  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 171  *
 172  * @ring: the engine to test on
 173  *
 174  */
 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 179         unsigned i;
 180         int r;
 181
 182         if (amdgpu_sriov_vf(adev))
 183                 return 0;
 184
 185         r = amdgpu_ring_alloc(ring, 16);
 186         if (r) {
 187                 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n",
 188                           ring->me, ring->idx, r);
 189                 return r;
 190         }
 191         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 192         amdgpu_ring_commit(ring);
 193
 194         for (i = 0; i < adev->usec_timeout; i++) {
 195                 if (amdgpu_ring_get_rptr(ring) != rptr)
 196                         break;
 197                 DRM_UDELAY(1);
 198         }
 199
 200         if (i < adev->usec_timeout) {
 201                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
 202                          ring->me, ring->idx, i);
 203         } else {
 204                 DRM_ERROR("amdgpu: (%d)ring %d test failed\n",
 205                           ring->me, ring->idx);
 206                 r = -ETIMEDOUT;
 207         }
 208
 209         return r;
 210 }
 211
 212 /**
 213  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 214  *
 215  * @adev: amdgpu_device pointer
 216  * @ring: ring we should submit the msg to
 217  * @handle: session handle to use
 218  * @fence: optional fence to return
 219  *
 220  * Open up a stream for HW test
 221  */
 222 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 223                                        struct dma_fence **fence)
 224 {
 225         const unsigned ib_size_dw = 16;
 226         struct amdgpu_job *job;
 227         struct amdgpu_ib *ib;
 228         struct dma_fence *f = NULL;
 229         uint64_t dummy;
 230         int i, r;
 231
 232         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 233         if (r)
 234                 return r;
 235
 236         ib = &job->ibs[0];
 237         dummy = ib->gpu_addr + 1024;
 238
 239         ib->length_dw = 0;
 240         ib->ptr[ib->length_dw++] = 0x00000018;
 241         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 242         ib->ptr[ib->length_dw++] = handle;
 243         ib->ptr[ib->length_dw++] = 0x00000000;
 244         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 245         ib->ptr[ib->length_dw++] = dummy;
 246
 247         ib->ptr[ib->length_dw++] = 0x00000014;
 248         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 249         ib->ptr[ib->length_dw++] = 0x0000001c;
 250         ib->ptr[ib->length_dw++] = 0x00000000;
 251         ib->ptr[ib->length_dw++] = 0x00000000;
 252
 253         ib->ptr[ib->length_dw++] = 0x00000008;
 254         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 255
 256         for (i = ib->length_dw; i < ib_size_dw; ++i)
 257                 ib->ptr[i] = 0x0;
 258
 259         r = amdgpu_job_submit_direct(job, ring, &f);
 260         if (r)
 261                 goto err;
 262
 263         if (fence)
 264                 *fence = dma_fence_get(f);
 265         dma_fence_put(f);
 266         return 0;
 267
 268 err:
 269         amdgpu_job_free(job);
 270         return r;
 271 }
 272
 273 /**
 274  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 275  *
 276  * @adev: amdgpu_device pointer
 277  * @ring: ring we should submit the msg to
 278  * @handle: session handle to use
 279  * @fence: optional fence to return
 280  *
 281  * Close up a stream for HW test or if userspace failed to do so
 282  */
 283 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 284                                 struct dma_fence **fence)
 285 {
 286         const unsigned ib_size_dw = 16;
 287         struct amdgpu_job *job;
 288         struct amdgpu_ib *ib;
 289         struct dma_fence *f = NULL;
 290         uint64_t dummy;
 291         int i, r;
 292
 293         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 294         if (r)
 295                 return r;
 296
 297         ib = &job->ibs[0];
 298         dummy = ib->gpu_addr + 1024;
 299
 300         ib->length_dw = 0;
 301         ib->ptr[ib->length_dw++] = 0x00000018;
 302         ib->ptr[ib->length_dw++] = 0x00000001;
 303         ib->ptr[ib->length_dw++] = handle;
 304         ib->ptr[ib->length_dw++] = 0x00000000;
 305         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 306         ib->ptr[ib->length_dw++] = dummy;
 307
 308         ib->ptr[ib->length_dw++] = 0x00000014;
 309         ib->ptr[ib->length_dw++] = 0x00000002;
 310         ib->ptr[ib->length_dw++] = 0x0000001c;
 311         ib->ptr[ib->length_dw++] = 0x00000000;
 312         ib->ptr[ib->length_dw++] = 0x00000000;
 313
 314         ib->ptr[ib->length_dw++] = 0x00000008;
 315         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 316
 317         for (i = ib->length_dw; i < ib_size_dw; ++i)
 318                 ib->ptr[i] = 0x0;
 319
 320         r = amdgpu_job_submit_direct(job, ring, &f);
 321         if (r)
 322                 goto err;
 323
 324         if (fence)
 325                 *fence = dma_fence_get(f);
 326         dma_fence_put(f);
 327         return 0;
 328
 329 err:
 330         amdgpu_job_free(job);
 331         return r;
 332 }
 333
 334 /**
 335  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 336  *
 337  * @ring: the engine to test on
 338  *
 339  */
 340 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 341 {
 342         struct dma_fence *fence = NULL;
 343         long r;
 344
 345         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 346         if (r) {
 347                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
 348                 goto error;
 349         }
 350
 351         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence);
 352         if (r) {
 353                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
 354                 goto error;
 355         }
 356
 357         r = dma_fence_wait_timeout(fence, false, timeout);
 358         if (r == 0) {
 359                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
 360                 r = -ETIMEDOUT;
 361         } else if (r < 0) {
 362                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
 363         } else {
 364                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
 365                 r = 0;
 366         }
 367 error:
 368         dma_fence_put(fence);
 369         return r;
 370 }
 371
 372 static int uvd_v7_0_early_init(void *handle)
 373 {
 374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 375
 376         if (adev->asic_type == CHIP_VEGA20) {
 377                 u32 harvest;
 378                 int i;
 379
 380                 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
 381                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 382                         harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
 383                         if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
 384                                 adev->uvd.harvest_config |= 1 << i;
 385                         }
 386                 }
 387                 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
 388                                                  AMDGPU_UVD_HARVEST_UVD1))
 389                         /* both instances are harvested, disable the block */
 390                         return -ENOENT;
 391         } else {
 392                 adev->uvd.num_uvd_inst = 1;
 393         }
 394
 395         if (amdgpu_sriov_vf(adev))
 396                 adev->uvd.num_enc_rings = 1;
 397         else
 398                 adev->uvd.num_enc_rings = 2;
 399         uvd_v7_0_set_ring_funcs(adev);
 400         uvd_v7_0_set_enc_ring_funcs(adev);
 401         uvd_v7_0_set_irq_funcs(adev);
 402
 403         return 0;
 404 }
 405
 406 static int uvd_v7_0_sw_init(void *handle)
 407 {
 408         struct amdgpu_ring *ring;
 409
 410         int i, j, r;
 411         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 412
 413         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 414                 if (adev->uvd.harvest_config & (1 << j))
 415                         continue;
 416                 /* UVD TRAP */
 417                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
 418                 if (r)
 419                         return r;
 420
 421                 /* UVD ENC TRAP */
 422                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 423                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
 424                         if (r)
 425                                 return r;
 426                 }
 427         }
 428
 429         r = amdgpu_uvd_sw_init(adev);
 430         if (r)
 431                 return r;
 432
 433         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 434                 const struct common_firmware_header *hdr;
 435                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 436                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 437                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 438                 adev->firmware.fw_size +=
 439                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 440
 441                 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
 442                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
 443                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
 444                         adev->firmware.fw_size +=
 445                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 446                 }
 447                 DRM_INFO("PSP loading UVD firmware\n");
 448         }
 449
 450         r = amdgpu_uvd_resume(adev);
 451         if (r)
 452                 return r;
 453
 454         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 455                 if (adev->uvd.harvest_config & (1 << j))
 456                         continue;
 457                 if (!amdgpu_sriov_vf(adev)) {
 458                         ring = &adev->uvd.inst[j].ring;
 459                         sprintf(ring->name, "uvd<%d>", j);
 460                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 461                         if (r)
 462                                 return r;
 463                 }
 464
 465                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 466                         ring = &adev->uvd.inst[j].ring_enc[i];
 467                         sprintf(ring->name, "uvd_enc%d<%d>", i, j);
 468                         if (amdgpu_sriov_vf(adev)) {
 469                                 ring->use_doorbell = true;
 470
 471                                 /* currently only use the first enconding ring for
 472                                  * sriov, so set unused location for other unused rings.
 473                                  */
 474                                 if (i == 0)
 475                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 476                                 else
 477                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 478                         }
 479                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 480                         if (r)
 481                                 return r;
 482                 }
 483         }
 484
 485         r = amdgpu_uvd_entity_init(adev);
 486         if (r)
 487                 return r;
 488
 489         r = amdgpu_virt_alloc_mm_table(adev);
 490         if (r)
 491                 return r;
 492
 493         return r;
 494 }
 495
 496 static int uvd_v7_0_sw_fini(void *handle)
 497 {
 498         int i, j, r;
 499         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 500
 501         amdgpu_virt_free_mm_table(adev);
 502
 503         r = amdgpu_uvd_suspend(adev);
 504         if (r)
 505                 return r;
 506
 507         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 508                 if (adev->uvd.harvest_config & (1 << j))
 509                         continue;
 510                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 511                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 512         }
 513         return amdgpu_uvd_sw_fini(adev);
 514 }
 515
 516 /**
 517  * uvd_v7_0_hw_init - start and test UVD block
 518  *
 519  * @adev: amdgpu_device pointer
 520  *
 521  * Initialize the hardware, boot up the VCPU and do some testing
 522  */
 523 static int uvd_v7_0_hw_init(void *handle)
 524 {
 525         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 526         struct amdgpu_ring *ring;
 527         uint32_t tmp;
 528         int i, j, r;
 529
 530         if (amdgpu_sriov_vf(adev))
 531                 r = uvd_v7_0_sriov_start(adev);
 532         else
 533                 r = uvd_v7_0_start(adev);
 534         if (r)
 535                 goto done;
 536
 537         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 538                 if (adev->uvd.harvest_config & (1 << j))
 539                         continue;
 540                 ring = &adev->uvd.inst[j].ring;
 541
 542                 if (!amdgpu_sriov_vf(adev)) {
 543                         ring->ready = true;
 544                         r = amdgpu_ring_test_ring(ring);
 545                         if (r) {
 546                                 ring->ready = false;
 547                                 goto done;
 548                         }
 549
 550                         r = amdgpu_ring_alloc(ring, 10);
 551                         if (r) {
 552                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 553                                 goto done;
 554                         }
 555
 556                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 557                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 558                         amdgpu_ring_write(ring, tmp);
 559                         amdgpu_ring_write(ring, 0xFFFFF);
 560
 561                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 562                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 563                         amdgpu_ring_write(ring, tmp);
 564                         amdgpu_ring_write(ring, 0xFFFFF);
 565
 566                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 567                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 568                         amdgpu_ring_write(ring, tmp);
 569                         amdgpu_ring_write(ring, 0xFFFFF);
 570
 571                         /* Clear timeout status bits */
 572                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 573                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 574                         amdgpu_ring_write(ring, 0x8);
 575
 576                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 577                                 mmUVD_SEMA_CNTL), 0));
 578                         amdgpu_ring_write(ring, 3);
 579
 580                         amdgpu_ring_commit(ring);
 581                 }
 582
 583                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 584                         ring = &adev->uvd.inst[j].ring_enc[i];
 585                         ring->ready = true;
 586                         r = amdgpu_ring_test_ring(ring);
 587                         if (r) {
 588                                 ring->ready = false;
 589                                 goto done;
 590                         }
 591                 }
 592         }
 593 done:
 594         if (!r)
 595                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 596
 597         return r;
 598 }
 599
 600 /**
 601  * uvd_v7_0_hw_fini - stop the hardware block
 602  *
 603  * @adev: amdgpu_device pointer
 604  *
 605  * Stop the UVD block, mark ring as not ready any more
 606  */
 607 static int uvd_v7_0_hw_fini(void *handle)
 608 {
 609         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 610         int i;
 611
 612         if (!amdgpu_sriov_vf(adev))
 613                 uvd_v7_0_stop(adev);
 614         else {
 615                 /* full access mode, so don't touch any UVD register */
 616                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 617         }
 618
 619         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 620                 if (adev->uvd.harvest_config & (1 << i))
 621                         continue;
 622                 adev->uvd.inst[i].ring.ready = false;
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int uvd_v7_0_suspend(void *handle)
 629 {
 630         int r;
 631         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 632
 633         r = uvd_v7_0_hw_fini(adev);
 634         if (r)
 635                 return r;
 636
 637         return amdgpu_uvd_suspend(adev);
 638 }
 639
 640 static int uvd_v7_0_resume(void *handle)
 641 {
 642         int r;
 643         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 644
 645         r = amdgpu_uvd_resume(adev);
 646         if (r)
 647                 return r;
 648
 649         return uvd_v7_0_hw_init(adev);
 650 }
 651
 652 /**
 653  * uvd_v7_0_mc_resume - memory controller programming
 654  *
 655  * @adev: amdgpu_device pointer
 656  *
 657  * Let the UVD memory controller know it's offsets
 658  */
 659 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 660 {
 661         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 662         uint32_t offset;
 663         int i;
 664
 665         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 666                 if (adev->uvd.harvest_config & (1 << i))
 667                         continue;
 668                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 669                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 670                                 i == 0 ?
 671                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
 672                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
 673                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 674                                 i == 0 ?
 675                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
 676                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
 677                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 678                         offset = 0;
 679                 } else {
 680                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 681                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 682                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 683                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 684                         offset = size;
 685                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 686                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 687                 }
 688
 689                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 690
 691                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 692                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 693                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 694                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 695                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 696                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 697
 698                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 699                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 700                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 701                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 702                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 703                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 704                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 705
 706                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 707                                 adev->gfx.config.gb_addr_config);
 708                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 709                                 adev->gfx.config.gb_addr_config);
 710                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 711                                 adev->gfx.config.gb_addr_config);
 712
 713                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 714         }
 715 }
 716
 717 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 718                                 struct amdgpu_mm_table *table)
 719 {
 720         uint32_t data = 0, loop;
 721         uint64_t addr = table->gpu_addr;
 722         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 723         uint32_t size;
 724         int i;
 725
 726         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 727
 728         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 729         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 730         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 731
 732         /* 2, update vmid of descriptor */
 733         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 734         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 735         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 736         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 737
 738         /* 3, notify mmsch about the size of this descriptor */
 739         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 740
 741         /* 4, set resp to zero */
 742         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 743
 744         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 745                 if (adev->uvd.harvest_config & (1 << i))
 746                         continue;
 747                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 748                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 749                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 750                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 751         }
 752         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 753         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 754
 755         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 756         loop = 1000;
 757         while ((data & 0x10000002) != 0x10000002) {
 758                 udelay(10);
 759                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 760                 loop--;
 761                 if (!loop)
 762                         break;
 763         }
 764
 765         if (!loop) {
 766                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 767                 return -EBUSY;
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 774 {
 775         struct amdgpu_ring *ring;
 776         uint32_t offset, size, tmp;
 777         uint32_t table_size = 0;
 778         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 779         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 780         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 781         struct mmsch_v1_0_cmd_end end = { {0} };
 782         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 783         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 784         uint8_t i = 0;
 785
 786         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 787         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 788         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 789         end.cmd_header.command_type = MMSCH_COMMAND__END;
 790
 791         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 792                 header->version = MMSCH_VERSION;
 793                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 794
 795                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 796                         header->uvd_table_offset = header->header_size;
 797                 else
 798                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 799
 800                 init_table += header->uvd_table_offset;
 801
 802                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 803                         if (adev->uvd.harvest_config & (1 << i))
 804                                 continue;
 805                         ring = &adev->uvd.inst[i].ring;
 806                         ring->wptr = 0;
 807                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 808
 809                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 810                                                            0xFFFFFFFF, 0x00000004);
 811                         /* mc resume*/
 812                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 813                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 814                                                             lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 815                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 816                                                             upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 817                                 offset = 0;
 818                         } else {
 819                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 820                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 821                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 822                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 823                                 offset = size;
 824                         }
 825
 826                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
 827                                                     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 828                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 829
 830                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 831                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 832                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 833                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 834                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 835                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 836
 837                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 838                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 839                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 840                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 841                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 842                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 843                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 844
 845                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 846                         /* mc resume end*/
 847
 848                         /* disable clock gating */
 849                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 850                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 851
 852                         /* disable interupt */
 853                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 854                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 855
 856                         /* stall UMC and register bus before resetting VCPU */
 857                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 858                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 859                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 860
 861                         /* put LMI, VCPU, RBC etc... into reset */
 862                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 863                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 864                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 865                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 866                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 867                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 868                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 869                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 870                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 871
 872                         /* initialize UVD memory controller */
 873                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 874                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 875                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 876                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 877                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 878                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 879                                                                0x00100000L));
 880
 881                         /* take all subblocks out of reset, except VCPU */
 882                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 883                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 884
 885                         /* enable VCPU clock */
 886                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 887                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 888
 889                         /* enable master interrupt */
 890                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 891                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 892                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 893
 894                         /* clear the bit 4 of UVD_STATUS */
 895                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 896                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 897
 898                         /* force RBC into idle state */
 899                         size = order_base_2(ring->ring_size);
 900                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 901                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 902                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 903
 904                         ring = &adev->uvd.inst[i].ring_enc[0];
 905                         ring->wptr = 0;
 906                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 907                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 908                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 909
 910                         /* boot up the VCPU */
 911                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 912
 913                         /* enable UMC */
 914                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 915                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 916
 917                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 918                 }
 919                 /* add end packet */
 920                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 921                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 922                 header->uvd_table_size = table_size;
 923
 924         }
 925         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 926 }
 927
 928 /**
 929  * uvd_v7_0_start - start UVD block
 930  *
 931  * @adev: amdgpu_device pointer
 932  *
 933  * Setup and start the UVD block
 934  */
 935 static int uvd_v7_0_start(struct amdgpu_device *adev)
 936 {
 937         struct amdgpu_ring *ring;
 938         uint32_t rb_bufsz, tmp;
 939         uint32_t lmi_swap_cntl;
 940         uint32_t mp_swap_cntl;
 941         int i, j, k, r;
 942
 943         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 944                 if (adev->uvd.harvest_config & (1 << k))
 945                         continue;
 946                 /* disable DPG */
 947                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 948                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 949         }
 950
 951         /* disable byte swapping */
 952         lmi_swap_cntl = 0;
 953         mp_swap_cntl = 0;
 954
 955         uvd_v7_0_mc_resume(adev);
 956
 957         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 958                 if (adev->uvd.harvest_config & (1 << k))
 959                         continue;
 960                 ring = &adev->uvd.inst[k].ring;
 961                 /* disable clock gating */
 962                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 963                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 964
 965                 /* disable interupt */
 966                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 967                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 968
 969                 /* stall UMC and register bus before resetting VCPU */
 970                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 971                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 972                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 973                 mdelay(1);
 974
 975                 /* put LMI, VCPU, RBC etc... into reset */
 976                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 977                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 978                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 979                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 980                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 981                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 982                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 983                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 984                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 985                 mdelay(5);
 986
 987                 /* initialize UVD memory controller */
 988                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 989                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 990                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 991                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 992                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 993                         UVD_LMI_CTRL__REQ_MODE_MASK |
 994                         0x00100000L);
 995
 996 #ifdef __BIG_ENDIAN
 997                 /* swap (8 in 32) RB and IB */
 998                 lmi_swap_cntl = 0xa;
 999                 mp_swap_cntl = 0;
1000 #endif
1001                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1002                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
1003
1004                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
1005                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
1006                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
1007                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
1008                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
1009                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
1010
1011                 /* take all subblocks out of reset, except VCPU */
1012                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
1013                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1014                 mdelay(5);
1015
1016                 /* enable VCPU clock */
1017                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1018                                 UVD_VCPU_CNTL__CLK_EN_MASK);
1019
1020                 /* enable UMC */
1021                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
1022                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1023
1024                 /* boot up the VCPU */
1025                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
1026                 mdelay(10);
1027
1028                 for (i = 0; i < 10; ++i) {
1029                         uint32_t status;
1030
1031                         for (j = 0; j < 100; ++j) {
1032                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1033                                 if (status & 2)
1034                                         break;
1035                                 mdelay(10);
1036                         }
1037                         r = 0;
1038                         if (status & 2)
1039                                 break;
1040
1041                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1042                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1043                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1044                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1045                         mdelay(10);
1046                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1047                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1048                         mdelay(10);
1049                         r = -1;
1050                 }
1051
1052                 if (r) {
1053                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1054                         return r;
1055                 }
1056                 /* enable master interrupt */
1057                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1058                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1059                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1060
1061                 /* clear the bit 4 of UVD_STATUS */
1062                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1063                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1064
1065                 /* force RBC into idle state */
1066                 rb_bufsz = order_base_2(ring->ring_size);
1067                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1068                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1069                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1070                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1071                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1072                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1073                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1074
1075                 /* set the write pointer delay */
1076                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1077
1078                 /* set the wb address */
1079                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1080                                 (upper_32_bits(ring->gpu_addr) >> 2));
1081
1082                 /* programm the RB_BASE for ring buffer */
1083                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1084                                 lower_32_bits(ring->gpu_addr));
1085                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1086                                 upper_32_bits(ring->gpu_addr));
1087
1088                 /* Initialize the ring buffer's read and write pointers */
1089                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1090
1091                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1092                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1093                                 lower_32_bits(ring->wptr));
1094
1095                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1096                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1097
1098                 ring = &adev->uvd.inst[k].ring_enc[0];
1099                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1100                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1101                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1102                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1103                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1104
1105                 ring = &adev->uvd.inst[k].ring_enc[1];
1106                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1107                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1108                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1109                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1110                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1111         }
1112         return 0;
1113 }
1114
1115 /**
1116  * uvd_v7_0_stop - stop UVD block
1117  *
1118  * @adev: amdgpu_device pointer
1119  *
1120  * stop the UVD block
1121  */
1122 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1123 {
1124         uint8_t i = 0;
1125
1126         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1127                 if (adev->uvd.harvest_config & (1 << i))
1128                         continue;
1129                 /* force RBC into idle state */
1130                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1131
1132                 /* Stall UMC and register bus before resetting VCPU */
1133                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1134                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1135                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1136                 mdelay(1);
1137
1138                 /* put VCPU into reset */
1139                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1140                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1141                 mdelay(5);
1142
1143                 /* disable VCPU clock */
1144                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1145
1146                 /* Unstall UMC and register bus */
1147                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1148                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1149         }
1150 }
1151
1152 /**
1153  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1154  *
1155  * @ring: amdgpu_ring pointer
1156  * @fence: fence to emit
1157  *
1158  * Write a fence and a trap command to the ring.
1159  */
1160 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1161                                      unsigned flags)
1162 {
1163         struct amdgpu_device *adev = ring->adev;
1164
1165         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1166
1167         amdgpu_ring_write(ring,
1168                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1169         amdgpu_ring_write(ring, seq);
1170         amdgpu_ring_write(ring,
1171                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1172         amdgpu_ring_write(ring, addr & 0xffffffff);
1173         amdgpu_ring_write(ring,
1174                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1175         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1176         amdgpu_ring_write(ring,
1177                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1178         amdgpu_ring_write(ring, 0);
1179
1180         amdgpu_ring_write(ring,
1181                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1182         amdgpu_ring_write(ring, 0);
1183         amdgpu_ring_write(ring,
1184                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1185         amdgpu_ring_write(ring, 0);
1186         amdgpu_ring_write(ring,
1187                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1188         amdgpu_ring_write(ring, 2);
1189 }
1190
1191 /**
1192  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1193  *
1194  * @ring: amdgpu_ring pointer
1195  * @fence: fence to emit
1196  *
1197  * Write enc a fence and a trap command to the ring.
1198  */
1199 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1200                         u64 seq, unsigned flags)
1201 {
1202
1203         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1204
1205         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1206         amdgpu_ring_write(ring, addr);
1207         amdgpu_ring_write(ring, upper_32_bits(addr));
1208         amdgpu_ring_write(ring, seq);
1209         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1210 }
1211
1212 /**
1213  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1214  *
1215  * @ring: amdgpu_ring pointer
1216  */
1217 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1218 {
1219         /* The firmware doesn't seem to like touching registers at this point. */
1220 }
1221
1222 /**
1223  * uvd_v7_0_ring_test_ring - register write test
1224  *
1225  * @ring: amdgpu_ring pointer
1226  *
1227  * Test if we can successfully write to the context register
1228  */
1229 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1230 {
1231         struct amdgpu_device *adev = ring->adev;
1232         uint32_t tmp = 0;
1233         unsigned i;
1234         int r;
1235
1236         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1237         r = amdgpu_ring_alloc(ring, 3);
1238         if (r) {
1239                 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n",
1240                           ring->me, ring->idx, r);
1241                 return r;
1242         }
1243         amdgpu_ring_write(ring,
1244                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1245         amdgpu_ring_write(ring, 0xDEADBEEF);
1246         amdgpu_ring_commit(ring);
1247         for (i = 0; i < adev->usec_timeout; i++) {
1248                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1249                 if (tmp == 0xDEADBEEF)
1250                         break;
1251                 DRM_UDELAY(1);
1252         }
1253
1254         if (i < adev->usec_timeout) {
1255                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
1256                          ring->me, ring->idx, i);
1257         } else {
1258                 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n",
1259                           ring->me, ring->idx, tmp);
1260                 r = -EINVAL;
1261         }
1262         return r;
1263 }
1264
1265 /**
1266  * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
1267  *
1268  * @p: the CS parser with the IBs
1269  * @ib_idx: which IB to patch
1270  *
1271  */
1272 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1273                                            uint32_t ib_idx)
1274 {
1275         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1276         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1277         unsigned i;
1278
1279         /* No patching necessary for the first instance */
1280         if (!ring->me)
1281                 return 0;
1282
1283         for (i = 0; i < ib->length_dw; i += 2) {
1284                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1285
1286                 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1287                 reg += p->adev->reg_offset[UVD_HWIP][1][1];
1288
1289                 amdgpu_set_ib_value(p, ib_idx, i, reg);
1290         }
1291         return 0;
1292 }
1293
1294 /**
1295  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1296  *
1297  * @ring: amdgpu_ring pointer
1298  * @ib: indirect buffer to execute
1299  *
1300  * Write ring commands to execute the indirect buffer
1301  */
1302 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1303                                   struct amdgpu_ib *ib,
1304                                   unsigned vmid, bool ctx_switch)
1305 {
1306         struct amdgpu_device *adev = ring->adev;
1307
1308         amdgpu_ring_write(ring,
1309                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1310         amdgpu_ring_write(ring, vmid);
1311
1312         amdgpu_ring_write(ring,
1313                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1314         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1315         amdgpu_ring_write(ring,
1316                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1317         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1318         amdgpu_ring_write(ring,
1319                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1320         amdgpu_ring_write(ring, ib->length_dw);
1321 }
1322
1323 /**
1324  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1325  *
1326  * @ring: amdgpu_ring pointer
1327  * @ib: indirect buffer to execute
1328  *
1329  * Write enc ring commands to execute the indirect buffer
1330  */
1331 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1332                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1333 {
1334         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1335         amdgpu_ring_write(ring, vmid);
1336         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1337         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1338         amdgpu_ring_write(ring, ib->length_dw);
1339 }
1340
1341 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1342                                     uint32_t reg, uint32_t val)
1343 {
1344         struct amdgpu_device *adev = ring->adev;
1345
1346         amdgpu_ring_write(ring,
1347                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1348         amdgpu_ring_write(ring, reg << 2);
1349         amdgpu_ring_write(ring,
1350                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1351         amdgpu_ring_write(ring, val);
1352         amdgpu_ring_write(ring,
1353                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1354         amdgpu_ring_write(ring, 8);
1355 }
1356
1357 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1358                                         uint32_t val, uint32_t mask)
1359 {
1360         struct amdgpu_device *adev = ring->adev;
1361
1362         amdgpu_ring_write(ring,
1363                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1364         amdgpu_ring_write(ring, reg << 2);
1365         amdgpu_ring_write(ring,
1366                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1367         amdgpu_ring_write(ring, val);
1368         amdgpu_ring_write(ring,
1369                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1370         amdgpu_ring_write(ring, mask);
1371         amdgpu_ring_write(ring,
1372                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1373         amdgpu_ring_write(ring, 12);
1374 }
1375
1376 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1377                                         unsigned vmid, uint64_t pd_addr)
1378 {
1379         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1380         uint32_t data0, data1, mask;
1381
1382         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1383
1384         /* wait for reg writes */
1385         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1386         data1 = lower_32_bits(pd_addr);
1387         mask = 0xffffffff;
1388         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1389 }
1390
1391 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1392 {
1393         struct amdgpu_device *adev = ring->adev;
1394         int i;
1395
1396         WARN_ON(ring->wptr % 2 || count % 2);
1397
1398         for (i = 0; i < count / 2; i++) {
1399                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1400                 amdgpu_ring_write(ring, 0);
1401         }
1402 }
1403
1404 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1405 {
1406         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1407 }
1408
1409 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1410                                             uint32_t reg, uint32_t val,
1411                                             uint32_t mask)
1412 {
1413         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1414         amdgpu_ring_write(ring, reg << 2);
1415         amdgpu_ring_write(ring, mask);
1416         amdgpu_ring_write(ring, val);
1417 }
1418
1419 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1420                                             unsigned int vmid, uint64_t pd_addr)
1421 {
1422         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1423
1424         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1425
1426         /* wait for reg writes */
1427         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1428                                         lower_32_bits(pd_addr), 0xffffffff);
1429 }
1430
1431 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1432                                         uint32_t reg, uint32_t val)
1433 {
1434         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1435         amdgpu_ring_write(ring, reg << 2);
1436         amdgpu_ring_write(ring, val);
1437 }
1438
1439 #if 0
1440 static bool uvd_v7_0_is_idle(void *handle)
1441 {
1442         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1443
1444         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1445 }
1446
1447 static int uvd_v7_0_wait_for_idle(void *handle)
1448 {
1449         unsigned i;
1450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451
1452         for (i = 0; i < adev->usec_timeout; i++) {
1453                 if (uvd_v7_0_is_idle(handle))
1454                         return 0;
1455         }
1456         return -ETIMEDOUT;
1457 }
1458
1459 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1460 static bool uvd_v7_0_check_soft_reset(void *handle)
1461 {
1462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463         u32 srbm_soft_reset = 0;
1464         u32 tmp = RREG32(mmSRBM_STATUS);
1465
1466         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1467             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1468             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1469                     AMDGPU_UVD_STATUS_BUSY_MASK))
1470                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1471                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1472
1473         if (srbm_soft_reset) {
1474                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1475                 return true;
1476         } else {
1477                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1478                 return false;
1479         }
1480 }
1481
1482 static int uvd_v7_0_pre_soft_reset(void *handle)
1483 {
1484         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1485
1486         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1487                 return 0;
1488
1489         uvd_v7_0_stop(adev);
1490         return 0;
1491 }
1492
1493 static int uvd_v7_0_soft_reset(void *handle)
1494 {
1495         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1496         u32 srbm_soft_reset;
1497
1498         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1499                 return 0;
1500         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1501
1502         if (srbm_soft_reset) {
1503                 u32 tmp;
1504
1505                 tmp = RREG32(mmSRBM_SOFT_RESET);
1506                 tmp |= srbm_soft_reset;
1507                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1508                 WREG32(mmSRBM_SOFT_RESET, tmp);
1509                 tmp = RREG32(mmSRBM_SOFT_RESET);
1510
1511                 udelay(50);
1512
1513                 tmp &= ~srbm_soft_reset;
1514                 WREG32(mmSRBM_SOFT_RESET, tmp);
1515                 tmp = RREG32(mmSRBM_SOFT_RESET);
1516
1517                 /* Wait a little for things to settle down */
1518                 udelay(50);
1519         }
1520
1521         return 0;
1522 }
1523
1524 static int uvd_v7_0_post_soft_reset(void *handle)
1525 {
1526         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1527
1528         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1529                 return 0;
1530
1531         mdelay(5);
1532
1533         return uvd_v7_0_start(adev);
1534 }
1535 #endif
1536
1537 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1538                                         struct amdgpu_irq_src *source,
1539                                         unsigned type,
1540                                         enum amdgpu_interrupt_state state)
1541 {
1542         // TODO
1543         return 0;
1544 }
1545
1546 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1547                                       struct amdgpu_irq_src *source,
1548                                       struct amdgpu_iv_entry *entry)
1549 {
1550         uint32_t ip_instance;
1551
1552         switch (entry->client_id) {
1553         case SOC15_IH_CLIENTID_UVD:
1554                 ip_instance = 0;
1555                 break;
1556         case SOC15_IH_CLIENTID_UVD1:
1557                 ip_instance = 1;
1558                 break;
1559         default:
1560                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1561                 return 0;
1562         }
1563
1564         DRM_DEBUG("IH: UVD TRAP\n");
1565
1566         switch (entry->src_id) {
1567         case 124:
1568                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1569                 break;
1570         case 119:
1571                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1572                 break;
1573         case 120:
1574                 if (!amdgpu_sriov_vf(adev))
1575                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1576                 break;
1577         default:
1578                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1579                           entry->src_id, entry->src_data[0]);
1580                 break;
1581         }
1582
1583         return 0;
1584 }
1585
1586 #if 0
1587 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1588 {
1589         uint32_t data, data1, data2, suvd_flags;
1590
1591         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1592         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1593         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1594
1595         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1596                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1597
1598         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1599                      UVD_SUVD_CGC_GATE__SIT_MASK |
1600                      UVD_SUVD_CGC_GATE__SMP_MASK |
1601                      UVD_SUVD_CGC_GATE__SCM_MASK |
1602                      UVD_SUVD_CGC_GATE__SDB_MASK;
1603
1604         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1605                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1606                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1607
1608         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1609                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1610                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1611                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1612                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1613                         UVD_CGC_CTRL__SYS_MODE_MASK |
1614                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1615                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1616                         UVD_CGC_CTRL__REGS_MODE_MASK |
1617                         UVD_CGC_CTRL__RBC_MODE_MASK |
1618                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1619                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1620                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1621                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1622                         UVD_CGC_CTRL__MPC_MODE_MASK |
1623                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1624                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1625                         UVD_CGC_CTRL__WCB_MODE_MASK |
1626                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1627                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1628                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1629                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1630         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1631                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1632                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1633                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1634                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1635         data1 |= suvd_flags;
1636
1637         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1638         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1639         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1640         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1641 }
1642
1643 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1644 {
1645         uint32_t data, data1, cgc_flags, suvd_flags;
1646
1647         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1648         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1649
1650         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1651                 UVD_CGC_GATE__UDEC_MASK |
1652                 UVD_CGC_GATE__MPEG2_MASK |
1653                 UVD_CGC_GATE__RBC_MASK |
1654                 UVD_CGC_GATE__LMI_MC_MASK |
1655                 UVD_CGC_GATE__IDCT_MASK |
1656                 UVD_CGC_GATE__MPRD_MASK |
1657                 UVD_CGC_GATE__MPC_MASK |
1658                 UVD_CGC_GATE__LBSI_MASK |
1659                 UVD_CGC_GATE__LRBBM_MASK |
1660                 UVD_CGC_GATE__UDEC_RE_MASK |
1661                 UVD_CGC_GATE__UDEC_CM_MASK |
1662                 UVD_CGC_GATE__UDEC_IT_MASK |
1663                 UVD_CGC_GATE__UDEC_DB_MASK |
1664                 UVD_CGC_GATE__UDEC_MP_MASK |
1665                 UVD_CGC_GATE__WCB_MASK |
1666                 UVD_CGC_GATE__VCPU_MASK |
1667                 UVD_CGC_GATE__SCPU_MASK |
1668                 UVD_CGC_GATE__JPEG_MASK |
1669                 UVD_CGC_GATE__JPEG2_MASK;
1670
1671         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1672                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1673                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1674                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1675                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1676
1677         data |= cgc_flags;
1678         data1 |= suvd_flags;
1679
1680         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1681         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1682 }
1683
1684 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1685 {
1686         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1687
1688         if (enable)
1689                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1690                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1691         else
1692                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1693                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1694
1695         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1696 }
1697
1698
1699 static int uvd_v7_0_set_clockgating_state(void *handle,
1700                                           enum amd_clockgating_state state)
1701 {
1702         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1703         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1704
1705         uvd_v7_0_set_bypass_mode(adev, enable);
1706
1707         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1708                 return 0;
1709
1710         if (enable) {
1711                 /* disable HW gating and enable Sw gating */
1712                 uvd_v7_0_set_sw_clock_gating(adev);
1713         } else {
1714                 /* wait for STATUS to clear */
1715                 if (uvd_v7_0_wait_for_idle(handle))
1716                         return -EBUSY;
1717
1718                 /* enable HW gates because UVD is idle */
1719                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1720         }
1721
1722         return 0;
1723 }
1724
1725 static int uvd_v7_0_set_powergating_state(void *handle,
1726                                           enum amd_powergating_state state)
1727 {
1728         /* This doesn't actually powergate the UVD block.
1729          * That's done in the dpm code via the SMC.  This
1730          * just re-inits the block as necessary.  The actual
1731          * gating still happens in the dpm code.  We should
1732          * revisit this when there is a cleaner line between
1733          * the smc and the hw blocks
1734          */
1735         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1736
1737         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1738                 return 0;
1739
1740         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1741
1742         if (state == AMD_PG_STATE_GATE) {
1743                 uvd_v7_0_stop(adev);
1744                 return 0;
1745         } else {
1746                 return uvd_v7_0_start(adev);
1747         }
1748 }
1749 #endif
1750
1751 static int uvd_v7_0_set_clockgating_state(void *handle,
1752                                           enum amd_clockgating_state state)
1753 {
1754         /* needed for driver unload*/
1755         return 0;
1756 }
1757
1758 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1759         .name = "uvd_v7_0",
1760         .early_init = uvd_v7_0_early_init,
1761         .late_init = NULL,
1762         .sw_init = uvd_v7_0_sw_init,
1763         .sw_fini = uvd_v7_0_sw_fini,
1764         .hw_init = uvd_v7_0_hw_init,
1765         .hw_fini = uvd_v7_0_hw_fini,
1766         .suspend = uvd_v7_0_suspend,
1767         .resume = uvd_v7_0_resume,
1768         .is_idle = NULL /* uvd_v7_0_is_idle */,
1769         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1770         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1771         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1772         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1773         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1774         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1775         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1776 };
1777
1778 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1779         .type = AMDGPU_RING_TYPE_UVD,
1780         .align_mask = 0xf,
1781         .support_64bit_ptrs = false,
1782         .vmhub = AMDGPU_MMHUB,
1783         .get_rptr = uvd_v7_0_ring_get_rptr,
1784         .get_wptr = uvd_v7_0_ring_get_wptr,
1785         .set_wptr = uvd_v7_0_ring_set_wptr,
1786         .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
1787         .emit_frame_size =
1788                 6 + /* hdp invalidate */
1789                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1790                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1791                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1792                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1793         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1794         .emit_ib = uvd_v7_0_ring_emit_ib,
1795         .emit_fence = uvd_v7_0_ring_emit_fence,
1796         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1797         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1798         .test_ring = uvd_v7_0_ring_test_ring,
1799         .test_ib = amdgpu_uvd_ring_test_ib,
1800         .insert_nop = uvd_v7_0_ring_insert_nop,
1801         .pad_ib = amdgpu_ring_generic_pad_ib,
1802         .begin_use = amdgpu_uvd_ring_begin_use,
1803         .end_use = amdgpu_uvd_ring_end_use,
1804         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1805         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1806         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1807 };
1808
1809 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1810         .type = AMDGPU_RING_TYPE_UVD_ENC,
1811         .align_mask = 0x3f,
1812         .nop = HEVC_ENC_CMD_NO_OP,
1813         .support_64bit_ptrs = false,
1814         .vmhub = AMDGPU_MMHUB,
1815         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1816         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1817         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1818         .emit_frame_size =
1819                 3 + 3 + /* hdp flush / invalidate */
1820                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1821                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1822                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1823                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1824                 1, /* uvd_v7_0_enc_ring_insert_end */
1825         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1826         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1827         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1828         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1829         .test_ring = uvd_v7_0_enc_ring_test_ring,
1830         .test_ib = uvd_v7_0_enc_ring_test_ib,
1831         .insert_nop = amdgpu_ring_insert_nop,
1832         .insert_end = uvd_v7_0_enc_ring_insert_end,
1833         .pad_ib = amdgpu_ring_generic_pad_ib,
1834         .begin_use = amdgpu_uvd_ring_begin_use,
1835         .end_use = amdgpu_uvd_ring_end_use,
1836         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1837         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1838         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1839 };
1840
1841 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1842 {
1843         int i;
1844
1845         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1846                 if (adev->uvd.harvest_config & (1 << i))
1847                         continue;
1848                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1849                 adev->uvd.inst[i].ring.me = i;
1850                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1851         }
1852 }
1853
1854 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1855 {
1856         int i, j;
1857
1858         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1859                 if (adev->uvd.harvest_config & (1 << j))
1860                         continue;
1861                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1862                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1863                         adev->uvd.inst[j].ring_enc[i].me = j;
1864                 }
1865
1866                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1867         }
1868 }
1869
1870 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1871         .set = uvd_v7_0_set_interrupt_state,
1872         .process = uvd_v7_0_process_interrupt,
1873 };
1874
1875 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1876 {
1877         int i;
1878
1879         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1880                 if (adev->uvd.harvest_config & (1 << i))
1881                         continue;
1882                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1883                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1884         }
1885 }
1886
1887 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1888 {
1889                 .type = AMD_IP_BLOCK_TYPE_UVD,
1890                 .major = 7,
1891                 .minor = 0,
1892                 .rev = 0,
1893                 .funcs = &uvd_v7_0_ip_funcs,
1894 };