drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_hw_ip.h"
  31 #include "vcn_v2_0.h"
  32
  33 #include "vcn/vcn_4_0_0_offset.h"
  34 #include "vcn/vcn_4_0_0_sh_mask.h"
  35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  36
  37 #include <drm/drm_drv.h>
  38
  39 #define mmUVD_DPG_LMA_CTL                                                       regUVD_DPG_LMA_CTL
  40 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                              regUVD_DPG_LMA_CTL_BASE_IDX
  41 #define mmUVD_DPG_LMA_DATA                                                      regUVD_DPG_LMA_DATA
  42 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                             regUVD_DPG_LMA_DATA_BASE_IDX
  43
  44 #define VCN_VID_SOC_ADDRESS_2_0                                                 0x1fb00
  45 #define VCN1_VID_SOC_ADDRESS_3_0                                                0x48300
  46
  47 static int amdgpu_ih_clientid_vcns[] = {
  48         SOC15_IH_CLIENTID_VCN,
  49         SOC15_IH_CLIENTID_VCN1
  50 };
  51
  52 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
  53 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  54 static int vcn_v4_0_set_powergating_state(void *handle,
  55         enum amd_powergating_state state);
  56 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
  57         int inst_idx, struct dpg_pause_state *new_state);
  58
  59 /**
  60  * vcn_v4_0_early_init - set function pointers
  61  *
  62  * @handle: amdgpu_device pointer
  63  *
  64  * Set ring and irq function pointers
  65  */
  66 static int vcn_v4_0_early_init(void *handle)
  67 {
  68         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  69
  70         /* re-use enc ring as unified ring */
  71         adev->vcn.num_enc_rings = 1;
  72
  73         vcn_v4_0_set_unified_ring_funcs(adev);
  74         vcn_v4_0_set_irq_funcs(adev);
  75
  76         return 0;
  77 }
  78
  79 /**
  80  * vcn_v4_0_sw_init - sw init for VCN block
  81  *
  82  * @handle: amdgpu_device pointer
  83  *
  84  * Load firmware and sw initialization
  85  */
  86 static int vcn_v4_0_sw_init(void *handle)
  87 {
  88         struct amdgpu_ring *ring;
  89         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  90         int i, r;
  91
  92         r = amdgpu_vcn_sw_init(adev);
  93         if (r)
  94                 return r;
  95
  96         amdgpu_vcn_setup_ucode(adev);
  97
  98         r = amdgpu_vcn_resume(adev);
  99         if (r)
 100                 return r;
 101
 102         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 103                 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 104
 105                 if (adev->vcn.harvest_config & (1 << i))
 106                         continue;
 107
 108                 atomic_set(&adev->vcn.inst[i].sched_score, 0);
 109
 110                 /* VCN UNIFIED TRAP */
 111                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 112                                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 113                 if (r)
 114                         return r;
 115
 116                 ring = &adev->vcn.inst[i].ring_enc[0];
 117                 ring->use_doorbell = true;
 118                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
 119
 120                 sprintf(ring->name, "vcn_unified_%d", i);
 121
 122                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 123                                                 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
 124                 if (r)
 125                         return r;
 126
 127                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 128                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 129                 fw_shared->sq.is_enabled = 1;
 130
 131                 if (amdgpu_vcnfw_log)
 132                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 133         }
 134
 135         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 136                 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
 137
 138         return 0;
 139 }
 140
 141 /**
 142  * vcn_v4_0_sw_fini - sw fini for VCN block
 143  *
 144  * @handle: amdgpu_device pointer
 145  *
 146  * VCN suspend and free up sw allocation
 147  */
 148 static int vcn_v4_0_sw_fini(void *handle)
 149 {
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151         int i, r, idx;
 152
 153         if (drm_dev_enter(&adev->ddev, &idx)) {
 154                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 155                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 156
 157                         if (adev->vcn.harvest_config & (1 << i))
 158                                 continue;
 159
 160                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 161                         fw_shared->present_flag_0 = 0;
 162                         fw_shared->sq.is_enabled = 0;
 163                 }
 164
 165                 drm_dev_exit(idx);
 166         }
 167
 168         r = amdgpu_vcn_suspend(adev);
 169         if (r)
 170                 return r;
 171
 172         r = amdgpu_vcn_sw_fini(adev);
 173
 174         return r;
 175 }
 176
 177 /**
 178  * vcn_v4_0_hw_init - start and test VCN block
 179  *
 180  * @handle: amdgpu_device pointer
 181  *
 182  * Initialize the hardware, boot up the VCPU and do some testing
 183  */
 184 static int vcn_v4_0_hw_init(void *handle)
 185 {
 186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 187         struct amdgpu_ring *ring;
 188         int i, r;
 189
 190         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 191                 if (adev->vcn.harvest_config & (1 << i))
 192                         continue;
 193
 194                 ring = &adev->vcn.inst[i].ring_enc[0];
 195
 196                 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 197                                 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
 198
 199                 r = amdgpu_ring_test_helper(ring);
 200                 if (r)
 201                         goto done;
 202         }
 203
 204 done:
 205         if (!r)
 206                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 207                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 208
 209         return r;
 210 }
 211
 212 /**
 213  * vcn_v4_0_hw_fini - stop the hardware block
 214  *
 215  * @handle: amdgpu_device pointer
 216  *
 217  * Stop the VCN block, mark ring as not ready any more
 218  */
 219 static int vcn_v4_0_hw_fini(void *handle)
 220 {
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222         int i;
 223
 224         cancel_delayed_work_sync(&adev->vcn.idle_work);
 225
 226         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 227                 if (adev->vcn.harvest_config & (1 << i))
 228                         continue;
 229
 230                 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 231                         (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 232                                 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
 233                         vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 234                 }
 235         }
 236
 237         return 0;
 238 }
 239
 240 /**
 241  * vcn_v4_0_suspend - suspend VCN block
 242  *
 243  * @handle: amdgpu_device pointer
 244  *
 245  * HW fini and suspend VCN block
 246  */
 247 static int vcn_v4_0_suspend(void *handle)
 248 {
 249         int r;
 250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 251
 252         r = vcn_v4_0_hw_fini(adev);
 253         if (r)
 254                 return r;
 255
 256         r = amdgpu_vcn_suspend(adev);
 257
 258         return r;
 259 }
 260
 261 /**
 262  * vcn_v4_0_resume - resume VCN block
 263  *
 264  * @handle: amdgpu_device pointer
 265  *
 266  * Resume firmware and hw init VCN block
 267  */
 268 static int vcn_v4_0_resume(void *handle)
 269 {
 270         int r;
 271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 272
 273         r = amdgpu_vcn_resume(adev);
 274         if (r)
 275                 return r;
 276
 277         r = vcn_v4_0_hw_init(adev);
 278
 279         return r;
 280 }
 281
 282 /**
 283  * vcn_v4_0_mc_resume - memory controller programming
 284  *
 285  * @adev: amdgpu_device pointer
 286  * @inst: instance number
 287  *
 288  * Let the VCN memory controller know it's offsets
 289  */
 290 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
 291 {
 292         uint32_t offset, size;
 293         const struct common_firmware_header *hdr;
 294
 295         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 296         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 297
 298         /* cache window 0: fw */
 299         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 300                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 301                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 302                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 303                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 304                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 305                 offset = 0;
 306         } else {
 307                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 308                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 309                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 310                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 311                 offset = size;
 312                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 313         }
 314         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
 315
 316         /* cache window 1: stack */
 317         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 318                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 319         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 320                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 321         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 322         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 323
 324         /* cache window 2: context */
 325         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 326                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 327         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 328                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 329         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 330         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 331
 332         /* non-cache window */
 333         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 334                 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 335         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 336                 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 337         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 338         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
 339                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 340 }
 341
 342 /**
 343  * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
 344  *
 345  * @adev: amdgpu_device pointer
 346  * @inst_idx: instance number index
 347  * @indirect: indirectly write sram
 348  *
 349  * Let the VCN memory controller know it's offsets with dpg mode
 350  */
 351 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 352 {
 353         uint32_t offset, size;
 354         const struct common_firmware_header *hdr;
 355         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 356         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 357
 358         /* cache window 0: fw */
 359         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 360                 if (!indirect) {
 361                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 362                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 363                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 364                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 365                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 366                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 367                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 368                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 369                 } else {
 370                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 371                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 372                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 373                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 374                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 375                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 376                 }
 377                 offset = 0;
 378         } else {
 379                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 380                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 381                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 382                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 383                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 384                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 385                 offset = size;
 386                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 387                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 388                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 389         }
 390
 391         if (!indirect)
 392                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 393                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 394         else
 395                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 396                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 397
 398         /* cache window 1: stack */
 399         if (!indirect) {
 400                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 401                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 402                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 403                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 404                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 405                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 406                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 407                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 408         } else {
 409                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 410                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 411                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 412                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 413                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 414                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 415         }
 416         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 417                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 418
 419         /* cache window 2: context */
 420         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 421                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 422                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 423         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 424                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 425                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 426         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 427                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 428         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 429                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 430
 431         /* non-cache window */
 432         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 433                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 434                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 435         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 436                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 437                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 438         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 439                         VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 440         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 441                         VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
 442                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 443
 444         /* VCN global tiling registers */
 445         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 446                 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 447 }
 448
 449 /**
 450  * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
 451  *
 452  * @adev: amdgpu_device pointer
 453  * @inst: instance number
 454  *
 455  * Disable static power gating for VCN block
 456  */
 457 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 458 {
 459         uint32_t data = 0;
 460
 461         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 462                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 463                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 464                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 465                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 466                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 467                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 468                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 469                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 470                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 471                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 472                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 473                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 474                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 475                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 476
 477                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 478                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
 479                         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
 480         } else {
 481                 uint32_t value;
 482
 483                 value = (inst) ? 0x2200800 : 0;
 484                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 485                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 486                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 487                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 488                         | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 489                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 490                         | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 491                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 492                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 493                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 494                         | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 495                         | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 496                         | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 497                         | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 498
 499                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 500                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value,  0x3F3FFFFF);
 501         }
 502
 503         data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 504         data &= ~0x103;
 505         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 506                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 507                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 508
 509         WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 510
 511         return;
 512 }
 513
 514 /**
 515  * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
 516  *
 517  * @adev: amdgpu_device pointer
 518  * @inst: instance number
 519  *
 520  * Enable static power gating for VCN block
 521  */
 522 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 523 {
 524         uint32_t data;
 525
 526         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 527                 /* Before power off, this indicator has to be turned on */
 528                 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 529                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 530                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 531                 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 532
 533                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 534                         | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 535                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 536                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 537                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 538                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 539                         | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 540                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 541                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 542                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 543                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 544                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 545                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 546                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 547                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 548
 549                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 550                         | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
 551                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 552                         | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
 553                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 554                         | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
 555                         | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
 556                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 557                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 558                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 559                         | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
 560                         | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
 561                         | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
 562                         | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
 563                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
 564         }
 565
 566         return;
 567 }
 568
 569 /**
 570  * vcn_v4_0_disable_clock_gating - disable VCN clock gating
 571  *
 572  * @adev: amdgpu_device pointer
 573  * @inst: instance number
 574  *
 575  * Disable clock gating for VCN block
 576  */
 577 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
 578 {
 579         uint32_t data;
 580
 581         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 582                 return;
 583
 584         /* VCN disable CGC */
 585         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 586         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 587         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 588         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 589         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 590
 591         data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
 592         data &= ~(UVD_CGC_GATE__SYS_MASK
 593                 | UVD_CGC_GATE__UDEC_MASK
 594                 | UVD_CGC_GATE__MPEG2_MASK
 595                 | UVD_CGC_GATE__REGS_MASK
 596                 | UVD_CGC_GATE__RBC_MASK
 597                 | UVD_CGC_GATE__LMI_MC_MASK
 598                 | UVD_CGC_GATE__LMI_UMC_MASK
 599                 | UVD_CGC_GATE__IDCT_MASK
 600                 | UVD_CGC_GATE__MPRD_MASK
 601                 | UVD_CGC_GATE__MPC_MASK
 602                 | UVD_CGC_GATE__LBSI_MASK
 603                 | UVD_CGC_GATE__LRBBM_MASK
 604                 | UVD_CGC_GATE__UDEC_RE_MASK
 605                 | UVD_CGC_GATE__UDEC_CM_MASK
 606                 | UVD_CGC_GATE__UDEC_IT_MASK
 607                 | UVD_CGC_GATE__UDEC_DB_MASK
 608                 | UVD_CGC_GATE__UDEC_MP_MASK
 609                 | UVD_CGC_GATE__WCB_MASK
 610                 | UVD_CGC_GATE__VCPU_MASK
 611                 | UVD_CGC_GATE__MMSCH_MASK);
 612
 613         WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
 614         SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);
 615
 616         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 617         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 618                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 619                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 620                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 621                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 622                 | UVD_CGC_CTRL__SYS_MODE_MASK
 623                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 624                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 625                 | UVD_CGC_CTRL__REGS_MODE_MASK
 626                 | UVD_CGC_CTRL__RBC_MODE_MASK
 627                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 628                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 629                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 630                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 631                 | UVD_CGC_CTRL__MPC_MODE_MASK
 632                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 633                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 634                 | UVD_CGC_CTRL__WCB_MODE_MASK
 635                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 636                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 637         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 638
 639         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
 640         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 641                 | UVD_SUVD_CGC_GATE__SIT_MASK
 642                 | UVD_SUVD_CGC_GATE__SMP_MASK
 643                 | UVD_SUVD_CGC_GATE__SCM_MASK
 644                 | UVD_SUVD_CGC_GATE__SDB_MASK
 645                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 646                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 647                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 648                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 649                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 650                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 651                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 652                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 653                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 654                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 655                 | UVD_SUVD_CGC_GATE__ENT_MASK
 656                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 657                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 658                 | UVD_SUVD_CGC_GATE__SITE_MASK
 659                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 660                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 661                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 662                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 663                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 664         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
 665
 666         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 667         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 668                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 669                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 670                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 671                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 672                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 673                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 674                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 675                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 676                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 677         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 678 }
 679
 680 /**
 681  * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 682  *
 683  * @adev: amdgpu_device pointer
 684  * @sram_sel: sram select
 685  * @inst_idx: instance number index
 686  * @indirect: indirectly write sram
 687  *
 688  * Disable clock gating for VCN block with dpg mode
 689  */
 690 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 691       int inst_idx, uint8_t indirect)
 692 {
 693         uint32_t reg_data = 0;
 694
 695         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 696                 return;
 697
 698         /* enable sw clock gating control */
 699         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 700         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 701         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 702         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 703                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 704                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 705                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 706                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 707                  UVD_CGC_CTRL__SYS_MODE_MASK |
 708                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 709                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 710                  UVD_CGC_CTRL__REGS_MODE_MASK |
 711                  UVD_CGC_CTRL__RBC_MODE_MASK |
 712                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 713                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 714                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 715                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 716                  UVD_CGC_CTRL__MPC_MODE_MASK |
 717                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 718                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 719                  UVD_CGC_CTRL__WCB_MODE_MASK |
 720                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 721         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 722                 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 723
 724         /* turn off clock gating */
 725         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 726                 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
 727
 728         /* turn on SUVD clock gating */
 729         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 730                 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 731
 732         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 733         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 734                 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 735 }
 736
 737 /**
 738  * vcn_v4_0_enable_clock_gating - enable VCN clock gating
 739  *
 740  * @adev: amdgpu_device pointer
 741  * @inst: instance number
 742  *
 743  * Enable clock gating for VCN block
 744  */
 745 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
 746 {
 747         uint32_t data;
 748
 749         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 750                 return;
 751
 752         /* enable VCN CGC */
 753         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 754         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 755         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 756         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 757         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 758
 759         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 760         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 761                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 762                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 763                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 764                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 765                 | UVD_CGC_CTRL__SYS_MODE_MASK
 766                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 767                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 768                 | UVD_CGC_CTRL__REGS_MODE_MASK
 769                 | UVD_CGC_CTRL__RBC_MODE_MASK
 770                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 771                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 772                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 773                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 774                 | UVD_CGC_CTRL__MPC_MODE_MASK
 775                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 776                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 777                 | UVD_CGC_CTRL__WCB_MODE_MASK
 778                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 779                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 780         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 781
 782         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 783         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 784                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 785                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 786                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 787                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 788                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 789                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 790                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 791                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 792                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 793         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 794
 795         return;
 796 }
 797
 798 /**
 799  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
 800  *
 801  * @adev: amdgpu_device pointer
 802  * @inst_idx: instance number index
 803  * @indirect: indirectly write sram
 804  *
 805  * Start VCN block with dpg mode
 806  */
 807 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 808 {
 809         volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 810         struct amdgpu_ring *ring;
 811         uint32_t tmp;
 812
 813         /* disable register anti-hang mechanism */
 814         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
 815                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 816         /* enable dynamic power gating mode */
 817         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
 818         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 819         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 820         WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
 821
 822         if (indirect)
 823                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 824
 825         /* enable clock gating */
 826         vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 827
 828         /* enable VCPU clock */
 829         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 830         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
 831         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 832                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 833
 834         /* disable master interupt */
 835         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 836                 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
 837
 838         /* setup regUVD_LMI_CTRL */
 839         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 840                 UVD_LMI_CTRL__REQ_MODE_MASK |
 841                 UVD_LMI_CTRL__CRC_RESET_MASK |
 842                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 843                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 844                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 845                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 846                 0x00100000L);
 847         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 848                 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
 849
 850         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 851                 VCN, inst_idx, regUVD_MPC_CNTL),
 852                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 853
 854         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 855                 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
 856                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 857                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 858                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 859                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 860
 861         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 862                 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
 863                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 864                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 865                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 866                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 867
 868         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 869                 VCN, inst_idx, regUVD_MPC_SET_MUX),
 870                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 871                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 872                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 873
 874         vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
 875
 876         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 877         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 878         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 879                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 880
 881         /* enable LMI MC and UMC channels */
 882         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
 883         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 884                 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
 885
 886         /* enable master interrupt */
 887         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 888                 VCN, inst_idx, regUVD_MASTINT_EN),
 889                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 890
 891
 892         if (indirect)
 893                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
 894                         (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 895                                 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 896
 897         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 898
 899         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
 900         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 901         WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
 902
 903         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
 904         tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 905         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
 906         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
 907         WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
 908         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
 909
 910         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
 911         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
 912         ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 913
 914         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
 915         tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
 916         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
 917         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 918
 919         WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
 920                         ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
 921                         VCN_RB1_DB_CTRL__EN_MASK);
 922
 923         return 0;
 924 }
 925
 926
 927 /**
 928  * vcn_v4_0_start - VCN start
 929  *
 930  * @adev: amdgpu_device pointer
 931  *
 932  * Start VCN block
 933  */
 934 static int vcn_v4_0_start(struct amdgpu_device *adev)
 935 {
 936         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 937         struct amdgpu_ring *ring;
 938         uint32_t tmp;
 939         int i, j, k, r;
 940
 941         if (adev->pm.dpm_enabled)
 942                 amdgpu_dpm_enable_uvd(adev, true);
 943
 944         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 945                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 946
 947                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 948                         r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 949                         continue;
 950                 }
 951
 952                 /* disable VCN power gating */
 953                 vcn_v4_0_disable_static_power_gating(adev, i);
 954
 955                 /* set VCN status busy */
 956                 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 957                 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
 958
 959                 /*SW clock gating */
 960                 vcn_v4_0_disable_clock_gating(adev, i);
 961
 962                 /* enable VCPU clock */
 963                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
 964                                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 965
 966                 /* disable master interrupt */
 967                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
 968                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 969
 970                 /* enable LMI MC and UMC channels */
 971                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
 972                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 973
 974                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
 975                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 976                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 977                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
 978
 979                 /* setup regUVD_LMI_CTRL */
 980                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
 981                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
 982                                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 983                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 984                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 985                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 986
 987                 /* setup regUVD_MPC_CNTL */
 988                 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
 989                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 990                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 991                 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
 992
 993                 /* setup UVD_MPC_SET_MUXA0 */
 994                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
 995                                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 996                                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 997                                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 998                                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 999
1000                 /* setup UVD_MPC_SET_MUXB0 */
1001                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1002                                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1003                                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1004                                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1005                                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1006
1007                 /* setup UVD_MPC_SET_MUX */
1008                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1009                                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1010                                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1011                                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1012
1013                 vcn_v4_0_mc_resume(adev, i);
1014
1015                 /* VCN global tiling registers */
1016                 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1017                                 adev->gfx.config.gb_addr_config);
1018
1019                 /* unblock VCPU register access */
1020                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1021                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1022
1023                 /* release VCPU reset to boot */
1024                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1025                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1026
1027                 for (j = 0; j < 10; ++j) {
1028                         uint32_t status;
1029
1030                         for (k = 0; k < 100; ++k) {
1031                                 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1032                                 if (status & 2)
1033                                         break;
1034                                 mdelay(10);
1035                                 if (amdgpu_emu_mode==1)
1036                                         msleep(1);
1037                         }
1038
1039                         if (amdgpu_emu_mode==1) {
1040                                 if (status & 2) {
1041                                         r = 0;
1042                                         break;
1043                                 }
1044                         } else {
1045                                 r = 0;
1046                                 if (status & 2)
1047                                         break;
1048
1049                                 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
1050                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1051                                                         UVD_VCPU_CNTL__BLK_RST_MASK,
1052                                                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1053                                 mdelay(10);
1054                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1055                                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1056
1057                                 mdelay(10);
1058                                 r = -1;
1059                         }
1060                 }
1061
1062                 if (r) {
1063                         dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1064                         return r;
1065                 }
1066
1067                 /* enable master interrupt */
1068                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1069                                 UVD_MASTINT_EN__VCPU_EN_MASK,
1070                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1071
1072                 /* clear the busy bit of VCN_STATUS */
1073                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1074                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1075
1076                 ring = &adev->vcn.inst[i].ring_enc[0];
1077                 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1078                                 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1079                                 VCN_RB1_DB_CTRL__EN_MASK);
1080
1081                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1082                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1083                 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1084
1085                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1086                 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1087                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1088                 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1089                 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1090                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1091
1092                 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1093                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1094                 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1095
1096                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1097                 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1098                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1099                 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1100         }
1101
1102         return 0;
1103 }
1104
1105 /**
1106  * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1107  *
1108  * @adev: amdgpu_device pointer
1109  * @inst_idx: instance number index
1110  *
1111  * Stop VCN block with dpg mode
1112  */
1113 static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1114 {
1115         uint32_t tmp;
1116
1117         /* Wait for power status to be 1 */
1118         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1119                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1120
1121         /* wait for read ptr to be equal to write ptr */
1122         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1123         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1124
1125         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1126                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1127
1128         /* disable dynamic power gating mode */
1129         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1130                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1131         return 0;
1132 }
1133
1134 /**
1135  * vcn_v4_0_stop - VCN stop
1136  *
1137  * @adev: amdgpu_device pointer
1138  *
1139  * Stop VCN block
1140  */
1141 static int vcn_v4_0_stop(struct amdgpu_device *adev)
1142 {
1143         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1144         uint32_t tmp;
1145         int i, r = 0;
1146
1147         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1148                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1149                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1150
1151                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1152                         r = vcn_v4_0_stop_dpg_mode(adev, i);
1153                         continue;
1154                 }
1155
1156                 /* wait for vcn idle */
1157                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1158                 if (r)
1159                         return r;
1160
1161                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1162                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1163                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1164                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1165                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1166                 if (r)
1167                         return r;
1168
1169                 /* disable LMI UMC channel */
1170                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1171                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1172                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1173                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1174                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1175                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1176                 if (r)
1177                         return r;
1178
1179                 /* block VCPU register access */
1180                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1181                                 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1182                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1183
1184                 /* reset VCPU */
1185                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1186                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1187                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1188
1189                 /* disable VCPU clock */
1190                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1191                                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1192
1193                 /* apply soft reset */
1194                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1195                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1196                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1197                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1198                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1199                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1200
1201                 /* clear status */
1202                 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1203
1204                 /* apply HW clock gating */
1205                 vcn_v4_0_enable_clock_gating(adev, i);
1206
1207                 /* enable VCN power gating */
1208                 vcn_v4_0_enable_static_power_gating(adev, i);
1209         }
1210
1211         if (adev->pm.dpm_enabled)
1212                 amdgpu_dpm_enable_uvd(adev, false);
1213
1214         return 0;
1215 }
1216
1217 /**
1218  * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
1219  *
1220  * @adev: amdgpu_device pointer
1221  * @inst_idx: instance number index
1222  * @new_state: pause state
1223  *
1224  * Pause dpg mode for VCN block
1225  */
1226 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1227       struct dpg_pause_state *new_state)
1228 {
1229         uint32_t reg_data = 0;
1230         int ret_code;
1231
1232         /* pause/unpause if state is changed */
1233         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1234                 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1235                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1236                 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1237                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1238
1239                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1240                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1241                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1242
1243                         if (!ret_code) {
1244                                 /* pause DPG */
1245                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1246                                 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1247
1248                                 /* wait for ACK */
1249                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1250                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1251                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1252
1253                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1254                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1255                         }
1256                 } else {
1257                         /* unpause dpg, no need to wait */
1258                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1259                         WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1260                 }
1261                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1262         }
1263
1264         return 0;
1265 }
1266
1267 /**
1268  * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
1269  *
1270  * @ring: amdgpu_ring pointer
1271  *
1272  * Returns the current hardware unified read pointer
1273  */
1274 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
1275 {
1276         struct amdgpu_device *adev = ring->adev;
1277
1278         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1279                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1280
1281         return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1282 }
1283
1284 /**
1285  * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
1286  *
1287  * @ring: amdgpu_ring pointer
1288  *
1289  * Returns the current hardware unified write pointer
1290  */
1291 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
1292 {
1293         struct amdgpu_device *adev = ring->adev;
1294
1295         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1296                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1297
1298         if (ring->use_doorbell)
1299                 return *ring->wptr_cpu_addr;
1300         else
1301                 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1302 }
1303
1304 /**
1305  * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
1306  *
1307  * @ring: amdgpu_ring pointer
1308  *
1309  * Commits the enc write pointer to the hardware
1310  */
1311 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
1312 {
1313         struct amdgpu_device *adev = ring->adev;
1314
1315         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1316                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1317
1318         if (ring->use_doorbell) {
1319                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1320                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1321         } else {
1322                 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1323         }
1324 }
1325
1326 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
1327         .type = AMDGPU_RING_TYPE_VCN_ENC,
1328         .align_mask = 0x3f,
1329         .nop = VCN_ENC_CMD_NO_OP,
1330         .vmhub = AMDGPU_MMHUB_0,
1331         .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1332         .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1333         .set_wptr = vcn_v4_0_unified_ring_set_wptr,
1334         .emit_frame_size =
1335                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1336                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1337                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1338                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1339                 1, /* vcn_v2_0_enc_ring_insert_end */
1340         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1341         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1342         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1343         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1344         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1345         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1346         .insert_nop = amdgpu_ring_insert_nop,
1347         .insert_end = vcn_v2_0_enc_ring_insert_end,
1348         .pad_ib = amdgpu_ring_generic_pad_ib,
1349         .begin_use = amdgpu_vcn_ring_begin_use,
1350         .end_use = amdgpu_vcn_ring_end_use,
1351         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1352         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1353         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1354 };
1355
1356 /**
1357  * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
1358  *
1359  * @adev: amdgpu_device pointer
1360  *
1361  * Set unified ring functions
1362  */
1363 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
1364 {
1365         int i;
1366
1367         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1368                 if (adev->vcn.harvest_config & (1 << i))
1369                         continue;
1370
1371                 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs;
1372                 adev->vcn.inst[i].ring_enc[0].me = i;
1373
1374                 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
1375         }
1376 }
1377
1378 /**
1379  * vcn_v4_0_is_idle - check VCN block is idle
1380  *
1381  * @handle: amdgpu_device pointer
1382  *
1383  * Check whether VCN block is idle
1384  */
1385 static bool vcn_v4_0_is_idle(void *handle)
1386 {
1387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1388         int i, ret = 1;
1389
1390         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1391                 if (adev->vcn.harvest_config & (1 << i))
1392                         continue;
1393
1394                 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1395         }
1396
1397         return ret;
1398 }
1399
1400 /**
1401  * vcn_v4_0_wait_for_idle - wait for VCN block idle
1402  *
1403  * @handle: amdgpu_device pointer
1404  *
1405  * Wait for VCN block idle
1406  */
1407 static int vcn_v4_0_wait_for_idle(void *handle)
1408 {
1409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410         int i, ret = 0;
1411
1412         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1413                 if (adev->vcn.harvest_config & (1 << i))
1414                         continue;
1415
1416                 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1417                         UVD_STATUS__IDLE);
1418                 if (ret)
1419                         return ret;
1420         }
1421
1422         return ret;
1423 }
1424
1425 /**
1426  * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
1427  *
1428  * @handle: amdgpu_device pointer
1429  * @state: clock gating state
1430  *
1431  * Set VCN block clockgating state
1432  */
1433 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
1434 {
1435         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1436         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1437         int i;
1438
1439         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1440                 if (adev->vcn.harvest_config & (1 << i))
1441                         continue;
1442
1443                 if (enable) {
1444                         if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
1445                                 return -EBUSY;
1446                         vcn_v4_0_enable_clock_gating(adev, i);
1447                 } else {
1448                         vcn_v4_0_disable_clock_gating(adev, i);
1449                 }
1450         }
1451
1452         return 0;
1453 }
1454
1455 /**
1456  * vcn_v4_0_set_powergating_state - set VCN block powergating state
1457  *
1458  * @handle: amdgpu_device pointer
1459  * @state: power gating state
1460  *
1461  * Set VCN block powergating state
1462  */
1463 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
1464 {
1465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1466         int ret;
1467
1468         if(state == adev->vcn.cur_state)
1469                 return 0;
1470
1471         if (state == AMD_PG_STATE_GATE)
1472                 ret = vcn_v4_0_stop(adev);
1473         else
1474                 ret = vcn_v4_0_start(adev);
1475
1476         if(!ret)
1477                 adev->vcn.cur_state = state;
1478
1479         return ret;
1480 }
1481
1482 /**
1483  * vcn_v4_0_set_interrupt_state - set VCN block interrupt state
1484  *
1485  * @adev: amdgpu_device pointer
1486  * @source: interrupt sources
1487  * @type: interrupt types
1488  * @state: interrupt states
1489  *
1490  * Set VCN block interrupt state
1491  */
1492 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1493       unsigned type, enum amdgpu_interrupt_state state)
1494 {
1495         return 0;
1496 }
1497
1498 /**
1499  * vcn_v4_0_process_interrupt - process VCN block interrupt
1500  *
1501  * @adev: amdgpu_device pointer
1502  * @source: interrupt sources
1503  * @entry: interrupt entry from clients and sources
1504  *
1505  * Process VCN block interrupt
1506  */
1507 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1508       struct amdgpu_iv_entry *entry)
1509 {
1510         uint32_t ip_instance;
1511
1512         switch (entry->client_id) {
1513         case SOC15_IH_CLIENTID_VCN:
1514                 ip_instance = 0;
1515                 break;
1516         case SOC15_IH_CLIENTID_VCN1:
1517                 ip_instance = 1;
1518                 break;
1519         default:
1520                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1521                 return 0;
1522         }
1523
1524         DRM_DEBUG("IH: VCN TRAP\n");
1525
1526         switch (entry->src_id) {
1527         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1528                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1529                 break;
1530         default:
1531                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1532                           entry->src_id, entry->src_data[0]);
1533                 break;
1534         }
1535
1536         return 0;
1537 }
1538
1539 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
1540         .set = vcn_v4_0_set_interrupt_state,
1541         .process = vcn_v4_0_process_interrupt,
1542 };
1543
1544 /**
1545  * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
1546  *
1547  * @adev: amdgpu_device pointer
1548  *
1549  * Set VCN block interrupt irq functions
1550  */
1551 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1552 {
1553         int i;
1554
1555         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1556                 if (adev->vcn.harvest_config & (1 << i))
1557                         continue;
1558
1559                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1560                 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
1561         }
1562 }
1563
1564 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
1565         .name = "vcn_v4_0",
1566         .early_init = vcn_v4_0_early_init,
1567         .late_init = NULL,
1568         .sw_init = vcn_v4_0_sw_init,
1569         .sw_fini = vcn_v4_0_sw_fini,
1570         .hw_init = vcn_v4_0_hw_init,
1571         .hw_fini = vcn_v4_0_hw_fini,
1572         .suspend = vcn_v4_0_suspend,
1573         .resume = vcn_v4_0_resume,
1574         .is_idle = vcn_v4_0_is_idle,
1575         .wait_for_idle = vcn_v4_0_wait_for_idle,
1576         .check_soft_reset = NULL,
1577         .pre_soft_reset = NULL,
1578         .soft_reset = NULL,
1579         .post_soft_reset = NULL,
1580         .set_clockgating_state = vcn_v4_0_set_clockgating_state,
1581         .set_powergating_state = vcn_v4_0_set_powergating_state,
1582 };
1583
1584 const struct amdgpu_ip_block_version vcn_v4_0_ip_block =
1585 {
1586         .type = AMD_IP_BLOCK_TYPE_VCN,
1587         .major = 4,
1588         .minor = 0,
1589         .rev = 0,
1590         .funcs = &vcn_v4_0_ip_funcs,
1591 };