drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_psp.h"
  25 #include "amdgpu_ucode.h"
  26 #include "soc15_common.h"
  27 #include "psp_v13_0.h"
  28
  29 #include "mp/mp_13_0_2_offset.h"
  30 #include "mp/mp_13_0_2_sh_mask.h"
  31
  32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  34 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  35 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  36 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  37 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  45
  46 /* For large FW files the time to complete can be very long */
  47 #define USBC_PD_POLLING_LIMIT_S 240
  48
  49 /* Read USB-PD from LFB */
  50 #define GFX_CMD_USB_PD_USE_LFB 0x480
  51
  52 /* VBIOS gfl defines */
  53 #define MBOX_READY_MASK 0x80000000
  54 #define MBOX_STATUS_MASK 0x0000FFFF
  55 #define MBOX_COMMAND_MASK 0x00FF0000
  56 #define MBOX_READY_FLAG 0x80000000
  57 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  58 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  59 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  60
  61 static int psp_v13_0_init_microcode(struct psp_context *psp)
  62 {
  63         struct amdgpu_device *adev = psp->adev;
  64         const char *chip_name;
  65         char ucode_prefix[30];
  66         int err = 0;
  67
  68         switch (adev->ip_versions[MP0_HWIP][0]) {
  69         case IP_VERSION(13, 0, 2):
  70                 chip_name = "aldebaran";
  71                 break;
  72         case IP_VERSION(13, 0, 1):
  73         case IP_VERSION(13, 0, 3):
  74                 chip_name = "yellow_carp";
  75                 break;
  76         default:
  77                 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  78                 chip_name = ucode_prefix;
  79                 break;
  80         }
  81
  82         switch (adev->ip_versions[MP0_HWIP][0]) {
  83         case IP_VERSION(13, 0, 2):
  84                 err = psp_init_sos_microcode(psp, chip_name);
  85                 if (err)
  86                         return err;
  87                 /* It's not necessary to load ras ta on Guest side */
  88                 if (!amdgpu_sriov_vf(adev)) {
  89                         err = psp_init_ta_microcode(&adev->psp, chip_name);
  90                         if (err)
  91                                 return err;
  92                 }
  93                 break;
  94         case IP_VERSION(13, 0, 1):
  95         case IP_VERSION(13, 0, 3):
  96         case IP_VERSION(13, 0, 5):
  97         case IP_VERSION(13, 0, 8):
  98                 err = psp_init_toc_microcode(psp, chip_name);
  99                 if (err)
 100                         return err;
 101                 err = psp_init_ta_microcode(psp, chip_name);
 102                 if (err)
 103                         return err;
 104                 break;
 105         case IP_VERSION(13, 0, 0):
 106         case IP_VERSION(13, 0, 7):
 107                 err = psp_init_sos_microcode(psp, chip_name);
 108                 if (err)
 109                         return err;
 110                 /* It's not necessary to load ras ta on Guest side */
 111                 err = psp_init_ta_microcode(psp, chip_name);
 112                 if (err)
 113                         return err;
 114                 break;
 115         default:
 116                 BUG();
 117         }
 118
 119         return 0;
 120 }
 121
 122 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 123 {
 124         struct amdgpu_device *adev = psp->adev;
 125         uint32_t sol_reg;
 126
 127         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 128
 129         return sol_reg != 0x0;
 130 }
 131
 132 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 133 {
 134         struct amdgpu_device *adev = psp->adev;
 135
 136         int ret;
 137         int retry_loop;
 138
 139         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 140                 /* Wait for bootloader to signify that is
 141                     ready having bit 31 of C2PMSG_35 set to 1 */
 142                 ret = psp_wait_for(psp,
 143                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 144                                    0x80000000,
 145                                    0x80000000,
 146                                    false);
 147
 148                 if (ret == 0)
 149                         return 0;
 150         }
 151
 152         return ret;
 153 }
 154
 155 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 156                                                struct psp_bin_desc      *bin_desc,
 157                                                enum psp_bootloader_cmd  bl_cmd)
 158 {
 159         int ret;
 160         uint32_t psp_gfxdrv_command_reg = 0;
 161         struct amdgpu_device *adev = psp->adev;
 162
 163         /* Check tOS sign of life register to confirm sys driver and sOS
 164          * are already been loaded.
 165          */
 166         if (psp_v13_0_is_sos_alive(psp))
 167                 return 0;
 168
 169         ret = psp_v13_0_wait_for_bootloader(psp);
 170         if (ret)
 171                 return ret;
 172
 173         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 174
 175         /* Copy PSP KDB binary to memory */
 176         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 177
 178         /* Provide the PSP KDB to bootloader */
 179         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 180                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 181         psp_gfxdrv_command_reg = bl_cmd;
 182         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 183                psp_gfxdrv_command_reg);
 184
 185         ret = psp_v13_0_wait_for_bootloader(psp);
 186
 187         return ret;
 188 }
 189
 190 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 191 {
 192         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 193 }
 194
 195 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 196 {
 197         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 198 }
 199
 200 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 201 {
 202         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 203 }
 204
 205 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 206 {
 207         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 208 }
 209
 210 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 211 {
 212         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 213 }
 214
 215 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 216 {
 217         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 218 }
 219
 220 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 221 {
 222         int ret;
 223         unsigned int psp_gfxdrv_command_reg = 0;
 224         struct amdgpu_device *adev = psp->adev;
 225
 226         /* Check sOS sign of life register to confirm sys driver and sOS
 227          * are already been loaded.
 228          */
 229         if (psp_v13_0_is_sos_alive(psp))
 230                 return 0;
 231
 232         ret = psp_v13_0_wait_for_bootloader(psp);
 233         if (ret)
 234                 return ret;
 235
 236         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 237
 238         /* Copy Secure OS binary to PSP memory */
 239         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 240
 241         /* Provide the PSP secure OS to bootloader */
 242         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 243                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 244         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 245         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 246                psp_gfxdrv_command_reg);
 247
 248         /* there might be handshake issue with hardware which needs delay */
 249         mdelay(20);
 250         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 251                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 252                            0, true);
 253
 254         return ret;
 255 }
 256
 257 static int psp_v13_0_ring_init(struct psp_context *psp,
 258                               enum psp_ring_type ring_type)
 259 {
 260         int ret = 0;
 261         struct psp_ring *ring;
 262         struct amdgpu_device *adev = psp->adev;
 263
 264         ring = &psp->km_ring;
 265
 266         ring->ring_type = ring_type;
 267
 268         /* allocate 4k Page of Local Frame Buffer memory for ring */
 269         ring->ring_size = 0x1000;
 270         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 271                                       AMDGPU_GEM_DOMAIN_VRAM,
 272                                       &adev->firmware.rbuf,
 273                                       &ring->ring_mem_mc_addr,
 274                                       (void **)&ring->ring_mem);
 275         if (ret) {
 276                 ring->ring_size = 0;
 277                 return ret;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int psp_v13_0_ring_stop(struct psp_context *psp,
 284                                enum psp_ring_type ring_type)
 285 {
 286         int ret = 0;
 287         struct amdgpu_device *adev = psp->adev;
 288
 289         if (amdgpu_sriov_vf(adev)) {
 290                 /* Write the ring destroy command*/
 291                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 292                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 293                 /* there might be handshake issue with hardware which needs delay */
 294                 mdelay(20);
 295                 /* Wait for response flag (bit 31) */
 296                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 297                                    0x80000000, 0x80000000, false);
 298         } else {
 299                 /* Write the ring destroy command*/
 300                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 301                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 302                 /* there might be handshake issue with hardware which needs delay */
 303                 mdelay(20);
 304                 /* Wait for response flag (bit 31) */
 305                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 306                                    0x80000000, 0x80000000, false);
 307         }
 308
 309         return ret;
 310 }
 311
 312 static int psp_v13_0_ring_create(struct psp_context *psp,
 313                                  enum psp_ring_type ring_type)
 314 {
 315         int ret = 0;
 316         unsigned int psp_ring_reg = 0;
 317         struct psp_ring *ring = &psp->km_ring;
 318         struct amdgpu_device *adev = psp->adev;
 319
 320         if (amdgpu_sriov_vf(adev)) {
 321                 ret = psp_v13_0_ring_stop(psp, ring_type);
 322                 if (ret) {
 323                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 324                         return ret;
 325                 }
 326
 327                 /* Write low address of the ring to C2PMSG_102 */
 328                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 329                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 330                 /* Write high address of the ring to C2PMSG_103 */
 331                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 332                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 333
 334                 /* Write the ring initialization command to C2PMSG_101 */
 335                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 336                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 337
 338                 /* there might be handshake issue with hardware which needs delay */
 339                 mdelay(20);
 340
 341                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 342                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 343                                    0x80000000, 0x8000FFFF, false);
 344
 345         } else {
 346                 /* Wait for sOS ready for ring creation */
 347                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 348                                    0x80000000, 0x80000000, false);
 349                 if (ret) {
 350                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 351                         return ret;
 352                 }
 353
 354                 /* Write low address of the ring to C2PMSG_69 */
 355                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 356                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 357                 /* Write high address of the ring to C2PMSG_70 */
 358                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 359                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 360                 /* Write size of ring to C2PMSG_71 */
 361                 psp_ring_reg = ring->ring_size;
 362                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 363                 /* Write the ring initialization command to C2PMSG_64 */
 364                 psp_ring_reg = ring_type;
 365                 psp_ring_reg = psp_ring_reg << 16;
 366                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 367
 368                 /* there might be handshake issue with hardware which needs delay */
 369                 mdelay(20);
 370
 371                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 372                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 373                                    0x80000000, 0x8000FFFF, false);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 380                                   enum psp_ring_type ring_type)
 381 {
 382         int ret = 0;
 383         struct psp_ring *ring = &psp->km_ring;
 384         struct amdgpu_device *adev = psp->adev;
 385
 386         ret = psp_v13_0_ring_stop(psp, ring_type);
 387         if (ret)
 388                 DRM_ERROR("Fail to stop psp ring\n");
 389
 390         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 391                               &ring->ring_mem_mc_addr,
 392                               (void **)&ring->ring_mem);
 393
 394         return ret;
 395 }
 396
 397 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 398 {
 399         uint32_t data;
 400         struct amdgpu_device *adev = psp->adev;
 401
 402         if (amdgpu_sriov_vf(adev))
 403                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 404         else
 405                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 406
 407         return data;
 408 }
 409
 410 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 411 {
 412         struct amdgpu_device *adev = psp->adev;
 413
 414         if (amdgpu_sriov_vf(adev)) {
 415                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 416                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 417                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 418         } else
 419                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 420 }
 421
 422 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 423 {
 424         struct amdgpu_device *adev = psp->adev;
 425         uint32_t reg_status;
 426         int ret, i = 0;
 427
 428         /*
 429          * LFB address which is aligned to 1MB address and has to be
 430          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 431          * register
 432          */
 433         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 434
 435         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 436                              0x80000000, 0x80000000, false);
 437         if (ret)
 438                 return ret;
 439
 440         /* Fireup interrupt so PSP can pick up the address */
 441         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 442
 443         /* FW load takes very long time */
 444         do {
 445                 msleep(1000);
 446                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 447
 448                 if (reg_status & 0x80000000)
 449                         goto done;
 450
 451         } while (++i < USBC_PD_POLLING_LIMIT_S);
 452
 453         return -ETIME;
 454 done:
 455
 456         if ((reg_status & 0xFFFF) != 0) {
 457                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 458                                 reg_status & 0xFFFF);
 459                 return -EIO;
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 466 {
 467         struct amdgpu_device *adev = psp->adev;
 468         int ret;
 469
 470         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 471
 472         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 473                                      0x80000000, 0x80000000, false);
 474         if (!ret)
 475                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 476
 477         return ret;
 478 }
 479
 480 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 481 {
 482         uint32_t reg_status = 0, reg_val = 0;
 483         struct amdgpu_device *adev = psp->adev;
 484         int ret;
 485
 486         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 487         reg_val |= (cmd << 16);
 488         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 489
 490         /* Ring the doorbell */
 491         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 492
 493         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 494                 return 0;
 495
 496         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 497                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 498         if (ret) {
 499                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 500                 return ret;
 501         }
 502
 503         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 504         if ((reg_status & 0xFFFF) != 0) {
 505                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 506                                 cmd, reg_status & 0xFFFF);
 507                 return -EIO;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int psp_v13_0_update_spirom(struct psp_context *psp,
 514                                    uint64_t fw_pri_mc_addr)
 515 {
 516         struct amdgpu_device *adev = psp->adev;
 517         int ret;
 518
 519         /* Confirm PSP is ready to start */
 520         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 521                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 522         if (ret) {
 523                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 524                 return ret;
 525         }
 526
 527         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 528
 529         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 530         if (ret)
 531                 return ret;
 532
 533         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 534
 535         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 536         if (ret)
 537                 return ret;
 538
 539         psp->vbflash_done = true;
 540
 541         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 542         if (ret)
 543                 return ret;
 544
 545         return 0;
 546 }
 547
 548 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 549 {
 550         struct amdgpu_device *adev = psp->adev;
 551
 552         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 553 }
 554
 555 static const struct psp_funcs psp_v13_0_funcs = {
 556         .init_microcode = psp_v13_0_init_microcode,
 557         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 558         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 559         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 560         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 561         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 562         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 563         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 564         .ring_init = psp_v13_0_ring_init,
 565         .ring_create = psp_v13_0_ring_create,
 566         .ring_stop = psp_v13_0_ring_stop,
 567         .ring_destroy = psp_v13_0_ring_destroy,
 568         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 569         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 570         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 571         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 572         .update_spirom = psp_v13_0_update_spirom,
 573         .vbflash_stat = psp_v13_0_vbflash_status
 574 };
 575
 576 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 577 {
 578         psp->funcs = &psp_v13_0_funcs;
 579 }