drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_VCN_H__
  25 #define __AMDGPU_VCN_H__
  26
  27 #include "amdgpu_ras.h"
  28
  29 #define AMDGPU_VCN_STACK_SIZE           (128*1024)
  30 #define AMDGPU_VCN_CONTEXT_SIZE         (512*1024)
  31
  32 #define AMDGPU_VCN_FIRMWARE_OFFSET      256
  33 #define AMDGPU_VCN_MAX_ENC_RINGS        3
  34
  35 #define AMDGPU_MAX_VCN_INSTANCES        2
  36 #define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
  37
  38 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
  39 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
  40
  41 #define VCN_DEC_KMD_CMD                 0x80000000
  42 #define VCN_DEC_CMD_FENCE               0x00000000
  43 #define VCN_DEC_CMD_TRAP                0x00000001
  44 #define VCN_DEC_CMD_WRITE_REG           0x00000004
  45 #define VCN_DEC_CMD_REG_READ_COND_WAIT  0x00000006
  46 #define VCN_DEC_CMD_PACKET_START        0x0000000a
  47 #define VCN_DEC_CMD_PACKET_END          0x0000000b
  48
  49 #define VCN_DEC_SW_CMD_NO_OP            0x00000000
  50 #define VCN_DEC_SW_CMD_END              0x00000001
  51 #define VCN_DEC_SW_CMD_IB               0x00000002
  52 #define VCN_DEC_SW_CMD_FENCE            0x00000003
  53 #define VCN_DEC_SW_CMD_TRAP             0x00000004
  54 #define VCN_DEC_SW_CMD_IB_AUTO          0x00000005
  55 #define VCN_DEC_SW_CMD_SEMAPHORE        0x00000006
  56 #define VCN_DEC_SW_CMD_PREEMPT_FENCE    0x00000009
  57 #define VCN_DEC_SW_CMD_REG_WRITE        0x0000000b
  58 #define VCN_DEC_SW_CMD_REG_WAIT         0x0000000c
  59
  60 #define VCN_ENC_CMD_NO_OP               0x00000000
  61 #define VCN_ENC_CMD_END                 0x00000001
  62 #define VCN_ENC_CMD_IB                  0x00000002
  63 #define VCN_ENC_CMD_FENCE               0x00000003
  64 #define VCN_ENC_CMD_TRAP                0x00000004
  65 #define VCN_ENC_CMD_REG_WRITE           0x0000000b
  66 #define VCN_ENC_CMD_REG_WAIT            0x0000000c
  67
  68 #define VCN_VID_SOC_ADDRESS_2_0         0x1fa00
  69 #define VCN1_VID_SOC_ADDRESS_3_0        0x48200
  70 #define VCN_AON_SOC_ADDRESS_2_0         0x1f800
  71 #define VCN1_AON_SOC_ADDRESS_3_0        0x48000
  72 #define VCN_VID_IP_ADDRESS_2_0          0x0
  73 #define VCN_AON_IP_ADDRESS_2_0          0x30000
  74
  75 #define mmUVD_RBC_XX_IB_REG_CHECK                                       0x026b
  76 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX                              1
  77 #define mmUVD_REG_XX_MASK                                               0x026c
  78 #define mmUVD_REG_XX_MASK_BASE_IDX                                      1
  79
  80 /* 1 second timeout */
  81 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  82
  83 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel)                    \
  84         ({      WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask);                   \
  85                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL,                           \
  86                         UVD_DPG_LMA_CTL__MASK_EN_MASK |                                 \
  87                         ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg)  \
  88                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
  89                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
  90                 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA);                         \
  91         })
  92
  93 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel)             \
  94         do {                                                                            \
  95                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value);                  \
  96                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask);                   \
  97                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL,                           \
  98                         UVD_DPG_LMA_CTL__READ_WRITE_MASK |                              \
  99                         ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg)  \
 100                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
 101                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
 102         } while (0)
 103
 104 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg)                                                \
 105         ({                                                                                      \
 106                 uint32_t internal_reg_offset, addr;                                             \
 107                 bool video_range, video1_range, aon_range, aon1_range;                          \
 108                                                                                                 \
 109                 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);           \
 110                 addr <<= 2;                                                                     \
 111                 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) &&              \
 112                                 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));    \
 113                 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) &&            \
 114                                 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600)))));   \
 115                 aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) &&              \
 116                                 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));     \
 117                 aon1_range   = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) &&            \
 118                                 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600)))));    \
 119                 if (video_range)                                                                \
 120                         internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) +   \
 121                                 (VCN_VID_IP_ADDRESS_2_0));                                      \
 122                 else if (aon_range)                                                             \
 123                         internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) +   \
 124                                 (VCN_AON_IP_ADDRESS_2_0));                                      \
 125                 else if (video1_range)                                                          \
 126                         internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) +  \
 127                                 (VCN_VID_IP_ADDRESS_2_0));                                      \
 128                 else if (aon1_range)                                                            \
 129                         internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) +  \
 130                                 (VCN_AON_IP_ADDRESS_2_0));                                      \
 131                 else                                                                            \
 132                         internal_reg_offset = (0xFFFFF & addr);                                 \
 133                                                                                                 \
 134                 internal_reg_offset >>= 2;                                                      \
 135         })
 136
 137 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en)                                        \
 138         ({                                                                                      \
 139                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,                                  \
 140                         (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                            \
 141                         mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                            \
 142                         offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));                    \
 143                 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);                                \
 144         })
 145
 146 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect)                       \
 147         do {                                                                                    \
 148                 if (!indirect) {                                                                \
 149                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value);                 \
 150                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,                          \
 151                                 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                    \
 152                                  mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                   \
 153                                  offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));           \
 154                 } else {                                                                        \
 155                         *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset;                \
 156                         *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value;                 \
 157                 }                                                                               \
 158         } while (0)
 159
 160 #define AMDGPU_VCN_FW_SHARED_FLAG_0_RB  (1 << 6)
 161 #define AMDGPU_VCN_MULTI_QUEUE_FLAG     (1 << 8)
 162 #define AMDGPU_VCN_SW_RING_FLAG         (1 << 9)
 163 #define AMDGPU_VCN_FW_LOGGING_FLAG      (1 << 10)
 164 #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
 165
 166 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER        0x00000001
 167 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER          0x00000001
 168
 169 #define VCN_CODEC_DISABLE_MASK_AV1  (1 << 0)
 170 #define VCN_CODEC_DISABLE_MASK_VP9  (1 << 1)
 171 #define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2)
 172 #define VCN_CODEC_DISABLE_MASK_H264 (1 << 3)
 173
 174 enum fw_queue_mode {
 175         FW_QUEUE_RING_RESET = 1,
 176         FW_QUEUE_DPG_HOLD_OFF = 2,
 177 };
 178
 179 enum engine_status_constants {
 180         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
 181         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
 182         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
 183         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
 184         UVD_STATUS__UVD_BUSY = 0x00000004,
 185         GB_ADDR_CONFIG_DEFAULT = 0x26010011,
 186         UVD_STATUS__IDLE = 0x2,
 187         UVD_STATUS__BUSY = 0x5,
 188         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
 189         UVD_STATUS__RBC_BUSY = 0x1,
 190         UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
 191 };
 192
 193 enum internal_dpg_state {
 194         VCN_DPG_STATE__UNPAUSE = 0,
 195         VCN_DPG_STATE__PAUSE,
 196 };
 197
 198 struct dpg_pause_state {
 199         enum internal_dpg_state fw_based;
 200         enum internal_dpg_state jpeg;
 201 };
 202
 203 struct amdgpu_vcn_reg{
 204         unsigned        data0;
 205         unsigned        data1;
 206         unsigned        cmd;
 207         unsigned        nop;
 208         unsigned        context_id;
 209         unsigned        ib_vmid;
 210         unsigned        ib_bar_low;
 211         unsigned        ib_bar_high;
 212         unsigned        ib_size;
 213         unsigned        gp_scratch8;
 214         unsigned        scratch9;
 215 };
 216
 217 struct amdgpu_vcn_fw_shared {
 218         void        *cpu_addr;
 219         uint64_t    gpu_addr;
 220         uint32_t    mem_size;
 221         uint32_t    log_offset;
 222 };
 223
 224 struct amdgpu_vcn_inst {
 225         struct amdgpu_bo        *vcpu_bo;
 226         void                    *cpu_addr;
 227         uint64_t                gpu_addr;
 228         void                    *saved_bo;
 229         struct amdgpu_ring      ring_dec;
 230         struct amdgpu_ring      ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
 231         atomic_t                sched_score;
 232         struct amdgpu_irq_src   irq;
 233         struct amdgpu_vcn_reg   external;
 234         struct amdgpu_bo        *dpg_sram_bo;
 235         struct dpg_pause_state  pause_state;
 236         void                    *dpg_sram_cpu_addr;
 237         uint64_t                dpg_sram_gpu_addr;
 238         uint32_t                *dpg_sram_curr_addr;
 239         atomic_t                dpg_enc_submission_cnt;
 240         struct amdgpu_vcn_fw_shared fw_shared;
 241 };
 242
 243 struct amdgpu_vcn_ras {
 244         struct amdgpu_ras_block_object ras_block;
 245 };
 246
 247 struct amdgpu_vcn {
 248         unsigned                fw_version;
 249         struct delayed_work     idle_work;
 250         const struct firmware   *fw;    /* VCN firmware */
 251         unsigned                num_enc_rings;
 252         enum amd_powergating_state cur_state;
 253         bool                    indirect_sram;
 254
 255         uint8_t num_vcn_inst;
 256         struct amdgpu_vcn_inst   inst[AMDGPU_MAX_VCN_INSTANCES];
 257         uint8_t                  vcn_config[AMDGPU_MAX_VCN_INSTANCES];
 258         uint32_t                 vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];
 259         struct amdgpu_vcn_reg    internal;
 260         struct mutex             vcn_pg_lock;
 261         struct mutex            vcn1_jpeg1_workaround;
 262         atomic_t                 total_submission_cnt;
 263
 264         unsigned        harvest_config;
 265         int (*pause_dpg_mode)(struct amdgpu_device *adev,
 266                 int inst_idx, struct dpg_pause_state *new_state);
 267
 268         struct ras_common_if    *ras_if;
 269         struct amdgpu_vcn_ras   *ras;
 270 };
 271
 272 struct amdgpu_fw_shared_rb_ptrs_struct {
 273         /* to WA DPG R/W ptr issues.*/
 274         uint32_t  rptr;
 275         uint32_t  wptr;
 276 };
 277
 278 struct amdgpu_fw_shared_multi_queue {
 279         uint8_t decode_queue_mode;
 280         uint8_t encode_generalpurpose_queue_mode;
 281         uint8_t encode_lowlatency_queue_mode;
 282         uint8_t encode_realtime_queue_mode;
 283         uint8_t padding[4];
 284 };
 285
 286 struct amdgpu_fw_shared_sw_ring {
 287         uint8_t is_enabled;
 288         uint8_t padding[3];
 289 };
 290
 291 struct amdgpu_fw_shared_fw_logging {
 292         uint8_t is_enabled;
 293         uint32_t addr_lo;
 294         uint32_t addr_hi;
 295         uint32_t size;
 296 };
 297
 298 struct amdgpu_fw_shared_smu_interface_info {
 299         uint8_t smu_interface_type;
 300         uint8_t padding[3];
 301 };
 302
 303 struct amdgpu_fw_shared {
 304         uint32_t present_flag_0;
 305         uint8_t pad[44];
 306         struct amdgpu_fw_shared_rb_ptrs_struct rb;
 307         uint8_t pad1[1];
 308         struct amdgpu_fw_shared_multi_queue multi_queue;
 309         struct amdgpu_fw_shared_sw_ring sw_ring;
 310         struct amdgpu_fw_shared_fw_logging fw_log;
 311         struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
 312 };
 313
 314 struct amdgpu_vcn_fwlog {
 315         uint32_t rptr;
 316         uint32_t wptr;
 317         uint32_t buffer_size;
 318         uint32_t header_size;
 319         uint8_t wrapped;
 320 };
 321
 322 struct amdgpu_vcn_decode_buffer {
 323         uint32_t valid_buf_flag;
 324         uint32_t msg_buffer_address_hi;
 325         uint32_t msg_buffer_address_lo;
 326         uint32_t pad[30];
 327 };
 328
 329 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
 330 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
 331 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
 332
 333 enum vcn_ring_type {
 334         VCN_ENCODE_RING,
 335         VCN_DECODE_RING,
 336         VCN_UNIFIED_RING,
 337 };
 338
 339 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
 340 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
 341 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
 342 int amdgpu_vcn_resume(struct amdgpu_device *adev);
 343 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
 344 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
 345
 346 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
 347                                 enum vcn_ring_type type, uint32_t vcn_instance);
 348
 349 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 350 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 351 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
 352 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 353
 354 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 355 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 356
 357 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
 358
 359 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
 360
 361 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
 362 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
 363                                    uint8_t i, struct amdgpu_vcn_inst *vcn);
 364 #endif