drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40
  41 #include "amdgpu_ras.h"
  42 #include "amdgpu_securedisplay.h"
  43 #include "amdgpu_atomfirmware.h"
  44
  45 static int psp_sysfs_init(struct amdgpu_device *adev);
  46 static void psp_sysfs_fini(struct amdgpu_device *adev);
  47
  48 static int psp_load_smu_fw(struct psp_context *psp);
  49 static int psp_rap_terminate(struct psp_context *psp);
  50 static int psp_securedisplay_terminate(struct psp_context *psp);
  51
  52 /*
  53  * Due to DF Cstate management centralized to PMFW, the firmware
  54  * loading sequence will be updated as below:
  55  *   - Load KDB
  56  *   - Load SYS_DRV
  57  *   - Load tOS
  58  *   - Load PMFW
  59  *   - Setup TMR
  60  *   - Load other non-psp fw
  61  *   - Load ASD
  62  *   - Load XGMI/RAS/HDCP/DTM TA if any
  63  *
  64  * This new sequence is required for
  65  *   - Arcturus and onwards
  66  */
  67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  68 {
  69         struct amdgpu_device *adev = psp->adev;
  70
  71         if (amdgpu_sriov_vf(adev)) {
  72                 psp->pmfw_centralized_cstate_management = false;
  73                 return;
  74         }
  75
  76         switch (adev->ip_versions[MP0_HWIP][0]) {
  77         case IP_VERSION(11, 0, 0):
  78         case IP_VERSION(11, 0, 4):
  79         case IP_VERSION(11, 0, 5):
  80         case IP_VERSION(11, 0, 7):
  81         case IP_VERSION(11, 0, 9):
  82         case IP_VERSION(11, 0, 11):
  83         case IP_VERSION(11, 0, 12):
  84         case IP_VERSION(11, 0, 13):
  85         case IP_VERSION(13, 0, 2):
  86                 psp->pmfw_centralized_cstate_management = true;
  87                 break;
  88         default:
  89                 psp->pmfw_centralized_cstate_management = false;
  90                 break;
  91         }
  92 }
  93
  94 static int psp_early_init(void *handle)
  95 {
  96         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  97         struct psp_context *psp = &adev->psp;
  98
  99         switch (adev->ip_versions[MP0_HWIP][0]) {
 100         case IP_VERSION(9, 0, 0):
 101                 psp_v3_1_set_psp_funcs(psp);
 102                 psp->autoload_supported = false;
 103                 break;
 104         case IP_VERSION(10, 0, 0):
 105         case IP_VERSION(10, 0, 1):
 106                 psp_v10_0_set_psp_funcs(psp);
 107                 psp->autoload_supported = false;
 108                 break;
 109         case IP_VERSION(11, 0, 2):
 110         case IP_VERSION(11, 0, 4):
 111                 psp_v11_0_set_psp_funcs(psp);
 112                 psp->autoload_supported = false;
 113                 break;
 114         case IP_VERSION(11, 0, 0):
 115         case IP_VERSION(11, 0, 5):
 116         case IP_VERSION(11, 0, 9):
 117         case IP_VERSION(11, 0, 7):
 118         case IP_VERSION(11, 0, 11):
 119         case IP_VERSION(11, 5, 0):
 120         case IP_VERSION(11, 0, 12):
 121         case IP_VERSION(11, 0, 13):
 122                 psp_v11_0_set_psp_funcs(psp);
 123                 psp->autoload_supported = true;
 124                 break;
 125         case IP_VERSION(11, 0, 3):
 126         case IP_VERSION(12, 0, 1):
 127                 psp_v12_0_set_psp_funcs(psp);
 128                 break;
 129         case IP_VERSION(13, 0, 2):
 130                 psp_v13_0_set_psp_funcs(psp);
 131                 break;
 132         case IP_VERSION(13, 0, 1):
 133         case IP_VERSION(13, 0, 3):
 134         case IP_VERSION(13, 0, 5):
 135         case IP_VERSION(13, 0, 8):
 136                 psp_v13_0_set_psp_funcs(psp);
 137                 psp->autoload_supported = true;
 138                 break;
 139         case IP_VERSION(11, 0, 8):
 140                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 141                         psp_v11_0_8_set_psp_funcs(psp);
 142                         psp->autoload_supported = false;
 143                 }
 144                 break;
 145         default:
 146                 return -EINVAL;
 147         }
 148
 149         psp->adev = adev;
 150
 151         psp_check_pmfw_centralized_cstate_management(psp);
 152
 153         return 0;
 154 }
 155
 156 static void psp_memory_training_fini(struct psp_context *psp)
 157 {
 158         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 159
 160         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 161         kfree(ctx->sys_cache);
 162         ctx->sys_cache = NULL;
 163 }
 164
 165 static int psp_memory_training_init(struct psp_context *psp)
 166 {
 167         int ret;
 168         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 169
 170         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 171                 DRM_DEBUG("memory training is not supported!\n");
 172                 return 0;
 173         }
 174
 175         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 176         if (ctx->sys_cache == NULL) {
 177                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 178                 ret = -ENOMEM;
 179                 goto Err_out;
 180         }
 181
 182         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 183                   ctx->train_data_size,
 184                   ctx->p2c_train_data_offset,
 185                   ctx->c2p_train_data_offset);
 186         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 187         return 0;
 188
 189 Err_out:
 190         psp_memory_training_fini(psp);
 191         return ret;
 192 }
 193
 194 /*
 195  * Helper funciton to query psp runtime database entry
 196  *
 197  * @adev: amdgpu_device pointer
 198  * @entry_type: the type of psp runtime database entry
 199  * @db_entry: runtime database entry pointer
 200  *
 201  * Return false if runtime database doesn't exit or entry is invalid
 202  * or true if the specific database entry is found, and copy to @db_entry
 203  */
 204 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 205                                      enum psp_runtime_entry_type entry_type,
 206                                      void *db_entry)
 207 {
 208         uint64_t db_header_pos, db_dir_pos;
 209         struct psp_runtime_data_header db_header = {0};
 210         struct psp_runtime_data_directory db_dir = {0};
 211         bool ret = false;
 212         int i;
 213
 214         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 215         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 216
 217         /* read runtime db header from vram */
 218         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 219                         sizeof(struct psp_runtime_data_header), false);
 220
 221         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 222                 /* runtime db doesn't exist, exit */
 223                 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
 224                 return false;
 225         }
 226
 227         /* read runtime database entry from vram */
 228         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 229                         sizeof(struct psp_runtime_data_directory), false);
 230
 231         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 232                 /* invalid db entry count, exit */
 233                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 234                 return false;
 235         }
 236
 237         /* look up for requested entry type */
 238         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 239                 if (db_dir.entry_list[i].entry_type == entry_type) {
 240                         switch (entry_type) {
 241                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 242                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 243                                         /* invalid db entry size */
 244                                         dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
 245                                         return false;
 246                                 }
 247                                 /* read runtime database entry */
 248                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 249                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 250                                 ret = true;
 251                                 break;
 252                         default:
 253                                 ret = false;
 254                                 break;
 255                         }
 256                 }
 257         }
 258
 259         return ret;
 260 }
 261
 262 static int psp_init_sriov_microcode(struct psp_context *psp)
 263 {
 264         struct amdgpu_device *adev = psp->adev;
 265         int ret = 0;
 266
 267         switch (adev->ip_versions[MP0_HWIP][0]) {
 268         case IP_VERSION(9, 0, 0):
 269                 ret = psp_init_cap_microcode(psp, "vega10");
 270                 break;
 271         case IP_VERSION(11, 0, 9):
 272                 ret = psp_init_cap_microcode(psp, "navi12");
 273                 break;
 274         case IP_VERSION(11, 0, 7):
 275                 ret = psp_init_cap_microcode(psp, "sienna_cichlid");
 276                 break;
 277         case IP_VERSION(13, 0, 2):
 278                 ret = psp_init_cap_microcode(psp, "aldebaran");
 279                 ret &= psp_init_ta_microcode(psp, "aldebaran");
 280                 break;
 281         default:
 282                 BUG();
 283                 break;
 284         }
 285
 286         return ret;
 287 }
 288
 289 static int psp_sw_init(void *handle)
 290 {
 291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 292         struct psp_context *psp = &adev->psp;
 293         int ret;
 294         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 295         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 296
 297         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 298         if (!psp->cmd) {
 299                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 300                 ret = -ENOMEM;
 301         }
 302
 303         if (amdgpu_sriov_vf(adev))
 304                 ret = psp_init_sriov_microcode(psp);
 305         else
 306                 ret = psp_init_microcode(psp);
 307         if (ret) {
 308                 DRM_ERROR("Failed to load psp firmware!\n");
 309                 return ret;
 310         }
 311
 312         adev->psp.xgmi_context.supports_extended_data =
 313                 !adev->gmc.xgmi.connected_to_cpu &&
 314                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 315
 316         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 317         if (psp_get_runtime_db_entry(adev,
 318                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 319                                 &boot_cfg_entry)) {
 320                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 321                 if ((psp->boot_cfg_bitmask) &
 322                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 323                         /* If psp runtime database exists, then
 324                          * only enable two stage memory training
 325                          * when TWO_STAGE_DRAM_TRAINING bit is set
 326                          * in runtime database */
 327                         mem_training_ctx->enable_mem_training = true;
 328                 }
 329
 330         } else {
 331                 /* If psp runtime database doesn't exist or
 332                  * is invalid, force enable two stage memory
 333                  * training */
 334                 mem_training_ctx->enable_mem_training = true;
 335         }
 336
 337         if (mem_training_ctx->enable_mem_training) {
 338                 ret = psp_memory_training_init(psp);
 339                 if (ret) {
 340                         DRM_ERROR("Failed to initialize memory training!\n");
 341                         return ret;
 342                 }
 343
 344                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 345                 if (ret) {
 346                         DRM_ERROR("Failed to process memory training!\n");
 347                         return ret;
 348                 }
 349         }
 350
 351         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 352             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 353                 ret= psp_sysfs_init(adev);
 354                 if (ret) {
 355                         return ret;
 356                 }
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int psp_sw_fini(void *handle)
 363 {
 364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 365         struct psp_context *psp = &adev->psp;
 366         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 367
 368         psp_memory_training_fini(psp);
 369         if (psp->sos_fw) {
 370                 release_firmware(psp->sos_fw);
 371                 psp->sos_fw = NULL;
 372         }
 373         if (psp->asd_fw) {
 374                 release_firmware(psp->asd_fw);
 375                 psp->asd_fw = NULL;
 376         }
 377         if (psp->ta_fw) {
 378                 release_firmware(psp->ta_fw);
 379                 psp->ta_fw = NULL;
 380         }
 381         if (adev->psp.cap_fw) {
 382                 release_firmware(psp->cap_fw);
 383                 psp->cap_fw = NULL;
 384         }
 385
 386         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 387             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 388                 psp_sysfs_fini(adev);
 389
 390         kfree(cmd);
 391         cmd = NULL;
 392
 393         return 0;
 394 }
 395
 396 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 397                  uint32_t reg_val, uint32_t mask, bool check_changed)
 398 {
 399         uint32_t val;
 400         int i;
 401         struct amdgpu_device *adev = psp->adev;
 402
 403         if (psp->adev->no_hw_access)
 404                 return 0;
 405
 406         for (i = 0; i < adev->usec_timeout; i++) {
 407                 val = RREG32(reg_index);
 408                 if (check_changed) {
 409                         if (val != reg_val)
 410                                 return 0;
 411                 } else {
 412                         if ((val & mask) == reg_val)
 413                                 return 0;
 414                 }
 415                 udelay(1);
 416         }
 417
 418         return -ETIME;
 419 }
 420
 421 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 422 {
 423         switch (cmd_id) {
 424         case GFX_CMD_ID_LOAD_TA:
 425                 return "LOAD_TA";
 426         case GFX_CMD_ID_UNLOAD_TA:
 427                 return "UNLOAD_TA";
 428         case GFX_CMD_ID_INVOKE_CMD:
 429                 return "INVOKE_CMD";
 430         case GFX_CMD_ID_LOAD_ASD:
 431                 return "LOAD_ASD";
 432         case GFX_CMD_ID_SETUP_TMR:
 433                 return "SETUP_TMR";
 434         case GFX_CMD_ID_LOAD_IP_FW:
 435                 return "LOAD_IP_FW";
 436         case GFX_CMD_ID_DESTROY_TMR:
 437                 return "DESTROY_TMR";
 438         case GFX_CMD_ID_SAVE_RESTORE:
 439                 return "SAVE_RESTORE_IP_FW";
 440         case GFX_CMD_ID_SETUP_VMR:
 441                 return "SETUP_VMR";
 442         case GFX_CMD_ID_DESTROY_VMR:
 443                 return "DESTROY_VMR";
 444         case GFX_CMD_ID_PROG_REG:
 445                 return "PROG_REG";
 446         case GFX_CMD_ID_GET_FW_ATTESTATION:
 447                 return "GET_FW_ATTESTATION";
 448         case GFX_CMD_ID_LOAD_TOC:
 449                 return "ID_LOAD_TOC";
 450         case GFX_CMD_ID_AUTOLOAD_RLC:
 451                 return "AUTOLOAD_RLC";
 452         case GFX_CMD_ID_BOOT_CFG:
 453                 return "BOOT_CFG";
 454         default:
 455                 return "UNKNOWN CMD";
 456         }
 457 }
 458
 459 static int
 460 psp_cmd_submit_buf(struct psp_context *psp,
 461                    struct amdgpu_firmware_info *ucode,
 462                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 463 {
 464         int ret;
 465         int index, idx;
 466         int timeout = 20000;
 467         bool ras_intr = false;
 468         bool skip_unsupport = false;
 469
 470         if (psp->adev->no_hw_access)
 471                 return 0;
 472
 473         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
 474                 return 0;
 475
 476         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 477
 478         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 479
 480         index = atomic_inc_return(&psp->fence_value);
 481         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 482         if (ret) {
 483                 atomic_dec(&psp->fence_value);
 484                 goto exit;
 485         }
 486
 487         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 488         while (*((unsigned int *)psp->fence_buf) != index) {
 489                 if (--timeout == 0)
 490                         break;
 491                 /*
 492                  * Shouldn't wait for timeout when err_event_athub occurs,
 493                  * because gpu reset thread triggered and lock resource should
 494                  * be released for psp resume sequence.
 495                  */
 496                 ras_intr = amdgpu_ras_intr_triggered();
 497                 if (ras_intr)
 498                         break;
 499                 usleep_range(10, 100);
 500                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 501         }
 502
 503         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 504         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 505                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 506
 507         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 508
 509         /* In some cases, psp response status is not 0 even there is no
 510          * problem while the command is submitted. Some version of PSP FW
 511          * doesn't write 0 to that field.
 512          * So here we would like to only print a warning instead of an error
 513          * during psp initialization to avoid breaking hw_init and it doesn't
 514          * return -EINVAL.
 515          */
 516         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 517                 if (ucode)
 518                         DRM_WARN("failed to load ucode %s(0x%X) ",
 519                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 520                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 521                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 522                          psp->cmd_buf_mem->resp.status);
 523                 /* If we load CAP FW, PSP must return 0 under SRIOV
 524                  * also return failure in case of timeout
 525                  */
 526                 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) {
 527                         ret = -EINVAL;
 528                         goto exit;
 529                 }
 530         }
 531
 532         if (ucode) {
 533                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 534                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 535         }
 536
 537 exit:
 538         drm_dev_exit(idx);
 539         return ret;
 540 }
 541
 542 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 543 {
 544         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 545
 546         mutex_lock(&psp->mutex);
 547
 548         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 549
 550         return cmd;
 551 }
 552
 553 static void release_psp_cmd_buf(struct psp_context *psp)
 554 {
 555         mutex_unlock(&psp->mutex);
 556 }
 557
 558 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 559                                  struct psp_gfx_cmd_resp *cmd,
 560                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 561 {
 562         struct amdgpu_device *adev = psp->adev;
 563         uint32_t size = amdgpu_bo_size(tmr_bo);
 564         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 565
 566         if (amdgpu_sriov_vf(psp->adev))
 567                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 568         else
 569                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 570         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 571         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 572         cmd->cmd.cmd_setup_tmr.buf_size = size;
 573         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 574         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 575         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 576 }
 577
 578 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 579                                       uint64_t pri_buf_mc, uint32_t size)
 580 {
 581         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 582         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 583         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 584         cmd->cmd.cmd_load_toc.toc_size = size;
 585 }
 586
 587 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 588 static int psp_load_toc(struct psp_context *psp,
 589                         uint32_t *tmr_size)
 590 {
 591         int ret;
 592         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 593
 594         /* Copy toc to psp firmware private buffer */
 595         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 596
 597         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 598
 599         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 600                                  psp->fence_buf_mc_addr);
 601         if (!ret)
 602                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 603
 604         release_psp_cmd_buf(psp);
 605
 606         return ret;
 607 }
 608
 609 /* Set up Trusted Memory Region */
 610 static int psp_tmr_init(struct psp_context *psp)
 611 {
 612         int ret;
 613         int tmr_size;
 614         void *tmr_buf;
 615         void **pptr;
 616
 617         /*
 618          * According to HW engineer, they prefer the TMR address be "naturally
 619          * aligned" , e.g. the start address be an integer divide of TMR size.
 620          *
 621          * Note: this memory need be reserved till the driver
 622          * uninitializes.
 623          */
 624         tmr_size = PSP_TMR_SIZE(psp->adev);
 625
 626         /* For ASICs support RLC autoload, psp will parse the toc
 627          * and calculate the total size of TMR needed */
 628         if (!amdgpu_sriov_vf(psp->adev) &&
 629             psp->toc.start_addr &&
 630             psp->toc.size_bytes &&
 631             psp->fw_pri_buf) {
 632                 ret = psp_load_toc(psp, &tmr_size);
 633                 if (ret) {
 634                         DRM_ERROR("Failed to load toc\n");
 635                         return ret;
 636                 }
 637         }
 638
 639         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 640         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 641                                       AMDGPU_GEM_DOMAIN_VRAM,
 642                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 643
 644         return ret;
 645 }
 646
 647 static bool psp_skip_tmr(struct psp_context *psp)
 648 {
 649         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 650         case IP_VERSION(11, 0, 9):
 651         case IP_VERSION(11, 0, 7):
 652         case IP_VERSION(13, 0, 2):
 653                 return true;
 654         default:
 655                 return false;
 656         }
 657 }
 658
 659 static int psp_tmr_load(struct psp_context *psp)
 660 {
 661         int ret;
 662         struct psp_gfx_cmd_resp *cmd;
 663
 664         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 665          * Already set up by host driver.
 666          */
 667         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 668                 return 0;
 669
 670         cmd = acquire_psp_cmd_buf(psp);
 671
 672         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 673         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 674                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 675
 676         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 677                                  psp->fence_buf_mc_addr);
 678
 679         release_psp_cmd_buf(psp);
 680
 681         return ret;
 682 }
 683
 684 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 685                                         struct psp_gfx_cmd_resp *cmd)
 686 {
 687         if (amdgpu_sriov_vf(psp->adev))
 688                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 689         else
 690                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 691 }
 692
 693 static int psp_tmr_unload(struct psp_context *psp)
 694 {
 695         int ret;
 696         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 697
 698         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 699         DRM_INFO("free PSP TMR buffer\n");
 700
 701         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 702                                  psp->fence_buf_mc_addr);
 703
 704         release_psp_cmd_buf(psp);
 705
 706         return ret;
 707 }
 708
 709 static int psp_tmr_terminate(struct psp_context *psp)
 710 {
 711         int ret;
 712         void *tmr_buf;
 713         void **pptr;
 714
 715         ret = psp_tmr_unload(psp);
 716         if (ret)
 717                 return ret;
 718
 719         /* free TMR memory buffer */
 720         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 721         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 722
 723         return 0;
 724 }
 725
 726 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 727                                         uint64_t *output_ptr)
 728 {
 729         int ret;
 730         struct psp_gfx_cmd_resp *cmd;
 731
 732         if (!output_ptr)
 733                 return -EINVAL;
 734
 735         if (amdgpu_sriov_vf(psp->adev))
 736                 return 0;
 737
 738         cmd = acquire_psp_cmd_buf(psp);
 739
 740         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 741
 742         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 743                                  psp->fence_buf_mc_addr);
 744
 745         if (!ret) {
 746                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 747                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 748         }
 749
 750         release_psp_cmd_buf(psp);
 751
 752         return ret;
 753 }
 754
 755 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 756 {
 757         struct psp_context *psp = &adev->psp;
 758         struct psp_gfx_cmd_resp *cmd;
 759         int ret;
 760
 761         if (amdgpu_sriov_vf(adev))
 762                 return 0;
 763
 764         cmd = acquire_psp_cmd_buf(psp);
 765
 766         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 767         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 768
 769         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 770         if (!ret) {
 771                 *boot_cfg =
 772                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 773         }
 774
 775         release_psp_cmd_buf(psp);
 776
 777         return ret;
 778 }
 779
 780 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 781 {
 782         int ret;
 783         struct psp_context *psp = &adev->psp;
 784         struct psp_gfx_cmd_resp *cmd;
 785
 786         if (amdgpu_sriov_vf(adev))
 787                 return 0;
 788
 789         cmd = acquire_psp_cmd_buf(psp);
 790
 791         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 792         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 793         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 794         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 795
 796         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 797
 798         release_psp_cmd_buf(psp);
 799
 800         return ret;
 801 }
 802
 803 static int psp_rl_load(struct amdgpu_device *adev)
 804 {
 805         int ret;
 806         struct psp_context *psp = &adev->psp;
 807         struct psp_gfx_cmd_resp *cmd;
 808
 809         if (!is_psp_fw_valid(psp->rl))
 810                 return 0;
 811
 812         cmd = acquire_psp_cmd_buf(psp);
 813
 814         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 815         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 816
 817         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 818         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 819         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 820         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 821         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 822
 823         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 824
 825         release_psp_cmd_buf(psp);
 826
 827         return ret;
 828 }
 829
 830 static int psp_asd_load(struct psp_context *psp)
 831 {
 832         return psp_ta_load(psp, &psp->asd_context);
 833 }
 834
 835 static int psp_asd_initialize(struct psp_context *psp)
 836 {
 837         int ret;
 838
 839         /* If PSP version doesn't match ASD version, asd loading will be failed.
 840          * add workaround to bypass it for sriov now.
 841          * TODO: add version check to make it common
 842          */
 843         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 844                 return 0;
 845
 846         psp->asd_context.mem_context.shared_mc_addr  = 0;
 847         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 848         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 849
 850         ret = psp_asd_load(psp);
 851         if (!ret)
 852                 psp->asd_context.initialized = true;
 853
 854         return ret;
 855 }
 856
 857 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 858                                        uint32_t session_id)
 859 {
 860         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 861         cmd->cmd.cmd_unload_ta.session_id = session_id;
 862 }
 863
 864 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
 865 {
 866         int ret;
 867         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 868
 869         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
 870
 871         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 872
 873         release_psp_cmd_buf(psp);
 874
 875         return ret;
 876 }
 877
 878 static int psp_asd_unload(struct psp_context *psp)
 879 {
 880         return psp_ta_unload(psp, &psp->asd_context);
 881 }
 882
 883 static int psp_asd_terminate(struct psp_context *psp)
 884 {
 885         int ret;
 886
 887         if (amdgpu_sriov_vf(psp->adev))
 888                 return 0;
 889
 890         if (!psp->asd_context.initialized)
 891                 return 0;
 892
 893         ret = psp_asd_unload(psp);
 894
 895         if (!ret)
 896                 psp->asd_context.initialized = false;
 897
 898         return ret;
 899 }
 900
 901 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 902                 uint32_t id, uint32_t value)
 903 {
 904         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 905         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 906         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 907 }
 908
 909 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 910                 uint32_t value)
 911 {
 912         struct psp_gfx_cmd_resp *cmd;
 913         int ret = 0;
 914
 915         if (reg >= PSP_REG_LAST)
 916                 return -EINVAL;
 917
 918         cmd = acquire_psp_cmd_buf(psp);
 919
 920         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 921         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 922         if (ret)
 923                 DRM_ERROR("PSP failed to program reg id %d", reg);
 924
 925         release_psp_cmd_buf(psp);
 926
 927         return ret;
 928 }
 929
 930 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 931                                      uint64_t ta_bin_mc,
 932                                      struct ta_context *context)
 933 {
 934         cmd->cmd_id                             = context->ta_load_type;
 935         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 936         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 937         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
 938
 939         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
 940                 lower_32_bits(context->mem_context.shared_mc_addr);
 941         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
 942                 upper_32_bits(context->mem_context.shared_mc_addr);
 943         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
 944 }
 945
 946 int psp_ta_init_shared_buf(struct psp_context *psp,
 947                                   struct ta_mem_context *mem_ctx)
 948 {
 949         /*
 950         * Allocate 16k memory aligned to 4k from Frame Buffer (local
 951         * physical) for ta to host memory
 952         */
 953         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
 954                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 955                                       &mem_ctx->shared_bo,
 956                                       &mem_ctx->shared_mc_addr,
 957                                       &mem_ctx->shared_buf);
 958 }
 959
 960 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 961 {
 962         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 963                               &mem_ctx->shared_buf);
 964 }
 965
 966 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 967 {
 968         return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
 969 }
 970
 971 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 972                                        uint32_t ta_cmd_id,
 973                                        struct ta_context *context)
 974 {
 975         cmd->cmd_id                         = GFX_CMD_ID_INVOKE_CMD;
 976         cmd->cmd.cmd_invoke_cmd.session_id  = context->session_id;
 977         cmd->cmd.cmd_invoke_cmd.ta_cmd_id   = ta_cmd_id;
 978
 979         cmd->cmd.cmd_invoke_cmd.buf.num_desc   = 1;
 980         cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
 981         cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
 982         cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
 983                                      lower_32_bits(context->mem_context.shared_mc_addr);
 984         cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
 985                                      upper_32_bits(context->mem_context.shared_mc_addr);
 986 }
 987
 988 int psp_ta_invoke_indirect(struct psp_context *psp,
 989                   uint32_t ta_cmd_id,
 990                   struct ta_context *context)
 991 {
 992         int ret;
 993         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 994
 995         psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);
 996
 997         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 998                                  psp->fence_buf_mc_addr);
 999
1000         context->resp_status = cmd->resp.status;
1001
1002         release_psp_cmd_buf(psp);
1003
1004         return ret;
1005 }
1006
1007 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1008                                        uint32_t ta_cmd_id,
1009                                        uint32_t session_id)
1010 {
1011         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1012         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1013         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1014 }
1015
1016 int psp_ta_invoke(struct psp_context *psp,
1017                   uint32_t ta_cmd_id,
1018                   struct ta_context *context)
1019 {
1020         int ret;
1021         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1022
1023         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1024
1025         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1026                                  psp->fence_buf_mc_addr);
1027
1028         context->resp_status = cmd->resp.status;
1029
1030         release_psp_cmd_buf(psp);
1031
1032         return ret;
1033 }
1034
1035 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1036 {
1037         int ret;
1038         struct psp_gfx_cmd_resp *cmd;
1039
1040         cmd = acquire_psp_cmd_buf(psp);
1041
1042         psp_copy_fw(psp, context->bin_desc.start_addr,
1043                     context->bin_desc.size_bytes);
1044
1045         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1046
1047         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1048                                  psp->fence_buf_mc_addr);
1049
1050         context->resp_status = cmd->resp.status;
1051
1052         if (!ret) {
1053                 context->session_id = cmd->resp.session_id;
1054         }
1055
1056         release_psp_cmd_buf(psp);
1057
1058         return ret;
1059 }
1060
1061 static int psp_xgmi_load(struct psp_context *psp)
1062 {
1063         return psp_ta_load(psp, &psp->xgmi_context.context);
1064 }
1065
1066 static int psp_xgmi_unload(struct psp_context *psp)
1067 {
1068         return psp_ta_unload(psp, &psp->xgmi_context.context);
1069 }
1070
1071 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1072 {
1073         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1074 }
1075
1076 int psp_xgmi_terminate(struct psp_context *psp)
1077 {
1078         int ret;
1079         struct amdgpu_device *adev = psp->adev;
1080
1081         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1082         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1083             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1084              adev->gmc.xgmi.connected_to_cpu))
1085                 return 0;
1086
1087         if (!psp->xgmi_context.context.initialized)
1088                 return 0;
1089
1090         ret = psp_xgmi_unload(psp);
1091         if (ret)
1092                 return ret;
1093
1094         psp->xgmi_context.context.initialized = false;
1095
1096         /* free xgmi shared memory */
1097         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
1098
1099         return 0;
1100 }
1101
1102 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1103 {
1104         struct ta_xgmi_shared_memory *xgmi_cmd;
1105         int ret;
1106
1107         if (!psp->ta_fw ||
1108             !psp->xgmi_context.context.bin_desc.size_bytes ||
1109             !psp->xgmi_context.context.bin_desc.start_addr)
1110                 return -ENOENT;
1111
1112         if (!load_ta)
1113                 goto invoke;
1114
1115         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1116         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1117
1118         if (!psp->xgmi_context.context.initialized) {
1119                 ret = psp_xgmi_init_shared_buf(psp);
1120                 if (ret)
1121                         return ret;
1122         }
1123
1124         /* Load XGMI TA */
1125         ret = psp_xgmi_load(psp);
1126         if (!ret)
1127                 psp->xgmi_context.context.initialized = true;
1128         else
1129                 return ret;
1130
1131 invoke:
1132         /* Initialize XGMI session */
1133         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1134         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1135         xgmi_cmd->flag_extend_link_record = set_extended_data;
1136         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1137
1138         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1139
1140         return ret;
1141 }
1142
1143 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1144 {
1145         struct ta_xgmi_shared_memory *xgmi_cmd;
1146         int ret;
1147
1148         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1149         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1150
1151         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1152
1153         /* Invoke xgmi ta to get hive id */
1154         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1155         if (ret)
1156                 return ret;
1157
1158         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1159
1160         return 0;
1161 }
1162
1163 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1164 {
1165         struct ta_xgmi_shared_memory *xgmi_cmd;
1166         int ret;
1167
1168         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1169         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1170
1171         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1172
1173         /* Invoke xgmi ta to get the node id */
1174         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1175         if (ret)
1176                 return ret;
1177
1178         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1179
1180         return 0;
1181 }
1182
1183 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1184 {
1185         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1186                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1187 }
1188
1189 /*
1190  * Chips that support extended topology information require the driver to
1191  * reflect topology information in the opposite direction.  This is
1192  * because the TA has already exceeded its link record limit and if the
1193  * TA holds bi-directional information, the driver would have to do
1194  * multiple fetches instead of just two.
1195  */
1196 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1197                                         struct psp_xgmi_node_info node_info)
1198 {
1199         struct amdgpu_device *mirror_adev;
1200         struct amdgpu_hive_info *hive;
1201         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1202         uint64_t dst_node_id = node_info.node_id;
1203         uint8_t dst_num_hops = node_info.num_hops;
1204         uint8_t dst_num_links = node_info.num_links;
1205
1206         hive = amdgpu_get_xgmi_hive(psp->adev);
1207         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1208                 struct psp_xgmi_topology_info *mirror_top_info;
1209                 int j;
1210
1211                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1212                         continue;
1213
1214                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1215                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1216                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1217                                 continue;
1218
1219                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1220                         /*
1221                          * prevent 0 num_links value re-reflection since reflection
1222                          * criteria is based on num_hops (direct or indirect).
1223                          *
1224                          */
1225                         if (dst_num_links)
1226                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1227
1228                         break;
1229                 }
1230
1231                 break;
1232         }
1233 }
1234
1235 int psp_xgmi_get_topology_info(struct psp_context *psp,
1236                                int number_devices,
1237                                struct psp_xgmi_topology_info *topology,
1238                                bool get_extended_data)
1239 {
1240         struct ta_xgmi_shared_memory *xgmi_cmd;
1241         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1242         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1243         int i;
1244         int ret;
1245
1246         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1247                 return -EINVAL;
1248
1249         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1250         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1251         xgmi_cmd->flag_extend_link_record = get_extended_data;
1252
1253         /* Fill in the shared memory with topology information as input */
1254         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1255         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1256         topology_info_input->num_nodes = number_devices;
1257
1258         for (i = 0; i < topology_info_input->num_nodes; i++) {
1259                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1260                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1261                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1262                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1263         }
1264
1265         /* Invoke xgmi ta to get the topology information */
1266         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1267         if (ret)
1268                 return ret;
1269
1270         /* Read the output topology information from the shared memory */
1271         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1272         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1273         for (i = 0; i < topology->num_nodes; i++) {
1274                 /* extended data will either be 0 or equal to non-extended data */
1275                 if (topology_info_output->nodes[i].num_hops)
1276                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1277
1278                 /* non-extended data gets everything here so no need to update */
1279                 if (!get_extended_data) {
1280                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1281                         topology->nodes[i].is_sharing_enabled =
1282                                         topology_info_output->nodes[i].is_sharing_enabled;
1283                         topology->nodes[i].sdma_engine =
1284                                         topology_info_output->nodes[i].sdma_engine;
1285                 }
1286
1287         }
1288
1289         /* Invoke xgmi ta again to get the link information */
1290         if (psp_xgmi_peer_link_info_supported(psp)) {
1291                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1292
1293                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1294
1295                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1296
1297                 if (ret)
1298                         return ret;
1299
1300                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1301                 for (i = 0; i < topology->num_nodes; i++) {
1302                         /* accumulate num_links on extended data */
1303                         topology->nodes[i].num_links = get_extended_data ?
1304                                         topology->nodes[i].num_links +
1305                                                         link_info_output->nodes[i].num_links :
1306                                         link_info_output->nodes[i].num_links;
1307
1308                         /* reflect the topology information for bi-directionality */
1309                         if (psp->xgmi_context.supports_extended_data &&
1310                                         get_extended_data && topology->nodes[i].num_hops)
1311                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1312                 }
1313         }
1314
1315         return 0;
1316 }
1317
1318 int psp_xgmi_set_topology_info(struct psp_context *psp,
1319                                int number_devices,
1320                                struct psp_xgmi_topology_info *topology)
1321 {
1322         struct ta_xgmi_shared_memory *xgmi_cmd;
1323         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1324         int i;
1325
1326         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1327                 return -EINVAL;
1328
1329         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1330         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1331
1332         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1333         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1334         topology_info_input->num_nodes = number_devices;
1335
1336         for (i = 0; i < topology_info_input->num_nodes; i++) {
1337                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1338                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1339                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1340                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1341         }
1342
1343         /* Invoke xgmi ta to set topology information */
1344         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1345 }
1346
1347 // ras begin
1348 static int psp_ras_init_shared_buf(struct psp_context *psp)
1349 {
1350         return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1351 }
1352
1353 static int psp_ras_load(struct psp_context *psp)
1354 {
1355         return psp_ta_load(psp, &psp->ras_context.context);
1356 }
1357
1358 static int psp_ras_unload(struct psp_context *psp)
1359 {
1360         return psp_ta_unload(psp, &psp->ras_context.context);
1361 }
1362
1363 static void psp_ras_ta_check_status(struct psp_context *psp)
1364 {
1365         struct ta_ras_shared_memory *ras_cmd =
1366                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1367
1368         switch (ras_cmd->ras_status) {
1369         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1370                 dev_warn(psp->adev->dev,
1371                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1372                 break;
1373         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1374                 dev_warn(psp->adev->dev,
1375                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1376                 break;
1377         case TA_RAS_STATUS__SUCCESS:
1378                 break;
1379         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1380                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1381                         dev_warn(psp->adev->dev,
1382                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1383                 break;
1384         default:
1385                 dev_warn(psp->adev->dev,
1386                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1387                 break;
1388         }
1389 }
1390
1391 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1392 {
1393         struct ta_ras_shared_memory *ras_cmd;
1394         int ret;
1395
1396         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1397
1398         /*
1399          * TODO: bypass the loading in sriov for now
1400          */
1401         if (amdgpu_sriov_vf(psp->adev))
1402                 return 0;
1403
1404         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1405
1406         if (amdgpu_ras_intr_triggered())
1407                 return ret;
1408
1409         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1410         {
1411                 DRM_WARN("RAS: Unsupported Interface");
1412                 return -EINVAL;
1413         }
1414
1415         if (!ret) {
1416                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1417                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1418
1419                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1420                 }
1421                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1422                         dev_warn(psp->adev->dev,
1423                                  "RAS internal register access blocked\n");
1424
1425                 psp_ras_ta_check_status(psp);
1426         }
1427
1428         return ret;
1429 }
1430
1431 int psp_ras_enable_features(struct psp_context *psp,
1432                 union ta_ras_cmd_input *info, bool enable)
1433 {
1434         struct ta_ras_shared_memory *ras_cmd;
1435         int ret;
1436
1437         if (!psp->ras_context.context.initialized)
1438                 return -EINVAL;
1439
1440         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1441         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1442
1443         if (enable)
1444                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1445         else
1446                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1447
1448         ras_cmd->ras_in_message = *info;
1449
1450         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1451         if (ret)
1452                 return -EINVAL;
1453
1454         return 0;
1455 }
1456
1457 int psp_ras_terminate(struct psp_context *psp)
1458 {
1459         int ret;
1460
1461         /*
1462          * TODO: bypass the terminate in sriov for now
1463          */
1464         if (amdgpu_sriov_vf(psp->adev))
1465                 return 0;
1466
1467         if (!psp->ras_context.context.initialized)
1468                 return 0;
1469
1470         ret = psp_ras_unload(psp);
1471         if (ret)
1472                 return ret;
1473
1474         psp->ras_context.context.initialized = false;
1475
1476         /* free ras shared memory */
1477         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
1478
1479         return 0;
1480 }
1481
1482 static int psp_ras_initialize(struct psp_context *psp)
1483 {
1484         int ret;
1485         uint32_t boot_cfg = 0xFF;
1486         struct amdgpu_device *adev = psp->adev;
1487         struct ta_ras_shared_memory *ras_cmd;
1488
1489         /*
1490          * TODO: bypass the initialize in sriov for now
1491          */
1492         if (amdgpu_sriov_vf(adev))
1493                 return 0;
1494
1495         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1496             !adev->psp.ras_context.context.bin_desc.start_addr) {
1497                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1498                 return 0;
1499         }
1500
1501         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1502                 /* query GECC enablement status from boot config
1503                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1504                  */
1505                 ret = psp_boot_config_get(adev, &boot_cfg);
1506                 if (ret)
1507                         dev_warn(adev->dev, "PSP get boot config failed\n");
1508
1509                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1510                         if (!boot_cfg) {
1511                                 dev_info(adev->dev, "GECC is disabled\n");
1512                         } else {
1513                                 /* disable GECC in next boot cycle if ras is
1514                                  * disabled by module parameter amdgpu_ras_enable
1515                                  * and/or amdgpu_ras_mask, or boot_config_get call
1516                                  * is failed
1517                                  */
1518                                 ret = psp_boot_config_set(adev, 0);
1519                                 if (ret)
1520                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1521                                 else
1522                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1523                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1524                         }
1525                 } else {
1526                         if (1 == boot_cfg) {
1527                                 dev_info(adev->dev, "GECC is enabled\n");
1528                         } else {
1529                                 /* enable GECC in next boot cycle if it is disabled
1530                                  * in boot config, or force enable GECC if failed to
1531                                  * get boot configuration
1532                                  */
1533                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1534                                 if (ret)
1535                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1536                                 else
1537                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1538                         }
1539                 }
1540         }
1541
1542         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1543         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1544
1545         if (!psp->ras_context.context.initialized) {
1546                 ret = psp_ras_init_shared_buf(psp);
1547                 if (ret)
1548                         return ret;
1549         }
1550
1551         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1552         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1553
1554         if (amdgpu_ras_is_poison_mode_supported(adev))
1555                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1556         if (!adev->gmc.xgmi.connected_to_cpu)
1557                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1558
1559         ret = psp_ras_load(psp);
1560
1561         if (!ret && !ras_cmd->ras_status)
1562                 psp->ras_context.context.initialized = true;
1563         else {
1564                 if (ras_cmd->ras_status)
1565                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1566                 amdgpu_ras_fini(psp->adev);
1567         }
1568
1569         return ret;
1570 }
1571
1572 int psp_ras_trigger_error(struct psp_context *psp,
1573                           struct ta_ras_trigger_error_input *info)
1574 {
1575         struct ta_ras_shared_memory *ras_cmd;
1576         int ret;
1577
1578         if (!psp->ras_context.context.initialized)
1579                 return -EINVAL;
1580
1581         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1582         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1583
1584         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1585         ras_cmd->ras_in_message.trigger_error = *info;
1586
1587         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1588         if (ret)
1589                 return -EINVAL;
1590
1591         /* If err_event_athub occurs error inject was successful, however
1592            return status from TA is no long reliable */
1593         if (amdgpu_ras_intr_triggered())
1594                 return 0;
1595
1596         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1597                 return -EACCES;
1598         else if (ras_cmd->ras_status)
1599                 return -EINVAL;
1600
1601         return 0;
1602 }
1603 // ras end
1604
1605 // HDCP start
1606 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1607 {
1608         return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1609 }
1610
1611 static int psp_hdcp_load(struct psp_context *psp)
1612 {
1613         return psp_ta_load(psp, &psp->hdcp_context.context);
1614 }
1615
1616 static int psp_hdcp_initialize(struct psp_context *psp)
1617 {
1618         int ret;
1619
1620         /*
1621          * TODO: bypass the initialize in sriov for now
1622          */
1623         if (amdgpu_sriov_vf(psp->adev))
1624                 return 0;
1625
1626         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1627             !psp->hdcp_context.context.bin_desc.start_addr) {
1628                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1629                 return 0;
1630         }
1631
1632         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1633         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1634
1635         if (!psp->hdcp_context.context.initialized) {
1636                 ret = psp_hdcp_init_shared_buf(psp);
1637                 if (ret)
1638                         return ret;
1639         }
1640
1641         ret = psp_hdcp_load(psp);
1642         if (!ret) {
1643                 psp->hdcp_context.context.initialized = true;
1644                 mutex_init(&psp->hdcp_context.mutex);
1645         }
1646
1647         return ret;
1648 }
1649
1650 static int psp_hdcp_unload(struct psp_context *psp)
1651 {
1652         return psp_ta_unload(psp, &psp->hdcp_context.context);
1653 }
1654
1655 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1656 {
1657         /*
1658          * TODO: bypass the loading in sriov for now
1659          */
1660         if (amdgpu_sriov_vf(psp->adev))
1661                 return 0;
1662
1663         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1664 }
1665
1666 static int psp_hdcp_terminate(struct psp_context *psp)
1667 {
1668         int ret;
1669
1670         /*
1671          * TODO: bypass the terminate in sriov for now
1672          */
1673         if (amdgpu_sriov_vf(psp->adev))
1674                 return 0;
1675
1676         if (!psp->hdcp_context.context.initialized) {
1677                 if (psp->hdcp_context.context.mem_context.shared_buf)
1678                         goto out;
1679                 else
1680                         return 0;
1681         }
1682
1683         ret = psp_hdcp_unload(psp);
1684         if (ret)
1685                 return ret;
1686
1687         psp->hdcp_context.context.initialized = false;
1688
1689 out:
1690         /* free hdcp shared memory */
1691         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
1692
1693         return 0;
1694 }
1695 // HDCP end
1696
1697 // DTM start
1698 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1699 {
1700         return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1701 }
1702
1703 static int psp_dtm_load(struct psp_context *psp)
1704 {
1705         return psp_ta_load(psp, &psp->dtm_context.context);
1706 }
1707
1708 static int psp_dtm_initialize(struct psp_context *psp)
1709 {
1710         int ret;
1711
1712         /*
1713          * TODO: bypass the initialize in sriov for now
1714          */
1715         if (amdgpu_sriov_vf(psp->adev))
1716                 return 0;
1717
1718         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1719             !psp->dtm_context.context.bin_desc.start_addr) {
1720                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1721                 return 0;
1722         }
1723
1724         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1725         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1726
1727         if (!psp->dtm_context.context.initialized) {
1728                 ret = psp_dtm_init_shared_buf(psp);
1729                 if (ret)
1730                         return ret;
1731         }
1732
1733         ret = psp_dtm_load(psp);
1734         if (!ret) {
1735                 psp->dtm_context.context.initialized = true;
1736                 mutex_init(&psp->dtm_context.mutex);
1737         }
1738
1739         return ret;
1740 }
1741
1742 static int psp_dtm_unload(struct psp_context *psp)
1743 {
1744         return psp_ta_unload(psp, &psp->dtm_context.context);
1745 }
1746
1747 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1748 {
1749         /*
1750          * TODO: bypass the loading in sriov for now
1751          */
1752         if (amdgpu_sriov_vf(psp->adev))
1753                 return 0;
1754
1755         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1756 }
1757
1758 static int psp_dtm_terminate(struct psp_context *psp)
1759 {
1760         int ret;
1761
1762         /*
1763          * TODO: bypass the terminate in sriov for now
1764          */
1765         if (amdgpu_sriov_vf(psp->adev))
1766                 return 0;
1767
1768         if (!psp->dtm_context.context.initialized) {
1769                 if (psp->dtm_context.context.mem_context.shared_buf)
1770                         goto out;
1771                 else
1772                         return 0;
1773         }
1774
1775         ret = psp_dtm_unload(psp);
1776         if (ret)
1777                 return ret;
1778
1779         psp->dtm_context.context.initialized = false;
1780
1781 out:
1782         /* free dtm shared memory */
1783         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
1784
1785         return 0;
1786 }
1787 // DTM end
1788
1789 // RAP start
1790 static int psp_rap_init_shared_buf(struct psp_context *psp)
1791 {
1792         return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1793 }
1794
1795 static int psp_rap_load(struct psp_context *psp)
1796 {
1797         return psp_ta_load(psp, &psp->rap_context.context);
1798 }
1799
1800 static int psp_rap_unload(struct psp_context *psp)
1801 {
1802         return psp_ta_unload(psp, &psp->rap_context.context);
1803 }
1804
1805 static int psp_rap_initialize(struct psp_context *psp)
1806 {
1807         int ret;
1808         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1809
1810         /*
1811          * TODO: bypass the initialize in sriov for now
1812          */
1813         if (amdgpu_sriov_vf(psp->adev))
1814                 return 0;
1815
1816         if (!psp->rap_context.context.bin_desc.size_bytes ||
1817             !psp->rap_context.context.bin_desc.start_addr) {
1818                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1819                 return 0;
1820         }
1821
1822         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1823         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1824
1825         if (!psp->rap_context.context.initialized) {
1826                 ret = psp_rap_init_shared_buf(psp);
1827                 if (ret)
1828                         return ret;
1829         }
1830
1831         ret = psp_rap_load(psp);
1832         if (!ret) {
1833                 psp->rap_context.context.initialized = true;
1834                 mutex_init(&psp->rap_context.mutex);
1835         } else
1836                 return ret;
1837
1838         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1839         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1840                 psp_rap_terminate(psp);
1841
1842                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1843                          ret, status);
1844
1845                 return ret;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static int psp_rap_terminate(struct psp_context *psp)
1852 {
1853         int ret;
1854
1855         if (!psp->rap_context.context.initialized)
1856                 return 0;
1857
1858         ret = psp_rap_unload(psp);
1859
1860         psp->rap_context.context.initialized = false;
1861
1862         /* free rap shared memory */
1863         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1864
1865         return ret;
1866 }
1867
1868 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1869 {
1870         struct ta_rap_shared_memory *rap_cmd;
1871         int ret = 0;
1872
1873         if (!psp->rap_context.context.initialized)
1874                 return 0;
1875
1876         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1877             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1878                 return -EINVAL;
1879
1880         mutex_lock(&psp->rap_context.mutex);
1881
1882         rap_cmd = (struct ta_rap_shared_memory *)
1883                   psp->rap_context.context.mem_context.shared_buf;
1884         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1885
1886         rap_cmd->cmd_id = ta_cmd_id;
1887         rap_cmd->validation_method_id = METHOD_A;
1888
1889         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1890         if (ret)
1891                 goto out_unlock;
1892
1893         if (status)
1894                 *status = rap_cmd->rap_status;
1895
1896 out_unlock:
1897         mutex_unlock(&psp->rap_context.mutex);
1898
1899         return ret;
1900 }
1901 // RAP end
1902
1903 /* securedisplay start */
1904 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1905 {
1906         return psp_ta_init_shared_buf(
1907                 psp, &psp->securedisplay_context.context.mem_context);
1908 }
1909
1910 static int psp_securedisplay_load(struct psp_context *psp)
1911 {
1912         return psp_ta_load(psp, &psp->securedisplay_context.context);
1913 }
1914
1915 static int psp_securedisplay_unload(struct psp_context *psp)
1916 {
1917         return psp_ta_unload(psp, &psp->securedisplay_context.context);
1918 }
1919
1920 static int psp_securedisplay_initialize(struct psp_context *psp)
1921 {
1922         int ret;
1923         struct securedisplay_cmd *securedisplay_cmd;
1924
1925         /*
1926          * TODO: bypass the initialize in sriov for now
1927          */
1928         if (amdgpu_sriov_vf(psp->adev))
1929                 return 0;
1930
1931         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1932             !psp->securedisplay_context.context.bin_desc.start_addr) {
1933                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1934                 return 0;
1935         }
1936
1937         psp->securedisplay_context.context.mem_context.shared_mem_size =
1938                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1939         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1940
1941         if (!psp->securedisplay_context.context.initialized) {
1942                 ret = psp_securedisplay_init_shared_buf(psp);
1943                 if (ret)
1944                         return ret;
1945         }
1946
1947         ret = psp_securedisplay_load(psp);
1948         if (!ret) {
1949                 psp->securedisplay_context.context.initialized = true;
1950                 mutex_init(&psp->securedisplay_context.mutex);
1951         } else
1952                 return ret;
1953
1954         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1955                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1956
1957         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1958         if (ret) {
1959                 psp_securedisplay_terminate(psp);
1960                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1961                 return -EINVAL;
1962         }
1963
1964         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1965                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1966                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1967                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1968         }
1969
1970         return 0;
1971 }
1972
1973 static int psp_securedisplay_terminate(struct psp_context *psp)
1974 {
1975         int ret;
1976
1977         /*
1978          * TODO:bypass the terminate in sriov for now
1979          */
1980         if (amdgpu_sriov_vf(psp->adev))
1981                 return 0;
1982
1983         if (!psp->securedisplay_context.context.initialized)
1984                 return 0;
1985
1986         ret = psp_securedisplay_unload(psp);
1987         if (ret)
1988                 return ret;
1989
1990         psp->securedisplay_context.context.initialized = false;
1991
1992         /* free securedisplay shared memory */
1993         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1994
1995         return ret;
1996 }
1997
1998 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1999 {
2000         int ret;
2001
2002         if (!psp->securedisplay_context.context.initialized)
2003                 return -EINVAL;
2004
2005         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2006             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2007                 return -EINVAL;
2008
2009         mutex_lock(&psp->securedisplay_context.mutex);
2010
2011         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2012
2013         mutex_unlock(&psp->securedisplay_context.mutex);
2014
2015         return ret;
2016 }
2017 /* SECUREDISPLAY end */
2018
2019 static int psp_hw_start(struct psp_context *psp)
2020 {
2021         struct amdgpu_device *adev = psp->adev;
2022         int ret;
2023
2024         if (!amdgpu_sriov_vf(adev)) {
2025                 if ((is_psp_fw_valid(psp->kdb)) &&
2026                     (psp->funcs->bootloader_load_kdb != NULL)) {
2027                         ret = psp_bootloader_load_kdb(psp);
2028                         if (ret) {
2029                                 DRM_ERROR("PSP load kdb failed!\n");
2030                                 return ret;
2031                         }
2032                 }
2033
2034                 if ((is_psp_fw_valid(psp->spl)) &&
2035                     (psp->funcs->bootloader_load_spl != NULL)) {
2036                         ret = psp_bootloader_load_spl(psp);
2037                         if (ret) {
2038                                 DRM_ERROR("PSP load spl failed!\n");
2039                                 return ret;
2040                         }
2041                 }
2042
2043                 if ((is_psp_fw_valid(psp->sys)) &&
2044                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2045                         ret = psp_bootloader_load_sysdrv(psp);
2046                         if (ret) {
2047                                 DRM_ERROR("PSP load sys drv failed!\n");
2048                                 return ret;
2049                         }
2050                 }
2051
2052                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2053                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2054                         ret = psp_bootloader_load_soc_drv(psp);
2055                         if (ret) {
2056                                 DRM_ERROR("PSP load soc drv failed!\n");
2057                                 return ret;
2058                         }
2059                 }
2060
2061                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2062                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2063                         ret = psp_bootloader_load_intf_drv(psp);
2064                         if (ret) {
2065                                 DRM_ERROR("PSP load intf drv failed!\n");
2066                                 return ret;
2067                         }
2068                 }
2069
2070                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2071                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2072                         ret = psp_bootloader_load_dbg_drv(psp);
2073                         if (ret) {
2074                                 DRM_ERROR("PSP load dbg drv failed!\n");
2075                                 return ret;
2076                         }
2077                 }
2078
2079                 if ((is_psp_fw_valid(psp->sos)) &&
2080                     (psp->funcs->bootloader_load_sos != NULL)) {
2081                         ret = psp_bootloader_load_sos(psp);
2082                         if (ret) {
2083                                 DRM_ERROR("PSP load sos failed!\n");
2084                                 return ret;
2085                         }
2086                 }
2087         }
2088
2089         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2090         if (ret) {
2091                 DRM_ERROR("PSP create ring failed!\n");
2092                 return ret;
2093         }
2094
2095         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2096                 goto skip_pin_bo;
2097
2098         ret = psp_tmr_init(psp);
2099         if (ret) {
2100                 DRM_ERROR("PSP tmr init failed!\n");
2101                 return ret;
2102         }
2103
2104 skip_pin_bo:
2105         /*
2106          * For ASICs with DF Cstate management centralized
2107          * to PMFW, TMR setup should be performed after PMFW
2108          * loaded and before other non-psp firmware loaded.
2109          */
2110         if (psp->pmfw_centralized_cstate_management) {
2111                 ret = psp_load_smu_fw(psp);
2112                 if (ret)
2113                         return ret;
2114         }
2115
2116         ret = psp_tmr_load(psp);
2117         if (ret) {
2118                 DRM_ERROR("PSP load tmr failed!\n");
2119                 return ret;
2120         }
2121
2122         return 0;
2123 }
2124
2125 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2126                            enum psp_gfx_fw_type *type)
2127 {
2128         switch (ucode->ucode_id) {
2129         case AMDGPU_UCODE_ID_CAP:
2130                 *type = GFX_FW_TYPE_CAP;
2131                 break;
2132         case AMDGPU_UCODE_ID_SDMA0:
2133                 *type = GFX_FW_TYPE_SDMA0;
2134                 break;
2135         case AMDGPU_UCODE_ID_SDMA1:
2136                 *type = GFX_FW_TYPE_SDMA1;
2137                 break;
2138         case AMDGPU_UCODE_ID_SDMA2:
2139                 *type = GFX_FW_TYPE_SDMA2;
2140                 break;
2141         case AMDGPU_UCODE_ID_SDMA3:
2142                 *type = GFX_FW_TYPE_SDMA3;
2143                 break;
2144         case AMDGPU_UCODE_ID_SDMA4:
2145                 *type = GFX_FW_TYPE_SDMA4;
2146                 break;
2147         case AMDGPU_UCODE_ID_SDMA5:
2148                 *type = GFX_FW_TYPE_SDMA5;
2149                 break;
2150         case AMDGPU_UCODE_ID_SDMA6:
2151                 *type = GFX_FW_TYPE_SDMA6;
2152                 break;
2153         case AMDGPU_UCODE_ID_SDMA7:
2154                 *type = GFX_FW_TYPE_SDMA7;
2155                 break;
2156         case AMDGPU_UCODE_ID_CP_MES:
2157                 *type = GFX_FW_TYPE_CP_MES;
2158                 break;
2159         case AMDGPU_UCODE_ID_CP_MES_DATA:
2160                 *type = GFX_FW_TYPE_MES_STACK;
2161                 break;
2162         case AMDGPU_UCODE_ID_CP_CE:
2163                 *type = GFX_FW_TYPE_CP_CE;
2164                 break;
2165         case AMDGPU_UCODE_ID_CP_PFP:
2166                 *type = GFX_FW_TYPE_CP_PFP;
2167                 break;
2168         case AMDGPU_UCODE_ID_CP_ME:
2169                 *type = GFX_FW_TYPE_CP_ME;
2170                 break;
2171         case AMDGPU_UCODE_ID_CP_MEC1:
2172                 *type = GFX_FW_TYPE_CP_MEC;
2173                 break;
2174         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2175                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2176                 break;
2177         case AMDGPU_UCODE_ID_CP_MEC2:
2178                 *type = GFX_FW_TYPE_CP_MEC;
2179                 break;
2180         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2181                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2182                 break;
2183         case AMDGPU_UCODE_ID_RLC_G:
2184                 *type = GFX_FW_TYPE_RLC_G;
2185                 break;
2186         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2187                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2188                 break;
2189         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2190                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2191                 break;
2192         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2193                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2194                 break;
2195         case AMDGPU_UCODE_ID_RLC_IRAM:
2196                 *type = GFX_FW_TYPE_RLC_IRAM;
2197                 break;
2198         case AMDGPU_UCODE_ID_RLC_DRAM:
2199                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2200                 break;
2201         case AMDGPU_UCODE_ID_SMC:
2202                 *type = GFX_FW_TYPE_SMU;
2203                 break;
2204         case AMDGPU_UCODE_ID_UVD:
2205                 *type = GFX_FW_TYPE_UVD;
2206                 break;
2207         case AMDGPU_UCODE_ID_UVD1:
2208                 *type = GFX_FW_TYPE_UVD1;
2209                 break;
2210         case AMDGPU_UCODE_ID_VCE:
2211                 *type = GFX_FW_TYPE_VCE;
2212                 break;
2213         case AMDGPU_UCODE_ID_VCN:
2214                 *type = GFX_FW_TYPE_VCN;
2215                 break;
2216         case AMDGPU_UCODE_ID_VCN1:
2217                 *type = GFX_FW_TYPE_VCN1;
2218                 break;
2219         case AMDGPU_UCODE_ID_DMCU_ERAM:
2220                 *type = GFX_FW_TYPE_DMCU_ERAM;
2221                 break;
2222         case AMDGPU_UCODE_ID_DMCU_INTV:
2223                 *type = GFX_FW_TYPE_DMCU_ISR;
2224                 break;
2225         case AMDGPU_UCODE_ID_VCN0_RAM:
2226                 *type = GFX_FW_TYPE_VCN0_RAM;
2227                 break;
2228         case AMDGPU_UCODE_ID_VCN1_RAM:
2229                 *type = GFX_FW_TYPE_VCN1_RAM;
2230                 break;
2231         case AMDGPU_UCODE_ID_DMCUB:
2232                 *type = GFX_FW_TYPE_DMUB;
2233                 break;
2234         case AMDGPU_UCODE_ID_MAXIMUM:
2235         default:
2236                 return -EINVAL;
2237         }
2238
2239         return 0;
2240 }
2241
2242 static void psp_print_fw_hdr(struct psp_context *psp,
2243                              struct amdgpu_firmware_info *ucode)
2244 {
2245         struct amdgpu_device *adev = psp->adev;
2246         struct common_firmware_header *hdr;
2247
2248         switch (ucode->ucode_id) {
2249         case AMDGPU_UCODE_ID_SDMA0:
2250         case AMDGPU_UCODE_ID_SDMA1:
2251         case AMDGPU_UCODE_ID_SDMA2:
2252         case AMDGPU_UCODE_ID_SDMA3:
2253         case AMDGPU_UCODE_ID_SDMA4:
2254         case AMDGPU_UCODE_ID_SDMA5:
2255         case AMDGPU_UCODE_ID_SDMA6:
2256         case AMDGPU_UCODE_ID_SDMA7:
2257                 hdr = (struct common_firmware_header *)
2258                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2259                 amdgpu_ucode_print_sdma_hdr(hdr);
2260                 break;
2261         case AMDGPU_UCODE_ID_CP_CE:
2262                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2263                 amdgpu_ucode_print_gfx_hdr(hdr);
2264                 break;
2265         case AMDGPU_UCODE_ID_CP_PFP:
2266                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2267                 amdgpu_ucode_print_gfx_hdr(hdr);
2268                 break;
2269         case AMDGPU_UCODE_ID_CP_ME:
2270                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2271                 amdgpu_ucode_print_gfx_hdr(hdr);
2272                 break;
2273         case AMDGPU_UCODE_ID_CP_MEC1:
2274                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2275                 amdgpu_ucode_print_gfx_hdr(hdr);
2276                 break;
2277         case AMDGPU_UCODE_ID_RLC_G:
2278                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2279                 amdgpu_ucode_print_rlc_hdr(hdr);
2280                 break;
2281         case AMDGPU_UCODE_ID_SMC:
2282                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2283                 amdgpu_ucode_print_smc_hdr(hdr);
2284                 break;
2285         default:
2286                 break;
2287         }
2288 }
2289
2290 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2291                                        struct psp_gfx_cmd_resp *cmd)
2292 {
2293         int ret;
2294         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2295
2296         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2297         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2298         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2299         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2300
2301         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2302         if (ret)
2303                 DRM_ERROR("Unknown firmware type\n");
2304
2305         return ret;
2306 }
2307
2308 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2309                                   struct amdgpu_firmware_info *ucode)
2310 {
2311         int ret = 0;
2312         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2313
2314         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2315         if (!ret) {
2316                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2317                                          psp->fence_buf_mc_addr);
2318         }
2319
2320         release_psp_cmd_buf(psp);
2321
2322         return ret;
2323 }
2324
2325 static int psp_load_smu_fw(struct psp_context *psp)
2326 {
2327         int ret;
2328         struct amdgpu_device *adev = psp->adev;
2329         struct amdgpu_firmware_info *ucode =
2330                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2331         struct amdgpu_ras *ras = psp->ras_context.ras;
2332
2333         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2334                 return 0;
2335
2336         if ((amdgpu_in_reset(adev) &&
2337              ras && adev->ras_enabled &&
2338              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2339               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2340                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2341                 if (ret) {
2342                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2343                 }
2344         }
2345
2346         ret = psp_execute_non_psp_fw_load(psp, ucode);
2347
2348         if (ret)
2349                 DRM_ERROR("PSP load smu failed!\n");
2350
2351         return ret;
2352 }
2353
2354 static bool fw_load_skip_check(struct psp_context *psp,
2355                                struct amdgpu_firmware_info *ucode)
2356 {
2357         if (!ucode->fw)
2358                 return true;
2359
2360         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2361             (psp_smu_reload_quirk(psp) ||
2362              psp->autoload_supported ||
2363              psp->pmfw_centralized_cstate_management))
2364                 return true;
2365
2366         if (amdgpu_sriov_vf(psp->adev) &&
2367            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2368             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2369             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2370             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2371             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2372             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2373             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2374             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2375             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2376             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2377             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2378             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2379             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2380                 /*skip ucode loading in SRIOV VF */
2381                 return true;
2382
2383         if (psp->autoload_supported &&
2384             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2385              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2386                 /* skip mec JT when autoload is enabled */
2387                 return true;
2388
2389         return false;
2390 }
2391
2392 int psp_load_fw_list(struct psp_context *psp,
2393                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2394 {
2395         int ret = 0, i;
2396         struct amdgpu_firmware_info *ucode;
2397
2398         for (i = 0; i < ucode_count; ++i) {
2399                 ucode = ucode_list[i];
2400                 psp_print_fw_hdr(psp, ucode);
2401                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2402                 if (ret)
2403                         return ret;
2404         }
2405         return ret;
2406 }
2407
2408 static int psp_load_non_psp_fw(struct psp_context *psp)
2409 {
2410         int i, ret;
2411         struct amdgpu_firmware_info *ucode;
2412         struct amdgpu_device *adev = psp->adev;
2413
2414         if (psp->autoload_supported &&
2415             !psp->pmfw_centralized_cstate_management) {
2416                 ret = psp_load_smu_fw(psp);
2417                 if (ret)
2418                         return ret;
2419         }
2420
2421         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2422                 ucode = &adev->firmware.ucode[i];
2423
2424                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2425                     !fw_load_skip_check(psp, ucode)) {
2426                         ret = psp_load_smu_fw(psp);
2427                         if (ret)
2428                                 return ret;
2429                         continue;
2430                 }
2431
2432                 if (fw_load_skip_check(psp, ucode))
2433                         continue;
2434
2435                 if (psp->autoload_supported &&
2436                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2437                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2438                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2439                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2440                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2441                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2442                         /* PSP only receive one SDMA fw for sienna_cichlid,
2443                          * as all four sdma fw are same */
2444                         continue;
2445
2446                 psp_print_fw_hdr(psp, ucode);
2447
2448                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2449                 if (ret)
2450                         return ret;
2451
2452                 /* Start rlc autoload after psp recieved all the gfx firmware */
2453                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2454                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2455                         ret = psp_rlc_autoload_start(psp);
2456                         if (ret) {
2457                                 DRM_ERROR("Failed to start rlc autoload\n");
2458                                 return ret;
2459                         }
2460                 }
2461         }
2462
2463         return 0;
2464 }
2465
2466 static int psp_load_fw(struct amdgpu_device *adev)
2467 {
2468         int ret;
2469         struct psp_context *psp = &adev->psp;
2470
2471         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2472                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2473                 goto skip_memalloc;
2474         }
2475
2476         if (amdgpu_sriov_vf(adev)) {
2477                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2478                                                 AMDGPU_GEM_DOMAIN_VRAM,
2479                                                 &psp->fw_pri_bo,
2480                                                 &psp->fw_pri_mc_addr,
2481                                                 &psp->fw_pri_buf);
2482         } else {
2483                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2484                                                 AMDGPU_GEM_DOMAIN_GTT,
2485                                                 &psp->fw_pri_bo,
2486                                                 &psp->fw_pri_mc_addr,
2487                                                 &psp->fw_pri_buf);
2488         }
2489
2490         if (ret)
2491                 goto failed;
2492
2493         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2494                                         AMDGPU_GEM_DOMAIN_VRAM,
2495                                         &psp->fence_buf_bo,
2496                                         &psp->fence_buf_mc_addr,
2497                                         &psp->fence_buf);
2498         if (ret)
2499                 goto failed;
2500
2501         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2502                                       AMDGPU_GEM_DOMAIN_VRAM,
2503                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2504                                       (void **)&psp->cmd_buf_mem);
2505         if (ret)
2506                 goto failed;
2507
2508         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2509
2510         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2511         if (ret) {
2512                 DRM_ERROR("PSP ring init failed!\n");
2513                 goto failed;
2514         }
2515
2516 skip_memalloc:
2517         ret = psp_hw_start(psp);
2518         if (ret)
2519                 goto failed;
2520
2521         ret = psp_load_non_psp_fw(psp);
2522         if (ret)
2523                 goto failed;
2524
2525         ret = psp_asd_initialize(psp);
2526         if (ret) {
2527                 DRM_ERROR("PSP load asd failed!\n");
2528                 return ret;
2529         }
2530
2531         ret = psp_rl_load(adev);
2532         if (ret) {
2533                 DRM_ERROR("PSP load RL failed!\n");
2534                 return ret;
2535         }
2536
2537         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2538                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2539                         ret = psp_xgmi_initialize(psp, false, true);
2540                         /* Warning the XGMI seesion initialize failure
2541                         * Instead of stop driver initialization
2542                         */
2543                         if (ret)
2544                                 dev_err(psp->adev->dev,
2545                                         "XGMI: Failed to initialize XGMI session\n");
2546                 }
2547         }
2548
2549         if (psp->ta_fw) {
2550                 ret = psp_ras_initialize(psp);
2551                 if (ret)
2552                         dev_err(psp->adev->dev,
2553                                         "RAS: Failed to initialize RAS\n");
2554
2555                 ret = psp_hdcp_initialize(psp);
2556                 if (ret)
2557                         dev_err(psp->adev->dev,
2558                                 "HDCP: Failed to initialize HDCP\n");
2559
2560                 ret = psp_dtm_initialize(psp);
2561                 if (ret)
2562                         dev_err(psp->adev->dev,
2563                                 "DTM: Failed to initialize DTM\n");
2564
2565                 ret = psp_rap_initialize(psp);
2566                 if (ret)
2567                         dev_err(psp->adev->dev,
2568                                 "RAP: Failed to initialize RAP\n");
2569
2570                 ret = psp_securedisplay_initialize(psp);
2571                 if (ret)
2572                         dev_err(psp->adev->dev,
2573                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2574         }
2575
2576         return 0;
2577
2578 failed:
2579         /*
2580          * all cleanup jobs (xgmi terminate, ras terminate,
2581          * ring destroy, cmd/fence/fw buffers destory,
2582          * psp->cmd destory) are delayed to psp_hw_fini
2583          */
2584         return ret;
2585 }
2586
2587 static int psp_hw_init(void *handle)
2588 {
2589         int ret;
2590         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2591
2592         mutex_lock(&adev->firmware.mutex);
2593         /*
2594          * This sequence is just used on hw_init only once, no need on
2595          * resume.
2596          */
2597         ret = amdgpu_ucode_init_bo(adev);
2598         if (ret)
2599                 goto failed;
2600
2601         ret = psp_load_fw(adev);
2602         if (ret) {
2603                 DRM_ERROR("PSP firmware loading failed\n");
2604                 goto failed;
2605         }
2606
2607         mutex_unlock(&adev->firmware.mutex);
2608         return 0;
2609
2610 failed:
2611         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2612         mutex_unlock(&adev->firmware.mutex);
2613         return -EINVAL;
2614 }
2615
2616 static int psp_hw_fini(void *handle)
2617 {
2618         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2619         struct psp_context *psp = &adev->psp;
2620
2621         if (psp->ta_fw) {
2622                 psp_ras_terminate(psp);
2623                 psp_securedisplay_terminate(psp);
2624                 psp_rap_terminate(psp);
2625                 psp_dtm_terminate(psp);
2626                 psp_hdcp_terminate(psp);
2627         }
2628
2629         psp_asd_terminate(psp);
2630
2631         psp_tmr_terminate(psp);
2632         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2633
2634         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2635                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2636         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2637                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2638         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2639                               (void **)&psp->cmd_buf_mem);
2640
2641         return 0;
2642 }
2643
2644 static int psp_suspend(void *handle)
2645 {
2646         int ret;
2647         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2648         struct psp_context *psp = &adev->psp;
2649
2650         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2651             psp->xgmi_context.context.initialized) {
2652                 ret = psp_xgmi_terminate(psp);
2653                 if (ret) {
2654                         DRM_ERROR("Failed to terminate xgmi ta\n");
2655                         return ret;
2656                 }
2657         }
2658
2659         if (psp->ta_fw) {
2660                 ret = psp_ras_terminate(psp);
2661                 if (ret) {
2662                         DRM_ERROR("Failed to terminate ras ta\n");
2663                         return ret;
2664                 }
2665                 ret = psp_hdcp_terminate(psp);
2666                 if (ret) {
2667                         DRM_ERROR("Failed to terminate hdcp ta\n");
2668                         return ret;
2669                 }
2670                 ret = psp_dtm_terminate(psp);
2671                 if (ret) {
2672                         DRM_ERROR("Failed to terminate dtm ta\n");
2673                         return ret;
2674                 }
2675                 ret = psp_rap_terminate(psp);
2676                 if (ret) {
2677                         DRM_ERROR("Failed to terminate rap ta\n");
2678                         return ret;
2679                 }
2680                 ret = psp_securedisplay_terminate(psp);
2681                 if (ret) {
2682                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2683                         return ret;
2684                 }
2685         }
2686
2687         ret = psp_asd_terminate(psp);
2688         if (ret) {
2689                 DRM_ERROR("Failed to terminate asd\n");
2690                 return ret;
2691         }
2692
2693         ret = psp_tmr_terminate(psp);
2694         if (ret) {
2695                 DRM_ERROR("Failed to terminate tmr\n");
2696                 return ret;
2697         }
2698
2699         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2700         if (ret) {
2701                 DRM_ERROR("PSP ring stop failed\n");
2702                 return ret;
2703         }
2704
2705         return 0;
2706 }
2707
2708 static int psp_resume(void *handle)
2709 {
2710         int ret;
2711         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2712         struct psp_context *psp = &adev->psp;
2713
2714         DRM_INFO("PSP is resuming...\n");
2715
2716         if (psp->mem_train_ctx.enable_mem_training) {
2717                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2718                 if (ret) {
2719                         DRM_ERROR("Failed to process memory training!\n");
2720                         return ret;
2721                 }
2722         }
2723
2724         mutex_lock(&adev->firmware.mutex);
2725
2726         ret = psp_hw_start(psp);
2727         if (ret)
2728                 goto failed;
2729
2730         ret = psp_load_non_psp_fw(psp);
2731         if (ret)
2732                 goto failed;
2733
2734         ret = psp_asd_initialize(psp);
2735         if (ret) {
2736                 DRM_ERROR("PSP load asd failed!\n");
2737                 goto failed;
2738         }
2739
2740         ret = psp_rl_load(adev);
2741         if (ret) {
2742                 dev_err(adev->dev, "PSP load RL failed!\n");
2743                 goto failed;
2744         }
2745
2746         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2747                 ret = psp_xgmi_initialize(psp, false, true);
2748                 /* Warning the XGMI seesion initialize failure
2749                  * Instead of stop driver initialization
2750                  */
2751                 if (ret)
2752                         dev_err(psp->adev->dev,
2753                                 "XGMI: Failed to initialize XGMI session\n");
2754         }
2755
2756         if (psp->ta_fw) {
2757                 ret = psp_ras_initialize(psp);
2758                 if (ret)
2759                         dev_err(psp->adev->dev,
2760                                         "RAS: Failed to initialize RAS\n");
2761
2762                 ret = psp_hdcp_initialize(psp);
2763                 if (ret)
2764                         dev_err(psp->adev->dev,
2765                                 "HDCP: Failed to initialize HDCP\n");
2766
2767                 ret = psp_dtm_initialize(psp);
2768                 if (ret)
2769                         dev_err(psp->adev->dev,
2770                                 "DTM: Failed to initialize DTM\n");
2771
2772                 ret = psp_rap_initialize(psp);
2773                 if (ret)
2774                         dev_err(psp->adev->dev,
2775                                 "RAP: Failed to initialize RAP\n");
2776
2777                 ret = psp_securedisplay_initialize(psp);
2778                 if (ret)
2779                         dev_err(psp->adev->dev,
2780                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2781         }
2782
2783         mutex_unlock(&adev->firmware.mutex);
2784
2785         return 0;
2786
2787 failed:
2788         DRM_ERROR("PSP resume failed\n");
2789         mutex_unlock(&adev->firmware.mutex);
2790         return ret;
2791 }
2792
2793 int psp_gpu_reset(struct amdgpu_device *adev)
2794 {
2795         int ret;
2796
2797         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2798                 return 0;
2799
2800         mutex_lock(&adev->psp.mutex);
2801         ret = psp_mode1_reset(&adev->psp);
2802         mutex_unlock(&adev->psp.mutex);
2803
2804         return ret;
2805 }
2806
2807 int psp_rlc_autoload_start(struct psp_context *psp)
2808 {
2809         int ret;
2810         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2811
2812         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2813
2814         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2815                                  psp->fence_buf_mc_addr);
2816
2817         release_psp_cmd_buf(psp);
2818
2819         return ret;
2820 }
2821
2822 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2823                         uint64_t cmd_gpu_addr, int cmd_size)
2824 {
2825         struct amdgpu_firmware_info ucode = {0};
2826
2827         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2828                 AMDGPU_UCODE_ID_VCN0_RAM;
2829         ucode.mc_addr = cmd_gpu_addr;
2830         ucode.ucode_size = cmd_size;
2831
2832         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2833 }
2834
2835 int psp_ring_cmd_submit(struct psp_context *psp,
2836                         uint64_t cmd_buf_mc_addr,
2837                         uint64_t fence_mc_addr,
2838                         int index)
2839 {
2840         unsigned int psp_write_ptr_reg = 0;
2841         struct psp_gfx_rb_frame *write_frame;
2842         struct psp_ring *ring = &psp->km_ring;
2843         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2844         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2845                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2846         struct amdgpu_device *adev = psp->adev;
2847         uint32_t ring_size_dw = ring->ring_size / 4;
2848         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2849
2850         /* KM (GPCOM) prepare write pointer */
2851         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2852
2853         /* Update KM RB frame pointer to new frame */
2854         /* write_frame ptr increments by size of rb_frame in bytes */
2855         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2856         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2857                 write_frame = ring_buffer_start;
2858         else
2859                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2860         /* Check invalid write_frame ptr address */
2861         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2862                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2863                           ring_buffer_start, ring_buffer_end, write_frame);
2864                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2865                 return -EINVAL;
2866         }
2867
2868         /* Initialize KM RB frame */
2869         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2870
2871         /* Update KM RB frame */
2872         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2873         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2874         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2875         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2876         write_frame->fence_value = index;
2877         amdgpu_device_flush_hdp(adev, NULL);
2878
2879         /* Update the write Pointer in DWORDs */
2880         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2881         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2882         return 0;
2883 }
2884
2885 int psp_init_asd_microcode(struct psp_context *psp,
2886                            const char *chip_name)
2887 {
2888         struct amdgpu_device *adev = psp->adev;
2889         char fw_name[PSP_FW_NAME_LEN];
2890         const struct psp_firmware_header_v1_0 *asd_hdr;
2891         int err = 0;
2892
2893         if (!chip_name) {
2894                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2895                 return -EINVAL;
2896         }
2897
2898         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2899         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2900         if (err)
2901                 goto out;
2902
2903         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2904         if (err)
2905                 goto out;
2906
2907         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2908         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2909         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2910         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2911         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2912                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2913         return 0;
2914 out:
2915         dev_err(adev->dev, "fail to initialize asd microcode\n");
2916         release_firmware(adev->psp.asd_fw);
2917         adev->psp.asd_fw = NULL;
2918         return err;
2919 }
2920
2921 int psp_init_toc_microcode(struct psp_context *psp,
2922                            const char *chip_name)
2923 {
2924         struct amdgpu_device *adev = psp->adev;
2925         char fw_name[PSP_FW_NAME_LEN];
2926         const struct psp_firmware_header_v1_0 *toc_hdr;
2927         int err = 0;
2928
2929         if (!chip_name) {
2930                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2931                 return -EINVAL;
2932         }
2933
2934         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2935         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2936         if (err)
2937                 goto out;
2938
2939         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2940         if (err)
2941                 goto out;
2942
2943         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2944         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2945         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2946         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2947         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2948                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2949         return 0;
2950 out:
2951         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2952         release_firmware(adev->psp.toc_fw);
2953         adev->psp.toc_fw = NULL;
2954         return err;
2955 }
2956
2957 static int parse_sos_bin_descriptor(struct psp_context *psp,
2958                                    const struct psp_fw_bin_desc *desc,
2959                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2960 {
2961         uint8_t *ucode_start_addr  = NULL;
2962
2963         if (!psp || !desc || !sos_hdr)
2964                 return -EINVAL;
2965
2966         ucode_start_addr  = (uint8_t *)sos_hdr +
2967                             le32_to_cpu(desc->offset_bytes) +
2968                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2969
2970         switch (desc->fw_type) {
2971         case PSP_FW_TYPE_PSP_SOS:
2972                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2973                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2974                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2975                 psp->sos.start_addr        = ucode_start_addr;
2976                 break;
2977         case PSP_FW_TYPE_PSP_SYS_DRV:
2978                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2979                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2980                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2981                 psp->sys.start_addr        = ucode_start_addr;
2982                 break;
2983         case PSP_FW_TYPE_PSP_KDB:
2984                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2985                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2986                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2987                 psp->kdb.start_addr        = ucode_start_addr;
2988                 break;
2989         case PSP_FW_TYPE_PSP_TOC:
2990                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2991                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2992                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2993                 psp->toc.start_addr        = ucode_start_addr;
2994                 break;
2995         case PSP_FW_TYPE_PSP_SPL:
2996                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2997                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2998                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2999                 psp->spl.start_addr        = ucode_start_addr;
3000                 break;
3001         case PSP_FW_TYPE_PSP_RL:
3002                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3003                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3004                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3005                 psp->rl.start_addr         = ucode_start_addr;
3006                 break;
3007         case PSP_FW_TYPE_PSP_SOC_DRV:
3008                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3009                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3010                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3011                 psp->soc_drv.start_addr         = ucode_start_addr;
3012                 break;
3013         case PSP_FW_TYPE_PSP_INTF_DRV:
3014                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3015                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3016                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3017                 psp->intf_drv.start_addr        = ucode_start_addr;
3018                 break;
3019         case PSP_FW_TYPE_PSP_DBG_DRV:
3020                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3021                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3022                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3023                 psp->dbg_drv.start_addr         = ucode_start_addr;
3024                 break;
3025         default:
3026                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3027                 break;
3028         }
3029
3030         return 0;
3031 }
3032
3033 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3034 {
3035         const struct psp_firmware_header_v1_0 *sos_hdr;
3036         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3037         uint8_t *ucode_array_start_addr;
3038
3039         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3040         ucode_array_start_addr = (uint8_t *)sos_hdr +
3041                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3042
3043         if (adev->gmc.xgmi.connected_to_cpu ||
3044             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3045                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3046                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3047
3048                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3049                 adev->psp.sys.start_addr = ucode_array_start_addr;
3050
3051                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3052                 adev->psp.sos.start_addr = ucode_array_start_addr +
3053                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3054         } else {
3055                 /* Load alternate PSP SOS FW */
3056                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3057
3058                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3059                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3060
3061                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3062                 adev->psp.sys.start_addr = ucode_array_start_addr +
3063                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3064
3065                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3066                 adev->psp.sos.start_addr = ucode_array_start_addr +
3067                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3068         }
3069
3070         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3071                 dev_warn(adev->dev, "PSP SOS FW not available");
3072                 return -EINVAL;
3073         }
3074
3075         return 0;
3076 }
3077
3078 int psp_init_sos_microcode(struct psp_context *psp,
3079                            const char *chip_name)
3080 {
3081         struct amdgpu_device *adev = psp->adev;
3082         char fw_name[PSP_FW_NAME_LEN];
3083         const struct psp_firmware_header_v1_0 *sos_hdr;
3084         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3085         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3086         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3087         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3088         int err = 0;
3089         uint8_t *ucode_array_start_addr;
3090         int fw_index = 0;
3091
3092         if (!chip_name) {
3093                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3094                 return -EINVAL;
3095         }
3096
3097         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3098         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3099         if (err)
3100                 goto out;
3101
3102         err = amdgpu_ucode_validate(adev->psp.sos_fw);
3103         if (err)
3104                 goto out;
3105
3106         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3107         ucode_array_start_addr = (uint8_t *)sos_hdr +
3108                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3109         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3110
3111         switch (sos_hdr->header.header_version_major) {
3112         case 1:
3113                 err = psp_init_sos_base_fw(adev);
3114                 if (err)
3115                         goto out;
3116
3117                 if (sos_hdr->header.header_version_minor == 1) {
3118                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3119                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3120                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3121                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3122                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3123                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3124                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3125                 }
3126                 if (sos_hdr->header.header_version_minor == 2) {
3127                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3128                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3129                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3130                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3131                 }
3132                 if (sos_hdr->header.header_version_minor == 3) {
3133                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3134                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3135                         adev->psp.toc.start_addr = ucode_array_start_addr +
3136                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3137                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3138                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3139                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3140                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3141                         adev->psp.spl.start_addr = ucode_array_start_addr +
3142                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3143                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3144                         adev->psp.rl.start_addr = ucode_array_start_addr +
3145                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3146                 }
3147                 break;
3148         case 2:
3149                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3150
3151                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3152                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3153                         err = -EINVAL;
3154                         goto out;
3155                 }
3156
3157                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3158                         err = parse_sos_bin_descriptor(psp,
3159                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3160                                                        sos_hdr_v2_0);
3161                         if (err)
3162                                 goto out;
3163                 }
3164                 break;
3165         default:
3166                 dev_err(adev->dev,
3167                         "unsupported psp sos firmware\n");
3168                 err = -EINVAL;
3169                 goto out;
3170         }
3171
3172         return 0;
3173 out:
3174         dev_err(adev->dev,
3175                 "failed to init sos firmware\n");
3176         release_firmware(adev->psp.sos_fw);
3177         adev->psp.sos_fw = NULL;
3178
3179         return err;
3180 }
3181
3182 static int parse_ta_bin_descriptor(struct psp_context *psp,
3183                                    const struct psp_fw_bin_desc *desc,
3184                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3185 {
3186         uint8_t *ucode_start_addr  = NULL;
3187
3188         if (!psp || !desc || !ta_hdr)
3189                 return -EINVAL;
3190
3191         ucode_start_addr  = (uint8_t *)ta_hdr +
3192                             le32_to_cpu(desc->offset_bytes) +
3193                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3194
3195         switch (desc->fw_type) {
3196         case TA_FW_TYPE_PSP_ASD:
3197                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3198                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3199                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3200                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3201                 break;
3202         case TA_FW_TYPE_PSP_XGMI:
3203                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3204                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3205                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3206                 break;
3207         case TA_FW_TYPE_PSP_RAS:
3208                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3209                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3210                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3211                 break;
3212         case TA_FW_TYPE_PSP_HDCP:
3213                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3214                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3215                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3216                 break;
3217         case TA_FW_TYPE_PSP_DTM:
3218                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3219                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3220                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3221                 break;
3222         case TA_FW_TYPE_PSP_RAP:
3223                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3224                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3225                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3226                 break;
3227         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3228                 psp->securedisplay_context.context.bin_desc.fw_version =
3229                         le32_to_cpu(desc->fw_version);
3230                 psp->securedisplay_context.context.bin_desc.size_bytes =
3231                         le32_to_cpu(desc->size_bytes);
3232                 psp->securedisplay_context.context.bin_desc.start_addr =
3233                         ucode_start_addr;
3234                 break;
3235         default:
3236                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3237                 break;
3238         }
3239
3240         return 0;
3241 }
3242
3243 int psp_init_ta_microcode(struct psp_context *psp,
3244                           const char *chip_name)
3245 {
3246         struct amdgpu_device *adev = psp->adev;
3247         char fw_name[PSP_FW_NAME_LEN];
3248         const struct ta_firmware_header_v2_0 *ta_hdr;
3249         int err = 0;
3250         int ta_index = 0;
3251
3252         if (!chip_name) {
3253                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3254                 return -EINVAL;
3255         }
3256
3257         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3258         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3259         if (err)
3260                 goto out;
3261
3262         err = amdgpu_ucode_validate(adev->psp.ta_fw);
3263         if (err)
3264                 goto out;
3265
3266         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3267
3268         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3269                 dev_err(adev->dev, "unsupported TA header version\n");
3270                 err = -EINVAL;
3271                 goto out;
3272         }
3273
3274         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3275                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3276                 err = -EINVAL;
3277                 goto out;
3278         }
3279
3280         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3281                 err = parse_ta_bin_descriptor(psp,
3282                                               &ta_hdr->ta_fw_bin[ta_index],
3283                                               ta_hdr);
3284                 if (err)
3285                         goto out;
3286         }
3287
3288         return 0;
3289 out:
3290         dev_err(adev->dev, "fail to initialize ta microcode\n");
3291         release_firmware(adev->psp.ta_fw);
3292         adev->psp.ta_fw = NULL;
3293         return err;
3294 }
3295
3296 int psp_init_cap_microcode(struct psp_context *psp,
3297                           const char *chip_name)
3298 {
3299         struct amdgpu_device *adev = psp->adev;
3300         char fw_name[PSP_FW_NAME_LEN];
3301         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3302         struct amdgpu_firmware_info *info = NULL;
3303         int err = 0;
3304
3305         if (!chip_name) {
3306                 dev_err(adev->dev, "invalid chip name for cap microcode\n");
3307                 return -EINVAL;
3308         }
3309
3310         if (!amdgpu_sriov_vf(adev)) {
3311                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3312                 return -EINVAL;
3313         }
3314
3315         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3316         err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3317         if (err) {
3318                 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3319                 err = 0;
3320                 goto out;
3321         }
3322
3323         err = amdgpu_ucode_validate(adev->psp.cap_fw);
3324         if (err) {
3325                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3326                 goto out;
3327         }
3328
3329         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3330         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3331         info->fw = adev->psp.cap_fw;
3332         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3333                 adev->psp.cap_fw->data;
3334         adev->firmware.fw_size += ALIGN(
3335                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3336         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3337         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3338         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3339
3340         return 0;
3341
3342 out:
3343         release_firmware(adev->psp.cap_fw);
3344         adev->psp.cap_fw = NULL;
3345         return err;
3346 }
3347
3348 static int psp_set_clockgating_state(void *handle,
3349                                      enum amd_clockgating_state state)
3350 {
3351         return 0;
3352 }
3353
3354 static int psp_set_powergating_state(void *handle,
3355                                      enum amd_powergating_state state)
3356 {
3357         return 0;
3358 }
3359
3360 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3361                                          struct device_attribute *attr,
3362                                          char *buf)
3363 {
3364         struct drm_device *ddev = dev_get_drvdata(dev);
3365         struct amdgpu_device *adev = drm_to_adev(ddev);
3366         uint32_t fw_ver;
3367         int ret;
3368
3369         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3370                 DRM_INFO("PSP block is not ready yet.");
3371                 return -EBUSY;
3372         }
3373
3374         mutex_lock(&adev->psp.mutex);
3375         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3376         mutex_unlock(&adev->psp.mutex);
3377
3378         if (ret) {
3379                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3380                 return ret;
3381         }
3382
3383         return sysfs_emit(buf, "%x\n", fw_ver);
3384 }
3385
3386 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3387                                                        struct device_attribute *attr,
3388                                                        const char *buf,
3389                                                        size_t count)
3390 {
3391         struct drm_device *ddev = dev_get_drvdata(dev);
3392         struct amdgpu_device *adev = drm_to_adev(ddev);
3393         int ret, idx;
3394         char fw_name[100];
3395         const struct firmware *usbc_pd_fw;
3396         struct amdgpu_bo *fw_buf_bo = NULL;
3397         uint64_t fw_pri_mc_addr;
3398         void *fw_pri_cpu_addr;
3399
3400         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3401                 DRM_INFO("PSP block is not ready yet.");
3402                 return -EBUSY;
3403         }
3404
3405         if (!drm_dev_enter(ddev, &idx))
3406                 return -ENODEV;
3407
3408         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3409         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3410         if (ret)
3411                 goto fail;
3412
3413         /* LFB address which is aligned to 1MB boundary per PSP request */
3414         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3415                                                 AMDGPU_GEM_DOMAIN_VRAM,
3416                                                 &fw_buf_bo,
3417                                                 &fw_pri_mc_addr,
3418                                                 &fw_pri_cpu_addr);
3419         if (ret)
3420                 goto rel_buf;
3421
3422         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3423
3424         mutex_lock(&adev->psp.mutex);
3425         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3426         mutex_unlock(&adev->psp.mutex);
3427
3428         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3429
3430 rel_buf:
3431         release_firmware(usbc_pd_fw);
3432 fail:
3433         if (ret) {
3434                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3435                 count = ret;
3436         }
3437
3438         drm_dev_exit(idx);
3439         return count;
3440 }
3441
3442 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3443 {
3444         int idx;
3445
3446         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3447                 return;
3448
3449         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3450         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3451
3452         drm_dev_exit(idx);
3453 }
3454
3455 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3456                    psp_usbc_pd_fw_sysfs_read,
3457                    psp_usbc_pd_fw_sysfs_write);
3458
3459 int is_psp_fw_valid(struct psp_bin_desc bin)
3460 {
3461         return bin.size_bytes;
3462 }
3463
3464 const struct amd_ip_funcs psp_ip_funcs = {
3465         .name = "psp",
3466         .early_init = psp_early_init,
3467         .late_init = NULL,
3468         .sw_init = psp_sw_init,
3469         .sw_fini = psp_sw_fini,
3470         .hw_init = psp_hw_init,
3471         .hw_fini = psp_hw_fini,
3472         .suspend = psp_suspend,
3473         .resume = psp_resume,
3474         .is_idle = NULL,
3475         .check_soft_reset = NULL,
3476         .wait_for_idle = NULL,
3477         .soft_reset = NULL,
3478         .set_clockgating_state = psp_set_clockgating_state,
3479         .set_powergating_state = psp_set_powergating_state,
3480 };
3481
3482 static int psp_sysfs_init(struct amdgpu_device *adev)
3483 {
3484         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3485
3486         if (ret)
3487                 DRM_ERROR("Failed to create USBC PD FW control file!");
3488
3489         return ret;
3490 }
3491
3492 static void psp_sysfs_fini(struct amdgpu_device *adev)
3493 {
3494         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3495 }
3496
3497 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3498 {
3499         .type = AMD_IP_BLOCK_TYPE_PSP,
3500         .major = 3,
3501         .minor = 1,
3502         .rev = 0,
3503         .funcs = &psp_ip_funcs,
3504 };
3505
3506 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3507 {
3508         .type = AMD_IP_BLOCK_TYPE_PSP,
3509         .major = 10,
3510         .minor = 0,
3511         .rev = 0,
3512         .funcs = &psp_ip_funcs,
3513 };
3514
3515 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3516 {
3517         .type = AMD_IP_BLOCK_TYPE_PSP,
3518         .major = 11,
3519         .minor = 0,
3520         .rev = 0,
3521         .funcs = &psp_ip_funcs,
3522 };
3523
3524 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3525         .type = AMD_IP_BLOCK_TYPE_PSP,
3526         .major = 11,
3527         .minor = 0,
3528         .rev = 8,
3529         .funcs = &psp_ip_funcs,
3530 };
3531
3532 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3533 {
3534         .type = AMD_IP_BLOCK_TYPE_PSP,
3535         .major = 12,
3536         .minor = 0,
3537         .rev = 0,
3538         .funcs = &psp_ip_funcs,
3539 };
3540
3541 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3542         .type = AMD_IP_BLOCK_TYPE_PSP,
3543         .major = 13,
3544         .minor = 0,
3545         .rev = 0,
3546         .funcs = &psp_ip_funcs,
3547 };