drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include "amdgpu_cs.h"
  36 #include "amdgpu.h"
  37 #include "amdgpu_trace.h"
  38 #include "amdgpu_gmc.h"
  39 #include "amdgpu_gem.h"
  40 #include "amdgpu_ras.h"
  41
  42 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
  43                                  struct amdgpu_device *adev,
  44                                  struct drm_file *filp,
  45                                  union drm_amdgpu_cs *cs)
  46 {
  47         struct amdgpu_fpriv *fpriv = filp->driver_priv;
  48
  49         if (cs->in.num_chunks == 0)
  50                 return -EINVAL;
  51
  52         memset(p, 0, sizeof(*p));
  53         p->adev = adev;
  54         p->filp = filp;
  55
  56         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  57         if (!p->ctx)
  58                 return -EINVAL;
  59
  60         if (atomic_read(&p->ctx->guilty)) {
  61                 amdgpu_ctx_put(p->ctx);
  62                 return -ECANCELED;
  63         }
  64         return 0;
  65 }
  66
  67 static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
  68                              struct drm_amdgpu_cs_chunk_ib *chunk_ib)
  69 {
  70         struct drm_sched_entity *entity;
  71         unsigned int i;
  72         int r;
  73
  74         r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
  75                                   chunk_ib->ip_instance,
  76                                   chunk_ib->ring, &entity);
  77         if (r)
  78                 return r;
  79
  80         /*
  81          * Abort if there is no run queue associated with this entity.
  82          * Possibly because of disabled HW IP.
  83          */
  84         if (entity->rq == NULL)
  85                 return -EINVAL;
  86
  87         /* Check if we can add this IB to some existing job */
  88         for (i = 0; i < p->gang_size; ++i)
  89                 if (p->entities[i] == entity)
  90                         return i;
  91
  92         /* If not increase the gang size if possible */
  93         if (i == AMDGPU_CS_GANG_SIZE)
  94                 return -EINVAL;
  95
  96         p->entities[i] = entity;
  97         p->gang_size = i + 1;
  98         return i;
  99 }
 100
 101 static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
 102                            struct drm_amdgpu_cs_chunk_ib *chunk_ib,
 103                            unsigned int *num_ibs)
 104 {
 105         int r;
 106
 107         r = amdgpu_cs_job_idx(p, chunk_ib);
 108         if (r < 0)
 109                 return r;
 110
 111         ++(num_ibs[r]);
 112         return 0;
 113 }
 114
 115 static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
 116                                    struct drm_amdgpu_cs_chunk_fence *data,
 117                                    uint32_t *offset)
 118 {
 119         struct drm_gem_object *gobj;
 120         struct amdgpu_bo *bo;
 121         unsigned long size;
 122         int r;
 123
 124         gobj = drm_gem_object_lookup(p->filp, data->handle);
 125         if (gobj == NULL)
 126                 return -EINVAL;
 127
 128         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
 129         p->uf_entry.priority = 0;
 130         p->uf_entry.tv.bo = &bo->tbo;
 131         /* One for TTM and two for the CS job */
 132         p->uf_entry.tv.num_shared = 3;
 133
 134         drm_gem_object_put(gobj);
 135
 136         size = amdgpu_bo_size(bo);
 137         if (size != PAGE_SIZE || (data->offset + 8) > size) {
 138                 r = -EINVAL;
 139                 goto error_unref;
 140         }
 141
 142         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
 143                 r = -EINVAL;
 144                 goto error_unref;
 145         }
 146
 147         *offset = data->offset;
 148
 149         return 0;
 150
 151 error_unref:
 152         amdgpu_bo_unref(&bo);
 153         return r;
 154 }
 155
 156 static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
 157                                    struct drm_amdgpu_bo_list_in *data)
 158 {
 159         struct drm_amdgpu_bo_list_entry *info;
 160         int r;
 161
 162         r = amdgpu_bo_create_list_entry_array(data, &info);
 163         if (r)
 164                 return r;
 165
 166         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
 167                                   &p->bo_list);
 168         if (r)
 169                 goto error_free;
 170
 171         kvfree(info);
 172         return 0;
 173
 174 error_free:
 175         kvfree(info);
 176
 177         return r;
 178 }
 179
 180 /* Copy the data from userspace and go over it the first time */
 181 static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
 182                            union drm_amdgpu_cs *cs)
 183 {
 184         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 185         unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
 186         struct amdgpu_vm *vm = &fpriv->vm;
 187         uint64_t *chunk_array_user;
 188         uint64_t *chunk_array;
 189         uint32_t uf_offset = 0;
 190         unsigned int size;
 191         int ret;
 192         int i;
 193
 194         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
 195                                      GFP_KERNEL);
 196         if (!chunk_array)
 197                 return -ENOMEM;
 198
 199         /* get chunks */
 200         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 201         if (copy_from_user(chunk_array, chunk_array_user,
 202                            sizeof(uint64_t)*cs->in.num_chunks)) {
 203                 ret = -EFAULT;
 204                 goto free_chunk;
 205         }
 206
 207         p->nchunks = cs->in.num_chunks;
 208         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 209                             GFP_KERNEL);
 210         if (!p->chunks) {
 211                 ret = -ENOMEM;
 212                 goto free_chunk;
 213         }
 214
 215         for (i = 0; i < p->nchunks; i++) {
 216                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 217                 struct drm_amdgpu_cs_chunk user_chunk;
 218                 uint32_t __user *cdata;
 219
 220                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 221                 if (copy_from_user(&user_chunk, chunk_ptr,
 222                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 223                         ret = -EFAULT;
 224                         i--;
 225                         goto free_partial_kdata;
 226                 }
 227                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 228                 p->chunks[i].length_dw = user_chunk.length_dw;
 229
 230                 size = p->chunks[i].length_dw;
 231                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 232
 233                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
 234                                                     GFP_KERNEL);
 235                 if (p->chunks[i].kdata == NULL) {
 236                         ret = -ENOMEM;
 237                         i--;
 238                         goto free_partial_kdata;
 239                 }
 240                 size *= sizeof(uint32_t);
 241                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 242                         ret = -EFAULT;
 243                         goto free_partial_kdata;
 244                 }
 245
 246                 /* Assume the worst on the following checks */
 247                 ret = -EINVAL;
 248                 switch (p->chunks[i].chunk_id) {
 249                 case AMDGPU_CHUNK_ID_IB:
 250                         if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
 251                                 goto free_partial_kdata;
 252
 253                         ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
 254                         if (ret)
 255                                 goto free_partial_kdata;
 256                         break;
 257
 258                 case AMDGPU_CHUNK_ID_FENCE:
 259                         if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
 260                                 goto free_partial_kdata;
 261
 262                         ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
 263                                                       &uf_offset);
 264                         if (ret)
 265                                 goto free_partial_kdata;
 266                         break;
 267
 268                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 269                         if (size < sizeof(struct drm_amdgpu_bo_list_in))
 270                                 goto free_partial_kdata;
 271
 272                         ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
 273                         if (ret)
 274                                 goto free_partial_kdata;
 275                         break;
 276
 277                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 278                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 279                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 280                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 281                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 282                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 283                         break;
 284
 285                 default:
 286                         goto free_partial_kdata;
 287                 }
 288         }
 289
 290         if (!p->gang_size)
 291                 return -EINVAL;
 292
 293         for (i = 0; i < p->gang_size; ++i) {
 294                 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
 295                                        num_ibs[i], &p->jobs[i]);
 296                 if (ret)
 297                         goto free_all_kdata;
 298         }
 299         p->gang_leader = p->jobs[p->gang_size - 1];
 300
 301         if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {
 302                 ret = -ECANCELED;
 303                 goto free_all_kdata;
 304         }
 305
 306         if (p->uf_entry.tv.bo)
 307                 p->gang_leader->uf_addr = uf_offset;
 308         kvfree(chunk_array);
 309
 310         /* Use this opportunity to fill in task info for the vm */
 311         amdgpu_vm_set_task_info(vm);
 312
 313         return 0;
 314
 315 free_all_kdata:
 316         i = p->nchunks - 1;
 317 free_partial_kdata:
 318         for (; i >= 0; i--)
 319                 kvfree(p->chunks[i].kdata);
 320         kvfree(p->chunks);
 321         p->chunks = NULL;
 322         p->nchunks = 0;
 323 free_chunk:
 324         kvfree(chunk_array);
 325
 326         return ret;
 327 }
 328
 329 static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
 330                            struct amdgpu_cs_chunk *chunk,
 331                            unsigned int *ce_preempt,
 332                            unsigned int *de_preempt)
 333 {
 334         struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
 335         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 336         struct amdgpu_vm *vm = &fpriv->vm;
 337         struct amdgpu_ring *ring;
 338         struct amdgpu_job *job;
 339         struct amdgpu_ib *ib;
 340         int r;
 341
 342         r = amdgpu_cs_job_idx(p, chunk_ib);
 343         if (r < 0)
 344                 return r;
 345
 346         job = p->jobs[r];
 347         ring = amdgpu_job_ring(job);
 348         ib = &job->ibs[job->num_ibs++];
 349
 350         /* MM engine doesn't support user fences */
 351         if (p->uf_entry.tv.bo && ring->funcs->no_user_fence)
 352                 return -EINVAL;
 353
 354         if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 355             chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 356                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 357                         (*ce_preempt)++;
 358                 else
 359                         (*de_preempt)++;
 360
 361                 /* Each GFX command submit allows only 1 IB max
 362                  * preemptible for CE & DE */
 363                 if (*ce_preempt > 1 || *de_preempt > 1)
 364                         return -EINVAL;
 365         }
 366
 367         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 368                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 369
 370         r =  amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
 371                            chunk_ib->ib_bytes : 0,
 372                            AMDGPU_IB_POOL_DELAYED, ib);
 373         if (r) {
 374                 DRM_ERROR("Failed to get ib !\n");
 375                 return r;
 376         }
 377
 378         ib->gpu_addr = chunk_ib->va_start;
 379         ib->length_dw = chunk_ib->ib_bytes / 4;
 380         ib->flags = chunk_ib->flags;
 381         return 0;
 382 }
 383
 384 static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
 385                                      struct amdgpu_cs_chunk *chunk)
 386 {
 387         struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
 388         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 389         unsigned num_deps;
 390         int i, r;
 391
 392         num_deps = chunk->length_dw * 4 /
 393                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 394
 395         for (i = 0; i < num_deps; ++i) {
 396                 struct amdgpu_ctx *ctx;
 397                 struct drm_sched_entity *entity;
 398                 struct dma_fence *fence;
 399
 400                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 401                 if (ctx == NULL)
 402                         return -EINVAL;
 403
 404                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 405                                           deps[i].ip_instance,
 406                                           deps[i].ring, &entity);
 407                 if (r) {
 408                         amdgpu_ctx_put(ctx);
 409                         return r;
 410                 }
 411
 412                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 413                 amdgpu_ctx_put(ctx);
 414
 415                 if (IS_ERR(fence))
 416                         return PTR_ERR(fence);
 417                 else if (!fence)
 418                         continue;
 419
 420                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 421                         struct drm_sched_fence *s_fence;
 422                         struct dma_fence *old = fence;
 423
 424                         s_fence = to_drm_sched_fence(fence);
 425                         fence = dma_fence_get(&s_fence->scheduled);
 426                         dma_fence_put(old);
 427                 }
 428
 429                 r = amdgpu_sync_fence(&p->gang_leader->sync, fence);
 430                 dma_fence_put(fence);
 431                 if (r)
 432                         return r;
 433         }
 434         return 0;
 435 }
 436
 437 static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
 438                                          uint32_t handle, u64 point,
 439                                          u64 flags)
 440 {
 441         struct dma_fence *fence;
 442         int r;
 443
 444         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
 445         if (r) {
 446                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
 447                           handle, point, r);
 448                 return r;
 449         }
 450
 451         r = amdgpu_sync_fence(&p->gang_leader->sync, fence);
 452         dma_fence_put(fence);
 453
 454         return r;
 455 }
 456
 457 static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
 458                                    struct amdgpu_cs_chunk *chunk)
 459 {
 460         struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
 461         unsigned num_deps;
 462         int i, r;
 463
 464         num_deps = chunk->length_dw * 4 /
 465                 sizeof(struct drm_amdgpu_cs_chunk_sem);
 466         for (i = 0; i < num_deps; ++i) {
 467                 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
 468                 if (r)
 469                         return r;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
 476                                               struct amdgpu_cs_chunk *chunk)
 477 {
 478         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
 479         unsigned num_deps;
 480         int i, r;
 481
 482         num_deps = chunk->length_dw * 4 /
 483                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
 484         for (i = 0; i < num_deps; ++i) {
 485                 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
 486                                                   syncobj_deps[i].point,
 487                                                   syncobj_deps[i].flags);
 488                 if (r)
 489                         return r;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
 496                                     struct amdgpu_cs_chunk *chunk)
 497 {
 498         struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
 499         unsigned num_deps;
 500         int i;
 501
 502         num_deps = chunk->length_dw * 4 /
 503                 sizeof(struct drm_amdgpu_cs_chunk_sem);
 504
 505         if (p->post_deps)
 506                 return -EINVAL;
 507
 508         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
 509                                      GFP_KERNEL);
 510         p->num_post_deps = 0;
 511
 512         if (!p->post_deps)
 513                 return -ENOMEM;
 514
 515
 516         for (i = 0; i < num_deps; ++i) {
 517                 p->post_deps[i].syncobj =
 518                         drm_syncobj_find(p->filp, deps[i].handle);
 519                 if (!p->post_deps[i].syncobj)
 520                         return -EINVAL;
 521                 p->post_deps[i].chain = NULL;
 522                 p->post_deps[i].point = 0;
 523                 p->num_post_deps++;
 524         }
 525
 526         return 0;
 527 }
 528
 529 static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
 530                                                 struct amdgpu_cs_chunk *chunk)
 531 {
 532         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
 533         unsigned num_deps;
 534         int i;
 535
 536         num_deps = chunk->length_dw * 4 /
 537                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
 538
 539         if (p->post_deps)
 540                 return -EINVAL;
 541
 542         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
 543                                      GFP_KERNEL);
 544         p->num_post_deps = 0;
 545
 546         if (!p->post_deps)
 547                 return -ENOMEM;
 548
 549         for (i = 0; i < num_deps; ++i) {
 550                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
 551
 552                 dep->chain = NULL;
 553                 if (syncobj_deps[i].point) {
 554                         dep->chain = dma_fence_chain_alloc();
 555                         if (!dep->chain)
 556                                 return -ENOMEM;
 557                 }
 558
 559                 dep->syncobj = drm_syncobj_find(p->filp,
 560                                                 syncobj_deps[i].handle);
 561                 if (!dep->syncobj) {
 562                         dma_fence_chain_free(dep->chain);
 563                         return -EINVAL;
 564                 }
 565                 dep->point = syncobj_deps[i].point;
 566                 p->num_post_deps++;
 567         }
 568
 569         return 0;
 570 }
 571
 572 static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
 573 {
 574         unsigned int ce_preempt = 0, de_preempt = 0;
 575         int i, r;
 576
 577         for (i = 0; i < p->nchunks; ++i) {
 578                 struct amdgpu_cs_chunk *chunk;
 579
 580                 chunk = &p->chunks[i];
 581
 582                 switch (chunk->chunk_id) {
 583                 case AMDGPU_CHUNK_ID_IB:
 584                         r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
 585                         if (r)
 586                                 return r;
 587                         break;
 588                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 589                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 590                         r = amdgpu_cs_p2_dependencies(p, chunk);
 591                         if (r)
 592                                 return r;
 593                         break;
 594                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 595                         r = amdgpu_cs_p2_syncobj_in(p, chunk);
 596                         if (r)
 597                                 return r;
 598                         break;
 599                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 600                         r = amdgpu_cs_p2_syncobj_out(p, chunk);
 601                         if (r)
 602                                 return r;
 603                         break;
 604                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 605                         r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
 606                         if (r)
 607                                 return r;
 608                         break;
 609                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 610                         r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
 611                         if (r)
 612                                 return r;
 613                         break;
 614                 }
 615         }
 616
 617         return 0;
 618 }
 619
 620 /* Convert microseconds to bytes. */
 621 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 622 {
 623         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 624                 return 0;
 625
 626         /* Since accum_us is incremented by a million per second, just
 627          * multiply it by the number of MB/s to get the number of bytes.
 628          */
 629         return us << adev->mm_stats.log2_max_MBps;
 630 }
 631
 632 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 633 {
 634         if (!adev->mm_stats.log2_max_MBps)
 635                 return 0;
 636
 637         return bytes >> adev->mm_stats.log2_max_MBps;
 638 }
 639
 640 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 641  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 642  * which means it can go over the threshold once. If that happens, the driver
 643  * will be in debt and no other buffer migrations can be done until that debt
 644  * is repaid.
 645  *
 646  * This approach allows moving a buffer of any size (it's important to allow
 647  * that).
 648  *
 649  * The currency is simply time in microseconds and it increases as the clock
 650  * ticks. The accumulated microseconds (us) are converted to bytes and
 651  * returned.
 652  */
 653 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 654                                               u64 *max_bytes,
 655                                               u64 *max_vis_bytes)
 656 {
 657         s64 time_us, increment_us;
 658         u64 free_vram, total_vram, used_vram;
 659         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 660          * throttling.
 661          *
 662          * It means that in order to get full max MBps, at least 5 IBs per
 663          * second must be submitted and not more than 200ms apart from each
 664          * other.
 665          */
 666         const s64 us_upper_bound = 200000;
 667
 668         if (!adev->mm_stats.log2_max_MBps) {
 669                 *max_bytes = 0;
 670                 *max_vis_bytes = 0;
 671                 return;
 672         }
 673
 674         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 675         used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 676         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 677
 678         spin_lock(&adev->mm_stats.lock);
 679
 680         /* Increase the amount of accumulated us. */
 681         time_us = ktime_to_us(ktime_get());
 682         increment_us = time_us - adev->mm_stats.last_update_us;
 683         adev->mm_stats.last_update_us = time_us;
 684         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 685                                       us_upper_bound);
 686
 687         /* This prevents the short period of low performance when the VRAM
 688          * usage is low and the driver is in debt or doesn't have enough
 689          * accumulated us to fill VRAM quickly.
 690          *
 691          * The situation can occur in these cases:
 692          * - a lot of VRAM is freed by userspace
 693          * - the presence of a big buffer causes a lot of evictions
 694          *   (solution: split buffers into smaller ones)
 695          *
 696          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 697          * accum_us to a positive number.
 698          */
 699         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 700                 s64 min_us;
 701
 702                 /* Be more aggressive on dGPUs. Try to fill a portion of free
 703                  * VRAM now.
 704                  */
 705                 if (!(adev->flags & AMD_IS_APU))
 706                         min_us = bytes_to_us(adev, free_vram / 4);
 707                 else
 708                         min_us = 0; /* Reset accum_us on APUs. */
 709
 710                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 711         }
 712
 713         /* This is set to 0 if the driver is in debt to disallow (optional)
 714          * buffer moves.
 715          */
 716         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 717
 718         /* Do the same for visible VRAM if half of it is free */
 719         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 720                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 721                 u64 used_vis_vram =
 722                   amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 723
 724                 if (used_vis_vram < total_vis_vram) {
 725                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 726                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 727                                                           increment_us, us_upper_bound);
 728
 729                         if (free_vis_vram >= total_vis_vram / 2)
 730                                 adev->mm_stats.accum_us_vis =
 731                                         max(bytes_to_us(adev, free_vis_vram / 2),
 732                                             adev->mm_stats.accum_us_vis);
 733                 }
 734
 735                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 736         } else {
 737                 *max_vis_bytes = 0;
 738         }
 739
 740         spin_unlock(&adev->mm_stats.lock);
 741 }
 742
 743 /* Report how many bytes have really been moved for the last command
 744  * submission. This can result in a debt that can stop buffer migrations
 745  * temporarily.
 746  */
 747 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 748                                   u64 num_vis_bytes)
 749 {
 750         spin_lock(&adev->mm_stats.lock);
 751         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 752         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 753         spin_unlock(&adev->mm_stats.lock);
 754 }
 755
 756 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 757 {
 758         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 759         struct amdgpu_cs_parser *p = param;
 760         struct ttm_operation_ctx ctx = {
 761                 .interruptible = true,
 762                 .no_wait_gpu = false,
 763                 .resv = bo->tbo.base.resv
 764         };
 765         uint32_t domain;
 766         int r;
 767
 768         if (bo->tbo.pin_count)
 769                 return 0;
 770
 771         /* Don't move this buffer if we have depleted our allowance
 772          * to move it. Don't move anything if the threshold is zero.
 773          */
 774         if (p->bytes_moved < p->bytes_moved_threshold &&
 775             (!bo->tbo.base.dma_buf ||
 776             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 777                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 778                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 779                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 780                          * visible VRAM if we've depleted our allowance to do
 781                          * that.
 782                          */
 783                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 784                                 domain = bo->preferred_domains;
 785                         else
 786                                 domain = bo->allowed_domains;
 787                 } else {
 788                         domain = bo->preferred_domains;
 789                 }
 790         } else {
 791                 domain = bo->allowed_domains;
 792         }
 793
 794 retry:
 795         amdgpu_bo_placement_from_domain(bo, domain);
 796         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 797
 798         p->bytes_moved += ctx.bytes_moved;
 799         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 800             amdgpu_bo_in_cpu_visible_vram(bo))
 801                 p->bytes_moved_vis += ctx.bytes_moved;
 802
 803         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 804                 domain = bo->allowed_domains;
 805                 goto retry;
 806         }
 807
 808         return r;
 809 }
 810
 811 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 812                             struct list_head *validated)
 813 {
 814         struct ttm_operation_ctx ctx = { true, false };
 815         struct amdgpu_bo_list_entry *lobj;
 816         int r;
 817
 818         list_for_each_entry(lobj, validated, tv.head) {
 819                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 820                 struct mm_struct *usermm;
 821
 822                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 823                 if (usermm && usermm != current->mm)
 824                         return -EPERM;
 825
 826                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 827                     lobj->user_invalidated && lobj->user_pages) {
 828                         amdgpu_bo_placement_from_domain(bo,
 829                                                         AMDGPU_GEM_DOMAIN_CPU);
 830                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 831                         if (r)
 832                                 return r;
 833
 834                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 835                                                      lobj->user_pages);
 836                 }
 837
 838                 r = amdgpu_cs_bo_validate(p, bo);
 839                 if (r)
 840                         return r;
 841
 842                 kvfree(lobj->user_pages);
 843                 lobj->user_pages = NULL;
 844         }
 845         return 0;
 846 }
 847
 848 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 849                                 union drm_amdgpu_cs *cs)
 850 {
 851         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 852         struct amdgpu_vm *vm = &fpriv->vm;
 853         struct amdgpu_bo_list_entry *e;
 854         struct list_head duplicates;
 855         unsigned int i;
 856         int r;
 857
 858         INIT_LIST_HEAD(&p->validated);
 859
 860         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 861         if (cs->in.bo_list_handle) {
 862                 if (p->bo_list)
 863                         return -EINVAL;
 864
 865                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 866                                        &p->bo_list);
 867                 if (r)
 868                         return r;
 869         } else if (!p->bo_list) {
 870                 /* Create a empty bo_list when no handle is provided */
 871                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 872                                           &p->bo_list);
 873                 if (r)
 874                         return r;
 875         }
 876
 877         mutex_lock(&p->bo_list->bo_list_mutex);
 878
 879         /* One for TTM and one for the CS job */
 880         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 881                 e->tv.num_shared = 2;
 882
 883         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 884
 885         INIT_LIST_HEAD(&duplicates);
 886         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 887
 888         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 889                 list_add(&p->uf_entry.tv.head, &p->validated);
 890
 891         /* Get userptr backing pages. If pages are updated after registered
 892          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 893          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 894          */
 895         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 896                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 897                 bool userpage_invalidated = false;
 898                 int i;
 899
 900                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 901                                         sizeof(struct page *),
 902                                         GFP_KERNEL | __GFP_ZERO);
 903                 if (!e->user_pages) {
 904                         DRM_ERROR("kvmalloc_array failure\n");
 905                         r = -ENOMEM;
 906                         goto out_free_user_pages;
 907                 }
 908
 909                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 910                 if (r) {
 911                         kvfree(e->user_pages);
 912                         e->user_pages = NULL;
 913                         goto out_free_user_pages;
 914                 }
 915
 916                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 917                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 918                                 userpage_invalidated = true;
 919                                 break;
 920                         }
 921                 }
 922                 e->user_invalidated = userpage_invalidated;
 923         }
 924
 925         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 926                                    &duplicates);
 927         if (unlikely(r != 0)) {
 928                 if (r != -ERESTARTSYS)
 929                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 930                 goto out_free_user_pages;
 931         }
 932
 933         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 934                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 935
 936                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 937         }
 938
 939         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 940                                           &p->bytes_moved_vis_threshold);
 941         p->bytes_moved = 0;
 942         p->bytes_moved_vis = 0;
 943
 944         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 945                                       amdgpu_cs_bo_validate, p);
 946         if (r) {
 947                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 948                 goto error_validate;
 949         }
 950
 951         r = amdgpu_cs_list_validate(p, &duplicates);
 952         if (r)
 953                 goto error_validate;
 954
 955         r = amdgpu_cs_list_validate(p, &p->validated);
 956         if (r)
 957                 goto error_validate;
 958
 959         if (p->uf_entry.tv.bo) {
 960                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 961
 962                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 963                 if (r)
 964                         goto error_validate;
 965
 966                 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(uf);
 967         }
 968
 969         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 970                                      p->bytes_moved_vis);
 971
 972         for (i = 0; i < p->gang_size; ++i)
 973                 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
 974                                          p->bo_list->gws_obj,
 975                                          p->bo_list->oa_obj);
 976         return 0;
 977
 978 error_validate:
 979         ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 980
 981 out_free_user_pages:
 982         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 983                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 984
 985                 if (!e->user_pages)
 986                         continue;
 987                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
 988                 kvfree(e->user_pages);
 989                 e->user_pages = NULL;
 990         }
 991         return r;
 992 }
 993
 994 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
 995 {
 996         int i, j;
 997
 998         if (!trace_amdgpu_cs_enabled())
 999                 return;
1000
1001         for (i = 0; i < p->gang_size; ++i) {
1002                 struct amdgpu_job *job = p->jobs[i];
1003
1004                 for (j = 0; j < job->num_ibs; ++j)
1005                         trace_amdgpu_cs(p, job, &job->ibs[j]);
1006         }
1007 }
1008
1009 static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1010                                struct amdgpu_job *job)
1011 {
1012         struct amdgpu_ring *ring = amdgpu_job_ring(job);
1013         unsigned int i;
1014         int r;
1015
1016         /* Only for UVD/VCE VM emulation */
1017         if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1018                 return 0;
1019
1020         for (i = 0; i < job->num_ibs; ++i) {
1021                 struct amdgpu_ib *ib = &job->ibs[i];
1022                 struct amdgpu_bo_va_mapping *m;
1023                 struct amdgpu_bo *aobj;
1024                 uint64_t va_start;
1025                 uint8_t *kptr;
1026
1027                 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1028                 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1029                 if (r) {
1030                         DRM_ERROR("IB va_start is invalid\n");
1031                         return r;
1032                 }
1033
1034                 if ((va_start + ib->length_dw * 4) >
1035                     (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1036                         DRM_ERROR("IB va_start+ib_bytes is invalid\n");
1037                         return -EINVAL;
1038                 }
1039
1040                 /* the IB should be reserved at this point */
1041                 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1042                 if (r) {
1043                         return r;
1044                 }
1045
1046                 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1047
1048                 if (ring->funcs->parse_cs) {
1049                         memcpy(ib->ptr, kptr, ib->length_dw * 4);
1050                         amdgpu_bo_kunmap(aobj);
1051
1052                         r = amdgpu_ring_parse_cs(ring, p, job, ib);
1053                         if (r)
1054                                 return r;
1055                 } else {
1056                         ib->ptr = (uint32_t *)kptr;
1057                         r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1058                         amdgpu_bo_kunmap(aobj);
1059                         if (r)
1060                                 return r;
1061                 }
1062         }
1063
1064         return 0;
1065 }
1066
1067 static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1068 {
1069         unsigned int i;
1070         int r;
1071
1072         for (i = 0; i < p->gang_size; ++i) {
1073                 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1074                 if (r)
1075                         return r;
1076         }
1077         return 0;
1078 }
1079
1080 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1081 {
1082         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1083         struct amdgpu_job *job = p->gang_leader;
1084         struct amdgpu_device *adev = p->adev;
1085         struct amdgpu_vm *vm = &fpriv->vm;
1086         struct amdgpu_bo_list_entry *e;
1087         struct amdgpu_bo_va *bo_va;
1088         struct amdgpu_bo *bo;
1089         unsigned int i;
1090         int r;
1091
1092         r = amdgpu_vm_clear_freed(adev, vm, NULL);
1093         if (r)
1094                 return r;
1095
1096         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1097         if (r)
1098                 return r;
1099
1100         r = amdgpu_sync_fence(&job->sync, fpriv->prt_va->last_pt_update);
1101         if (r)
1102                 return r;
1103
1104         if (fpriv->csa_va) {
1105                 bo_va = fpriv->csa_va;
1106                 BUG_ON(!bo_va);
1107                 r = amdgpu_vm_bo_update(adev, bo_va, false);
1108                 if (r)
1109                         return r;
1110
1111                 r = amdgpu_sync_fence(&job->sync, bo_va->last_pt_update);
1112                 if (r)
1113                         return r;
1114         }
1115
1116         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1117                 /* ignore duplicates */
1118                 bo = ttm_to_amdgpu_bo(e->tv.bo);
1119                 if (!bo)
1120                         continue;
1121
1122                 bo_va = e->bo_va;
1123                 if (bo_va == NULL)
1124                         continue;
1125
1126                 r = amdgpu_vm_bo_update(adev, bo_va, false);
1127                 if (r)
1128                         return r;
1129
1130                 r = amdgpu_sync_fence(&job->sync, bo_va->last_pt_update);
1131                 if (r)
1132                         return r;
1133         }
1134
1135         r = amdgpu_vm_handle_moved(adev, vm);
1136         if (r)
1137                 return r;
1138
1139         r = amdgpu_vm_update_pdes(adev, vm, false);
1140         if (r)
1141                 return r;
1142
1143         r = amdgpu_sync_fence(&job->sync, vm->last_update);
1144         if (r)
1145                 return r;
1146
1147         for (i = 0; i < p->gang_size; ++i) {
1148                 job = p->jobs[i];
1149
1150                 if (!job->vm)
1151                         continue;
1152
1153                 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1154         }
1155
1156         if (amdgpu_vm_debug) {
1157                 /* Invalidate all BOs to test for userspace bugs */
1158                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1159                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1160
1161                         /* ignore duplicates */
1162                         if (!bo)
1163                                 continue;
1164
1165                         amdgpu_vm_bo_invalidate(adev, bo, false);
1166                 }
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1173 {
1174         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1175         struct amdgpu_job *leader = p->gang_leader;
1176         struct amdgpu_bo_list_entry *e;
1177         unsigned int i;
1178         int r;
1179
1180         list_for_each_entry(e, &p->validated, tv.head) {
1181                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1182                 struct dma_resv *resv = bo->tbo.base.resv;
1183                 enum amdgpu_sync_mode sync_mode;
1184
1185                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1186                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1187                 r = amdgpu_sync_resv(p->adev, &leader->sync, resv, sync_mode,
1188                                      &fpriv->vm);
1189                 if (r)
1190                         return r;
1191         }
1192
1193         for (i = 0; i < p->gang_size - 1; ++i) {
1194                 r = amdgpu_sync_clone(&leader->sync, &p->jobs[i]->sync);
1195                 if (r)
1196                         return r;
1197         }
1198
1199         r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_size - 1]);
1200         if (r && r != -ERESTARTSYS)
1201                 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
1202
1203         return r;
1204 }
1205
1206 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1207 {
1208         int i;
1209
1210         for (i = 0; i < p->num_post_deps; ++i) {
1211                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1212                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1213                                               p->post_deps[i].chain,
1214                                               p->fence, p->post_deps[i].point);
1215                         p->post_deps[i].chain = NULL;
1216                 } else {
1217                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1218                                                   p->fence);
1219                 }
1220         }
1221 }
1222
1223 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1224                             union drm_amdgpu_cs *cs)
1225 {
1226         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1227         struct amdgpu_job *leader = p->gang_leader;
1228         struct amdgpu_bo_list_entry *e;
1229         unsigned int i;
1230         uint64_t seq;
1231         int r;
1232
1233         for (i = 0; i < p->gang_size; ++i)
1234                 drm_sched_job_arm(&p->jobs[i]->base);
1235
1236         for (i = 0; i < (p->gang_size - 1); ++i) {
1237                 struct dma_fence *fence;
1238
1239                 fence = &p->jobs[i]->base.s_fence->scheduled;
1240                 r = amdgpu_sync_fence(&leader->sync, fence);
1241                 if (r)
1242                         goto error_cleanup;
1243         }
1244
1245         if (p->gang_size > 1) {
1246                 for (i = 0; i < p->gang_size; ++i)
1247                         amdgpu_job_set_gang_leader(p->jobs[i], leader);
1248         }
1249
1250         /* No memory allocation is allowed while holding the notifier lock.
1251          * The lock is held until amdgpu_cs_submit is finished and fence is
1252          * added to BOs.
1253          */
1254         mutex_lock(&p->adev->notifier_lock);
1255
1256         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1257          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1258          */
1259         r = 0;
1260         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1261                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1262
1263                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1264         }
1265         if (r) {
1266                 r = -EAGAIN;
1267                 goto error_unlock;
1268         }
1269
1270         p->fence = dma_fence_get(&leader->base.s_fence->finished);
1271         list_for_each_entry(e, &p->validated, tv.head) {
1272
1273                 /* Everybody except for the gang leader uses READ */
1274                 for (i = 0; i < (p->gang_size - 1); ++i) {
1275                         dma_resv_add_fence(e->tv.bo->base.resv,
1276                                            &p->jobs[i]->base.s_fence->finished,
1277                                            DMA_RESV_USAGE_READ);
1278                 }
1279
1280                 /* The gang leader is remembered as writer */
1281                 e->tv.num_shared = 0;
1282         }
1283
1284         seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_size - 1],
1285                                    p->fence);
1286         amdgpu_cs_post_dependencies(p);
1287
1288         if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1289             !p->ctx->preamble_presented) {
1290                 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1291                 p->ctx->preamble_presented = true;
1292         }
1293
1294         cs->out.handle = seq;
1295         leader->uf_sequence = seq;
1296
1297         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1298         for (i = 0; i < p->gang_size; ++i) {
1299                 amdgpu_job_free_resources(p->jobs[i]);
1300                 trace_amdgpu_cs_ioctl(p->jobs[i]);
1301                 drm_sched_entity_push_job(&p->jobs[i]->base);
1302                 p->jobs[i] = NULL;
1303         }
1304
1305         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1306         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1307
1308         mutex_unlock(&p->adev->notifier_lock);
1309         mutex_unlock(&p->bo_list->bo_list_mutex);
1310         return 0;
1311
1312 error_unlock:
1313         mutex_unlock(&p->adev->notifier_lock);
1314
1315 error_cleanup:
1316         for (i = 0; i < p->gang_size; ++i)
1317                 drm_sched_job_cleanup(&p->jobs[i]->base);
1318         return r;
1319 }
1320
1321 /* Cleanup the parser structure */
1322 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1323 {
1324         unsigned i;
1325
1326         for (i = 0; i < parser->num_post_deps; i++) {
1327                 drm_syncobj_put(parser->post_deps[i].syncobj);
1328                 kfree(parser->post_deps[i].chain);
1329         }
1330         kfree(parser->post_deps);
1331
1332         dma_fence_put(parser->fence);
1333
1334         if (parser->ctx)
1335                 amdgpu_ctx_put(parser->ctx);
1336         if (parser->bo_list)
1337                 amdgpu_bo_list_put(parser->bo_list);
1338
1339         for (i = 0; i < parser->nchunks; i++)
1340                 kvfree(parser->chunks[i].kdata);
1341         kvfree(parser->chunks);
1342         for (i = 0; i < parser->gang_size; ++i) {
1343                 if (parser->jobs[i])
1344                         amdgpu_job_free(parser->jobs[i]);
1345         }
1346         if (parser->uf_entry.tv.bo) {
1347                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
1348
1349                 amdgpu_bo_unref(&uf);
1350         }
1351 }
1352
1353 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1354 {
1355         struct amdgpu_device *adev = drm_to_adev(dev);
1356         struct amdgpu_cs_parser parser;
1357         int r;
1358
1359         if (amdgpu_ras_intr_triggered())
1360                 return -EHWPOISON;
1361
1362         if (!adev->accel_working)
1363                 return -EBUSY;
1364
1365         r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1366         if (r) {
1367                 if (printk_ratelimit())
1368                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1369                 return r;
1370         }
1371
1372         r = amdgpu_cs_pass1(&parser, data);
1373         if (r)
1374                 goto error_fini;
1375
1376         r = amdgpu_cs_pass2(&parser);
1377         if (r)
1378                 goto error_fini;
1379
1380         r = amdgpu_cs_parser_bos(&parser, data);
1381         if (r) {
1382                 if (r == -ENOMEM)
1383                         DRM_ERROR("Not enough memory for command submission!\n");
1384                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1385                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1386                 goto error_fini;
1387         }
1388
1389         r = amdgpu_cs_patch_jobs(&parser);
1390         if (r)
1391                 goto error_backoff;
1392
1393         r = amdgpu_cs_vm_handling(&parser);
1394         if (r)
1395                 goto error_backoff;
1396
1397         r = amdgpu_cs_sync_rings(&parser);
1398         if (r)
1399                 goto error_backoff;
1400
1401         trace_amdgpu_cs_ibs(&parser);
1402
1403         r = amdgpu_cs_submit(&parser, data);
1404         if (r)
1405                 goto error_backoff;
1406
1407         amdgpu_cs_parser_fini(&parser);
1408         return 0;
1409
1410 error_backoff:
1411         ttm_eu_backoff_reservation(&parser.ticket, &parser.validated);
1412         mutex_unlock(&parser.bo_list->bo_list_mutex);
1413
1414 error_fini:
1415         amdgpu_cs_parser_fini(&parser);
1416         return r;
1417 }
1418
1419 /**
1420  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1421  *
1422  * @dev: drm device
1423  * @data: data from userspace
1424  * @filp: file private
1425  *
1426  * Wait for the command submission identified by handle to finish.
1427  */
1428 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1429                          struct drm_file *filp)
1430 {
1431         union drm_amdgpu_wait_cs *wait = data;
1432         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1433         struct drm_sched_entity *entity;
1434         struct amdgpu_ctx *ctx;
1435         struct dma_fence *fence;
1436         long r;
1437
1438         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1439         if (ctx == NULL)
1440                 return -EINVAL;
1441
1442         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1443                                   wait->in.ring, &entity);
1444         if (r) {
1445                 amdgpu_ctx_put(ctx);
1446                 return r;
1447         }
1448
1449         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1450         if (IS_ERR(fence))
1451                 r = PTR_ERR(fence);
1452         else if (fence) {
1453                 r = dma_fence_wait_timeout(fence, true, timeout);
1454                 if (r > 0 && fence->error)
1455                         r = fence->error;
1456                 dma_fence_put(fence);
1457         } else
1458                 r = 1;
1459
1460         amdgpu_ctx_put(ctx);
1461         if (r < 0)
1462                 return r;
1463
1464         memset(wait, 0, sizeof(*wait));
1465         wait->out.status = (r == 0);
1466
1467         return 0;
1468 }
1469
1470 /**
1471  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1472  *
1473  * @adev: amdgpu device
1474  * @filp: file private
1475  * @user: drm_amdgpu_fence copied from user space
1476  */
1477 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1478                                              struct drm_file *filp,
1479                                              struct drm_amdgpu_fence *user)
1480 {
1481         struct drm_sched_entity *entity;
1482         struct amdgpu_ctx *ctx;
1483         struct dma_fence *fence;
1484         int r;
1485
1486         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1487         if (ctx == NULL)
1488                 return ERR_PTR(-EINVAL);
1489
1490         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1491                                   user->ring, &entity);
1492         if (r) {
1493                 amdgpu_ctx_put(ctx);
1494                 return ERR_PTR(r);
1495         }
1496
1497         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1498         amdgpu_ctx_put(ctx);
1499
1500         return fence;
1501 }
1502
1503 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1504                                     struct drm_file *filp)
1505 {
1506         struct amdgpu_device *adev = drm_to_adev(dev);
1507         union drm_amdgpu_fence_to_handle *info = data;
1508         struct dma_fence *fence;
1509         struct drm_syncobj *syncobj;
1510         struct sync_file *sync_file;
1511         int fd, r;
1512
1513         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1514         if (IS_ERR(fence))
1515                 return PTR_ERR(fence);
1516
1517         if (!fence)
1518                 fence = dma_fence_get_stub();
1519
1520         switch (info->in.what) {
1521         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1522                 r = drm_syncobj_create(&syncobj, 0, fence);
1523                 dma_fence_put(fence);
1524                 if (r)
1525                         return r;
1526                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1527                 drm_syncobj_put(syncobj);
1528                 return r;
1529
1530         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1531                 r = drm_syncobj_create(&syncobj, 0, fence);
1532                 dma_fence_put(fence);
1533                 if (r)
1534                         return r;
1535                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1536                 drm_syncobj_put(syncobj);
1537                 return r;
1538
1539         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1540                 fd = get_unused_fd_flags(O_CLOEXEC);
1541                 if (fd < 0) {
1542                         dma_fence_put(fence);
1543                         return fd;
1544                 }
1545
1546                 sync_file = sync_file_create(fence);
1547                 dma_fence_put(fence);
1548                 if (!sync_file) {
1549                         put_unused_fd(fd);
1550                         return -ENOMEM;
1551                 }
1552
1553                 fd_install(fd, sync_file->file);
1554                 info->out.handle = fd;
1555                 return 0;
1556
1557         default:
1558                 dma_fence_put(fence);
1559                 return -EINVAL;
1560         }
1561 }
1562
1563 /**
1564  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1565  *
1566  * @adev: amdgpu device
1567  * @filp: file private
1568  * @wait: wait parameters
1569  * @fences: array of drm_amdgpu_fence
1570  */
1571 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1572                                      struct drm_file *filp,
1573                                      union drm_amdgpu_wait_fences *wait,
1574                                      struct drm_amdgpu_fence *fences)
1575 {
1576         uint32_t fence_count = wait->in.fence_count;
1577         unsigned int i;
1578         long r = 1;
1579
1580         for (i = 0; i < fence_count; i++) {
1581                 struct dma_fence *fence;
1582                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1583
1584                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1585                 if (IS_ERR(fence))
1586                         return PTR_ERR(fence);
1587                 else if (!fence)
1588                         continue;
1589
1590                 r = dma_fence_wait_timeout(fence, true, timeout);
1591                 dma_fence_put(fence);
1592                 if (r < 0)
1593                         return r;
1594
1595                 if (r == 0)
1596                         break;
1597
1598                 if (fence->error)
1599                         return fence->error;
1600         }
1601
1602         memset(wait, 0, sizeof(*wait));
1603         wait->out.status = (r > 0);
1604
1605         return 0;
1606 }
1607
1608 /**
1609  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1610  *
1611  * @adev: amdgpu device
1612  * @filp: file private
1613  * @wait: wait parameters
1614  * @fences: array of drm_amdgpu_fence
1615  */
1616 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1617                                     struct drm_file *filp,
1618                                     union drm_amdgpu_wait_fences *wait,
1619                                     struct drm_amdgpu_fence *fences)
1620 {
1621         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1622         uint32_t fence_count = wait->in.fence_count;
1623         uint32_t first = ~0;
1624         struct dma_fence **array;
1625         unsigned int i;
1626         long r;
1627
1628         /* Prepare the fence array */
1629         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1630
1631         if (array == NULL)
1632                 return -ENOMEM;
1633
1634         for (i = 0; i < fence_count; i++) {
1635                 struct dma_fence *fence;
1636
1637                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1638                 if (IS_ERR(fence)) {
1639                         r = PTR_ERR(fence);
1640                         goto err_free_fence_array;
1641                 } else if (fence) {
1642                         array[i] = fence;
1643                 } else { /* NULL, the fence has been already signaled */
1644                         r = 1;
1645                         first = i;
1646                         goto out;
1647                 }
1648         }
1649
1650         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1651                                        &first);
1652         if (r < 0)
1653                 goto err_free_fence_array;
1654
1655 out:
1656         memset(wait, 0, sizeof(*wait));
1657         wait->out.status = (r > 0);
1658         wait->out.first_signaled = first;
1659
1660         if (first < fence_count && array[first])
1661                 r = array[first]->error;
1662         else
1663                 r = 0;
1664
1665 err_free_fence_array:
1666         for (i = 0; i < fence_count; i++)
1667                 dma_fence_put(array[i]);
1668         kfree(array);
1669
1670         return r;
1671 }
1672
1673 /**
1674  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1675  *
1676  * @dev: drm device
1677  * @data: data from userspace
1678  * @filp: file private
1679  */
1680 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1681                                 struct drm_file *filp)
1682 {
1683         struct amdgpu_device *adev = drm_to_adev(dev);
1684         union drm_amdgpu_wait_fences *wait = data;
1685         uint32_t fence_count = wait->in.fence_count;
1686         struct drm_amdgpu_fence *fences_user;
1687         struct drm_amdgpu_fence *fences;
1688         int r;
1689
1690         /* Get the fences from userspace */
1691         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1692                         GFP_KERNEL);
1693         if (fences == NULL)
1694                 return -ENOMEM;
1695
1696         fences_user = u64_to_user_ptr(wait->in.fences);
1697         if (copy_from_user(fences, fences_user,
1698                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1699                 r = -EFAULT;
1700                 goto err_free_fences;
1701         }
1702
1703         if (wait->in.wait_all)
1704                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1705         else
1706                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1707
1708 err_free_fences:
1709         kfree(fences);
1710
1711         return r;
1712 }
1713
1714 /**
1715  * amdgpu_cs_find_mapping - find bo_va for VM address
1716  *
1717  * @parser: command submission parser context
1718  * @addr: VM address
1719  * @bo: resulting BO of the mapping found
1720  * @map: Placeholder to return found BO mapping
1721  *
1722  * Search the buffer objects in the command submission context for a certain
1723  * virtual memory address. Returns allocation structure when found, NULL
1724  * otherwise.
1725  */
1726 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1727                            uint64_t addr, struct amdgpu_bo **bo,
1728                            struct amdgpu_bo_va_mapping **map)
1729 {
1730         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1731         struct ttm_operation_ctx ctx = { false, false };
1732         struct amdgpu_vm *vm = &fpriv->vm;
1733         struct amdgpu_bo_va_mapping *mapping;
1734         int r;
1735
1736         addr /= AMDGPU_GPU_PAGE_SIZE;
1737
1738         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1739         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1740                 return -EINVAL;
1741
1742         *bo = mapping->bo_va->base.bo;
1743         *map = mapping;
1744
1745         /* Double check that the BO is reserved by this CS */
1746         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1747                 return -EINVAL;
1748
1749         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1750                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1751                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1752                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1753                 if (r)
1754                         return r;
1755         }
1756
1757         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1758 }