drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *    Daniel Vetter <[email protected]>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 401         (POWER_DOMAIN_MASK & ~(                         \
 402         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 403         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 404         BIT(POWER_DOMAIN_INIT))
 405
 406 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 407         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 408         BIT(POWER_DOMAIN_PIPE_B) |                      \
 409         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 410         BIT(POWER_DOMAIN_PIPE_C) |                      \
 411         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 412         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 413         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 414         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 415         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 416         BIT(POWER_DOMAIN_AUX_B) |                       \
 417         BIT(POWER_DOMAIN_AUX_C) |                       \
 418         BIT(POWER_DOMAIN_AUDIO) |                       \
 419         BIT(POWER_DOMAIN_VGA) |                         \
 420         BIT(POWER_DOMAIN_GMBUS) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 423         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 424         BIT(POWER_DOMAIN_MODESET) |                     \
 425         BIT(POWER_DOMAIN_AUX_A) |                       \
 426         BIT(POWER_DOMAIN_INIT))
 427 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 428         (POWER_DOMAIN_MASK & ~(                         \
 429         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 430         BIT(POWER_DOMAIN_INIT))
 431
 432 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 433 {
 434         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 435                   "DC9 already programmed to be enabled.\n");
 436         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 437                   "DC5 still not disabled to enable DC9.\n");
 438         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 439         WARN_ONCE(intel_irqs_enabled(dev_priv),
 440                   "Interrupts not disabled yet.\n");
 441
 442          /*
 443           * TODO: check for the following to verify the conditions to enter DC9
 444           * state are satisfied:
 445           * 1] Check relevant display engine registers to verify if mode set
 446           * disable sequence was followed.
 447           * 2] Check if display uninitialize sequence is initialized.
 448           */
 449 }
 450
 451 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 452 {
 453         WARN_ONCE(intel_irqs_enabled(dev_priv),
 454                   "Interrupts not disabled yet.\n");
 455         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 456                   "DC5 still not disabled.\n");
 457
 458          /*
 459           * TODO: check for the following to verify DC9 state was indeed
 460           * entered before programming to disable it:
 461           * 1] Check relevant display engine registers to verify if mode
 462           *  set disable sequence was followed.
 463           * 2] Check if display uninitialize sequence is initialized.
 464           */
 465 }
 466
 467 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 468                                 u32 state)
 469 {
 470         int rewrites = 0;
 471         int rereads = 0;
 472         u32 v;
 473
 474         I915_WRITE(DC_STATE_EN, state);
 475
 476         /* It has been observed that disabling the dc6 state sometimes
 477          * doesn't stick and dmc keeps returning old value. Make sure
 478          * the write really sticks enough times and also force rewrite until
 479          * we are confident that state is exactly what we want.
 480          */
 481         do  {
 482                 v = I915_READ(DC_STATE_EN);
 483
 484                 if (v != state) {
 485                         I915_WRITE(DC_STATE_EN, state);
 486                         rewrites++;
 487                         rereads = 0;
 488                 } else if (rereads++ > 5) {
 489                         break;
 490                 }
 491
 492         } while (rewrites < 100);
 493
 494         if (v != state)
 495                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 496                           state, v);
 497
 498         /* Most of the times we need one retry, avoid spam */
 499         if (rewrites > 1)
 500                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 501                               state, rewrites);
 502 }
 503
 504 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 505 {
 506         uint32_t val;
 507         uint32_t mask;
 508
 509         mask = DC_STATE_EN_UPTO_DC5;
 510         if (IS_BROXTON(dev_priv))
 511                 mask |= DC_STATE_EN_DC9;
 512         else
 513                 mask |= DC_STATE_EN_UPTO_DC6;
 514
 515         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 516                 state &= dev_priv->csr.allowed_dc_mask;
 517
 518         val = I915_READ(DC_STATE_EN);
 519         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 520                       val & mask, state);
 521
 522         /* Check if DMC is ignoring our DC state requests */
 523         if ((val & mask) != dev_priv->csr.dc_state)
 524                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 525                           dev_priv->csr.dc_state, val & mask);
 526
 527         val &= ~mask;
 528         val |= state;
 529
 530         gen9_write_dc_state(dev_priv, val);
 531
 532         dev_priv->csr.dc_state = val & mask;
 533 }
 534
 535 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 536 {
 537         assert_can_enable_dc9(dev_priv);
 538
 539         DRM_DEBUG_KMS("Enabling DC9\n");
 540
 541         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 542 }
 543
 544 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 545 {
 546         assert_can_disable_dc9(dev_priv);
 547
 548         DRM_DEBUG_KMS("Disabling DC9\n");
 549
 550         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 551 }
 552
 553 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 554 {
 555         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 556                   "CSR program storage start is NULL\n");
 557         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 558         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 559 }
 560
 561 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 562 {
 563         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 564                                         SKL_DISP_PW_2);
 565
 566         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 567
 568         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 569                   "DC5 already programmed to be enabled.\n");
 570         assert_rpm_wakelock_held(dev_priv);
 571
 572         assert_csr_loaded(dev_priv);
 573 }
 574
 575 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 576 {
 577         assert_can_enable_dc5(dev_priv);
 578
 579         DRM_DEBUG_KMS("Enabling DC5\n");
 580
 581         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 582 }
 583
 584 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 585 {
 586         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 587                   "Backlight is not disabled.\n");
 588         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 589                   "DC6 already programmed to be enabled.\n");
 590
 591         assert_csr_loaded(dev_priv);
 592 }
 593
 594 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 595 {
 596         assert_can_enable_dc6(dev_priv);
 597
 598         DRM_DEBUG_KMS("Enabling DC6\n");
 599
 600         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 601
 602 }
 603
 604 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 605 {
 606         DRM_DEBUG_KMS("Disabling DC6\n");
 607
 608         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 609 }
 610
 611 static void
 612 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 613                                   struct i915_power_well *power_well)
 614 {
 615         enum skl_disp_power_wells power_well_id = power_well->data;
 616         u32 val;
 617         u32 mask;
 618
 619         mask = SKL_POWER_WELL_REQ(power_well_id);
 620
 621         val = I915_READ(HSW_PWR_WELL_KVMR);
 622         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 623                       power_well->name))
 624                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 625
 626         val = I915_READ(HSW_PWR_WELL_BIOS);
 627         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 628
 629         if (!(val & mask))
 630                 return;
 631
 632         /*
 633          * DMC is known to force on the request bits for power well 1 on SKL
 634          * and BXT and the misc IO power well on SKL but we don't expect any
 635          * other request bits to be set, so WARN for those.
 636          */
 637         if (power_well_id == SKL_DISP_PW_1 ||
 638             (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
 639                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 640                                  "by DMC\n", power_well->name);
 641         else
 642                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 643                           power_well->name);
 644
 645         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 646         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 647 }
 648
 649 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 650                         struct i915_power_well *power_well, bool enable)
 651 {
 652         uint32_t tmp, fuse_status;
 653         uint32_t req_mask, state_mask;
 654         bool is_enabled, enable_requested, check_fuse_status = false;
 655
 656         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 657         fuse_status = I915_READ(SKL_FUSE_STATUS);
 658
 659         switch (power_well->data) {
 660         case SKL_DISP_PW_1:
 661                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 662                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 663                         DRM_ERROR("PG0 not enabled\n");
 664                         return;
 665                 }
 666                 break;
 667         case SKL_DISP_PW_2:
 668                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 669                         DRM_ERROR("PG1 in disabled state\n");
 670                         return;
 671                 }
 672                 break;
 673         case SKL_DISP_PW_DDI_A_E:
 674         case SKL_DISP_PW_DDI_B:
 675         case SKL_DISP_PW_DDI_C:
 676         case SKL_DISP_PW_DDI_D:
 677         case SKL_DISP_PW_MISC_IO:
 678                 break;
 679         default:
 680                 WARN(1, "Unknown power well %lu\n", power_well->data);
 681                 return;
 682         }
 683
 684         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 685         enable_requested = tmp & req_mask;
 686         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 687         is_enabled = tmp & state_mask;
 688
 689         if (!enable && enable_requested)
 690                 skl_power_well_pre_disable(dev_priv, power_well);
 691
 692         if (enable) {
 693                 if (!enable_requested) {
 694                         WARN((tmp & state_mask) &&
 695                                 !I915_READ(HSW_PWR_WELL_BIOS),
 696                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 697                                 when request is to disable!\n");
 698                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 699                 }
 700
 701                 if (!is_enabled) {
 702                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 703                         check_fuse_status = true;
 704                 }
 705         } else {
 706                 if (enable_requested) {
 707                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 708                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 709                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 710                 }
 711
 712                 if (IS_GEN9(dev_priv))
 713                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 714         }
 715
 716         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 717                      1))
 718                 DRM_ERROR("%s %s timeout\n",
 719                           power_well->name, enable ? "enable" : "disable");
 720
 721         if (check_fuse_status) {
 722                 if (power_well->data == SKL_DISP_PW_1) {
 723                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 724                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 725                                 DRM_ERROR("PG1 distributing status timeout\n");
 726                 } else if (power_well->data == SKL_DISP_PW_2) {
 727                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 728                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 729                                 DRM_ERROR("PG2 distributing status timeout\n");
 730                 }
 731         }
 732
 733         if (enable && !is_enabled)
 734                 skl_power_well_post_enable(dev_priv, power_well);
 735 }
 736
 737 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 738                                    struct i915_power_well *power_well)
 739 {
 740         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 741
 742         /*
 743          * We're taking over the BIOS, so clear any requests made by it since
 744          * the driver is in charge now.
 745          */
 746         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 747                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 748 }
 749
 750 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 751                                   struct i915_power_well *power_well)
 752 {
 753         hsw_set_power_well(dev_priv, power_well, true);
 754 }
 755
 756 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 757                                    struct i915_power_well *power_well)
 758 {
 759         hsw_set_power_well(dev_priv, power_well, false);
 760 }
 761
 762 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 763                                         struct i915_power_well *power_well)
 764 {
 765         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 766                 SKL_POWER_WELL_STATE(power_well->data);
 767
 768         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 769 }
 770
 771 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 772                                 struct i915_power_well *power_well)
 773 {
 774         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 775
 776         /* Clear any request made by BIOS as driver is taking over */
 777         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 778 }
 779
 780 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 781                                 struct i915_power_well *power_well)
 782 {
 783         skl_set_power_well(dev_priv, power_well, true);
 784 }
 785
 786 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 787                                 struct i915_power_well *power_well)
 788 {
 789         skl_set_power_well(dev_priv, power_well, false);
 790 }
 791
 792 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 793                                            struct i915_power_well *power_well)
 794 {
 795         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 796 }
 797
 798 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 799                                           struct i915_power_well *power_well)
 800 {
 801         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 802
 803         if (IS_BROXTON(dev_priv)) {
 804                 broxton_cdclk_verify_state(dev_priv);
 805                 broxton_ddi_phy_verify_state(dev_priv);
 806         }
 807 }
 808
 809 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 810                                            struct i915_power_well *power_well)
 811 {
 812         if (!dev_priv->csr.dmc_payload)
 813                 return;
 814
 815         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 816                 skl_enable_dc6(dev_priv);
 817         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 818                 gen9_enable_dc5(dev_priv);
 819 }
 820
 821 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 822                                            struct i915_power_well *power_well)
 823 {
 824         if (power_well->count > 0)
 825                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 826         else
 827                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 828 }
 829
 830 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 831                                            struct i915_power_well *power_well)
 832 {
 833 }
 834
 835 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 836                                              struct i915_power_well *power_well)
 837 {
 838         return true;
 839 }
 840
 841 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 842                                struct i915_power_well *power_well, bool enable)
 843 {
 844         enum punit_power_well power_well_id = power_well->data;
 845         u32 mask;
 846         u32 state;
 847         u32 ctrl;
 848
 849         mask = PUNIT_PWRGT_MASK(power_well_id);
 850         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 851                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 852
 853         mutex_lock(&dev_priv->rps.hw_lock);
 854
 855 #define COND \
 856         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 857
 858         if (COND)
 859                 goto out;
 860
 861         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 862         ctrl &= ~mask;
 863         ctrl |= state;
 864         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 865
 866         if (wait_for(COND, 100))
 867                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 868                           state,
 869                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 870
 871 #undef COND
 872
 873 out:
 874         mutex_unlock(&dev_priv->rps.hw_lock);
 875 }
 876
 877 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 878                                    struct i915_power_well *power_well)
 879 {
 880         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 881 }
 882
 883 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 884                                   struct i915_power_well *power_well)
 885 {
 886         vlv_set_power_well(dev_priv, power_well, true);
 887 }
 888
 889 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 890                                    struct i915_power_well *power_well)
 891 {
 892         vlv_set_power_well(dev_priv, power_well, false);
 893 }
 894
 895 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 896                                    struct i915_power_well *power_well)
 897 {
 898         int power_well_id = power_well->data;
 899         bool enabled = false;
 900         u32 mask;
 901         u32 state;
 902         u32 ctrl;
 903
 904         mask = PUNIT_PWRGT_MASK(power_well_id);
 905         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 906
 907         mutex_lock(&dev_priv->rps.hw_lock);
 908
 909         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 910         /*
 911          * We only ever set the power-on and power-gate states, anything
 912          * else is unexpected.
 913          */
 914         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 915                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 916         if (state == ctrl)
 917                 enabled = true;
 918
 919         /*
 920          * A transient state at this point would mean some unexpected party
 921          * is poking at the power controls too.
 922          */
 923         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 924         WARN_ON(ctrl != state);
 925
 926         mutex_unlock(&dev_priv->rps.hw_lock);
 927
 928         return enabled;
 929 }
 930
 931 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 932 {
 933         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 934
 935         /*
 936          * Disable trickle feed and enable pnd deadline calculation
 937          */
 938         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 939         I915_WRITE(CBR1_VLV, 0);
 940 }
 941
 942 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 943 {
 944         enum pipe pipe;
 945
 946         /*
 947          * Enable the CRI clock source so we can get at the
 948          * display and the reference clock for VGA
 949          * hotplug / manual detection. Supposedly DSI also
 950          * needs the ref clock up and running.
 951          *
 952          * CHV DPLL B/C have some issues if VGA mode is enabled.
 953          */
 954         for_each_pipe(dev_priv->dev, pipe) {
 955                 u32 val = I915_READ(DPLL(pipe));
 956
 957                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 958                 if (pipe != PIPE_A)
 959                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 960
 961                 I915_WRITE(DPLL(pipe), val);
 962         }
 963
 964         vlv_init_display_clock_gating(dev_priv);
 965
 966         spin_lock_irq(&dev_priv->irq_lock);
 967         valleyview_enable_display_irqs(dev_priv);
 968         spin_unlock_irq(&dev_priv->irq_lock);
 969
 970         /*
 971          * During driver initialization/resume we can avoid restoring the
 972          * part of the HW/SW state that will be inited anyway explicitly.
 973          */
 974         if (dev_priv->power_domains.initializing)
 975                 return;
 976
 977         intel_hpd_init(dev_priv);
 978
 979         i915_redisable_vga_power_on(dev_priv->dev);
 980 }
 981
 982 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 983 {
 984         spin_lock_irq(&dev_priv->irq_lock);
 985         valleyview_disable_display_irqs(dev_priv);
 986         spin_unlock_irq(&dev_priv->irq_lock);
 987
 988         /* make sure we're done processing display irqs */
 989         synchronize_irq(dev_priv->dev->irq);
 990
 991         vlv_power_sequencer_reset(dev_priv);
 992 }
 993
 994 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 995                                           struct i915_power_well *power_well)
 996 {
 997         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 998
 999         vlv_set_power_well(dev_priv, power_well, true);
1000
1001         vlv_display_power_well_init(dev_priv);
1002 }
1003
1004 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1005                                            struct i915_power_well *power_well)
1006 {
1007         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1008
1009         vlv_display_power_well_deinit(dev_priv);
1010
1011         vlv_set_power_well(dev_priv, power_well, false);
1012 }
1013
1014 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1015                                            struct i915_power_well *power_well)
1016 {
1017         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1018
1019         /* since ref/cri clock was enabled */
1020         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1021
1022         vlv_set_power_well(dev_priv, power_well, true);
1023
1024         /*
1025          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1026          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1027          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1028          *   b. The other bits such as sfr settings / modesel may all
1029          *      be set to 0.
1030          *
1031          * This should only be done on init and resume from S3 with
1032          * both PLLs disabled, or we risk losing DPIO and PLL
1033          * synchronization.
1034          */
1035         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1036 }
1037
1038 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1039                                             struct i915_power_well *power_well)
1040 {
1041         enum pipe pipe;
1042
1043         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1044
1045         for_each_pipe(dev_priv, pipe)
1046                 assert_pll_disabled(dev_priv, pipe);
1047
1048         /* Assert common reset */
1049         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1050
1051         vlv_set_power_well(dev_priv, power_well, false);
1052 }
1053
1054 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1055
1056 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1057                                                  int power_well_id)
1058 {
1059         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1060         int i;
1061
1062         for (i = 0; i < power_domains->power_well_count; i++) {
1063                 struct i915_power_well *power_well;
1064
1065                 power_well = &power_domains->power_wells[i];
1066                 if (power_well->data == power_well_id)
1067                         return power_well;
1068         }
1069
1070         return NULL;
1071 }
1072
1073 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1074
1075 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1076 {
1077         struct i915_power_well *cmn_bc =
1078                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1079         struct i915_power_well *cmn_d =
1080                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1081         u32 phy_control = dev_priv->chv_phy_control;
1082         u32 phy_status = 0;
1083         u32 phy_status_mask = 0xffffffff;
1084         u32 tmp;
1085
1086         /*
1087          * The BIOS can leave the PHY is some weird state
1088          * where it doesn't fully power down some parts.
1089          * Disable the asserts until the PHY has been fully
1090          * reset (ie. the power well has been disabled at
1091          * least once).
1092          */
1093         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1094                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1095                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1096                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1097                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1098                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1099                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1100
1101         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1102                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1103                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1104                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1105
1106         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1107                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1108
1109                 /* this assumes override is only used to enable lanes */
1110                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1111                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1112
1113                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1114                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1115
1116                 /* CL1 is on whenever anything is on in either channel */
1117                 if (BITS_SET(phy_control,
1118                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1119                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1120                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1121
1122                 /*
1123                  * The DPLLB check accounts for the pipe B + port A usage
1124                  * with CL2 powered up but all the lanes in the second channel
1125                  * powered down.
1126                  */
1127                 if (BITS_SET(phy_control,
1128                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1129                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1130                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1131
1132                 if (BITS_SET(phy_control,
1133                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1134                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1135                 if (BITS_SET(phy_control,
1136                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1137                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1138
1139                 if (BITS_SET(phy_control,
1140                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1141                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1142                 if (BITS_SET(phy_control,
1143                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1144                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1145         }
1146
1147         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1148                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1149
1150                 /* this assumes override is only used to enable lanes */
1151                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1152                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1153
1154                 if (BITS_SET(phy_control,
1155                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1156                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1157
1158                 if (BITS_SET(phy_control,
1159                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1160                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1161                 if (BITS_SET(phy_control,
1162                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1163                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1164         }
1165
1166         phy_status &= phy_status_mask;
1167
1168         /*
1169          * The PHY may be busy with some initial calibration and whatnot,
1170          * so the power state can take a while to actually change.
1171          */
1172         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1173                 WARN(phy_status != tmp,
1174                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1175                      tmp, phy_status, dev_priv->chv_phy_control);
1176 }
1177
1178 #undef BITS_SET
1179
1180 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1181                                            struct i915_power_well *power_well)
1182 {
1183         enum dpio_phy phy;
1184         enum pipe pipe;
1185         uint32_t tmp;
1186
1187         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1188                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1189
1190         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1191                 pipe = PIPE_A;
1192                 phy = DPIO_PHY0;
1193         } else {
1194                 pipe = PIPE_C;
1195                 phy = DPIO_PHY1;
1196         }
1197
1198         /* since ref/cri clock was enabled */
1199         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1200         vlv_set_power_well(dev_priv, power_well, true);
1201
1202         /* Poll for phypwrgood signal */
1203         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1204                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1205
1206         mutex_lock(&dev_priv->sb_lock);
1207
1208         /* Enable dynamic power down */
1209         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1210         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1211                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1212         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1213
1214         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1215                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1216                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1217                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1218         } else {
1219                 /*
1220                  * Force the non-existing CL2 off. BXT does this
1221                  * too, so maybe it saves some power even though
1222                  * CL2 doesn't exist?
1223                  */
1224                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1225                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1226                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1227         }
1228
1229         mutex_unlock(&dev_priv->sb_lock);
1230
1231         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1232         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1233
1234         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1235                       phy, dev_priv->chv_phy_control);
1236
1237         assert_chv_phy_status(dev_priv);
1238 }
1239
1240 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1241                                             struct i915_power_well *power_well)
1242 {
1243         enum dpio_phy phy;
1244
1245         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1246                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1247
1248         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1249                 phy = DPIO_PHY0;
1250                 assert_pll_disabled(dev_priv, PIPE_A);
1251                 assert_pll_disabled(dev_priv, PIPE_B);
1252         } else {
1253                 phy = DPIO_PHY1;
1254                 assert_pll_disabled(dev_priv, PIPE_C);
1255         }
1256
1257         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1258         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1259
1260         vlv_set_power_well(dev_priv, power_well, false);
1261
1262         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1263                       phy, dev_priv->chv_phy_control);
1264
1265         /* PHY is fully reset now, so we can enable the PHY state asserts */
1266         dev_priv->chv_phy_assert[phy] = true;
1267
1268         assert_chv_phy_status(dev_priv);
1269 }
1270
1271 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1272                                      enum dpio_channel ch, bool override, unsigned int mask)
1273 {
1274         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1275         u32 reg, val, expected, actual;
1276
1277         /*
1278          * The BIOS can leave the PHY is some weird state
1279          * where it doesn't fully power down some parts.
1280          * Disable the asserts until the PHY has been fully
1281          * reset (ie. the power well has been disabled at
1282          * least once).
1283          */
1284         if (!dev_priv->chv_phy_assert[phy])
1285                 return;
1286
1287         if (ch == DPIO_CH0)
1288                 reg = _CHV_CMN_DW0_CH0;
1289         else
1290                 reg = _CHV_CMN_DW6_CH1;
1291
1292         mutex_lock(&dev_priv->sb_lock);
1293         val = vlv_dpio_read(dev_priv, pipe, reg);
1294         mutex_unlock(&dev_priv->sb_lock);
1295
1296         /*
1297          * This assumes !override is only used when the port is disabled.
1298          * All lanes should power down even without the override when
1299          * the port is disabled.
1300          */
1301         if (!override || mask == 0xf) {
1302                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1303                 /*
1304                  * If CH1 common lane is not active anymore
1305                  * (eg. for pipe B DPLL) the entire channel will
1306                  * shut down, which causes the common lane registers
1307                  * to read as 0. That means we can't actually check
1308                  * the lane power down status bits, but as the entire
1309                  * register reads as 0 it's a good indication that the
1310                  * channel is indeed entirely powered down.
1311                  */
1312                 if (ch == DPIO_CH1 && val == 0)
1313                         expected = 0;
1314         } else if (mask != 0x0) {
1315                 expected = DPIO_ANYDL_POWERDOWN;
1316         } else {
1317                 expected = 0;
1318         }
1319
1320         if (ch == DPIO_CH0)
1321                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1322         else
1323                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1324         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1325
1326         WARN(actual != expected,
1327              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1328              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1329              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1330              reg, val);
1331 }
1332
1333 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1334                           enum dpio_channel ch, bool override)
1335 {
1336         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1337         bool was_override;
1338
1339         mutex_lock(&power_domains->lock);
1340
1341         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1342
1343         if (override == was_override)
1344                 goto out;
1345
1346         if (override)
1347                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1348         else
1349                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1350
1351         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1352
1353         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1354                       phy, ch, dev_priv->chv_phy_control);
1355
1356         assert_chv_phy_status(dev_priv);
1357
1358 out:
1359         mutex_unlock(&power_domains->lock);
1360
1361         return was_override;
1362 }
1363
1364 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1365                              bool override, unsigned int mask)
1366 {
1367         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1368         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1369         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1370         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1371
1372         mutex_lock(&power_domains->lock);
1373
1374         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1375         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1376
1377         if (override)
1378                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1379         else
1380                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1381
1382         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1383
1384         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1385                       phy, ch, mask, dev_priv->chv_phy_control);
1386
1387         assert_chv_phy_status(dev_priv);
1388
1389         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1390
1391         mutex_unlock(&power_domains->lock);
1392 }
1393
1394 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1395                                         struct i915_power_well *power_well)
1396 {
1397         enum pipe pipe = power_well->data;
1398         bool enabled;
1399         u32 state, ctrl;
1400
1401         mutex_lock(&dev_priv->rps.hw_lock);
1402
1403         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1404         /*
1405          * We only ever set the power-on and power-gate states, anything
1406          * else is unexpected.
1407          */
1408         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1409         enabled = state == DP_SSS_PWR_ON(pipe);
1410
1411         /*
1412          * A transient state at this point would mean some unexpected party
1413          * is poking at the power controls too.
1414          */
1415         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1416         WARN_ON(ctrl << 16 != state);
1417
1418         mutex_unlock(&dev_priv->rps.hw_lock);
1419
1420         return enabled;
1421 }
1422
1423 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1424                                     struct i915_power_well *power_well,
1425                                     bool enable)
1426 {
1427         enum pipe pipe = power_well->data;
1428         u32 state;
1429         u32 ctrl;
1430
1431         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1432
1433         mutex_lock(&dev_priv->rps.hw_lock);
1434
1435 #define COND \
1436         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1437
1438         if (COND)
1439                 goto out;
1440
1441         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1442         ctrl &= ~DP_SSC_MASK(pipe);
1443         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1444         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1445
1446         if (wait_for(COND, 100))
1447                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1448                           state,
1449                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1450
1451 #undef COND
1452
1453 out:
1454         mutex_unlock(&dev_priv->rps.hw_lock);
1455 }
1456
1457 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1458                                         struct i915_power_well *power_well)
1459 {
1460         WARN_ON_ONCE(power_well->data != PIPE_A);
1461
1462         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1463 }
1464
1465 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1466                                        struct i915_power_well *power_well)
1467 {
1468         WARN_ON_ONCE(power_well->data != PIPE_A);
1469
1470         chv_set_pipe_power_well(dev_priv, power_well, true);
1471
1472         vlv_display_power_well_init(dev_priv);
1473 }
1474
1475 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1476                                         struct i915_power_well *power_well)
1477 {
1478         WARN_ON_ONCE(power_well->data != PIPE_A);
1479
1480         vlv_display_power_well_deinit(dev_priv);
1481
1482         chv_set_pipe_power_well(dev_priv, power_well, false);
1483 }
1484
1485 static void
1486 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1487                                  enum intel_display_power_domain domain)
1488 {
1489         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1490         struct i915_power_well *power_well;
1491         int i;
1492
1493         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1494                 if (!power_well->count++)
1495                         intel_power_well_enable(dev_priv, power_well);
1496         }
1497
1498         power_domains->domain_use_count[domain]++;
1499 }
1500
1501 /**
1502  * intel_display_power_get - grab a power domain reference
1503  * @dev_priv: i915 device instance
1504  * @domain: power domain to reference
1505  *
1506  * This function grabs a power domain reference for @domain and ensures that the
1507  * power domain and all its parents are powered up. Therefore users should only
1508  * grab a reference to the innermost power domain they need.
1509  *
1510  * Any power domain reference obtained by this function must have a symmetric
1511  * call to intel_display_power_put() to release the reference again.
1512  */
1513 void intel_display_power_get(struct drm_i915_private *dev_priv,
1514                              enum intel_display_power_domain domain)
1515 {
1516         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1517
1518         intel_runtime_pm_get(dev_priv);
1519
1520         mutex_lock(&power_domains->lock);
1521
1522         __intel_display_power_get_domain(dev_priv, domain);
1523
1524         mutex_unlock(&power_domains->lock);
1525 }
1526
1527 /**
1528  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1529  * @dev_priv: i915 device instance
1530  * @domain: power domain to reference
1531  *
1532  * This function grabs a power domain reference for @domain and ensures that the
1533  * power domain and all its parents are powered up. Therefore users should only
1534  * grab a reference to the innermost power domain they need.
1535  *
1536  * Any power domain reference obtained by this function must have a symmetric
1537  * call to intel_display_power_put() to release the reference again.
1538  */
1539 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1540                                         enum intel_display_power_domain domain)
1541 {
1542         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1543         bool is_enabled;
1544
1545         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1546                 return false;
1547
1548         mutex_lock(&power_domains->lock);
1549
1550         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1551                 __intel_display_power_get_domain(dev_priv, domain);
1552                 is_enabled = true;
1553         } else {
1554                 is_enabled = false;
1555         }
1556
1557         mutex_unlock(&power_domains->lock);
1558
1559         if (!is_enabled)
1560                 intel_runtime_pm_put(dev_priv);
1561
1562         return is_enabled;
1563 }
1564
1565 /**
1566  * intel_display_power_put - release a power domain reference
1567  * @dev_priv: i915 device instance
1568  * @domain: power domain to reference
1569  *
1570  * This function drops the power domain reference obtained by
1571  * intel_display_power_get() and might power down the corresponding hardware
1572  * block right away if this is the last reference.
1573  */
1574 void intel_display_power_put(struct drm_i915_private *dev_priv,
1575                              enum intel_display_power_domain domain)
1576 {
1577         struct i915_power_domains *power_domains;
1578         struct i915_power_well *power_well;
1579         int i;
1580
1581         power_domains = &dev_priv->power_domains;
1582
1583         mutex_lock(&power_domains->lock);
1584
1585         WARN(!power_domains->domain_use_count[domain],
1586              "Use count on domain %s is already zero\n",
1587              intel_display_power_domain_str(domain));
1588         power_domains->domain_use_count[domain]--;
1589
1590         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1591                 WARN(!power_well->count,
1592                      "Use count on power well %s is already zero",
1593                      power_well->name);
1594
1595                 if (!--power_well->count)
1596                         intel_power_well_disable(dev_priv, power_well);
1597         }
1598
1599         mutex_unlock(&power_domains->lock);
1600
1601         intel_runtime_pm_put(dev_priv);
1602 }
1603
1604 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1605         BIT(POWER_DOMAIN_PIPE_A) |                      \
1606         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1607         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1608         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1609         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1610         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1611         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1612         BIT(POWER_DOMAIN_PLLS) |                        \
1613         BIT(POWER_DOMAIN_AUX_A) |                       \
1614         BIT(POWER_DOMAIN_AUX_B) |                       \
1615         BIT(POWER_DOMAIN_AUX_C) |                       \
1616         BIT(POWER_DOMAIN_AUX_D) |                       \
1617         BIT(POWER_DOMAIN_GMBUS) |                       \
1618         BIT(POWER_DOMAIN_INIT))
1619 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1620         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1621         BIT(POWER_DOMAIN_INIT))
1622
1623 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1624         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1625         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1626 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1627         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1628         BIT(POWER_DOMAIN_INIT))
1629
1630 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1631 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1632
1633 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1634         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1635         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1636         BIT(POWER_DOMAIN_PORT_CRT) |            \
1637         BIT(POWER_DOMAIN_AUX_B) |               \
1638         BIT(POWER_DOMAIN_AUX_C) |               \
1639         BIT(POWER_DOMAIN_INIT))
1640
1641 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1642         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1643         BIT(POWER_DOMAIN_AUX_B) |               \
1644         BIT(POWER_DOMAIN_INIT))
1645
1646 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1647         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1648         BIT(POWER_DOMAIN_AUX_B) |               \
1649         BIT(POWER_DOMAIN_INIT))
1650
1651 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1652         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1653         BIT(POWER_DOMAIN_AUX_C) |               \
1654         BIT(POWER_DOMAIN_INIT))
1655
1656 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1657         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1658         BIT(POWER_DOMAIN_AUX_C) |               \
1659         BIT(POWER_DOMAIN_INIT))
1660
1661 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1662         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1663         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1664         BIT(POWER_DOMAIN_AUX_B) |               \
1665         BIT(POWER_DOMAIN_AUX_C) |               \
1666         BIT(POWER_DOMAIN_INIT))
1667
1668 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1669         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1670         BIT(POWER_DOMAIN_AUX_D) |               \
1671         BIT(POWER_DOMAIN_INIT))
1672
1673 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1674         .sync_hw = i9xx_always_on_power_well_noop,
1675         .enable = i9xx_always_on_power_well_noop,
1676         .disable = i9xx_always_on_power_well_noop,
1677         .is_enabled = i9xx_always_on_power_well_enabled,
1678 };
1679
1680 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1681         .sync_hw = chv_pipe_power_well_sync_hw,
1682         .enable = chv_pipe_power_well_enable,
1683         .disable = chv_pipe_power_well_disable,
1684         .is_enabled = chv_pipe_power_well_enabled,
1685 };
1686
1687 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1688         .sync_hw = vlv_power_well_sync_hw,
1689         .enable = chv_dpio_cmn_power_well_enable,
1690         .disable = chv_dpio_cmn_power_well_disable,
1691         .is_enabled = vlv_power_well_enabled,
1692 };
1693
1694 static struct i915_power_well i9xx_always_on_power_well[] = {
1695         {
1696                 .name = "always-on",
1697                 .always_on = 1,
1698                 .domains = POWER_DOMAIN_MASK,
1699                 .ops = &i9xx_always_on_power_well_ops,
1700         },
1701 };
1702
1703 static const struct i915_power_well_ops hsw_power_well_ops = {
1704         .sync_hw = hsw_power_well_sync_hw,
1705         .enable = hsw_power_well_enable,
1706         .disable = hsw_power_well_disable,
1707         .is_enabled = hsw_power_well_enabled,
1708 };
1709
1710 static const struct i915_power_well_ops skl_power_well_ops = {
1711         .sync_hw = skl_power_well_sync_hw,
1712         .enable = skl_power_well_enable,
1713         .disable = skl_power_well_disable,
1714         .is_enabled = skl_power_well_enabled,
1715 };
1716
1717 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1718         .sync_hw = gen9_dc_off_power_well_sync_hw,
1719         .enable = gen9_dc_off_power_well_enable,
1720         .disable = gen9_dc_off_power_well_disable,
1721         .is_enabled = gen9_dc_off_power_well_enabled,
1722 };
1723
1724 static struct i915_power_well hsw_power_wells[] = {
1725         {
1726                 .name = "always-on",
1727                 .always_on = 1,
1728                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1729                 .ops = &i9xx_always_on_power_well_ops,
1730         },
1731         {
1732                 .name = "display",
1733                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1734                 .ops = &hsw_power_well_ops,
1735         },
1736 };
1737
1738 static struct i915_power_well bdw_power_wells[] = {
1739         {
1740                 .name = "always-on",
1741                 .always_on = 1,
1742                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1743                 .ops = &i9xx_always_on_power_well_ops,
1744         },
1745         {
1746                 .name = "display",
1747                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1748                 .ops = &hsw_power_well_ops,
1749         },
1750 };
1751
1752 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1753         .sync_hw = vlv_power_well_sync_hw,
1754         .enable = vlv_display_power_well_enable,
1755         .disable = vlv_display_power_well_disable,
1756         .is_enabled = vlv_power_well_enabled,
1757 };
1758
1759 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1760         .sync_hw = vlv_power_well_sync_hw,
1761         .enable = vlv_dpio_cmn_power_well_enable,
1762         .disable = vlv_dpio_cmn_power_well_disable,
1763         .is_enabled = vlv_power_well_enabled,
1764 };
1765
1766 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1767         .sync_hw = vlv_power_well_sync_hw,
1768         .enable = vlv_power_well_enable,
1769         .disable = vlv_power_well_disable,
1770         .is_enabled = vlv_power_well_enabled,
1771 };
1772
1773 static struct i915_power_well vlv_power_wells[] = {
1774         {
1775                 .name = "always-on",
1776                 .always_on = 1,
1777                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1778                 .ops = &i9xx_always_on_power_well_ops,
1779                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1780         },
1781         {
1782                 .name = "display",
1783                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1784                 .data = PUNIT_POWER_WELL_DISP2D,
1785                 .ops = &vlv_display_power_well_ops,
1786         },
1787         {
1788                 .name = "dpio-tx-b-01",
1789                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1790                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1791                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1792                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1793                 .ops = &vlv_dpio_power_well_ops,
1794                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1795         },
1796         {
1797                 .name = "dpio-tx-b-23",
1798                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1799                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1800                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1801                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1802                 .ops = &vlv_dpio_power_well_ops,
1803                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1804         },
1805         {
1806                 .name = "dpio-tx-c-01",
1807                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1808                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1809                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1810                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1811                 .ops = &vlv_dpio_power_well_ops,
1812                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1813         },
1814         {
1815                 .name = "dpio-tx-c-23",
1816                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1817                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1818                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1819                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1820                 .ops = &vlv_dpio_power_well_ops,
1821                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1822         },
1823         {
1824                 .name = "dpio-common",
1825                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1826                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1827                 .ops = &vlv_dpio_cmn_power_well_ops,
1828         },
1829 };
1830
1831 static struct i915_power_well chv_power_wells[] = {
1832         {
1833                 .name = "always-on",
1834                 .always_on = 1,
1835                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1836                 .ops = &i9xx_always_on_power_well_ops,
1837         },
1838         {
1839                 .name = "display",
1840                 /*
1841                  * Pipe A power well is the new disp2d well. Pipe B and C
1842                  * power wells don't actually exist. Pipe A power well is
1843                  * required for any pipe to work.
1844                  */
1845                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1846                 .data = PIPE_A,
1847                 .ops = &chv_pipe_power_well_ops,
1848         },
1849         {
1850                 .name = "dpio-common-bc",
1851                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1852                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1853                 .ops = &chv_dpio_cmn_power_well_ops,
1854         },
1855         {
1856                 .name = "dpio-common-d",
1857                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1858                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1859                 .ops = &chv_dpio_cmn_power_well_ops,
1860         },
1861 };
1862
1863 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1864                                     int power_well_id)
1865 {
1866         struct i915_power_well *power_well;
1867         bool ret;
1868
1869         power_well = lookup_power_well(dev_priv, power_well_id);
1870         ret = power_well->ops->is_enabled(dev_priv, power_well);
1871
1872         return ret;
1873 }
1874
1875 static struct i915_power_well skl_power_wells[] = {
1876         {
1877                 .name = "always-on",
1878                 .always_on = 1,
1879                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1880                 .ops = &i9xx_always_on_power_well_ops,
1881                 .data = SKL_DISP_PW_ALWAYS_ON,
1882         },
1883         {
1884                 .name = "power well 1",
1885                 /* Handled by the DMC firmware */
1886                 .domains = 0,
1887                 .ops = &skl_power_well_ops,
1888                 .data = SKL_DISP_PW_1,
1889         },
1890         {
1891                 .name = "MISC IO power well",
1892                 /* Handled by the DMC firmware */
1893                 .domains = 0,
1894                 .ops = &skl_power_well_ops,
1895                 .data = SKL_DISP_PW_MISC_IO,
1896         },
1897         {
1898                 .name = "DC off",
1899                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1900                 .ops = &gen9_dc_off_power_well_ops,
1901                 .data = SKL_DISP_PW_DC_OFF,
1902         },
1903         {
1904                 .name = "power well 2",
1905                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1906                 .ops = &skl_power_well_ops,
1907                 .data = SKL_DISP_PW_2,
1908         },
1909         {
1910                 .name = "DDI A/E power well",
1911                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1912                 .ops = &skl_power_well_ops,
1913                 .data = SKL_DISP_PW_DDI_A_E,
1914         },
1915         {
1916                 .name = "DDI B power well",
1917                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1918                 .ops = &skl_power_well_ops,
1919                 .data = SKL_DISP_PW_DDI_B,
1920         },
1921         {
1922                 .name = "DDI C power well",
1923                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1924                 .ops = &skl_power_well_ops,
1925                 .data = SKL_DISP_PW_DDI_C,
1926         },
1927         {
1928                 .name = "DDI D power well",
1929                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1930                 .ops = &skl_power_well_ops,
1931                 .data = SKL_DISP_PW_DDI_D,
1932         },
1933 };
1934
1935 static struct i915_power_well bxt_power_wells[] = {
1936         {
1937                 .name = "always-on",
1938                 .always_on = 1,
1939                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1940                 .ops = &i9xx_always_on_power_well_ops,
1941         },
1942         {
1943                 .name = "power well 1",
1944                 .domains = 0,
1945                 .ops = &skl_power_well_ops,
1946                 .data = SKL_DISP_PW_1,
1947         },
1948         {
1949                 .name = "DC off",
1950                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1951                 .ops = &gen9_dc_off_power_well_ops,
1952                 .data = SKL_DISP_PW_DC_OFF,
1953         },
1954         {
1955                 .name = "power well 2",
1956                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1957                 .ops = &skl_power_well_ops,
1958                 .data = SKL_DISP_PW_2,
1959         },
1960 };
1961
1962 static int
1963 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1964                                    int disable_power_well)
1965 {
1966         if (disable_power_well >= 0)
1967                 return !!disable_power_well;
1968
1969         return 1;
1970 }
1971
1972 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
1973                                     int enable_dc)
1974 {
1975         uint32_t mask;
1976         int requested_dc;
1977         int max_dc;
1978
1979         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1980                 max_dc = 2;
1981                 mask = 0;
1982         } else if (IS_BROXTON(dev_priv)) {
1983                 max_dc = 1;
1984                 /*
1985                  * DC9 has a separate HW flow from the rest of the DC states,
1986                  * not depending on the DMC firmware. It's needed by system
1987                  * suspend/resume, so allow it unconditionally.
1988                  */
1989                 mask = DC_STATE_EN_DC9;
1990         } else {
1991                 max_dc = 0;
1992                 mask = 0;
1993         }
1994
1995         if (!i915.disable_power_well)
1996                 max_dc = 0;
1997
1998         if (enable_dc >= 0 && enable_dc <= max_dc) {
1999                 requested_dc = enable_dc;
2000         } else if (enable_dc == -1) {
2001                 requested_dc = max_dc;
2002         } else if (enable_dc > max_dc && enable_dc <= 2) {
2003                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2004                               enable_dc, max_dc);
2005                 requested_dc = max_dc;
2006         } else {
2007                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2008                 requested_dc = max_dc;
2009         }
2010
2011         if (requested_dc > 1)
2012                 mask |= DC_STATE_EN_UPTO_DC6;
2013         if (requested_dc > 0)
2014                 mask |= DC_STATE_EN_UPTO_DC5;
2015
2016         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2017
2018         return mask;
2019 }
2020
2021 #define set_power_wells(power_domains, __power_wells) ({                \
2022         (power_domains)->power_wells = (__power_wells);                 \
2023         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2024 })
2025
2026 /**
2027  * intel_power_domains_init - initializes the power domain structures
2028  * @dev_priv: i915 device instance
2029  *
2030  * Initializes the power domain structures for @dev_priv depending upon the
2031  * supported platform.
2032  */
2033 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2034 {
2035         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2036
2037         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2038                                                      i915.disable_power_well);
2039         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2040                                                             i915.enable_dc);
2041
2042         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2043
2044         mutex_init(&power_domains->lock);
2045
2046         /*
2047          * The enabling order will be from lower to higher indexed wells,
2048          * the disabling order is reversed.
2049          */
2050         if (IS_HASWELL(dev_priv)) {
2051                 set_power_wells(power_domains, hsw_power_wells);
2052         } else if (IS_BROADWELL(dev_priv)) {
2053                 set_power_wells(power_domains, bdw_power_wells);
2054         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2055                 set_power_wells(power_domains, skl_power_wells);
2056         } else if (IS_BROXTON(dev_priv)) {
2057                 set_power_wells(power_domains, bxt_power_wells);
2058         } else if (IS_CHERRYVIEW(dev_priv)) {
2059                 set_power_wells(power_domains, chv_power_wells);
2060         } else if (IS_VALLEYVIEW(dev_priv)) {
2061                 set_power_wells(power_domains, vlv_power_wells);
2062         } else {
2063                 set_power_wells(power_domains, i9xx_always_on_power_well);
2064         }
2065
2066         return 0;
2067 }
2068
2069 /**
2070  * intel_power_domains_fini - finalizes the power domain structures
2071  * @dev_priv: i915 device instance
2072  *
2073  * Finalizes the power domain structures for @dev_priv depending upon the
2074  * supported platform. This function also disables runtime pm and ensures that
2075  * the device stays powered up so that the driver can be reloaded.
2076  */
2077 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2078 {
2079         struct device *device = &dev_priv->dev->pdev->dev;
2080
2081         /*
2082          * The i915.ko module is still not prepared to be loaded when
2083          * the power well is not enabled, so just enable it in case
2084          * we're going to unload/reload.
2085          * The following also reacquires the RPM reference the core passed
2086          * to the driver during loading, which is dropped in
2087          * intel_runtime_pm_enable(). We have to hand back the control of the
2088          * device to the core with this reference held.
2089          */
2090         intel_display_set_init_power(dev_priv, true);
2091
2092         /* Remove the refcount we took to keep power well support disabled. */
2093         if (!i915.disable_power_well)
2094                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2095
2096         /*
2097          * Remove the refcount we took in intel_runtime_pm_enable() in case
2098          * the platform doesn't support runtime PM.
2099          */
2100         if (!HAS_RUNTIME_PM(dev_priv))
2101                 pm_runtime_put(device);
2102 }
2103
2104 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2105 {
2106         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2107         struct i915_power_well *power_well;
2108         int i;
2109
2110         mutex_lock(&power_domains->lock);
2111         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2112                 power_well->ops->sync_hw(dev_priv, power_well);
2113                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2114                                                                      power_well);
2115         }
2116         mutex_unlock(&power_domains->lock);
2117 }
2118
2119 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2120                                    bool resume)
2121 {
2122         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2123         struct i915_power_well *well;
2124         uint32_t val;
2125
2126         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2127
2128         /* enable PCH reset handshake */
2129         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2130         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2131
2132         /* enable PG1 and Misc I/O */
2133         mutex_lock(&power_domains->lock);
2134
2135         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2136         intel_power_well_enable(dev_priv, well);
2137
2138         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2139         intel_power_well_enable(dev_priv, well);
2140
2141         mutex_unlock(&power_domains->lock);
2142
2143         if (!resume)
2144                 return;
2145
2146         skl_init_cdclk(dev_priv);
2147
2148         if (dev_priv->csr.dmc_payload)
2149                 intel_csr_load_program(dev_priv);
2150 }
2151
2152 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2153 {
2154         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2155         struct i915_power_well *well;
2156
2157         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2158
2159         skl_uninit_cdclk(dev_priv);
2160
2161         /* The spec doesn't call for removing the reset handshake flag */
2162         /* disable PG1 and Misc I/O */
2163
2164         mutex_lock(&power_domains->lock);
2165
2166         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2167         intel_power_well_disable(dev_priv, well);
2168
2169         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2170         intel_power_well_disable(dev_priv, well);
2171
2172         mutex_unlock(&power_domains->lock);
2173 }
2174
2175 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2176                            bool resume)
2177 {
2178         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2179         struct i915_power_well *well;
2180         uint32_t val;
2181
2182         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2183
2184         /*
2185          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2186          * or else the reset will hang because there is no PCH to respond.
2187          * Move the handshake programming to initialization sequence.
2188          * Previously was left up to BIOS.
2189          */
2190         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2191         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2192         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2193
2194         /* Enable PG1 */
2195         mutex_lock(&power_domains->lock);
2196
2197         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2198         intel_power_well_enable(dev_priv, well);
2199
2200         mutex_unlock(&power_domains->lock);
2201
2202         broxton_init_cdclk(dev_priv);
2203         broxton_ddi_phy_init(dev_priv);
2204
2205         broxton_cdclk_verify_state(dev_priv);
2206         broxton_ddi_phy_verify_state(dev_priv);
2207
2208         if (resume && dev_priv->csr.dmc_payload)
2209                 intel_csr_load_program(dev_priv);
2210 }
2211
2212 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2213 {
2214         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2215         struct i915_power_well *well;
2216
2217         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2218
2219         broxton_ddi_phy_uninit(dev_priv);
2220         broxton_uninit_cdclk(dev_priv);
2221
2222         /* The spec doesn't call for removing the reset handshake flag */
2223
2224         /* Disable PG1 */
2225         mutex_lock(&power_domains->lock);
2226
2227         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2228         intel_power_well_disable(dev_priv, well);
2229
2230         mutex_unlock(&power_domains->lock);
2231 }
2232
2233 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2234 {
2235         struct i915_power_well *cmn_bc =
2236                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2237         struct i915_power_well *cmn_d =
2238                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2239
2240         /*
2241          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2242          * workaround never ever read DISPLAY_PHY_CONTROL, and
2243          * instead maintain a shadow copy ourselves. Use the actual
2244          * power well state and lane status to reconstruct the
2245          * expected initial value.
2246          */
2247         dev_priv->chv_phy_control =
2248                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2249                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2250                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2251                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2252                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2253
2254         /*
2255          * If all lanes are disabled we leave the override disabled
2256          * with all power down bits cleared to match the state we
2257          * would use after disabling the port. Otherwise enable the
2258          * override and set the lane powerdown bits accding to the
2259          * current lane status.
2260          */
2261         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2262                 uint32_t status = I915_READ(DPLL(PIPE_A));
2263                 unsigned int mask;
2264
2265                 mask = status & DPLL_PORTB_READY_MASK;
2266                 if (mask == 0xf)
2267                         mask = 0x0;
2268                 else
2269                         dev_priv->chv_phy_control |=
2270                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2271
2272                 dev_priv->chv_phy_control |=
2273                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2274
2275                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2276                 if (mask == 0xf)
2277                         mask = 0x0;
2278                 else
2279                         dev_priv->chv_phy_control |=
2280                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2281
2282                 dev_priv->chv_phy_control |=
2283                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2284
2285                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2286
2287                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2288         } else {
2289                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2290         }
2291
2292         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2293                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2294                 unsigned int mask;
2295
2296                 mask = status & DPLL_PORTD_READY_MASK;
2297
2298                 if (mask == 0xf)
2299                         mask = 0x0;
2300                 else
2301                         dev_priv->chv_phy_control |=
2302                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2303
2304                 dev_priv->chv_phy_control |=
2305                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2306
2307                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2308
2309                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2310         } else {
2311                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2312         }
2313
2314         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2315
2316         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2317                       dev_priv->chv_phy_control);
2318 }
2319
2320 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2321 {
2322         struct i915_power_well *cmn =
2323                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2324         struct i915_power_well *disp2d =
2325                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2326
2327         /* If the display might be already active skip this */
2328         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2329             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2330             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2331                 return;
2332
2333         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2334
2335         /* cmnlane needs DPLL registers */
2336         disp2d->ops->enable(dev_priv, disp2d);
2337
2338         /*
2339          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2340          * Need to assert and de-assert PHY SB reset by gating the
2341          * common lane power, then un-gating it.
2342          * Simply ungating isn't enough to reset the PHY enough to get
2343          * ports and lanes running.
2344          */
2345         cmn->ops->disable(dev_priv, cmn);
2346 }
2347
2348 /**
2349  * intel_power_domains_init_hw - initialize hardware power domain state
2350  * @dev_priv: i915 device instance
2351  *
2352  * This function initializes the hardware power domain state and enables all
2353  * power domains using intel_display_set_init_power().
2354  */
2355 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2356 {
2357         struct drm_device *dev = dev_priv->dev;
2358         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2359
2360         power_domains->initializing = true;
2361
2362         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2363                 skl_display_core_init(dev_priv, resume);
2364         } else if (IS_BROXTON(dev)) {
2365                 bxt_display_core_init(dev_priv, resume);
2366         } else if (IS_CHERRYVIEW(dev)) {
2367                 mutex_lock(&power_domains->lock);
2368                 chv_phy_control_init(dev_priv);
2369                 mutex_unlock(&power_domains->lock);
2370         } else if (IS_VALLEYVIEW(dev)) {
2371                 mutex_lock(&power_domains->lock);
2372                 vlv_cmnlane_wa(dev_priv);
2373                 mutex_unlock(&power_domains->lock);
2374         }
2375
2376         /* For now, we need the power well to be always enabled. */
2377         intel_display_set_init_power(dev_priv, true);
2378         /* Disable power support if the user asked so. */
2379         if (!i915.disable_power_well)
2380                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2381         intel_power_domains_sync_hw(dev_priv);
2382         power_domains->initializing = false;
2383 }
2384
2385 /**
2386  * intel_power_domains_suspend - suspend power domain state
2387  * @dev_priv: i915 device instance
2388  *
2389  * This function prepares the hardware power domain state before entering
2390  * system suspend. It must be paired with intel_power_domains_init_hw().
2391  */
2392 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2393 {
2394         /*
2395          * Even if power well support was disabled we still want to disable
2396          * power wells while we are system suspended.
2397          */
2398         if (!i915.disable_power_well)
2399                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2400
2401         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2402                 skl_display_core_uninit(dev_priv);
2403         else if (IS_BROXTON(dev_priv))
2404                 bxt_display_core_uninit(dev_priv);
2405 }
2406
2407 /**
2408  * intel_runtime_pm_get - grab a runtime pm reference
2409  * @dev_priv: i915 device instance
2410  *
2411  * This function grabs a device-level runtime pm reference (mostly used for GEM
2412  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2413  *
2414  * Any runtime pm reference obtained by this function must have a symmetric
2415  * call to intel_runtime_pm_put() to release the reference again.
2416  */
2417 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2418 {
2419         struct drm_device *dev = dev_priv->dev;
2420         struct device *device = &dev->pdev->dev;
2421
2422         pm_runtime_get_sync(device);
2423
2424         atomic_inc(&dev_priv->pm.wakeref_count);
2425         assert_rpm_wakelock_held(dev_priv);
2426 }
2427
2428 /**
2429  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2430  * @dev_priv: i915 device instance
2431  *
2432  * This function grabs a device-level runtime pm reference if the device is
2433  * already in use and ensures that it is powered up.
2434  *
2435  * Any runtime pm reference obtained by this function must have a symmetric
2436  * call to intel_runtime_pm_put() to release the reference again.
2437  */
2438 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2439 {
2440         struct drm_device *dev = dev_priv->dev;
2441         struct device *device = &dev->pdev->dev;
2442
2443         if (IS_ENABLED(CONFIG_PM)) {
2444                 int ret = pm_runtime_get_if_in_use(device);
2445
2446                 /*
2447                  * In cases runtime PM is disabled by the RPM core and we get
2448                  * an -EINVAL return value we are not supposed to call this
2449                  * function, since the power state is undefined. This applies
2450                  * atm to the late/early system suspend/resume handlers.
2451                  */
2452                 WARN_ON_ONCE(ret < 0);
2453                 if (ret <= 0)
2454                         return false;
2455         }
2456
2457         atomic_inc(&dev_priv->pm.wakeref_count);
2458         assert_rpm_wakelock_held(dev_priv);
2459
2460         return true;
2461 }
2462
2463 /**
2464  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2465  * @dev_priv: i915 device instance
2466  *
2467  * This function grabs a device-level runtime pm reference (mostly used for GEM
2468  * code to ensure the GTT or GT is on).
2469  *
2470  * It will _not_ power up the device but instead only check that it's powered
2471  * on.  Therefore it is only valid to call this functions from contexts where
2472  * the device is known to be powered up and where trying to power it up would
2473  * result in hilarity and deadlocks. That pretty much means only the system
2474  * suspend/resume code where this is used to grab runtime pm references for
2475  * delayed setup down in work items.
2476  *
2477  * Any runtime pm reference obtained by this function must have a symmetric
2478  * call to intel_runtime_pm_put() to release the reference again.
2479  */
2480 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2481 {
2482         struct drm_device *dev = dev_priv->dev;
2483         struct device *device = &dev->pdev->dev;
2484
2485         assert_rpm_wakelock_held(dev_priv);
2486         pm_runtime_get_noresume(device);
2487
2488         atomic_inc(&dev_priv->pm.wakeref_count);
2489 }
2490
2491 /**
2492  * intel_runtime_pm_put - release a runtime pm reference
2493  * @dev_priv: i915 device instance
2494  *
2495  * This function drops the device-level runtime pm reference obtained by
2496  * intel_runtime_pm_get() and might power down the corresponding
2497  * hardware block right away if this is the last reference.
2498  */
2499 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2500 {
2501         struct drm_device *dev = dev_priv->dev;
2502         struct device *device = &dev->pdev->dev;
2503
2504         assert_rpm_wakelock_held(dev_priv);
2505         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2506                 atomic_inc(&dev_priv->pm.atomic_seq);
2507
2508         pm_runtime_mark_last_busy(device);
2509         pm_runtime_put_autosuspend(device);
2510 }
2511
2512 /**
2513  * intel_runtime_pm_enable - enable runtime pm
2514  * @dev_priv: i915 device instance
2515  *
2516  * This function enables runtime pm at the end of the driver load sequence.
2517  *
2518  * Note that this function does currently not enable runtime pm for the
2519  * subordinate display power domains. That is only done on the first modeset
2520  * using intel_display_set_init_power().
2521  */
2522 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2523 {
2524         struct drm_device *dev = dev_priv->dev;
2525         struct device *device = &dev->pdev->dev;
2526
2527         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2528         pm_runtime_mark_last_busy(device);
2529
2530         /*
2531          * Take a permanent reference to disable the RPM functionality and drop
2532          * it only when unloading the driver. Use the low level get/put helpers,
2533          * so the driver's own RPM reference tracking asserts also work on
2534          * platforms without RPM support.
2535          */
2536         if (!HAS_RUNTIME_PM(dev)) {
2537                 pm_runtime_dont_use_autosuspend(device);
2538                 pm_runtime_get_sync(device);
2539         } else {
2540                 pm_runtime_use_autosuspend(device);
2541         }
2542
2543         /*
2544          * The core calls the driver load handler with an RPM reference held.
2545          * We drop that here and will reacquire it during unloading in
2546          * intel_power_domains_fini().
2547          */
2548         pm_runtime_put_autosuspend(device);
2549 }
2550