drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
  50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
  51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
  52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
  53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
  54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
  55
  56 /* For large FW files the time to complete can be very long */
  57 #define USBC_PD_POLLING_LIMIT_S 240
  58
  59 /* Read USB-PD from LFB */
  60 #define GFX_CMD_USB_PD_USE_LFB 0x480
  61
  62 /* Retry times for vmbx ready wait */
  63 #define PSP_VMBX_POLLING_LIMIT 20000
  64
  65 /* VBIOS gfl defines */
  66 #define MBOX_READY_MASK 0x80000000
  67 #define MBOX_STATUS_MASK 0x0000FFFF
  68 #define MBOX_COMMAND_MASK 0x00FF0000
  69 #define MBOX_READY_FLAG 0x80000000
  70 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  71 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  72 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  73
  74 /* memory training timeout define */
  75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  76
  77 static int psp_v13_0_init_microcode(struct psp_context *psp)
  78 {
  79         struct amdgpu_device *adev = psp->adev;
  80         char ucode_prefix[30];
  81         int err = 0;
  82
  83         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  84
  85         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
  86         case IP_VERSION(13, 0, 2):
  87                 err = psp_init_sos_microcode(psp, ucode_prefix);
  88                 if (err)
  89                         return err;
  90                 /* It's not necessary to load ras ta on Guest side */
  91                 if (!amdgpu_sriov_vf(adev)) {
  92                         err = psp_init_ta_microcode(psp, ucode_prefix);
  93                         if (err)
  94                                 return err;
  95                 }
  96                 break;
  97         case IP_VERSION(13, 0, 1):
  98         case IP_VERSION(13, 0, 3):
  99         case IP_VERSION(13, 0, 5):
 100         case IP_VERSION(13, 0, 8):
 101         case IP_VERSION(13, 0, 11):
 102         case IP_VERSION(14, 0, 0):
 103                 err = psp_init_toc_microcode(psp, ucode_prefix);
 104                 if (err)
 105                         return err;
 106                 err = psp_init_ta_microcode(psp, ucode_prefix);
 107                 if (err)
 108                         return err;
 109                 break;
 110         case IP_VERSION(13, 0, 0):
 111         case IP_VERSION(13, 0, 6):
 112         case IP_VERSION(13, 0, 7):
 113         case IP_VERSION(13, 0, 10):
 114                 err = psp_init_sos_microcode(psp, ucode_prefix);
 115                 if (err)
 116                         return err;
 117                 /* It's not necessary to load ras ta on Guest side */
 118                 err = psp_init_ta_microcode(psp, ucode_prefix);
 119                 if (err)
 120                         return err;
 121                 break;
 122         default:
 123                 BUG();
 124         }
 125
 126         return 0;
 127 }
 128
 129 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 130 {
 131         struct amdgpu_device *adev = psp->adev;
 132         uint32_t sol_reg;
 133
 134         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 135
 136         return sol_reg != 0x0;
 137 }
 138
 139 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
 140 {
 141         struct amdgpu_device *adev = psp->adev;
 142         int retry_loop, ret;
 143
 144         for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
 145                 /* Wait for bootloader to signify that is
 146                    ready having bit 31 of C2PMSG_33 set to 1 */
 147                 ret = psp_wait_for(
 148                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
 149                         0x80000000, 0xffffffff, false);
 150
 151                 if (ret == 0)
 152                         break;
 153         }
 154
 155         if (ret)
 156                 dev_warn(adev->dev, "Bootloader wait timed out");
 157
 158         return ret;
 159 }
 160
 161 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 162 {
 163         struct amdgpu_device *adev = psp->adev;
 164         int retry_loop, ret;
 165
 166         /* Wait for bootloader to signify that it is ready having bit 31 of
 167          * C2PMSG_35 set to 1. All other bits are expected to be cleared.
 168          * If there is an error in processing command, bits[7:0] will be set.
 169          * This is applicable for PSP v13.0.6 and newer.
 170          */
 171         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 172                 ret = psp_wait_for(
 173                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 174                         0x80000000, 0xffffffff, false);
 175
 176                 if (ret == 0)
 177                         return 0;
 178         }
 179
 180         return ret;
 181 }
 182
 183 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
 184 {
 185         struct amdgpu_device *adev = psp->adev;
 186
 187         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
 188                 psp_v13_0_wait_for_vmbx_ready(psp);
 189
 190                 return psp_v13_0_wait_for_bootloader(psp);
 191         }
 192
 193         return 0;
 194 }
 195
 196 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 197                                                struct psp_bin_desc      *bin_desc,
 198                                                enum psp_bootloader_cmd  bl_cmd)
 199 {
 200         int ret;
 201         uint32_t psp_gfxdrv_command_reg = 0;
 202         struct amdgpu_device *adev = psp->adev;
 203
 204         /* Check tOS sign of life register to confirm sys driver and sOS
 205          * are already been loaded.
 206          */
 207         if (psp_v13_0_is_sos_alive(psp))
 208                 return 0;
 209
 210         ret = psp_v13_0_wait_for_bootloader(psp);
 211         if (ret)
 212                 return ret;
 213
 214         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 215
 216         /* Copy PSP KDB binary to memory */
 217         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 218
 219         /* Provide the PSP KDB to bootloader */
 220         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 221                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 222         psp_gfxdrv_command_reg = bl_cmd;
 223         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 224                psp_gfxdrv_command_reg);
 225
 226         ret = psp_v13_0_wait_for_bootloader(psp);
 227
 228         return ret;
 229 }
 230
 231 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 232 {
 233         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 234 }
 235
 236 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 237 {
 238         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 239 }
 240
 241 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 242 {
 243         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 244 }
 245
 246 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 247 {
 248         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 249 }
 250
 251 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 252 {
 253         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 254 }
 255
 256 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 257 {
 258         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 259 }
 260
 261 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
 262 {
 263         return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 264 }
 265
 266
 267 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 268 {
 269         int ret;
 270         unsigned int psp_gfxdrv_command_reg = 0;
 271         struct amdgpu_device *adev = psp->adev;
 272
 273         /* Check sOS sign of life register to confirm sys driver and sOS
 274          * are already been loaded.
 275          */
 276         if (psp_v13_0_is_sos_alive(psp))
 277                 return 0;
 278
 279         ret = psp_v13_0_wait_for_bootloader(psp);
 280         if (ret)
 281                 return ret;
 282
 283         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 284
 285         /* Copy Secure OS binary to PSP memory */
 286         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 287
 288         /* Provide the PSP secure OS to bootloader */
 289         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 290                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 291         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 292         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 293                psp_gfxdrv_command_reg);
 294
 295         /* there might be handshake issue with hardware which needs delay */
 296         mdelay(20);
 297         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 298                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 299                            0, true);
 300
 301         return ret;
 302 }
 303
 304 static int psp_v13_0_ring_stop(struct psp_context *psp,
 305                                enum psp_ring_type ring_type)
 306 {
 307         int ret = 0;
 308         struct amdgpu_device *adev = psp->adev;
 309
 310         if (amdgpu_sriov_vf(adev)) {
 311                 /* Write the ring destroy command*/
 312                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 313                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 314                 /* there might be handshake issue with hardware which needs delay */
 315                 mdelay(20);
 316                 /* Wait for response flag (bit 31) */
 317                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 318                                    0x80000000, 0x80000000, false);
 319         } else {
 320                 /* Write the ring destroy command*/
 321                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 322                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 323                 /* there might be handshake issue with hardware which needs delay */
 324                 mdelay(20);
 325                 /* Wait for response flag (bit 31) */
 326                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 327                                    0x80000000, 0x80000000, false);
 328         }
 329
 330         return ret;
 331 }
 332
 333 static int psp_v13_0_ring_create(struct psp_context *psp,
 334                                  enum psp_ring_type ring_type)
 335 {
 336         int ret = 0;
 337         unsigned int psp_ring_reg = 0;
 338         struct psp_ring *ring = &psp->km_ring;
 339         struct amdgpu_device *adev = psp->adev;
 340
 341         if (amdgpu_sriov_vf(adev)) {
 342                 ret = psp_v13_0_ring_stop(psp, ring_type);
 343                 if (ret) {
 344                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 345                         return ret;
 346                 }
 347
 348                 /* Write low address of the ring to C2PMSG_102 */
 349                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 350                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 351                 /* Write high address of the ring to C2PMSG_103 */
 352                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 353                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 354
 355                 /* Write the ring initialization command to C2PMSG_101 */
 356                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 357                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 358
 359                 /* there might be handshake issue with hardware which needs delay */
 360                 mdelay(20);
 361
 362                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 363                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 364                                    0x80000000, 0x8000FFFF, false);
 365
 366         } else {
 367                 /* Wait for sOS ready for ring creation */
 368                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 369                                    0x80000000, 0x80000000, false);
 370                 if (ret) {
 371                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 372                         return ret;
 373                 }
 374
 375                 /* Write low address of the ring to C2PMSG_69 */
 376                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 377                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 378                 /* Write high address of the ring to C2PMSG_70 */
 379                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 380                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 381                 /* Write size of ring to C2PMSG_71 */
 382                 psp_ring_reg = ring->ring_size;
 383                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 384                 /* Write the ring initialization command to C2PMSG_64 */
 385                 psp_ring_reg = ring_type;
 386                 psp_ring_reg = psp_ring_reg << 16;
 387                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 388
 389                 /* there might be handshake issue with hardware which needs delay */
 390                 mdelay(20);
 391
 392                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 393                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 394                                    0x80000000, 0x8000FFFF, false);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 401                                   enum psp_ring_type ring_type)
 402 {
 403         int ret = 0;
 404         struct psp_ring *ring = &psp->km_ring;
 405         struct amdgpu_device *adev = psp->adev;
 406
 407         ret = psp_v13_0_ring_stop(psp, ring_type);
 408         if (ret)
 409                 DRM_ERROR("Fail to stop psp ring\n");
 410
 411         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 412                               &ring->ring_mem_mc_addr,
 413                               (void **)&ring->ring_mem);
 414
 415         return ret;
 416 }
 417
 418 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 419 {
 420         uint32_t data;
 421         struct amdgpu_device *adev = psp->adev;
 422
 423         if (amdgpu_sriov_vf(adev))
 424                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 425         else
 426                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 427
 428         return data;
 429 }
 430
 431 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 432 {
 433         struct amdgpu_device *adev = psp->adev;
 434
 435         if (amdgpu_sriov_vf(adev)) {
 436                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 437                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 438                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 439         } else
 440                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 441 }
 442
 443 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 444 {
 445         int ret;
 446         int i;
 447         uint32_t data_32;
 448         int max_wait;
 449         struct amdgpu_device *adev = psp->adev;
 450
 451         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 452         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 453         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 454
 455         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 456         for (i = 0; i < max_wait; i++) {
 457                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 458                                    0x80000000, 0x80000000, false);
 459                 if (ret == 0)
 460                         break;
 461         }
 462         if (i < max_wait)
 463                 ret = 0;
 464         else
 465                 ret = -ETIME;
 466
 467         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 468                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 469                   (ret == 0) ? "succeed" : "failed",
 470                   i, adev->usec_timeout/1000);
 471         return ret;
 472 }
 473
 474
 475 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 476 {
 477         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 478         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 479         struct amdgpu_device *adev = psp->adev;
 480         uint32_t p2c_header[4];
 481         uint32_t sz;
 482         void *buf;
 483         int ret, idx;
 484
 485         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 486                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 487                 return 0;
 488         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 489                 dev_err(adev->dev, "Memory training initialization failure.\n");
 490                 return -EINVAL;
 491         }
 492
 493         if (psp_v13_0_is_sos_alive(psp)) {
 494                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 495                 return 0;
 496         }
 497
 498         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 499         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 500                   pcache[0], pcache[1], pcache[2], pcache[3],
 501                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 502
 503         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 504                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 505                 ops |= PSP_MEM_TRAIN_RESTORE;
 506         }
 507
 508         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 509             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 510                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 511                 ops |= PSP_MEM_TRAIN_SAVE;
 512         }
 513
 514         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 515             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 516               pcache[3] == p2c_header[3])) {
 517                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 518                 ops |= PSP_MEM_TRAIN_SAVE;
 519         }
 520
 521         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 522             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 523                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 524                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 525         }
 526
 527         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 528                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 529                 ops |= PSP_MEM_TRAIN_SAVE;
 530         }
 531
 532         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 533
 534         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 535                 /*
 536                  * Long training will encroach a certain amount on the bottom of VRAM;
 537                  * save the content from the bottom of VRAM to system memory
 538                  * before training, and restore it after training to avoid
 539                  * VRAM corruption.
 540                  */
 541                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 542
 543                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 544                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 545                                   adev->gmc.visible_vram_size,
 546                                   adev->mman.aper_base_kaddr);
 547                         return -EINVAL;
 548                 }
 549
 550                 buf = vmalloc(sz);
 551                 if (!buf) {
 552                         dev_err(adev->dev, "failed to allocate system memory.\n");
 553                         return -ENOMEM;
 554                 }
 555
 556                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 557                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 558                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 559                         if (ret) {
 560                                 DRM_ERROR("Send long training msg failed.\n");
 561                                 vfree(buf);
 562                                 drm_dev_exit(idx);
 563                                 return ret;
 564                         }
 565
 566                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 567                         adev->hdp.funcs->flush_hdp(adev, NULL);
 568                         vfree(buf);
 569                         drm_dev_exit(idx);
 570                 } else {
 571                         vfree(buf);
 572                         return -ENODEV;
 573                 }
 574         }
 575
 576         if (ops & PSP_MEM_TRAIN_SAVE) {
 577                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 578         }
 579
 580         if (ops & PSP_MEM_TRAIN_RESTORE) {
 581                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 582         }
 583
 584         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 585                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 586                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 587                 if (ret) {
 588                         dev_err(adev->dev, "send training msg failed.\n");
 589                         return ret;
 590                 }
 591         }
 592         ctx->training_cnt++;
 593         return 0;
 594 }
 595
 596 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 597 {
 598         struct amdgpu_device *adev = psp->adev;
 599         uint32_t reg_status;
 600         int ret, i = 0;
 601
 602         /*
 603          * LFB address which is aligned to 1MB address and has to be
 604          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 605          * register
 606          */
 607         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 608
 609         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 610                              0x80000000, 0x80000000, false);
 611         if (ret)
 612                 return ret;
 613
 614         /* Fireup interrupt so PSP can pick up the address */
 615         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 616
 617         /* FW load takes very long time */
 618         do {
 619                 msleep(1000);
 620                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 621
 622                 if (reg_status & 0x80000000)
 623                         goto done;
 624
 625         } while (++i < USBC_PD_POLLING_LIMIT_S);
 626
 627         return -ETIME;
 628 done:
 629
 630         if ((reg_status & 0xFFFF) != 0) {
 631                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 632                                 reg_status & 0xFFFF);
 633                 return -EIO;
 634         }
 635
 636         return 0;
 637 }
 638
 639 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 640 {
 641         struct amdgpu_device *adev = psp->adev;
 642         int ret;
 643
 644         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 645
 646         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 647                                      0x80000000, 0x80000000, false);
 648         if (!ret)
 649                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 650
 651         return ret;
 652 }
 653
 654 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 655 {
 656         uint32_t reg_status = 0, reg_val = 0;
 657         struct amdgpu_device *adev = psp->adev;
 658         int ret;
 659
 660         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 661         reg_val |= (cmd << 16);
 662         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 663
 664         /* Ring the doorbell */
 665         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 666
 667         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 668                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 669                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 670         else
 671                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 672                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 673         if (ret) {
 674                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 675                 return ret;
 676         }
 677
 678         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 679         if ((reg_status & 0xFFFF) != 0) {
 680                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 681                                 cmd, reg_status & 0xFFFF);
 682                 return -EIO;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int psp_v13_0_update_spirom(struct psp_context *psp,
 689                                    uint64_t fw_pri_mc_addr)
 690 {
 691         struct amdgpu_device *adev = psp->adev;
 692         int ret;
 693
 694         /* Confirm PSP is ready to start */
 695         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 696                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 697         if (ret) {
 698                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 699                 return ret;
 700         }
 701
 702         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 703
 704         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 705         if (ret)
 706                 return ret;
 707
 708         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 709
 710         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 711         if (ret)
 712                 return ret;
 713
 714         psp->vbflash_done = true;
 715
 716         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 717         if (ret)
 718                 return ret;
 719
 720         return 0;
 721 }
 722
 723 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 724 {
 725         struct amdgpu_device *adev = psp->adev;
 726
 727         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 728 }
 729
 730 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
 731 {
 732         struct amdgpu_device *adev = psp->adev;
 733
 734         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
 735                 uint32_t  reg_data;
 736                 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
 737                  * during MP1 triggered sync flood.
 738                  */
 739                 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 740                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
 741
 742                 /* delay 1000ms for the mode1 reset for fatal error
 743                  * to be recovered back.
 744                  */
 745                 msleep(1000);
 746         }
 747
 748         return 0;
 749 }
 750
 751 static const struct psp_funcs psp_v13_0_funcs = {
 752         .init_microcode = psp_v13_0_init_microcode,
 753         .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
 754         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 755         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 756         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 757         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 758         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 759         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 760         .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 761         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 762         .ring_create = psp_v13_0_ring_create,
 763         .ring_stop = psp_v13_0_ring_stop,
 764         .ring_destroy = psp_v13_0_ring_destroy,
 765         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 766         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 767         .mem_training = psp_v13_0_memory_training,
 768         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 769         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 770         .update_spirom = psp_v13_0_update_spirom,
 771         .vbflash_stat = psp_v13_0_vbflash_status,
 772         .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
 773 };
 774
 775 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 776 {
 777         psp->funcs = &psp_v13_0_funcs;
 778 }