drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

   1 /*
   2  * DMM IOMMU driver support functions for TI OMAP processors.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  * Author: Rob Clark <[email protected]>
   6  *         Andy Gross <[email protected]>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation version 2.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/completion.h>
  19 #include <linux/delay.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/errno.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/list.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h> /* platform_device() */
  28 #include <linux/sched.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 #include <linux/time.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/wait.h>
  34
  35 #include "omap_dmm_tiler.h"
  36 #include "omap_dmm_priv.h"
  37
  38 #define DMM_DRIVER_NAME "dmm"
  39
  40 /* mappings for associating views to luts */
  41 static struct tcm *containers[TILFMT_NFORMATS];
  42 static struct dmm *omap_dmm;
  43
  44 #if defined(CONFIG_OF)
  45 static const struct of_device_id dmm_of_match[];
  46 #endif
  47
  48 /* global spinlock for protecting lists */
  49 static DEFINE_SPINLOCK(list_lock);
  50
  51 /* Geometry table */
  52 #define GEOM(xshift, yshift, bytes_per_pixel) { \
  53                 .x_shft = (xshift), \
  54                 .y_shft = (yshift), \
  55                 .cpp    = (bytes_per_pixel), \
  56                 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
  57                 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
  58         }
  59
  60 static const struct {
  61         u32 x_shft;     /* unused X-bits (as part of bpp) */
  62         u32 y_shft;     /* unused Y-bits (as part of bpp) */
  63         u32 cpp;                /* bytes/chars per pixel */
  64         u32 slot_w;     /* width of each slot (in pixels) */
  65         u32 slot_h;     /* height of each slot (in pixels) */
  66 } geom[TILFMT_NFORMATS] = {
  67         [TILFMT_8BIT]  = GEOM(0, 0, 1),
  68         [TILFMT_16BIT] = GEOM(0, 1, 2),
  69         [TILFMT_32BIT] = GEOM(1, 1, 4),
  70         [TILFMT_PAGE]  = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
  71 };
  72
  73
  74 /* lookup table for registers w/ per-engine instances */
  75 static const u32 reg[][4] = {
  76         [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
  77                         DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
  78         [PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
  79                         DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
  80 };
  81
  82 static u32 dmm_read(struct dmm *dmm, u32 reg)
  83 {
  84         return readl(dmm->base + reg);
  85 }
  86
  87 static void dmm_write(struct dmm *dmm, u32 val, u32 reg)
  88 {
  89         writel(val, dmm->base + reg);
  90 }
  91
  92 /* simple allocator to grab next 16 byte aligned memory from txn */
  93 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
  94 {
  95         void *ptr;
  96         struct refill_engine *engine = txn->engine_handle;
  97
  98         /* dmm programming requires 16 byte aligned addresses */
  99         txn->current_pa = round_up(txn->current_pa, 16);
 100         txn->current_va = (void *)round_up((long)txn->current_va, 16);
 101
 102         ptr = txn->current_va;
 103         *pa = txn->current_pa;
 104
 105         txn->current_pa += sz;
 106         txn->current_va += sz;
 107
 108         BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
 109
 110         return ptr;
 111 }
 112
 113 /* check status and spin until wait_mask comes true */
 114 static int wait_status(struct refill_engine *engine, u32 wait_mask)
 115 {
 116         struct dmm *dmm = engine->dmm;
 117         u32 r = 0, err, i;
 118
 119         i = DMM_FIXED_RETRY_COUNT;
 120         while (true) {
 121                 r = dmm_read(dmm, reg[PAT_STATUS][engine->id]);
 122                 err = r & DMM_PATSTATUS_ERR;
 123                 if (err) {
 124                         dev_err(dmm->dev,
 125                                 "%s: error (engine%d). PAT_STATUS: 0x%08x\n",
 126                                 __func__, engine->id, r);
 127                         return -EFAULT;
 128                 }
 129
 130                 if ((r & wait_mask) == wait_mask)
 131                         break;
 132
 133                 if (--i == 0) {
 134                         dev_err(dmm->dev,
 135                                 "%s: timeout (engine%d). PAT_STATUS: 0x%08x\n",
 136                                 __func__, engine->id, r);
 137                         return -ETIMEDOUT;
 138                 }
 139
 140                 udelay(1);
 141         }
 142
 143         return 0;
 144 }
 145
 146 static void release_engine(struct refill_engine *engine)
 147 {
 148         unsigned long flags;
 149
 150         spin_lock_irqsave(&list_lock, flags);
 151         list_add(&engine->idle_node, &omap_dmm->idle_head);
 152         spin_unlock_irqrestore(&list_lock, flags);
 153
 154         atomic_inc(&omap_dmm->engine_counter);
 155         wake_up_interruptible(&omap_dmm->engine_queue);
 156 }
 157
 158 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
 159 {
 160         struct dmm *dmm = arg;
 161         u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS);
 162         int i;
 163
 164         /* ack IRQ */
 165         dmm_write(dmm, status, DMM_PAT_IRQSTATUS);
 166
 167         for (i = 0; i < dmm->num_engines; i++) {
 168                 if (status & DMM_IRQSTAT_ERR_MASK)
 169                         dev_err(dmm->dev,
 170                                 "irq error(engine%d): IRQSTAT 0x%02x\n",
 171                                 i, status & 0xff);
 172
 173                 if (status & DMM_IRQSTAT_LST) {
 174                         if (dmm->engines[i].async)
 175                                 release_engine(&dmm->engines[i]);
 176
 177                         complete(&dmm->engines[i].compl);
 178                 }
 179
 180                 status >>= 8;
 181         }
 182
 183         return IRQ_HANDLED;
 184 }
 185
 186 /**
 187  * Get a handle for a DMM transaction
 188  */
 189 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
 190 {
 191         struct dmm_txn *txn = NULL;
 192         struct refill_engine *engine = NULL;
 193         int ret;
 194         unsigned long flags;
 195
 196
 197         /* wait until an engine is available */
 198         ret = wait_event_interruptible(omap_dmm->engine_queue,
 199                 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
 200         if (ret)
 201                 return ERR_PTR(ret);
 202
 203         /* grab an idle engine */
 204         spin_lock_irqsave(&list_lock, flags);
 205         if (!list_empty(&dmm->idle_head)) {
 206                 engine = list_entry(dmm->idle_head.next, struct refill_engine,
 207                                         idle_node);
 208                 list_del(&engine->idle_node);
 209         }
 210         spin_unlock_irqrestore(&list_lock, flags);
 211
 212         BUG_ON(!engine);
 213
 214         txn = &engine->txn;
 215         engine->tcm = tcm;
 216         txn->engine_handle = engine;
 217         txn->last_pat = NULL;
 218         txn->current_va = engine->refill_va;
 219         txn->current_pa = engine->refill_pa;
 220
 221         return txn;
 222 }
 223
 224 /**
 225  * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 226  * corresponding slot is cleared (ie. dummy_pa is programmed)
 227  */
 228 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
 229                 struct page **pages, u32 npages, u32 roll)
 230 {
 231         dma_addr_t pat_pa = 0, data_pa = 0;
 232         u32 *data;
 233         struct pat *pat;
 234         struct refill_engine *engine = txn->engine_handle;
 235         int columns = (1 + area->x1 - area->x0);
 236         int rows = (1 + area->y1 - area->y0);
 237         int i = columns*rows;
 238
 239         pat = alloc_dma(txn, sizeof(*pat), &pat_pa);
 240
 241         if (txn->last_pat)
 242                 txn->last_pat->next_pa = (u32)pat_pa;
 243
 244         pat->area = *area;
 245
 246         /* adjust Y coordinates based off of container parameters */
 247         pat->area.y0 += engine->tcm->y_offset;
 248         pat->area.y1 += engine->tcm->y_offset;
 249
 250         pat->ctrl = (struct pat_ctrl){
 251                         .start = 1,
 252                         .lut_id = engine->tcm->lut_id,
 253                 };
 254
 255         data = alloc_dma(txn, 4*i, &data_pa);
 256         /* FIXME: what if data_pa is more than 32-bit ? */
 257         pat->data_pa = data_pa;
 258
 259         while (i--) {
 260                 int n = i + roll;
 261                 if (n >= npages)
 262                         n -= npages;
 263                 data[i] = (pages && pages[n]) ?
 264                         page_to_phys(pages[n]) : engine->dmm->dummy_pa;
 265         }
 266
 267         txn->last_pat = pat;
 268
 269         return;
 270 }
 271
 272 /**
 273  * Commit the DMM transaction.
 274  */
 275 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
 276 {
 277         int ret = 0;
 278         struct refill_engine *engine = txn->engine_handle;
 279         struct dmm *dmm = engine->dmm;
 280
 281         if (!txn->last_pat) {
 282                 dev_err(engine->dmm->dev, "need at least one txn\n");
 283                 ret = -EINVAL;
 284                 goto cleanup;
 285         }
 286
 287         txn->last_pat->next_pa = 0;
 288
 289         /* write to PAT_DESCR to clear out any pending transaction */
 290         dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);
 291
 292         /* wait for engine ready: */
 293         ret = wait_status(engine, DMM_PATSTATUS_READY);
 294         if (ret) {
 295                 ret = -EFAULT;
 296                 goto cleanup;
 297         }
 298
 299         /* mark whether it is async to denote list management in IRQ handler */
 300         engine->async = wait ? false : true;
 301         reinit_completion(&engine->compl);
 302         /* verify that the irq handler sees the 'async' and completion value */
 303         smp_mb();
 304
 305         /* kick reload */
 306         dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);
 307
 308         if (wait) {
 309                 if (!wait_for_completion_timeout(&engine->compl,
 310                                 msecs_to_jiffies(100))) {
 311                         dev_err(dmm->dev, "timed out waiting for done\n");
 312                         ret = -ETIMEDOUT;
 313                         goto cleanup;
 314                 }
 315
 316                 /* Check the engine status before continue */
 317                 ret = wait_status(engine, DMM_PATSTATUS_READY |
 318                                   DMM_PATSTATUS_VALID | DMM_PATSTATUS_DONE);
 319         }
 320
 321 cleanup:
 322         /* only place engine back on list if we are done with it */
 323         if (ret || wait)
 324                 release_engine(engine);
 325
 326         return ret;
 327 }
 328
 329 /*
 330  * DMM programming
 331  */
 332 static int fill(struct tcm_area *area, struct page **pages,
 333                 u32 npages, u32 roll, bool wait)
 334 {
 335         int ret = 0;
 336         struct tcm_area slice, area_s;
 337         struct dmm_txn *txn;
 338
 339         /*
 340          * FIXME
 341          *
 342          * Asynchronous fill does not work reliably, as the driver does not
 343          * handle errors in the async code paths. The fill operation may
 344          * silently fail, leading to leaking DMM engines, which may eventually
 345          * lead to deadlock if we run out of DMM engines.
 346          *
 347          * For now, always set 'wait' so that we only use sync fills. Async
 348          * fills should be fixed, or alternatively we could decide to only
 349          * support sync fills and so the whole async code path could be removed.
 350          */
 351
 352         wait = true;
 353
 354         txn = dmm_txn_init(omap_dmm, area->tcm);
 355         if (IS_ERR_OR_NULL(txn))
 356                 return -ENOMEM;
 357
 358         tcm_for_each_slice(slice, *area, area_s) {
 359                 struct pat_area p_area = {
 360                                 .x0 = slice.p0.x,  .y0 = slice.p0.y,
 361                                 .x1 = slice.p1.x,  .y1 = slice.p1.y,
 362                 };
 363
 364                 dmm_txn_append(txn, &p_area, pages, npages, roll);
 365
 366                 roll += tcm_sizeof(slice);
 367         }
 368
 369         ret = dmm_txn_commit(txn, wait);
 370
 371         return ret;
 372 }
 373
 374 /*
 375  * Pin/unpin
 376  */
 377
 378 /* note: slots for which pages[i] == NULL are filled w/ dummy page
 379  */
 380 int tiler_pin(struct tiler_block *block, struct page **pages,
 381                 u32 npages, u32 roll, bool wait)
 382 {
 383         int ret;
 384
 385         ret = fill(&block->area, pages, npages, roll, wait);
 386
 387         if (ret)
 388                 tiler_unpin(block);
 389
 390         return ret;
 391 }
 392
 393 int tiler_unpin(struct tiler_block *block)
 394 {
 395         return fill(&block->area, NULL, 0, 0, false);
 396 }
 397
 398 /*
 399  * Reserve/release
 400  */
 401 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,
 402                 u16 h, u16 align)
 403 {
 404         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 405         u32 min_align = 128;
 406         int ret;
 407         unsigned long flags;
 408         u32 slot_bytes;
 409
 410         BUG_ON(!validfmt(fmt));
 411
 412         /* convert width/height to slots */
 413         w = DIV_ROUND_UP(w, geom[fmt].slot_w);
 414         h = DIV_ROUND_UP(h, geom[fmt].slot_h);
 415
 416         /* convert alignment to slots */
 417         slot_bytes = geom[fmt].slot_w * geom[fmt].cpp;
 418         min_align = max(min_align, slot_bytes);
 419         align = (align > min_align) ? ALIGN(align, min_align) : min_align;
 420         align /= slot_bytes;
 421
 422         block->fmt = fmt;
 423
 424         ret = tcm_reserve_2d(containers[fmt], w, h, align, -1, slot_bytes,
 425                         &block->area);
 426         if (ret) {
 427                 kfree(block);
 428                 return ERR_PTR(-ENOMEM);
 429         }
 430
 431         /* add to allocation list */
 432         spin_lock_irqsave(&list_lock, flags);
 433         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 434         spin_unlock_irqrestore(&list_lock, flags);
 435
 436         return block;
 437 }
 438
 439 struct tiler_block *tiler_reserve_1d(size_t size)
 440 {
 441         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 442         int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 443         unsigned long flags;
 444
 445         if (!block)
 446                 return ERR_PTR(-ENOMEM);
 447
 448         block->fmt = TILFMT_PAGE;
 449
 450         if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
 451                                 &block->area)) {
 452                 kfree(block);
 453                 return ERR_PTR(-ENOMEM);
 454         }
 455
 456         spin_lock_irqsave(&list_lock, flags);
 457         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 458         spin_unlock_irqrestore(&list_lock, flags);
 459
 460         return block;
 461 }
 462
 463 /* note: if you have pin'd pages, you should have already unpin'd first! */
 464 int tiler_release(struct tiler_block *block)
 465 {
 466         int ret = tcm_free(&block->area);
 467         unsigned long flags;
 468
 469         if (block->area.tcm)
 470                 dev_err(omap_dmm->dev, "failed to release block\n");
 471
 472         spin_lock_irqsave(&list_lock, flags);
 473         list_del(&block->alloc_node);
 474         spin_unlock_irqrestore(&list_lock, flags);
 475
 476         kfree(block);
 477         return ret;
 478 }
 479
 480 /*
 481  * Utils
 482  */
 483
 484 /* calculate the tiler space address of a pixel in a view orientation...
 485  * below description copied from the display subsystem section of TRM:
 486  *
 487  * When the TILER is addressed, the bits:
 488  *   [28:27] = 0x0 for 8-bit tiled
 489  *             0x1 for 16-bit tiled
 490  *             0x2 for 32-bit tiled
 491  *             0x3 for page mode
 492  *   [31:29] = 0x0 for 0-degree view
 493  *             0x1 for 180-degree view + mirroring
 494  *             0x2 for 0-degree view + mirroring
 495  *             0x3 for 180-degree view
 496  *             0x4 for 270-degree view + mirroring
 497  *             0x5 for 270-degree view
 498  *             0x6 for 90-degree view
 499  *             0x7 for 90-degree view + mirroring
 500  * Otherwise the bits indicated the corresponding bit address to access
 501  * the SDRAM.
 502  */
 503 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
 504 {
 505         u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
 506
 507         x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
 508         y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
 509         alignment = geom[fmt].x_shft + geom[fmt].y_shft;
 510
 511         /* validate coordinate */
 512         x_mask = MASK(x_bits);
 513         y_mask = MASK(y_bits);
 514
 515         if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
 516                 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
 517                                 x, x, x_mask, y, y, y_mask);
 518                 return 0;
 519         }
 520
 521         /* account for mirroring */
 522         if (orient & MASK_X_INVERT)
 523                 x ^= x_mask;
 524         if (orient & MASK_Y_INVERT)
 525                 y ^= y_mask;
 526
 527         /* get coordinate address */
 528         if (orient & MASK_XY_FLIP)
 529                 tmp = ((x << y_bits) + y);
 530         else
 531                 tmp = ((y << x_bits) + x);
 532
 533         return TIL_ADDR((tmp << alignment), orient, fmt);
 534 }
 535
 536 dma_addr_t tiler_ssptr(struct tiler_block *block)
 537 {
 538         BUG_ON(!validfmt(block->fmt));
 539
 540         return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
 541                         block->area.p0.x * geom[block->fmt].slot_w,
 542                         block->area.p0.y * geom[block->fmt].slot_h);
 543 }
 544
 545 dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,
 546                 u32 x, u32 y)
 547 {
 548         struct tcm_pt *p = &block->area.p0;
 549         BUG_ON(!validfmt(block->fmt));
 550
 551         return tiler_get_address(block->fmt, orient,
 552                         (p->x * geom[block->fmt].slot_w) + x,
 553                         (p->y * geom[block->fmt].slot_h) + y);
 554 }
 555
 556 void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h)
 557 {
 558         BUG_ON(!validfmt(fmt));
 559         *w = round_up(*w, geom[fmt].slot_w);
 560         *h = round_up(*h, geom[fmt].slot_h);
 561 }
 562
 563 u32 tiler_stride(enum tiler_fmt fmt, u32 orient)
 564 {
 565         BUG_ON(!validfmt(fmt));
 566
 567         if (orient & MASK_XY_FLIP)
 568                 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
 569         else
 570                 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
 571 }
 572
 573 size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h)
 574 {
 575         tiler_align(fmt, &w, &h);
 576         return geom[fmt].cpp * w * h;
 577 }
 578
 579 size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h)
 580 {
 581         BUG_ON(!validfmt(fmt));
 582         return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
 583 }
 584
 585 u32 tiler_get_cpu_cache_flags(void)
 586 {
 587         return omap_dmm->plat_data->cpu_cache_flags;
 588 }
 589
 590 bool dmm_is_available(void)
 591 {
 592         return omap_dmm ? true : false;
 593 }
 594
 595 static int omap_dmm_remove(struct platform_device *dev)
 596 {
 597         struct tiler_block *block, *_block;
 598         int i;
 599         unsigned long flags;
 600
 601         if (omap_dmm) {
 602                 /* free all area regions */
 603                 spin_lock_irqsave(&list_lock, flags);
 604                 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
 605                                         alloc_node) {
 606                         list_del(&block->alloc_node);
 607                         kfree(block);
 608                 }
 609                 spin_unlock_irqrestore(&list_lock, flags);
 610
 611                 for (i = 0; i < omap_dmm->num_lut; i++)
 612                         if (omap_dmm->tcm && omap_dmm->tcm[i])
 613                                 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
 614                 kfree(omap_dmm->tcm);
 615
 616                 kfree(omap_dmm->engines);
 617                 if (omap_dmm->refill_va)
 618                         dma_free_wc(omap_dmm->dev,
 619                                     REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 620                                     omap_dmm->refill_va, omap_dmm->refill_pa);
 621                 if (omap_dmm->dummy_page)
 622                         __free_page(omap_dmm->dummy_page);
 623
 624                 if (omap_dmm->irq > 0)
 625                         free_irq(omap_dmm->irq, omap_dmm);
 626
 627                 iounmap(omap_dmm->base);
 628                 kfree(omap_dmm);
 629                 omap_dmm = NULL;
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int omap_dmm_probe(struct platform_device *dev)
 636 {
 637         int ret = -EFAULT, i;
 638         struct tcm_area area = {0};
 639         u32 hwinfo, pat_geom;
 640         struct resource *mem;
 641
 642         omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
 643         if (!omap_dmm)
 644                 goto fail;
 645
 646         /* initialize lists */
 647         INIT_LIST_HEAD(&omap_dmm->alloc_head);
 648         INIT_LIST_HEAD(&omap_dmm->idle_head);
 649
 650         init_waitqueue_head(&omap_dmm->engine_queue);
 651
 652         if (dev->dev.of_node) {
 653                 const struct of_device_id *match;
 654
 655                 match = of_match_node(dmm_of_match, dev->dev.of_node);
 656                 if (!match) {
 657                         dev_err(&dev->dev, "failed to find matching device node\n");
 658                         ret = -ENODEV;
 659                         goto fail;
 660                 }
 661
 662                 omap_dmm->plat_data = match->data;
 663         }
 664
 665         /* lookup hwmod data - base address and irq */
 666         mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
 667         if (!mem) {
 668                 dev_err(&dev->dev, "failed to get base address resource\n");
 669                 goto fail;
 670         }
 671
 672         omap_dmm->base = ioremap(mem->start, SZ_2K);
 673
 674         if (!omap_dmm->base) {
 675                 dev_err(&dev->dev, "failed to get dmm base address\n");
 676                 goto fail;
 677         }
 678
 679         omap_dmm->irq = platform_get_irq(dev, 0);
 680         if (omap_dmm->irq < 0) {
 681                 dev_err(&dev->dev, "failed to get IRQ resource\n");
 682                 goto fail;
 683         }
 684
 685         omap_dmm->dev = &dev->dev;
 686
 687         hwinfo = dmm_read(omap_dmm, DMM_PAT_HWINFO);
 688         omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
 689         omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
 690         omap_dmm->container_width = 256;
 691         omap_dmm->container_height = 128;
 692
 693         atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
 694
 695         /* read out actual LUT width and height */
 696         pat_geom = dmm_read(omap_dmm, DMM_PAT_GEOMETRY);
 697         omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
 698         omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
 699
 700         /* increment LUT by one if on OMAP5 */
 701         /* LUT has twice the height, and is split into a separate container */
 702         if (omap_dmm->lut_height != omap_dmm->container_height)
 703                 omap_dmm->num_lut++;
 704
 705         /* initialize DMM registers */
 706         dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__0);
 707         dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__1);
 708         dmm_write(omap_dmm, 0x80808080, DMM_PAT_VIEW_MAP__0);
 709         dmm_write(omap_dmm, 0x80000000, DMM_PAT_VIEW_MAP_BASE);
 710         dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__0);
 711         dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__1);
 712
 713         ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
 714                                 "omap_dmm_irq_handler", omap_dmm);
 715
 716         if (ret) {
 717                 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
 718                         omap_dmm->irq, ret);
 719                 omap_dmm->irq = -1;
 720                 goto fail;
 721         }
 722
 723         /* Enable all interrupts for each refill engine except
 724          * ERR_LUT_MISS<n> (which is just advisory, and we don't care
 725          * about because we want to be able to refill live scanout
 726          * buffers for accelerated pan/scroll) and FILL_DSC<n> which
 727          * we just generally don't care about.
 728          */
 729         dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_SET);
 730
 731         omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
 732         if (!omap_dmm->dummy_page) {
 733                 dev_err(&dev->dev, "could not allocate dummy page\n");
 734                 ret = -ENOMEM;
 735                 goto fail;
 736         }
 737
 738         /* set dma mask for device */
 739         ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 740         if (ret)
 741                 goto fail;
 742
 743         omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
 744
 745         /* alloc refill memory */
 746         omap_dmm->refill_va = dma_alloc_wc(&dev->dev,
 747                                            REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 748                                            &omap_dmm->refill_pa, GFP_KERNEL);
 749         if (!omap_dmm->refill_va) {
 750                 dev_err(&dev->dev, "could not allocate refill memory\n");
 751                 goto fail;
 752         }
 753
 754         /* alloc engines */
 755         omap_dmm->engines = kcalloc(omap_dmm->num_engines,
 756                                     sizeof(*omap_dmm->engines), GFP_KERNEL);
 757         if (!omap_dmm->engines) {
 758                 ret = -ENOMEM;
 759                 goto fail;
 760         }
 761
 762         for (i = 0; i < omap_dmm->num_engines; i++) {
 763                 omap_dmm->engines[i].id = i;
 764                 omap_dmm->engines[i].dmm = omap_dmm;
 765                 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
 766                                                 (REFILL_BUFFER_SIZE * i);
 767                 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
 768                                                 (REFILL_BUFFER_SIZE * i);
 769                 init_completion(&omap_dmm->engines[i].compl);
 770
 771                 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
 772         }
 773
 774         omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm),
 775                                 GFP_KERNEL);
 776         if (!omap_dmm->tcm) {
 777                 ret = -ENOMEM;
 778                 goto fail;
 779         }
 780
 781         /* init containers */
 782         /* Each LUT is associated with a TCM (container manager).  We use the
 783            lut_id to denote the lut_id used to identify the correct LUT for
 784            programming during reill operations */
 785         for (i = 0; i < omap_dmm->num_lut; i++) {
 786                 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
 787                                                 omap_dmm->container_height);
 788
 789                 if (!omap_dmm->tcm[i]) {
 790                         dev_err(&dev->dev, "failed to allocate container\n");
 791                         ret = -ENOMEM;
 792                         goto fail;
 793                 }
 794
 795                 omap_dmm->tcm[i]->lut_id = i;
 796         }
 797
 798         /* assign access mode containers to applicable tcm container */
 799         /* OMAP 4 has 1 container for all 4 views */
 800         /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
 801         containers[TILFMT_8BIT] = omap_dmm->tcm[0];
 802         containers[TILFMT_16BIT] = omap_dmm->tcm[0];
 803         containers[TILFMT_32BIT] = omap_dmm->tcm[0];
 804
 805         if (omap_dmm->container_height != omap_dmm->lut_height) {
 806                 /* second LUT is used for PAGE mode.  Programming must use
 807                    y offset that is added to all y coordinates.  LUT id is still
 808                    0, because it is the same LUT, just the upper 128 lines */
 809                 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
 810                 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
 811                 omap_dmm->tcm[1]->lut_id = 0;
 812         } else {
 813                 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
 814         }
 815
 816         area = (struct tcm_area) {
 817                 .tcm = NULL,
 818                 .p1.x = omap_dmm->container_width - 1,
 819                 .p1.y = omap_dmm->container_height - 1,
 820         };
 821
 822         /* initialize all LUTs to dummy page entries */
 823         for (i = 0; i < omap_dmm->num_lut; i++) {
 824                 area.tcm = omap_dmm->tcm[i];
 825                 if (fill(&area, NULL, 0, 0, true))
 826                         dev_err(omap_dmm->dev, "refill failed");
 827         }
 828
 829         dev_info(omap_dmm->dev, "initialized all PAT entries\n");
 830
 831         return 0;
 832
 833 fail:
 834         if (omap_dmm_remove(dev))
 835                 dev_err(&dev->dev, "cleanup failed\n");
 836         return ret;
 837 }
 838
 839 /*
 840  * debugfs support
 841  */
 842
 843 #ifdef CONFIG_DEBUG_FS
 844
 845 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
 846                                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
 847 static const char *special = ".,:;'\"`~!^-+";
 848
 849 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
 850                                                         char c, bool ovw)
 851 {
 852         int x, y;
 853         for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
 854                 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
 855                         if (map[y][x] == ' ' || ovw)
 856                                 map[y][x] = c;
 857 }
 858
 859 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
 860                                                                         char c)
 861 {
 862         map[p->y / ydiv][p->x / xdiv] = c;
 863 }
 864
 865 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
 866 {
 867         return map[p->y / ydiv][p->x / xdiv];
 868 }
 869
 870 static int map_width(int xdiv, int x0, int x1)
 871 {
 872         return (x1 / xdiv) - (x0 / xdiv) + 1;
 873 }
 874
 875 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
 876 {
 877         char *p = map[yd] + (x0 / xdiv);
 878         int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
 879         if (w >= 0) {
 880                 p += w;
 881                 while (*nice)
 882                         *p++ = *nice++;
 883         }
 884 }
 885
 886 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
 887                                                         struct tcm_area *a)
 888 {
 889         sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
 890         if (a->p0.y + 1 < a->p1.y) {
 891                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
 892                                                         256 - 1);
 893         } else if (a->p0.y < a->p1.y) {
 894                 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
 895                         text_map(map, xdiv, nice, a->p0.y / ydiv,
 896                                         a->p0.x + xdiv, 256 - 1);
 897                 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
 898                         text_map(map, xdiv, nice, a->p1.y / ydiv,
 899                                         0, a->p1.y - xdiv);
 900         } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
 901                 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
 902         }
 903 }
 904
 905 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
 906                                                         struct tcm_area *a)
 907 {
 908         sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
 909         if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
 910                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
 911                                                         a->p0.x, a->p1.x);
 912 }
 913
 914 int tiler_map_show(struct seq_file *s, void *arg)
 915 {
 916         int xdiv = 2, ydiv = 1;
 917         char **map = NULL, *global_map;
 918         struct tiler_block *block;
 919         struct tcm_area a, p;
 920         int i;
 921         const char *m2d = alphabet;
 922         const char *a2d = special;
 923         const char *m2dp = m2d, *a2dp = a2d;
 924         char nice[128];
 925         int h_adj;
 926         int w_adj;
 927         unsigned long flags;
 928         int lut_idx;
 929
 930
 931         if (!omap_dmm) {
 932                 /* early return if dmm/tiler device is not initialized */
 933                 return 0;
 934         }
 935
 936         h_adj = omap_dmm->container_height / ydiv;
 937         w_adj = omap_dmm->container_width / xdiv;
 938
 939         map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL);
 940         global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL);
 941
 942         if (!map || !global_map)
 943                 goto error;
 944
 945         for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
 946                 memset(map, 0, h_adj * sizeof(*map));
 947                 memset(global_map, ' ', (w_adj + 1) * h_adj);
 948
 949                 for (i = 0; i < omap_dmm->container_height; i++) {
 950                         map[i] = global_map + i * (w_adj + 1);
 951                         map[i][w_adj] = 0;
 952                 }
 953
 954                 spin_lock_irqsave(&list_lock, flags);
 955
 956                 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
 957                         if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
 958                                 if (block->fmt != TILFMT_PAGE) {
 959                                         fill_map(map, xdiv, ydiv, &block->area,
 960                                                 *m2dp, true);
 961                                         if (!*++a2dp)
 962                                                 a2dp = a2d;
 963                                         if (!*++m2dp)
 964                                                 m2dp = m2d;
 965                                         map_2d_info(map, xdiv, ydiv, nice,
 966                                                         &block->area);
 967                                 } else {
 968                                         bool start = read_map_pt(map, xdiv,
 969                                                 ydiv, &block->area.p0) == ' ';
 970                                         bool end = read_map_pt(map, xdiv, ydiv,
 971                                                         &block->area.p1) == ' ';
 972
 973                                         tcm_for_each_slice(a, block->area, p)
 974                                                 fill_map(map, xdiv, ydiv, &a,
 975                                                         '=', true);
 976                                         fill_map_pt(map, xdiv, ydiv,
 977                                                         &block->area.p0,
 978                                                         start ? '<' : 'X');
 979                                         fill_map_pt(map, xdiv, ydiv,
 980                                                         &block->area.p1,
 981                                                         end ? '>' : 'X');
 982                                         map_1d_info(map, xdiv, ydiv, nice,
 983                                                         &block->area);
 984                                 }
 985                         }
 986                 }
 987
 988                 spin_unlock_irqrestore(&list_lock, flags);
 989
 990                 if (s) {
 991                         seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
 992                         for (i = 0; i < 128; i++)
 993                                 seq_printf(s, "%03d:%s\n", i, map[i]);
 994                         seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
 995                 } else {
 996                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
 997                                 lut_idx);
 998                         for (i = 0; i < 128; i++)
 999                                 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
1000                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
1001                                 lut_idx);
1002                 }
1003         }
1004
1005 error:
1006         kfree(map);
1007         kfree(global_map);
1008
1009         return 0;
1010 }
1011 #endif
1012
1013 #ifdef CONFIG_PM_SLEEP
1014 static int omap_dmm_resume(struct device *dev)
1015 {
1016         struct tcm_area area;
1017         int i;
1018
1019         if (!omap_dmm)
1020                 return -ENODEV;
1021
1022         area = (struct tcm_area) {
1023                 .tcm = NULL,
1024                 .p1.x = omap_dmm->container_width - 1,
1025                 .p1.y = omap_dmm->container_height - 1,
1026         };
1027
1028         /* initialize all LUTs to dummy page entries */
1029         for (i = 0; i < omap_dmm->num_lut; i++) {
1030                 area.tcm = omap_dmm->tcm[i];
1031                 if (fill(&area, NULL, 0, 0, true))
1032                         dev_err(dev, "refill failed");
1033         }
1034
1035         return 0;
1036 }
1037 #endif
1038
1039 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
1040
1041 #if defined(CONFIG_OF)
1042 static const struct dmm_platform_data dmm_omap4_platform_data = {
1043         .cpu_cache_flags = OMAP_BO_WC,
1044 };
1045
1046 static const struct dmm_platform_data dmm_omap5_platform_data = {
1047         .cpu_cache_flags = OMAP_BO_UNCACHED,
1048 };
1049
1050 static const struct of_device_id dmm_of_match[] = {
1051         {
1052                 .compatible = "ti,omap4-dmm",
1053                 .data = &dmm_omap4_platform_data,
1054         },
1055         {
1056                 .compatible = "ti,omap5-dmm",
1057                 .data = &dmm_omap5_platform_data,
1058         },
1059         {},
1060 };
1061 #endif
1062
1063 struct platform_driver omap_dmm_driver = {
1064         .probe = omap_dmm_probe,
1065         .remove = omap_dmm_remove,
1066         .driver = {
1067                 .owner = THIS_MODULE,
1068                 .name = DMM_DRIVER_NAME,
1069                 .of_match_table = of_match_ptr(dmm_of_match),
1070                 .pm = &omap_dmm_pm_ops,
1071         },
1072 };
1073
1074 MODULE_LICENSE("GPL v2");
1075 MODULE_AUTHOR("Andy Gross <[email protected]>");
1076 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");