drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  42
  43 #define GFX9_NUM_GFX_RINGS     1
  44 #define GFX9_MEC_HPD_SIZE 4096
  45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  47
  48 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  54
  55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  61
  62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  68
  69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
  86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
  89 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
  90
  91 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
  92 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
  93 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
  94 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
  95 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
  96 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
  97
  98 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  99 {
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 120 };
 121
 122 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 123 {
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 142 };
 143
 144 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 145 {
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 157 };
 158
 159 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 160 {
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 185 };
 186
 187 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 188 {
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 196 };
 197
 198 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
 199 {
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 219 };
 220
 221 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 222 {
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 226 };
 227
 228 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 229 {
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 246 };
 247
 248 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 249 {
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 263 };
 264
 265 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 266 {
 267         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 268         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 269         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 270         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 271         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 272         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 273         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 274         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 275 };
 276
 277 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 278 {
 279         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 280         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 281         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 282         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 283         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 284         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 285         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 286         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 287 };
 288
 289 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 290 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 291 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 292 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
 293
 294 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 295 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 296 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 297 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 298 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 299                                  struct amdgpu_cu_info *cu_info);
 300 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 301 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 302 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 303
 304 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 305 {
 306         switch (adev->asic_type) {
 307         case CHIP_VEGA10:
 308                 soc15_program_register_sequence(adev,
 309                                                  golden_settings_gc_9_0,
 310                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 311                 soc15_program_register_sequence(adev,
 312                                                  golden_settings_gc_9_0_vg10,
 313                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 314                 break;
 315         case CHIP_VEGA12:
 316                 soc15_program_register_sequence(adev,
 317                                                 golden_settings_gc_9_2_1,
 318                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 319                 soc15_program_register_sequence(adev,
 320                                                 golden_settings_gc_9_2_1_vg12,
 321                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 322                 break;
 323         case CHIP_VEGA20:
 324                 soc15_program_register_sequence(adev,
 325                                                 golden_settings_gc_9_0,
 326                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 327                 soc15_program_register_sequence(adev,
 328                                                 golden_settings_gc_9_0_vg20,
 329                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 330                 break;
 331         case CHIP_RAVEN:
 332                 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
 333                                                 ARRAY_SIZE(golden_settings_gc_9_1));
 334                 if (adev->rev_id >= 8)
 335                         soc15_program_register_sequence(adev,
 336                                                         golden_settings_gc_9_1_rv2,
 337                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv2));
 338                 else
 339                         soc15_program_register_sequence(adev,
 340                                                         golden_settings_gc_9_1_rv1,
 341                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 342                 break;
 343         default:
 344                 break;
 345         }
 346
 347         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 348                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 349 }
 350
 351 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 352 {
 353         adev->gfx.scratch.num_reg = 8;
 354         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 355         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 356 }
 357
 358 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 359                                        bool wc, uint32_t reg, uint32_t val)
 360 {
 361         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 362         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 363                                 WRITE_DATA_DST_SEL(0) |
 364                                 (wc ? WR_CONFIRM : 0));
 365         amdgpu_ring_write(ring, reg);
 366         amdgpu_ring_write(ring, 0);
 367         amdgpu_ring_write(ring, val);
 368 }
 369
 370 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 371                                   int mem_space, int opt, uint32_t addr0,
 372                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 373                                   uint32_t inv)
 374 {
 375         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 376         amdgpu_ring_write(ring,
 377                                  /* memory (1) or register (0) */
 378                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 379                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 380                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 381                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 382
 383         if (mem_space)
 384                 BUG_ON(addr0 & 0x3); /* Dword align */
 385         amdgpu_ring_write(ring, addr0);
 386         amdgpu_ring_write(ring, addr1);
 387         amdgpu_ring_write(ring, ref);
 388         amdgpu_ring_write(ring, mask);
 389         amdgpu_ring_write(ring, inv); /* poll interval */
 390 }
 391
 392 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 393 {
 394         struct amdgpu_device *adev = ring->adev;
 395         uint32_t scratch;
 396         uint32_t tmp = 0;
 397         unsigned i;
 398         int r;
 399
 400         r = amdgpu_gfx_scratch_get(adev, &scratch);
 401         if (r)
 402                 return r;
 403
 404         WREG32(scratch, 0xCAFEDEAD);
 405         r = amdgpu_ring_alloc(ring, 3);
 406         if (r)
 407                 goto error_free_scratch;
 408
 409         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 410         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 411         amdgpu_ring_write(ring, 0xDEADBEEF);
 412         amdgpu_ring_commit(ring);
 413
 414         for (i = 0; i < adev->usec_timeout; i++) {
 415                 tmp = RREG32(scratch);
 416                 if (tmp == 0xDEADBEEF)
 417                         break;
 418                 DRM_UDELAY(1);
 419         }
 420
 421         if (i >= adev->usec_timeout)
 422                 r = -ETIMEDOUT;
 423
 424 error_free_scratch:
 425         amdgpu_gfx_scratch_free(adev, scratch);
 426         return r;
 427 }
 428
 429 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 430 {
 431         struct amdgpu_device *adev = ring->adev;
 432         struct amdgpu_ib ib;
 433         struct dma_fence *f = NULL;
 434
 435         unsigned index;
 436         uint64_t gpu_addr;
 437         uint32_t tmp;
 438         long r;
 439
 440         r = amdgpu_device_wb_get(adev, &index);
 441         if (r)
 442                 return r;
 443
 444         gpu_addr = adev->wb.gpu_addr + (index * 4);
 445         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 446         memset(&ib, 0, sizeof(ib));
 447         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 448         if (r)
 449                 goto err1;
 450
 451         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 452         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 453         ib.ptr[2] = lower_32_bits(gpu_addr);
 454         ib.ptr[3] = upper_32_bits(gpu_addr);
 455         ib.ptr[4] = 0xDEADBEEF;
 456         ib.length_dw = 5;
 457
 458         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 459         if (r)
 460                 goto err2;
 461
 462         r = dma_fence_wait_timeout(f, false, timeout);
 463         if (r == 0) {
 464                 r = -ETIMEDOUT;
 465                 goto err2;
 466         } else if (r < 0) {
 467                 goto err2;
 468         }
 469
 470         tmp = adev->wb.wb[index];
 471         if (tmp == 0xDEADBEEF)
 472                 r = 0;
 473         else
 474                 r = -EINVAL;
 475
 476 err2:
 477         amdgpu_ib_free(adev, &ib, NULL);
 478         dma_fence_put(f);
 479 err1:
 480         amdgpu_device_wb_free(adev, index);
 481         return r;
 482 }
 483
 484
 485 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 486 {
 487         release_firmware(adev->gfx.pfp_fw);
 488         adev->gfx.pfp_fw = NULL;
 489         release_firmware(adev->gfx.me_fw);
 490         adev->gfx.me_fw = NULL;
 491         release_firmware(adev->gfx.ce_fw);
 492         adev->gfx.ce_fw = NULL;
 493         release_firmware(adev->gfx.rlc_fw);
 494         adev->gfx.rlc_fw = NULL;
 495         release_firmware(adev->gfx.mec_fw);
 496         adev->gfx.mec_fw = NULL;
 497         release_firmware(adev->gfx.mec2_fw);
 498         adev->gfx.mec2_fw = NULL;
 499
 500         kfree(adev->gfx.rlc.register_list_format);
 501 }
 502
 503 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 504 {
 505         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 506
 507         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 508         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 509         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 510         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 511         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 512         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 513         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 514         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 515         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 516         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 517         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 518         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 519         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 520         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 521                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 522 }
 523
 524 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
 525 {
 526         adev->gfx.me_fw_write_wait = false;
 527         adev->gfx.mec_fw_write_wait = false;
 528
 529         switch (adev->asic_type) {
 530         case CHIP_VEGA10:
 531                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 532                     (adev->gfx.me_feature_version >= 42) &&
 533                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 534                     (adev->gfx.pfp_feature_version >= 42))
 535                         adev->gfx.me_fw_write_wait = true;
 536
 537                 if ((adev->gfx.mec_fw_version >=  0x00000193) &&
 538                     (adev->gfx.mec_feature_version >= 42))
 539                         adev->gfx.mec_fw_write_wait = true;
 540                 break;
 541         case CHIP_VEGA12:
 542                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 543                     (adev->gfx.me_feature_version >= 44) &&
 544                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 545                     (adev->gfx.pfp_feature_version >= 44))
 546                         adev->gfx.me_fw_write_wait = true;
 547
 548                 if ((adev->gfx.mec_fw_version >=  0x00000196) &&
 549                     (adev->gfx.mec_feature_version >= 44))
 550                         adev->gfx.mec_fw_write_wait = true;
 551                 break;
 552         case CHIP_VEGA20:
 553                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 554                     (adev->gfx.me_feature_version >= 44) &&
 555                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 556                     (adev->gfx.pfp_feature_version >= 44))
 557                         adev->gfx.me_fw_write_wait = true;
 558
 559                 if ((adev->gfx.mec_fw_version >=  0x00000197) &&
 560                     (adev->gfx.mec_feature_version >= 44))
 561                         adev->gfx.mec_fw_write_wait = true;
 562                 break;
 563         case CHIP_RAVEN:
 564                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 565                     (adev->gfx.me_feature_version >= 42) &&
 566                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 567                     (adev->gfx.pfp_feature_version >= 42))
 568                         adev->gfx.me_fw_write_wait = true;
 569
 570                 if ((adev->gfx.mec_fw_version >=  0x00000192) &&
 571                     (adev->gfx.mec_feature_version >= 42))
 572                         adev->gfx.mec_fw_write_wait = true;
 573                 break;
 574         default:
 575                 break;
 576         }
 577 }
 578
 579 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 580 {
 581         const char *chip_name;
 582         char fw_name[30];
 583         int err;
 584         struct amdgpu_firmware_info *info = NULL;
 585         const struct common_firmware_header *header = NULL;
 586         const struct gfx_firmware_header_v1_0 *cp_hdr;
 587         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 588         unsigned int *tmp = NULL;
 589         unsigned int i = 0;
 590         uint16_t version_major;
 591         uint16_t version_minor;
 592
 593         DRM_DEBUG("\n");
 594
 595         switch (adev->asic_type) {
 596         case CHIP_VEGA10:
 597                 chip_name = "vega10";
 598                 break;
 599         case CHIP_VEGA12:
 600                 chip_name = "vega12";
 601                 break;
 602         case CHIP_VEGA20:
 603                 chip_name = "vega20";
 604                 break;
 605         case CHIP_RAVEN:
 606                 if (adev->rev_id >= 8)
 607                         chip_name = "raven2";
 608                 else if (adev->pdev->device == 0x15d8)
 609                         chip_name = "picasso";
 610                 else
 611                         chip_name = "raven";
 612                 break;
 613         default:
 614                 BUG();
 615         }
 616
 617         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 618         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 619         if (err)
 620                 goto out;
 621         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 622         if (err)
 623                 goto out;
 624         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 625         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 626         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 627
 628         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 629         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 630         if (err)
 631                 goto out;
 632         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 633         if (err)
 634                 goto out;
 635         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 636         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 637         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 638
 639         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 640         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 641         if (err)
 642                 goto out;
 643         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 644         if (err)
 645                 goto out;
 646         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 647         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 648         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 649
 650         /*
 651          * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
 652          * instead of picasso_rlc.bin.
 653          * Judgment method:
 654          * PCO AM4: revision >= 0xC8 && revision <= 0xCF
 655          *          or revision >= 0xD8 && revision <= 0xDF
 656          * otherwise is PCO FP5
 657          */
 658         if (!strcmp(chip_name, "picasso") &&
 659                 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
 660                 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
 661                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
 662         else
 663                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 664         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 665         if (err)
 666                 goto out;
 667         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 668         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 669
 670         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 671         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 672         if (version_major == 2 && version_minor == 1)
 673                 adev->gfx.rlc.is_rlc_v2_1 = true;
 674
 675         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 676         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 677         adev->gfx.rlc.save_and_restore_offset =
 678                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 679         adev->gfx.rlc.clear_state_descriptor_offset =
 680                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 681         adev->gfx.rlc.avail_scratch_ram_locations =
 682                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 683         adev->gfx.rlc.reg_restore_list_size =
 684                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 685         adev->gfx.rlc.reg_list_format_start =
 686                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 687         adev->gfx.rlc.reg_list_format_separate_start =
 688                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 689         adev->gfx.rlc.starting_offsets_start =
 690                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 691         adev->gfx.rlc.reg_list_format_size_bytes =
 692                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 693         adev->gfx.rlc.reg_list_size_bytes =
 694                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 695         adev->gfx.rlc.register_list_format =
 696                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 697                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 698         if (!adev->gfx.rlc.register_list_format) {
 699                 err = -ENOMEM;
 700                 goto out;
 701         }
 702
 703         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 704                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 705         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
 706                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 707
 708         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 709
 710         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 711                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 712         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
 713                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 714
 715         if (adev->gfx.rlc.is_rlc_v2_1)
 716                 gfx_v9_0_init_rlc_ext_microcode(adev);
 717
 718         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 719         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 720         if (err)
 721                 goto out;
 722         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 723         if (err)
 724                 goto out;
 725         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 726         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 727         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 728
 729
 730         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 731         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 732         if (!err) {
 733                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 734                 if (err)
 735                         goto out;
 736                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 737                 adev->gfx.mec2_fw->data;
 738                 adev->gfx.mec2_fw_version =
 739                 le32_to_cpu(cp_hdr->header.ucode_version);
 740                 adev->gfx.mec2_feature_version =
 741                 le32_to_cpu(cp_hdr->ucode_feature_version);
 742         } else {
 743                 err = 0;
 744                 adev->gfx.mec2_fw = NULL;
 745         }
 746
 747         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 748                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 749                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 750                 info->fw = adev->gfx.pfp_fw;
 751                 header = (const struct common_firmware_header *)info->fw->data;
 752                 adev->firmware.fw_size +=
 753                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 754
 755                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 756                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 757                 info->fw = adev->gfx.me_fw;
 758                 header = (const struct common_firmware_header *)info->fw->data;
 759                 adev->firmware.fw_size +=
 760                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 761
 762                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 763                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 764                 info->fw = adev->gfx.ce_fw;
 765                 header = (const struct common_firmware_header *)info->fw->data;
 766                 adev->firmware.fw_size +=
 767                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 768
 769                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 770                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 771                 info->fw = adev->gfx.rlc_fw;
 772                 header = (const struct common_firmware_header *)info->fw->data;
 773                 adev->firmware.fw_size +=
 774                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 775
 776                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 777                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 778                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 779                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 780                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 781                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 782                         info->fw = adev->gfx.rlc_fw;
 783                         adev->firmware.fw_size +=
 784                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 785
 786                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 787                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 788                         info->fw = adev->gfx.rlc_fw;
 789                         adev->firmware.fw_size +=
 790                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 791
 792                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 793                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 794                         info->fw = adev->gfx.rlc_fw;
 795                         adev->firmware.fw_size +=
 796                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 797                 }
 798
 799                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 800                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 801                 info->fw = adev->gfx.mec_fw;
 802                 header = (const struct common_firmware_header *)info->fw->data;
 803                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 804                 adev->firmware.fw_size +=
 805                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 806
 807                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 808                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 809                 info->fw = adev->gfx.mec_fw;
 810                 adev->firmware.fw_size +=
 811                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 812
 813                 if (adev->gfx.mec2_fw) {
 814                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 815                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 816                         info->fw = adev->gfx.mec2_fw;
 817                         header = (const struct common_firmware_header *)info->fw->data;
 818                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 819                         adev->firmware.fw_size +=
 820                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 821                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 822                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 823                         info->fw = adev->gfx.mec2_fw;
 824                         adev->firmware.fw_size +=
 825                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 826                 }
 827
 828         }
 829
 830 out:
 831         gfx_v9_0_check_fw_write_wait(adev);
 832         if (err) {
 833                 dev_err(adev->dev,
 834                         "gfx9: Failed to load firmware \"%s\"\n",
 835                         fw_name);
 836                 release_firmware(adev->gfx.pfp_fw);
 837                 adev->gfx.pfp_fw = NULL;
 838                 release_firmware(adev->gfx.me_fw);
 839                 adev->gfx.me_fw = NULL;
 840                 release_firmware(adev->gfx.ce_fw);
 841                 adev->gfx.ce_fw = NULL;
 842                 release_firmware(adev->gfx.rlc_fw);
 843                 adev->gfx.rlc_fw = NULL;
 844                 release_firmware(adev->gfx.mec_fw);
 845                 adev->gfx.mec_fw = NULL;
 846                 release_firmware(adev->gfx.mec2_fw);
 847                 adev->gfx.mec2_fw = NULL;
 848         }
 849         return err;
 850 }
 851
 852 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 853 {
 854         u32 count = 0;
 855         const struct cs_section_def *sect = NULL;
 856         const struct cs_extent_def *ext = NULL;
 857
 858         /* begin clear state */
 859         count += 2;
 860         /* context control state */
 861         count += 3;
 862
 863         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 864                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 865                         if (sect->id == SECT_CONTEXT)
 866                                 count += 2 + ext->reg_count;
 867                         else
 868                                 return 0;
 869                 }
 870         }
 871
 872         /* end clear state */
 873         count += 2;
 874         /* clear state */
 875         count += 2;
 876
 877         return count;
 878 }
 879
 880 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 881                                     volatile u32 *buffer)
 882 {
 883         u32 count = 0, i;
 884         const struct cs_section_def *sect = NULL;
 885         const struct cs_extent_def *ext = NULL;
 886
 887         if (adev->gfx.rlc.cs_data == NULL)
 888                 return;
 889         if (buffer == NULL)
 890                 return;
 891
 892         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 893         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 894
 895         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 896         buffer[count++] = cpu_to_le32(0x80000000);
 897         buffer[count++] = cpu_to_le32(0x80000000);
 898
 899         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 900                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 901                         if (sect->id == SECT_CONTEXT) {
 902                                 buffer[count++] =
 903                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 904                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 905                                                 PACKET3_SET_CONTEXT_REG_START);
 906                                 for (i = 0; i < ext->reg_count; i++)
 907                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 908                         } else {
 909                                 return;
 910                         }
 911                 }
 912         }
 913
 914         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 915         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 916
 917         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 918         buffer[count++] = cpu_to_le32(0);
 919 }
 920
 921 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
 922 {
 923         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
 924         uint32_t pg_always_on_cu_num = 2;
 925         uint32_t always_on_cu_num;
 926         uint32_t i, j, k;
 927         uint32_t mask, cu_bitmap, counter;
 928
 929         if (adev->flags & AMD_IS_APU)
 930                 always_on_cu_num = 4;
 931         else if (adev->asic_type == CHIP_VEGA12)
 932                 always_on_cu_num = 8;
 933         else
 934                 always_on_cu_num = 12;
 935
 936         mutex_lock(&adev->grbm_idx_mutex);
 937         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 938                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 939                         mask = 1;
 940                         cu_bitmap = 0;
 941                         counter = 0;
 942                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
 943
 944                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
 945                                 if (cu_info->bitmap[i][j] & mask) {
 946                                         if (counter == pg_always_on_cu_num)
 947                                                 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
 948                                         if (counter < always_on_cu_num)
 949                                                 cu_bitmap |= mask;
 950                                         else
 951                                                 break;
 952                                         counter++;
 953                                 }
 954                                 mask <<= 1;
 955                         }
 956
 957                         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
 958                         cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
 959                 }
 960         }
 961         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 962         mutex_unlock(&adev->grbm_idx_mutex);
 963 }
 964
 965 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 966 {
 967         uint32_t data;
 968
 969         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 970         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 971         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 972         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 973         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 974
 975         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 976         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 977
 978         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 979         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 980
 981         mutex_lock(&adev->grbm_idx_mutex);
 982         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 983         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 984         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 985
 986         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 987         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 988         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 989         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 990         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 991
 992         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 993         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 994         data &= 0x0000FFFF;
 995         data |= 0x00C00000;
 996         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 997
 998         /*
 999          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
1000          * programmed in gfx_v9_0_init_always_on_cu_mask()
1001          */
1002
1003         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1004          * but used for RLC_LB_CNTL configuration */
1005         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1006         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1007         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1008         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1009         mutex_unlock(&adev->grbm_idx_mutex);
1010
1011         gfx_v9_0_init_always_on_cu_mask(adev);
1012 }
1013
1014 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1015 {
1016         uint32_t data;
1017
1018         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1019         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1020         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1021         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1022         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1023
1024         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1025         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1026
1027         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1028         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1029
1030         mutex_lock(&adev->grbm_idx_mutex);
1031         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1032         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1033         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1034
1035         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1036         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1037         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1038         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1039         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1040
1041         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1042         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1043         data &= 0x0000FFFF;
1044         data |= 0x00C00000;
1045         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1046
1047         /*
1048          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1049          * programmed in gfx_v9_0_init_always_on_cu_mask()
1050          */
1051
1052         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1053          * but used for RLC_LB_CNTL configuration */
1054         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1055         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1056         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1057         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1058         mutex_unlock(&adev->grbm_idx_mutex);
1059
1060         gfx_v9_0_init_always_on_cu_mask(adev);
1061 }
1062
1063 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1064 {
1065         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1066 }
1067
1068 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev)
1069 {
1070         return 5;
1071 }
1072
1073 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1074 {
1075         const struct cs_section_def *cs_data;
1076         int r;
1077
1078         adev->gfx.rlc.cs_data = gfx9_cs_data;
1079
1080         cs_data = adev->gfx.rlc.cs_data;
1081
1082         if (cs_data) {
1083                 /* init clear state block */
1084                 r = amdgpu_gfx_rlc_init_csb(adev);
1085                 if (r)
1086                         return r;
1087         }
1088
1089         if (adev->asic_type == CHIP_RAVEN) {
1090                 /* TODO: double check the cp_table_size for RV */
1091                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1092                 r = amdgpu_gfx_rlc_init_cpt(adev);
1093                 if (r)
1094                         return r;
1095         }
1096
1097         switch (adev->asic_type) {
1098         case CHIP_RAVEN:
1099                 gfx_v9_0_init_lbpw(adev);
1100                 break;
1101         case CHIP_VEGA20:
1102                 gfx_v9_4_init_lbpw(adev);
1103                 break;
1104         default:
1105                 break;
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
1112 {
1113         int r;
1114
1115         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1116         if (unlikely(r != 0))
1117                 return r;
1118
1119         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1120                         AMDGPU_GEM_DOMAIN_VRAM);
1121         if (!r)
1122                 adev->gfx.rlc.clear_state_gpu_addr =
1123                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1124
1125         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1126
1127         return r;
1128 }
1129
1130 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1131 {
1132         int r;
1133
1134         if (!adev->gfx.rlc.clear_state_obj)
1135                 return;
1136
1137         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1138         if (likely(r == 0)) {
1139                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1140                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1141         }
1142 }
1143
1144 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1145 {
1146         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1147         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1148 }
1149
1150 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1151 {
1152         int r;
1153         u32 *hpd;
1154         const __le32 *fw_data;
1155         unsigned fw_size;
1156         u32 *fw;
1157         size_t mec_hpd_size;
1158
1159         const struct gfx_firmware_header_v1_0 *mec_hdr;
1160
1161         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1162
1163         /* take ownership of the relevant compute queues */
1164         amdgpu_gfx_compute_queue_acquire(adev);
1165         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1166
1167         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1168                                       AMDGPU_GEM_DOMAIN_VRAM,
1169                                       &adev->gfx.mec.hpd_eop_obj,
1170                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1171                                       (void **)&hpd);
1172         if (r) {
1173                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1174                 gfx_v9_0_mec_fini(adev);
1175                 return r;
1176         }
1177
1178         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1179
1180         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1181         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1182
1183         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1184
1185         fw_data = (const __le32 *)
1186                 (adev->gfx.mec_fw->data +
1187                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1188         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1189
1190         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1191                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1192                                       &adev->gfx.mec.mec_fw_obj,
1193                                       &adev->gfx.mec.mec_fw_gpu_addr,
1194                                       (void **)&fw);
1195         if (r) {
1196                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1197                 gfx_v9_0_mec_fini(adev);
1198                 return r;
1199         }
1200
1201         memcpy(fw, fw_data, fw_size);
1202
1203         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1204         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1205
1206         return 0;
1207 }
1208
1209 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1210 {
1211         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1212                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1213                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1214                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1215                 (SQ_IND_INDEX__FORCE_READ_MASK));
1216         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1217 }
1218
1219 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1220                            uint32_t wave, uint32_t thread,
1221                            uint32_t regno, uint32_t num, uint32_t *out)
1222 {
1223         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1224                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1225                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1226                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1227                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1228                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1229                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1230         while (num--)
1231                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1232 }
1233
1234 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1235 {
1236         /* type 1 wave data */
1237         dst[(*no_fields)++] = 1;
1238         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1239         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1240         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1241         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1242         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1243         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1244         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1245         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1246         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1247         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1248         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1249         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1250         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1251         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1252 }
1253
1254 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1255                                      uint32_t wave, uint32_t start,
1256                                      uint32_t size, uint32_t *dst)
1257 {
1258         wave_read_regs(
1259                 adev, simd, wave, 0,
1260                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1261 }
1262
1263 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1264                                      uint32_t wave, uint32_t thread,
1265                                      uint32_t start, uint32_t size,
1266                                      uint32_t *dst)
1267 {
1268         wave_read_regs(
1269                 adev, simd, wave, thread,
1270                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1271 }
1272
1273 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1274                                   u32 me, u32 pipe, u32 q)
1275 {
1276         soc15_grbm_select(adev, me, pipe, q, 0);
1277 }
1278
1279 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1280         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1281         .select_se_sh = &gfx_v9_0_select_se_sh,
1282         .read_wave_data = &gfx_v9_0_read_wave_data,
1283         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1284         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1285         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1286 };
1287
1288 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1289 {
1290         u32 gb_addr_config;
1291         int err;
1292
1293         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1294
1295         switch (adev->asic_type) {
1296         case CHIP_VEGA10:
1297                 adev->gfx.config.max_hw_contexts = 8;
1298                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1299                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1300                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1301                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1302                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1303                 break;
1304         case CHIP_VEGA12:
1305                 adev->gfx.config.max_hw_contexts = 8;
1306                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1307                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1308                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1309                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1310                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1311                 DRM_INFO("fix gfx.config for vega12\n");
1312                 break;
1313         case CHIP_VEGA20:
1314                 adev->gfx.config.max_hw_contexts = 8;
1315                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1316                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1317                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1318                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1319                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1320                 gb_addr_config &= ~0xf3e777ff;
1321                 gb_addr_config |= 0x22014042;
1322                 /* check vbios table if gpu info is not available */
1323                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1324                 if (err)
1325                         return err;
1326                 break;
1327         case CHIP_RAVEN:
1328                 adev->gfx.config.max_hw_contexts = 8;
1329                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1330                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1331                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1332                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1333                 if (adev->rev_id >= 8)
1334                         gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
1335                 else
1336                         gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1337                 break;
1338         default:
1339                 BUG();
1340                 break;
1341         }
1342
1343         adev->gfx.config.gb_addr_config = gb_addr_config;
1344
1345         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1346                         REG_GET_FIELD(
1347                                         adev->gfx.config.gb_addr_config,
1348                                         GB_ADDR_CONFIG,
1349                                         NUM_PIPES);
1350
1351         adev->gfx.config.max_tile_pipes =
1352                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1353
1354         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1355                         REG_GET_FIELD(
1356                                         adev->gfx.config.gb_addr_config,
1357                                         GB_ADDR_CONFIG,
1358                                         NUM_BANKS);
1359         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1360                         REG_GET_FIELD(
1361                                         adev->gfx.config.gb_addr_config,
1362                                         GB_ADDR_CONFIG,
1363                                         MAX_COMPRESSED_FRAGS);
1364         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1365                         REG_GET_FIELD(
1366                                         adev->gfx.config.gb_addr_config,
1367                                         GB_ADDR_CONFIG,
1368                                         NUM_RB_PER_SE);
1369         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1370                         REG_GET_FIELD(
1371                                         adev->gfx.config.gb_addr_config,
1372                                         GB_ADDR_CONFIG,
1373                                         NUM_SHADER_ENGINES);
1374         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1375                         REG_GET_FIELD(
1376                                         adev->gfx.config.gb_addr_config,
1377                                         GB_ADDR_CONFIG,
1378                                         PIPE_INTERLEAVE_SIZE));
1379
1380         return 0;
1381 }
1382
1383 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1384                                    struct amdgpu_ngg_buf *ngg_buf,
1385                                    int size_se,
1386                                    int default_size_se)
1387 {
1388         int r;
1389
1390         if (size_se < 0) {
1391                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1392                 return -EINVAL;
1393         }
1394         size_se = size_se ? size_se : default_size_se;
1395
1396         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1397         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1398                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1399                                     &ngg_buf->bo,
1400                                     &ngg_buf->gpu_addr,
1401                                     NULL);
1402         if (r) {
1403                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1404                 return r;
1405         }
1406         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1407
1408         return r;
1409 }
1410
1411 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1412 {
1413         int i;
1414
1415         for (i = 0; i < NGG_BUF_MAX; i++)
1416                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1417                                       &adev->gfx.ngg.buf[i].gpu_addr,
1418                                       NULL);
1419
1420         memset(&adev->gfx.ngg.buf[0], 0,
1421                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1422
1423         adev->gfx.ngg.init = false;
1424
1425         return 0;
1426 }
1427
1428 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1429 {
1430         int r;
1431
1432         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1433                 return 0;
1434
1435         /* GDS reserve memory: 64 bytes alignment */
1436         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1437         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1438         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1439         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1440         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1441
1442         /* Primitive Buffer */
1443         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1444                                     amdgpu_prim_buf_per_se,
1445                                     64 * 1024);
1446         if (r) {
1447                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1448                 goto err;
1449         }
1450
1451         /* Position Buffer */
1452         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1453                                     amdgpu_pos_buf_per_se,
1454                                     256 * 1024);
1455         if (r) {
1456                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1457                 goto err;
1458         }
1459
1460         /* Control Sideband */
1461         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1462                                     amdgpu_cntl_sb_buf_per_se,
1463                                     256);
1464         if (r) {
1465                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1466                 goto err;
1467         }
1468
1469         /* Parameter Cache, not created by default */
1470         if (amdgpu_param_buf_per_se <= 0)
1471                 goto out;
1472
1473         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1474                                     amdgpu_param_buf_per_se,
1475                                     512 * 1024);
1476         if (r) {
1477                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1478                 goto err;
1479         }
1480
1481 out:
1482         adev->gfx.ngg.init = true;
1483         return 0;
1484 err:
1485         gfx_v9_0_ngg_fini(adev);
1486         return r;
1487 }
1488
1489 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1490 {
1491         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1492         int r;
1493         u32 data, base;
1494
1495         if (!amdgpu_ngg)
1496                 return 0;
1497
1498         /* Program buffer size */
1499         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1500                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1501         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1502                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1503         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1504
1505         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1506                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1507         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1508                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1509         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1510
1511         /* Program buffer base address */
1512         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1513         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1514         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1515
1516         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1517         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1518         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1519
1520         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1521         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1522         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1523
1524         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1525         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1526         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1527
1528         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1529         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1530         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1531
1532         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1533         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1534         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1535
1536         /* Clear GDS reserved memory */
1537         r = amdgpu_ring_alloc(ring, 17);
1538         if (r) {
1539                 DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n",
1540                           ring->name, r);
1541                 return r;
1542         }
1543
1544         gfx_v9_0_write_data_to_reg(ring, 0, false,
1545                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1546                                    (adev->gds.mem.total_size +
1547                                     adev->gfx.ngg.gds_reserve_size));
1548
1549         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1550         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1551                                 PACKET3_DMA_DATA_DST_SEL(1) |
1552                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1553         amdgpu_ring_write(ring, 0);
1554         amdgpu_ring_write(ring, 0);
1555         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1556         amdgpu_ring_write(ring, 0);
1557         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1558                                 adev->gfx.ngg.gds_reserve_size);
1559
1560         gfx_v9_0_write_data_to_reg(ring, 0, false,
1561                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1562
1563         amdgpu_ring_commit(ring);
1564
1565         return 0;
1566 }
1567
1568 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1569                                       int mec, int pipe, int queue)
1570 {
1571         int r;
1572         unsigned irq_type;
1573         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1574
1575         ring = &adev->gfx.compute_ring[ring_id];
1576
1577         /* mec0 is me1 */
1578         ring->me = mec + 1;
1579         ring->pipe = pipe;
1580         ring->queue = queue;
1581
1582         ring->ring_obj = NULL;
1583         ring->use_doorbell = true;
1584         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1585         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1586                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1587         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1588
1589         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1590                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1591                 + ring->pipe;
1592
1593         /* type-2 packets are deprecated on MEC, use type-3 instead */
1594         r = amdgpu_ring_init(adev, ring, 1024,
1595                              &adev->gfx.eop_irq, irq_type);
1596         if (r)
1597                 return r;
1598
1599
1600         return 0;
1601 }
1602
1603 static int gfx_v9_0_sw_init(void *handle)
1604 {
1605         int i, j, k, r, ring_id;
1606         struct amdgpu_ring *ring;
1607         struct amdgpu_kiq *kiq;
1608         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1609
1610         switch (adev->asic_type) {
1611         case CHIP_VEGA10:
1612         case CHIP_VEGA12:
1613         case CHIP_VEGA20:
1614         case CHIP_RAVEN:
1615                 adev->gfx.mec.num_mec = 2;
1616                 break;
1617         default:
1618                 adev->gfx.mec.num_mec = 1;
1619                 break;
1620         }
1621
1622         adev->gfx.mec.num_pipe_per_mec = 4;
1623         adev->gfx.mec.num_queue_per_pipe = 8;
1624
1625         /* EOP Event */
1626         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1627         if (r)
1628                 return r;
1629
1630         /* Privileged reg */
1631         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1632                               &adev->gfx.priv_reg_irq);
1633         if (r)
1634                 return r;
1635
1636         /* Privileged inst */
1637         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1638                               &adev->gfx.priv_inst_irq);
1639         if (r)
1640                 return r;
1641
1642         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1643
1644         gfx_v9_0_scratch_init(adev);
1645
1646         r = gfx_v9_0_init_microcode(adev);
1647         if (r) {
1648                 DRM_ERROR("Failed to load gfx firmware!\n");
1649                 return r;
1650         }
1651
1652         r = adev->gfx.rlc.funcs->init(adev);
1653         if (r) {
1654                 DRM_ERROR("Failed to init rlc BOs!\n");
1655                 return r;
1656         }
1657
1658         r = gfx_v9_0_mec_init(adev);
1659         if (r) {
1660                 DRM_ERROR("Failed to init MEC BOs!\n");
1661                 return r;
1662         }
1663
1664         /* set up the gfx ring */
1665         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1666                 ring = &adev->gfx.gfx_ring[i];
1667                 ring->ring_obj = NULL;
1668                 if (!i)
1669                         sprintf(ring->name, "gfx");
1670                 else
1671                         sprintf(ring->name, "gfx_%d", i);
1672                 ring->use_doorbell = true;
1673                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1674                 r = amdgpu_ring_init(adev, ring, 1024,
1675                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1676                 if (r)
1677                         return r;
1678         }
1679
1680         /* set up the compute queues - allocate horizontally across pipes */
1681         ring_id = 0;
1682         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1683                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1684                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1685                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1686                                         continue;
1687
1688                                 r = gfx_v9_0_compute_ring_init(adev,
1689                                                                ring_id,
1690                                                                i, k, j);
1691                                 if (r)
1692                                         return r;
1693
1694                                 ring_id++;
1695                         }
1696                 }
1697         }
1698
1699         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1700         if (r) {
1701                 DRM_ERROR("Failed to init KIQ BOs!\n");
1702                 return r;
1703         }
1704
1705         kiq = &adev->gfx.kiq;
1706         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1707         if (r)
1708                 return r;
1709
1710         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1711         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1712         if (r)
1713                 return r;
1714
1715         adev->gfx.ce_ram_size = 0x8000;
1716
1717         r = gfx_v9_0_gpu_early_init(adev);
1718         if (r)
1719                 return r;
1720
1721         r = gfx_v9_0_ngg_init(adev);
1722         if (r)
1723                 return r;
1724
1725         return 0;
1726 }
1727
1728
1729 static int gfx_v9_0_sw_fini(void *handle)
1730 {
1731         int i;
1732         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1733
1734         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1735         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1736         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1737
1738         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1739                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1740         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1741                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1742
1743         amdgpu_gfx_compute_mqd_sw_fini(adev);
1744         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1745         amdgpu_gfx_kiq_fini(adev);
1746
1747         gfx_v9_0_mec_fini(adev);
1748         gfx_v9_0_ngg_fini(adev);
1749         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1750                                 &adev->gfx.rlc.clear_state_gpu_addr,
1751                                 (void **)&adev->gfx.rlc.cs_ptr);
1752         if (adev->asic_type == CHIP_RAVEN) {
1753                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1754                                 &adev->gfx.rlc.cp_table_gpu_addr,
1755                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1756         }
1757         gfx_v9_0_free_microcode(adev);
1758
1759         return 0;
1760 }
1761
1762
1763 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1764 {
1765         /* TODO */
1766 }
1767
1768 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1769 {
1770         u32 data;
1771
1772         if (instance == 0xffffffff)
1773                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1774         else
1775                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1776
1777         if (se_num == 0xffffffff)
1778                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1779         else
1780                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1781
1782         if (sh_num == 0xffffffff)
1783                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1784         else
1785                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1786
1787         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1788 }
1789
1790 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1791 {
1792         u32 data, mask;
1793
1794         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1795         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1796
1797         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1798         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1799
1800         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1801                                          adev->gfx.config.max_sh_per_se);
1802
1803         return (~data) & mask;
1804 }
1805
1806 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1807 {
1808         int i, j;
1809         u32 data;
1810         u32 active_rbs = 0;
1811         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1812                                         adev->gfx.config.max_sh_per_se;
1813
1814         mutex_lock(&adev->grbm_idx_mutex);
1815         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1816                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1817                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1818                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1819                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1820                                                rb_bitmap_width_per_sh);
1821                 }
1822         }
1823         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1824         mutex_unlock(&adev->grbm_idx_mutex);
1825
1826         adev->gfx.config.backend_enable_mask = active_rbs;
1827         adev->gfx.config.num_rbs = hweight32(active_rbs);
1828 }
1829
1830 #define DEFAULT_SH_MEM_BASES    (0x6000)
1831 #define FIRST_COMPUTE_VMID      (8)
1832 #define LAST_COMPUTE_VMID       (16)
1833 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1834 {
1835         int i;
1836         uint32_t sh_mem_config;
1837         uint32_t sh_mem_bases;
1838
1839         /*
1840          * Configure apertures:
1841          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1842          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1843          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1844          */
1845         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1846
1847         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1848                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1849                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1850
1851         mutex_lock(&adev->srbm_mutex);
1852         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1853                 soc15_grbm_select(adev, 0, 0, 0, i);
1854                 /* CP and shaders */
1855                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1856                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1857         }
1858         soc15_grbm_select(adev, 0, 0, 0, 0);
1859         mutex_unlock(&adev->srbm_mutex);
1860 }
1861
1862 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
1863 {
1864         u32 tmp;
1865         int i;
1866
1867         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1868
1869         gfx_v9_0_tiling_mode_table_init(adev);
1870
1871         gfx_v9_0_setup_rb(adev);
1872         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1873         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1874
1875         /* XXX SH_MEM regs */
1876         /* where to put LDS, scratch, GPUVM in FSA64 space */
1877         mutex_lock(&adev->srbm_mutex);
1878         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1879                 soc15_grbm_select(adev, 0, 0, 0, i);
1880                 /* CP and shaders */
1881                 if (i == 0) {
1882                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1883                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1884                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1885                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1886                 } else {
1887                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1888                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1889                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1890                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1891                                 (adev->gmc.private_aperture_start >> 48));
1892                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1893                                 (adev->gmc.shared_aperture_start >> 48));
1894                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1895                 }
1896         }
1897         soc15_grbm_select(adev, 0, 0, 0, 0);
1898
1899         mutex_unlock(&adev->srbm_mutex);
1900
1901         gfx_v9_0_init_compute_vmid(adev);
1902
1903         mutex_lock(&adev->grbm_idx_mutex);
1904         /*
1905          * making sure that the following register writes will be broadcasted
1906          * to all the shaders
1907          */
1908         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1909
1910         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1911                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1912                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1913                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1914                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1915                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1916                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1917                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1918                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1919         mutex_unlock(&adev->grbm_idx_mutex);
1920
1921 }
1922
1923 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1924 {
1925         u32 i, j, k;
1926         u32 mask;
1927
1928         mutex_lock(&adev->grbm_idx_mutex);
1929         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1930                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1931                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1932                         for (k = 0; k < adev->usec_timeout; k++) {
1933                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1934                                         break;
1935                                 udelay(1);
1936                         }
1937                         if (k == adev->usec_timeout) {
1938                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1939                                                       0xffffffff, 0xffffffff);
1940                                 mutex_unlock(&adev->grbm_idx_mutex);
1941                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1942                                          i, j);
1943                                 return;
1944                         }
1945                 }
1946         }
1947         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1948         mutex_unlock(&adev->grbm_idx_mutex);
1949
1950         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1951                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1952                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1953                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1954         for (k = 0; k < adev->usec_timeout; k++) {
1955                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1956                         break;
1957                 udelay(1);
1958         }
1959 }
1960
1961 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1962                                                bool enable)
1963 {
1964         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1965
1966         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1967         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1968         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1969         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1970
1971         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1972 }
1973
1974 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1975 {
1976         /* csib */
1977         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1978                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1979         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1980                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1981         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1982                         adev->gfx.rlc.clear_state_size);
1983 }
1984
1985 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1986                                 int indirect_offset,
1987                                 int list_size,
1988                                 int *unique_indirect_regs,
1989                                 int unique_indirect_reg_count,
1990                                 int *indirect_start_offsets,
1991                                 int *indirect_start_offsets_count,
1992                                 int max_start_offsets_count)
1993 {
1994         int idx;
1995
1996         for (; indirect_offset < list_size; indirect_offset++) {
1997                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1998                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1999                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2000
2001                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2002                         indirect_offset += 2;
2003
2004                         /* look for the matching indice */
2005                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2006                                 if (unique_indirect_regs[idx] ==
2007                                         register_list_format[indirect_offset] ||
2008                                         !unique_indirect_regs[idx])
2009                                         break;
2010                         }
2011
2012                         BUG_ON(idx >= unique_indirect_reg_count);
2013
2014                         if (!unique_indirect_regs[idx])
2015                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2016
2017                         indirect_offset++;
2018                 }
2019         }
2020 }
2021
2022 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2023 {
2024         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2025         int unique_indirect_reg_count = 0;
2026
2027         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2028         int indirect_start_offsets_count = 0;
2029
2030         int list_size = 0;
2031         int i = 0, j = 0;
2032         u32 tmp = 0;
2033
2034         u32 *register_list_format =
2035                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2036         if (!register_list_format)
2037                 return -ENOMEM;
2038         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
2039                 adev->gfx.rlc.reg_list_format_size_bytes);
2040
2041         /* setup unique_indirect_regs array and indirect_start_offsets array */
2042         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2043         gfx_v9_1_parse_ind_reg_list(register_list_format,
2044                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2045                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2046                                     unique_indirect_regs,
2047                                     unique_indirect_reg_count,
2048                                     indirect_start_offsets,
2049                                     &indirect_start_offsets_count,
2050                                     ARRAY_SIZE(indirect_start_offsets));
2051
2052         /* enable auto inc in case it is disabled */
2053         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2054         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2055         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2056
2057         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2058         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2059                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2060         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2061                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2062                         adev->gfx.rlc.register_restore[i]);
2063
2064         /* load indirect register */
2065         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2066                 adev->gfx.rlc.reg_list_format_start);
2067
2068         /* direct register portion */
2069         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2070                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2071                         register_list_format[i]);
2072
2073         /* indirect register portion */
2074         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2075                 if (register_list_format[i] == 0xFFFFFFFF) {
2076                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2077                         continue;
2078                 }
2079
2080                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2081                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2082
2083                 for (j = 0; j < unique_indirect_reg_count; j++) {
2084                         if (register_list_format[i] == unique_indirect_regs[j]) {
2085                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2086                                 break;
2087                         }
2088                 }
2089
2090                 BUG_ON(j >= unique_indirect_reg_count);
2091
2092                 i++;
2093         }
2094
2095         /* set save/restore list size */
2096         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2097         list_size = list_size >> 1;
2098         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2099                 adev->gfx.rlc.reg_restore_list_size);
2100         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2101
2102         /* write the starting offsets to RLC scratch ram */
2103         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2104                 adev->gfx.rlc.starting_offsets_start);
2105         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2106                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2107                        indirect_start_offsets[i]);
2108
2109         /* load unique indirect regs*/
2110         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2111                 if (unique_indirect_regs[i] != 0) {
2112                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2113                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2114                                unique_indirect_regs[i] & 0x3FFFF);
2115
2116                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2117                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2118                                unique_indirect_regs[i] >> 20);
2119                 }
2120         }
2121
2122         kfree(register_list_format);
2123         return 0;
2124 }
2125
2126 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2127 {
2128         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2129 }
2130
2131 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2132                                              bool enable)
2133 {
2134         uint32_t data = 0;
2135         uint32_t default_data = 0;
2136
2137         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2138         if (enable == true) {
2139                 /* enable GFXIP control over CGPG */
2140                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2141                 if(default_data != data)
2142                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2143
2144                 /* update status */
2145                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2146                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2147                 if(default_data != data)
2148                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2149         } else {
2150                 /* restore GFXIP control over GCPG */
2151                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2152                 if(default_data != data)
2153                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2154         }
2155 }
2156
2157 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2158 {
2159         uint32_t data = 0;
2160
2161         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2162                               AMD_PG_SUPPORT_GFX_SMG |
2163                               AMD_PG_SUPPORT_GFX_DMG)) {
2164                 /* init IDLE_POLL_COUNT = 60 */
2165                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2166                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2167                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2168                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2169
2170                 /* init RLC PG Delay */
2171                 data = 0;
2172                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2173                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2174                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2175                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2176                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2177
2178                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2179                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2180                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2181                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2182
2183                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2184                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2185                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2186                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2187
2188                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2189                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2190
2191                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2192                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2193                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2194
2195                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2196         }
2197 }
2198
2199 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2200                                                 bool enable)
2201 {
2202         uint32_t data = 0;
2203         uint32_t default_data = 0;
2204
2205         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2206         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2207                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2208                              enable ? 1 : 0);
2209         if (default_data != data)
2210                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2211 }
2212
2213 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2214                                                 bool enable)
2215 {
2216         uint32_t data = 0;
2217         uint32_t default_data = 0;
2218
2219         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2220         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2221                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2222                              enable ? 1 : 0);
2223         if(default_data != data)
2224                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2225 }
2226
2227 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2228                                         bool enable)
2229 {
2230         uint32_t data = 0;
2231         uint32_t default_data = 0;
2232
2233         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2234         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2235                              CP_PG_DISABLE,
2236                              enable ? 0 : 1);
2237         if(default_data != data)
2238                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2239 }
2240
2241 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2242                                                 bool enable)
2243 {
2244         uint32_t data, default_data;
2245
2246         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2247         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2248                              GFX_POWER_GATING_ENABLE,
2249                              enable ? 1 : 0);
2250         if(default_data != data)
2251                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2252 }
2253
2254 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2255                                                 bool enable)
2256 {
2257         uint32_t data, default_data;
2258
2259         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2260         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2261                              GFX_PIPELINE_PG_ENABLE,
2262                              enable ? 1 : 0);
2263         if(default_data != data)
2264                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2265
2266         if (!enable)
2267                 /* read any GFX register to wake up GFX */
2268                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2269 }
2270
2271 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2272                                                        bool enable)
2273 {
2274         uint32_t data, default_data;
2275
2276         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2277         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2278                              STATIC_PER_CU_PG_ENABLE,
2279                              enable ? 1 : 0);
2280         if(default_data != data)
2281                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2282 }
2283
2284 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2285                                                 bool enable)
2286 {
2287         uint32_t data, default_data;
2288
2289         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2290         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2291                              DYN_PER_CU_PG_ENABLE,
2292                              enable ? 1 : 0);
2293         if(default_data != data)
2294                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2295 }
2296
2297 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2298 {
2299         gfx_v9_0_init_csb(adev);
2300
2301         /*
2302          * Rlc save restore list is workable since v2_1.
2303          * And it's needed by gfxoff feature.
2304          */
2305         if (adev->gfx.rlc.is_rlc_v2_1) {
2306                 gfx_v9_1_init_rlc_save_restore_list(adev);
2307                 gfx_v9_0_enable_save_restore_machine(adev);
2308         }
2309
2310         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2311                               AMD_PG_SUPPORT_GFX_SMG |
2312                               AMD_PG_SUPPORT_GFX_DMG |
2313                               AMD_PG_SUPPORT_CP |
2314                               AMD_PG_SUPPORT_GDS |
2315                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2316                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2317                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2318                 gfx_v9_0_init_gfx_power_gating(adev);
2319         }
2320 }
2321
2322 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2323 {
2324         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2325         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2326         gfx_v9_0_wait_for_rlc_serdes(adev);
2327 }
2328
2329 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2330 {
2331         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2332         udelay(50);
2333         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2334         udelay(50);
2335 }
2336
2337 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2338 {
2339 #ifdef AMDGPU_RLC_DEBUG_RETRY
2340         u32 rlc_ucode_ver;
2341 #endif
2342
2343         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2344         udelay(50);
2345
2346         /* carrizo do enable cp interrupt after cp inited */
2347         if (!(adev->flags & AMD_IS_APU)) {
2348                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2349                 udelay(50);
2350         }
2351
2352 #ifdef AMDGPU_RLC_DEBUG_RETRY
2353         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2354         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2355         if(rlc_ucode_ver == 0x108) {
2356                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2357                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2358                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2359                  * default is 0x9C4 to create a 100us interval */
2360                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2361                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2362                  * to disable the page fault retry interrupts, default is
2363                  * 0x100 (256) */
2364                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2365         }
2366 #endif
2367 }
2368
2369 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2370 {
2371         const struct rlc_firmware_header_v2_0 *hdr;
2372         const __le32 *fw_data;
2373         unsigned i, fw_size;
2374
2375         if (!adev->gfx.rlc_fw)
2376                 return -EINVAL;
2377
2378         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2379         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2380
2381         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2382                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2383         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2384
2385         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2386                         RLCG_UCODE_LOADING_START_ADDRESS);
2387         for (i = 0; i < fw_size; i++)
2388                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2389         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2390
2391         return 0;
2392 }
2393
2394 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2395 {
2396         int r;
2397
2398         if (amdgpu_sriov_vf(adev)) {
2399                 gfx_v9_0_init_csb(adev);
2400                 return 0;
2401         }
2402
2403         adev->gfx.rlc.funcs->stop(adev);
2404
2405         /* disable CG */
2406         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2407
2408         gfx_v9_0_init_pg(adev);
2409
2410         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2411                 /* legacy rlc firmware loading */
2412                 r = gfx_v9_0_rlc_load_microcode(adev);
2413                 if (r)
2414                         return r;
2415         }
2416
2417         switch (adev->asic_type) {
2418         case CHIP_RAVEN:
2419                 if (amdgpu_lbpw == 0)
2420                         gfx_v9_0_enable_lbpw(adev, false);
2421                 else
2422                         gfx_v9_0_enable_lbpw(adev, true);
2423                 break;
2424         case CHIP_VEGA20:
2425                 if (amdgpu_lbpw > 0)
2426                         gfx_v9_0_enable_lbpw(adev, true);
2427                 else
2428                         gfx_v9_0_enable_lbpw(adev, false);
2429                 break;
2430         default:
2431                 break;
2432         }
2433
2434         adev->gfx.rlc.funcs->start(adev);
2435
2436         return 0;
2437 }
2438
2439 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2440 {
2441         int i;
2442         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2443
2444         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2445         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2446         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2447         if (!enable) {
2448                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2449                         adev->gfx.gfx_ring[i].sched.ready = false;
2450         }
2451         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2452         udelay(50);
2453 }
2454
2455 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2456 {
2457         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2458         const struct gfx_firmware_header_v1_0 *ce_hdr;
2459         const struct gfx_firmware_header_v1_0 *me_hdr;
2460         const __le32 *fw_data;
2461         unsigned i, fw_size;
2462
2463         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2464                 return -EINVAL;
2465
2466         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2467                 adev->gfx.pfp_fw->data;
2468         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2469                 adev->gfx.ce_fw->data;
2470         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2471                 adev->gfx.me_fw->data;
2472
2473         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2474         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2475         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2476
2477         gfx_v9_0_cp_gfx_enable(adev, false);
2478
2479         /* PFP */
2480         fw_data = (const __le32 *)
2481                 (adev->gfx.pfp_fw->data +
2482                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2483         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2484         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2485         for (i = 0; i < fw_size; i++)
2486                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2487         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2488
2489         /* CE */
2490         fw_data = (const __le32 *)
2491                 (adev->gfx.ce_fw->data +
2492                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2493         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2494         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2495         for (i = 0; i < fw_size; i++)
2496                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2497         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2498
2499         /* ME */
2500         fw_data = (const __le32 *)
2501                 (adev->gfx.me_fw->data +
2502                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2503         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2504         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2505         for (i = 0; i < fw_size; i++)
2506                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2507         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2508
2509         return 0;
2510 }
2511
2512 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2513 {
2514         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2515         const struct cs_section_def *sect = NULL;
2516         const struct cs_extent_def *ext = NULL;
2517         int r, i, tmp;
2518
2519         /* init the CP */
2520         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2521         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2522
2523         gfx_v9_0_cp_gfx_enable(adev, true);
2524
2525         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2526         if (r) {
2527                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2528                 return r;
2529         }
2530
2531         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2532         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2533
2534         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2535         amdgpu_ring_write(ring, 0x80000000);
2536         amdgpu_ring_write(ring, 0x80000000);
2537
2538         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2539                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2540                         if (sect->id == SECT_CONTEXT) {
2541                                 amdgpu_ring_write(ring,
2542                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2543                                                ext->reg_count));
2544                                 amdgpu_ring_write(ring,
2545                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2546                                 for (i = 0; i < ext->reg_count; i++)
2547                                         amdgpu_ring_write(ring, ext->extent[i]);
2548                         }
2549                 }
2550         }
2551
2552         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2553         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2554
2555         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2556         amdgpu_ring_write(ring, 0);
2557
2558         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2559         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2560         amdgpu_ring_write(ring, 0x8000);
2561         amdgpu_ring_write(ring, 0x8000);
2562
2563         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2564         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2565                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2566         amdgpu_ring_write(ring, tmp);
2567         amdgpu_ring_write(ring, 0);
2568
2569         amdgpu_ring_commit(ring);
2570
2571         return 0;
2572 }
2573
2574 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2575 {
2576         struct amdgpu_ring *ring;
2577         u32 tmp;
2578         u32 rb_bufsz;
2579         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2580
2581         /* Set the write pointer delay */
2582         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2583
2584         /* set the RB to use vmid 0 */
2585         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2586
2587         /* Set ring buffer size */
2588         ring = &adev->gfx.gfx_ring[0];
2589         rb_bufsz = order_base_2(ring->ring_size / 8);
2590         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2591         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2592 #ifdef __BIG_ENDIAN
2593         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2594 #endif
2595         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2596
2597         /* Initialize the ring buffer's write pointers */
2598         ring->wptr = 0;
2599         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2600         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2601
2602         /* set the wb address wether it's enabled or not */
2603         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2604         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2605         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2606
2607         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2608         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2609         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2610
2611         mdelay(1);
2612         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2613
2614         rb_addr = ring->gpu_addr >> 8;
2615         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2616         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2617
2618         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2619         if (ring->use_doorbell) {
2620                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2621                                     DOORBELL_OFFSET, ring->doorbell_index);
2622                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2623                                     DOORBELL_EN, 1);
2624         } else {
2625                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2626         }
2627         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2628
2629         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2630                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2631         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2632
2633         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2634                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2635
2636
2637         /* start the ring */
2638         gfx_v9_0_cp_gfx_start(adev);
2639         ring->sched.ready = true;
2640
2641         return 0;
2642 }
2643
2644 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2645 {
2646         int i;
2647
2648         if (enable) {
2649                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2650         } else {
2651                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2652                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2653                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2654                         adev->gfx.compute_ring[i].sched.ready = false;
2655                 adev->gfx.kiq.ring.sched.ready = false;
2656         }
2657         udelay(50);
2658 }
2659
2660 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2661 {
2662         const struct gfx_firmware_header_v1_0 *mec_hdr;
2663         const __le32 *fw_data;
2664         unsigned i;
2665         u32 tmp;
2666
2667         if (!adev->gfx.mec_fw)
2668                 return -EINVAL;
2669
2670         gfx_v9_0_cp_compute_enable(adev, false);
2671
2672         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2673         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2674
2675         fw_data = (const __le32 *)
2676                 (adev->gfx.mec_fw->data +
2677                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2678         tmp = 0;
2679         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2680         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2681         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2682
2683         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2684                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2685         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2686                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2687
2688         /* MEC1 */
2689         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2690                          mec_hdr->jt_offset);
2691         for (i = 0; i < mec_hdr->jt_size; i++)
2692                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2693                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2694
2695         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2696                         adev->gfx.mec_fw_version);
2697         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2698
2699         return 0;
2700 }
2701
2702 /* KIQ functions */
2703 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2704 {
2705         uint32_t tmp;
2706         struct amdgpu_device *adev = ring->adev;
2707
2708         /* tell RLC which is KIQ queue */
2709         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2710         tmp &= 0xffffff00;
2711         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2712         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2713         tmp |= 0x80;
2714         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2715 }
2716
2717 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2718 {
2719         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2720         uint64_t queue_mask = 0;
2721         int r, i;
2722
2723         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2724                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2725                         continue;
2726
2727                 /* This situation may be hit in the future if a new HW
2728                  * generation exposes more than 64 queues. If so, the
2729                  * definition of queue_mask needs updating */
2730                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2731                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2732                         break;
2733                 }
2734
2735                 queue_mask |= (1ull << i);
2736         }
2737
2738         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
2739         if (r) {
2740                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2741                 return r;
2742         }
2743
2744         /* set resources */
2745         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2746         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2747                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2748         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2749         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2750         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2751         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2752         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2753         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2754         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2755                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2756                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2757                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2758
2759                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2760                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2761                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2762                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2763                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2764                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2765                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2766                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2767                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2768                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2769                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2770                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2771                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2772                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2773                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2774                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2775                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2776         }
2777
2778         r = amdgpu_ring_test_helper(kiq_ring);
2779         if (r)
2780                 DRM_ERROR("KCQ enable failed\n");
2781
2782         return r;
2783 }
2784
2785 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2786 {
2787         struct amdgpu_device *adev = ring->adev;
2788         struct v9_mqd *mqd = ring->mqd_ptr;
2789         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2790         uint32_t tmp;
2791
2792         mqd->header = 0xC0310800;
2793         mqd->compute_pipelinestat_enable = 0x00000001;
2794         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2795         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2796         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2797         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2798         mqd->compute_misc_reserved = 0x00000003;
2799
2800         mqd->dynamic_cu_mask_addr_lo =
2801                 lower_32_bits(ring->mqd_gpu_addr
2802                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2803         mqd->dynamic_cu_mask_addr_hi =
2804                 upper_32_bits(ring->mqd_gpu_addr
2805                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2806
2807         eop_base_addr = ring->eop_gpu_addr >> 8;
2808         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2809         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2810
2811         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2812         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2813         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2814                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2815
2816         mqd->cp_hqd_eop_control = tmp;
2817
2818         /* enable doorbell? */
2819         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2820
2821         if (ring->use_doorbell) {
2822                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2823                                     DOORBELL_OFFSET, ring->doorbell_index);
2824                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2825                                     DOORBELL_EN, 1);
2826                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2827                                     DOORBELL_SOURCE, 0);
2828                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2829                                     DOORBELL_HIT, 0);
2830         } else {
2831                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2832                                          DOORBELL_EN, 0);
2833         }
2834
2835         mqd->cp_hqd_pq_doorbell_control = tmp;
2836
2837         /* disable the queue if it's active */
2838         ring->wptr = 0;
2839         mqd->cp_hqd_dequeue_request = 0;
2840         mqd->cp_hqd_pq_rptr = 0;
2841         mqd->cp_hqd_pq_wptr_lo = 0;
2842         mqd->cp_hqd_pq_wptr_hi = 0;
2843
2844         /* set the pointer to the MQD */
2845         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2846         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2847
2848         /* set MQD vmid to 0 */
2849         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2850         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2851         mqd->cp_mqd_control = tmp;
2852
2853         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2854         hqd_gpu_addr = ring->gpu_addr >> 8;
2855         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2856         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2857
2858         /* set up the HQD, this is similar to CP_RB0_CNTL */
2859         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2860         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2861                             (order_base_2(ring->ring_size / 4) - 1));
2862         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2863                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2864 #ifdef __BIG_ENDIAN
2865         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2866 #endif
2867         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2868         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2869         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2870         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2871         mqd->cp_hqd_pq_control = tmp;
2872
2873         /* set the wb address whether it's enabled or not */
2874         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2875         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2876         mqd->cp_hqd_pq_rptr_report_addr_hi =
2877                 upper_32_bits(wb_gpu_addr) & 0xffff;
2878
2879         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2880         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2881         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2882         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2883
2884         tmp = 0;
2885         /* enable the doorbell if requested */
2886         if (ring->use_doorbell) {
2887                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2888                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2889                                 DOORBELL_OFFSET, ring->doorbell_index);
2890
2891                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2892                                          DOORBELL_EN, 1);
2893                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2894                                          DOORBELL_SOURCE, 0);
2895                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2896                                          DOORBELL_HIT, 0);
2897         }
2898
2899         mqd->cp_hqd_pq_doorbell_control = tmp;
2900
2901         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2902         ring->wptr = 0;
2903         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2904
2905         /* set the vmid for the queue */
2906         mqd->cp_hqd_vmid = 0;
2907
2908         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2909         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2910         mqd->cp_hqd_persistent_state = tmp;
2911
2912         /* set MIN_IB_AVAIL_SIZE */
2913         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2914         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2915         mqd->cp_hqd_ib_control = tmp;
2916
2917         /* activate the queue */
2918         mqd->cp_hqd_active = 1;
2919
2920         return 0;
2921 }
2922
2923 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2924 {
2925         struct amdgpu_device *adev = ring->adev;
2926         struct v9_mqd *mqd = ring->mqd_ptr;
2927         int j;
2928
2929         /* disable wptr polling */
2930         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2931
2932         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2933                mqd->cp_hqd_eop_base_addr_lo);
2934         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2935                mqd->cp_hqd_eop_base_addr_hi);
2936
2937         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2938         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2939                mqd->cp_hqd_eop_control);
2940
2941         /* enable doorbell? */
2942         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2943                mqd->cp_hqd_pq_doorbell_control);
2944
2945         /* disable the queue if it's active */
2946         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2947                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2948                 for (j = 0; j < adev->usec_timeout; j++) {
2949                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2950                                 break;
2951                         udelay(1);
2952                 }
2953                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2954                        mqd->cp_hqd_dequeue_request);
2955                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2956                        mqd->cp_hqd_pq_rptr);
2957                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2958                        mqd->cp_hqd_pq_wptr_lo);
2959                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2960                        mqd->cp_hqd_pq_wptr_hi);
2961         }
2962
2963         /* set the pointer to the MQD */
2964         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2965                mqd->cp_mqd_base_addr_lo);
2966         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2967                mqd->cp_mqd_base_addr_hi);
2968
2969         /* set MQD vmid to 0 */
2970         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2971                mqd->cp_mqd_control);
2972
2973         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2974         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2975                mqd->cp_hqd_pq_base_lo);
2976         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2977                mqd->cp_hqd_pq_base_hi);
2978
2979         /* set up the HQD, this is similar to CP_RB0_CNTL */
2980         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2981                mqd->cp_hqd_pq_control);
2982
2983         /* set the wb address whether it's enabled or not */
2984         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2985                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2986         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2987                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2988
2989         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2990         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2991                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2992         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2993                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2994
2995         /* enable the doorbell if requested */
2996         if (ring->use_doorbell) {
2997                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2998                                         (adev->doorbell_index.kiq * 2) << 2);
2999                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3000                                         (adev->doorbell_index.userqueue_end * 2) << 2);
3001         }
3002
3003         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3004                mqd->cp_hqd_pq_doorbell_control);
3005
3006         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3007         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3008                mqd->cp_hqd_pq_wptr_lo);
3009         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3010                mqd->cp_hqd_pq_wptr_hi);
3011
3012         /* set the vmid for the queue */
3013         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3014
3015         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3016                mqd->cp_hqd_persistent_state);
3017
3018         /* activate the queue */
3019         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3020                mqd->cp_hqd_active);
3021
3022         if (ring->use_doorbell)
3023                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3024
3025         return 0;
3026 }
3027
3028 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3029 {
3030         struct amdgpu_device *adev = ring->adev;
3031         int j;
3032
3033         /* disable the queue if it's active */
3034         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3035
3036                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3037
3038                 for (j = 0; j < adev->usec_timeout; j++) {
3039                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3040                                 break;
3041                         udelay(1);
3042                 }
3043
3044                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3045                         DRM_DEBUG("KIQ dequeue request failed.\n");
3046
3047                         /* Manual disable if dequeue request times out */
3048                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
3049                 }
3050
3051                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3052                       0);
3053         }
3054
3055         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3056         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3057         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3058         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3059         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3060         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3061         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3062         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3063
3064         return 0;
3065 }
3066
3067 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3068 {
3069         struct amdgpu_device *adev = ring->adev;
3070         struct v9_mqd *mqd = ring->mqd_ptr;
3071         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3072
3073         gfx_v9_0_kiq_setting(ring);
3074
3075         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3076                 /* reset MQD to a clean status */
3077                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3078                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3079
3080                 /* reset ring buffer */
3081                 ring->wptr = 0;
3082                 amdgpu_ring_clear_ring(ring);
3083
3084                 mutex_lock(&adev->srbm_mutex);
3085                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3086                 gfx_v9_0_kiq_init_register(ring);
3087                 soc15_grbm_select(adev, 0, 0, 0, 0);
3088                 mutex_unlock(&adev->srbm_mutex);
3089         } else {
3090                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3091                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3092                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3093                 mutex_lock(&adev->srbm_mutex);
3094                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3095                 gfx_v9_0_mqd_init(ring);
3096                 gfx_v9_0_kiq_init_register(ring);
3097                 soc15_grbm_select(adev, 0, 0, 0, 0);
3098                 mutex_unlock(&adev->srbm_mutex);
3099
3100                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3101                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3102         }
3103
3104         return 0;
3105 }
3106
3107 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3108 {
3109         struct amdgpu_device *adev = ring->adev;
3110         struct v9_mqd *mqd = ring->mqd_ptr;
3111         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3112
3113         if (!adev->in_gpu_reset && !adev->in_suspend) {
3114                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3115                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3116                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3117                 mutex_lock(&adev->srbm_mutex);
3118                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3119                 gfx_v9_0_mqd_init(ring);
3120                 soc15_grbm_select(adev, 0, 0, 0, 0);
3121                 mutex_unlock(&adev->srbm_mutex);
3122
3123                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3124                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3125         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3126                 /* reset MQD to a clean status */
3127                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3128                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3129
3130                 /* reset ring buffer */
3131                 ring->wptr = 0;
3132                 amdgpu_ring_clear_ring(ring);
3133         } else {
3134                 amdgpu_ring_clear_ring(ring);
3135         }
3136
3137         return 0;
3138 }
3139
3140 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3141 {
3142         struct amdgpu_ring *ring;
3143         int r;
3144
3145         ring = &adev->gfx.kiq.ring;
3146
3147         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3148         if (unlikely(r != 0))
3149                 return r;
3150
3151         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3152         if (unlikely(r != 0))
3153                 return r;
3154
3155         gfx_v9_0_kiq_init_queue(ring);
3156         amdgpu_bo_kunmap(ring->mqd_obj);
3157         ring->mqd_ptr = NULL;
3158         amdgpu_bo_unreserve(ring->mqd_obj);
3159         ring->sched.ready = true;
3160         return 0;
3161 }
3162
3163 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3164 {
3165         struct amdgpu_ring *ring = NULL;
3166         int r = 0, i;
3167
3168         gfx_v9_0_cp_compute_enable(adev, true);
3169
3170         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3171                 ring = &adev->gfx.compute_ring[i];
3172
3173                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3174                 if (unlikely(r != 0))
3175                         goto done;
3176                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3177                 if (!r) {
3178                         r = gfx_v9_0_kcq_init_queue(ring);
3179                         amdgpu_bo_kunmap(ring->mqd_obj);
3180                         ring->mqd_ptr = NULL;
3181                 }
3182                 amdgpu_bo_unreserve(ring->mqd_obj);
3183                 if (r)
3184                         goto done;
3185         }
3186
3187         r = gfx_v9_0_kiq_kcq_enable(adev);
3188 done:
3189         return r;
3190 }
3191
3192 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3193 {
3194         int r, i;
3195         struct amdgpu_ring *ring;
3196
3197         if (!(adev->flags & AMD_IS_APU))
3198                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3199
3200         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3201                 /* legacy firmware loading */
3202                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3203                 if (r)
3204                         return r;
3205
3206                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3207                 if (r)
3208                         return r;
3209         }
3210
3211         r = gfx_v9_0_kiq_resume(adev);
3212         if (r)
3213                 return r;
3214
3215         r = gfx_v9_0_cp_gfx_resume(adev);
3216         if (r)
3217                 return r;
3218
3219         r = gfx_v9_0_kcq_resume(adev);
3220         if (r)
3221                 return r;
3222
3223         ring = &adev->gfx.gfx_ring[0];
3224         r = amdgpu_ring_test_helper(ring);
3225         if (r)
3226                 return r;
3227
3228         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3229                 ring = &adev->gfx.compute_ring[i];
3230                 amdgpu_ring_test_helper(ring);
3231         }
3232
3233         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3234
3235         return 0;
3236 }
3237
3238 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3239 {
3240         gfx_v9_0_cp_gfx_enable(adev, enable);
3241         gfx_v9_0_cp_compute_enable(adev, enable);
3242 }
3243
3244 static int gfx_v9_0_hw_init(void *handle)
3245 {
3246         int r;
3247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3248
3249         gfx_v9_0_init_golden_registers(adev);
3250
3251         gfx_v9_0_constants_init(adev);
3252
3253         r = gfx_v9_0_csb_vram_pin(adev);
3254         if (r)
3255                 return r;
3256
3257         r = adev->gfx.rlc.funcs->resume(adev);
3258         if (r)
3259                 return r;
3260
3261         r = gfx_v9_0_cp_resume(adev);
3262         if (r)
3263                 return r;
3264
3265         r = gfx_v9_0_ngg_en(adev);
3266         if (r)
3267                 return r;
3268
3269         return r;
3270 }
3271
3272 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev)
3273 {
3274         int r, i;
3275         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3276
3277         r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
3278         if (r)
3279                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3280
3281         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3282                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3283
3284                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3285                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3286                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3287                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3288                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3289                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3290                 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3291                 amdgpu_ring_write(kiq_ring, 0);
3292                 amdgpu_ring_write(kiq_ring, 0);
3293                 amdgpu_ring_write(kiq_ring, 0);
3294         }
3295         r = amdgpu_ring_test_helper(kiq_ring);
3296         if (r)
3297                 DRM_ERROR("KCQ disable failed\n");
3298
3299         return r;
3300 }
3301
3302 static int gfx_v9_0_hw_fini(void *handle)
3303 {
3304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3305
3306         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3307         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3308
3309         /* disable KCQ to avoid CPC touch memory not valid anymore */
3310         gfx_v9_0_kcq_disable(adev);
3311
3312         if (amdgpu_sriov_vf(adev)) {
3313                 gfx_v9_0_cp_gfx_enable(adev, false);
3314                 /* must disable polling for SRIOV when hw finished, otherwise
3315                  * CPC engine may still keep fetching WB address which is already
3316                  * invalid after sw finished and trigger DMAR reading error in
3317                  * hypervisor side.
3318                  */
3319                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3320                 return 0;
3321         }
3322
3323         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3324          * otherwise KIQ is hanging when binding back
3325          */
3326         if (!adev->in_gpu_reset && !adev->in_suspend) {
3327                 mutex_lock(&adev->srbm_mutex);
3328                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3329                                 adev->gfx.kiq.ring.pipe,
3330                                 adev->gfx.kiq.ring.queue, 0);
3331                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3332                 soc15_grbm_select(adev, 0, 0, 0, 0);
3333                 mutex_unlock(&adev->srbm_mutex);
3334         }
3335
3336         gfx_v9_0_cp_enable(adev, false);
3337         adev->gfx.rlc.funcs->stop(adev);
3338
3339         gfx_v9_0_csb_vram_unpin(adev);
3340
3341         return 0;
3342 }
3343
3344 static int gfx_v9_0_suspend(void *handle)
3345 {
3346         return gfx_v9_0_hw_fini(handle);
3347 }
3348
3349 static int gfx_v9_0_resume(void *handle)
3350 {
3351         return gfx_v9_0_hw_init(handle);
3352 }
3353
3354 static bool gfx_v9_0_is_idle(void *handle)
3355 {
3356         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3357
3358         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3359                                 GRBM_STATUS, GUI_ACTIVE))
3360                 return false;
3361         else
3362                 return true;
3363 }
3364
3365 static int gfx_v9_0_wait_for_idle(void *handle)
3366 {
3367         unsigned i;
3368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3369
3370         for (i = 0; i < adev->usec_timeout; i++) {
3371                 if (gfx_v9_0_is_idle(handle))
3372                         return 0;
3373                 udelay(1);
3374         }
3375         return -ETIMEDOUT;
3376 }
3377
3378 static int gfx_v9_0_soft_reset(void *handle)
3379 {
3380         u32 grbm_soft_reset = 0;
3381         u32 tmp;
3382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3383
3384         /* GRBM_STATUS */
3385         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3386         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3387                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3388                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3389                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3390                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3391                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3392                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3393                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3394                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3395                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3396         }
3397
3398         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3399                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3400                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3401         }
3402
3403         /* GRBM_STATUS2 */
3404         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3405         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3406                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3407                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3408
3409
3410         if (grbm_soft_reset) {
3411                 /* stop the rlc */
3412                 adev->gfx.rlc.funcs->stop(adev);
3413
3414                 /* Disable GFX parsing/prefetching */
3415                 gfx_v9_0_cp_gfx_enable(adev, false);
3416
3417                 /* Disable MEC parsing/prefetching */
3418                 gfx_v9_0_cp_compute_enable(adev, false);
3419
3420                 if (grbm_soft_reset) {
3421                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3422                         tmp |= grbm_soft_reset;
3423                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3424                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3425                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3426
3427                         udelay(50);
3428
3429                         tmp &= ~grbm_soft_reset;
3430                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3431                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3432                 }
3433
3434                 /* Wait a little for things to settle down */
3435                 udelay(50);
3436         }
3437         return 0;
3438 }
3439
3440 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3441 {
3442         uint64_t clock;
3443
3444         mutex_lock(&adev->gfx.gpu_clock_mutex);
3445         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3446         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3447                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3448         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3449         return clock;
3450 }
3451
3452 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3453                                           uint32_t vmid,
3454                                           uint32_t gds_base, uint32_t gds_size,
3455                                           uint32_t gws_base, uint32_t gws_size,
3456                                           uint32_t oa_base, uint32_t oa_size)
3457 {
3458         struct amdgpu_device *adev = ring->adev;
3459
3460         /* GDS Base */
3461         gfx_v9_0_write_data_to_reg(ring, 0, false,
3462                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3463                                    gds_base);
3464
3465         /* GDS Size */
3466         gfx_v9_0_write_data_to_reg(ring, 0, false,
3467                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3468                                    gds_size);
3469
3470         /* GWS */
3471         gfx_v9_0_write_data_to_reg(ring, 0, false,
3472                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3473                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3474
3475         /* OA */
3476         gfx_v9_0_write_data_to_reg(ring, 0, false,
3477                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3478                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3479 }
3480
3481 static int gfx_v9_0_early_init(void *handle)
3482 {
3483         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3484
3485         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3486         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3487         gfx_v9_0_set_ring_funcs(adev);
3488         gfx_v9_0_set_irq_funcs(adev);
3489         gfx_v9_0_set_gds_init(adev);
3490         gfx_v9_0_set_rlc_funcs(adev);
3491
3492         return 0;
3493 }
3494
3495 static int gfx_v9_0_late_init(void *handle)
3496 {
3497         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3498         int r;
3499
3500         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3501         if (r)
3502                 return r;
3503
3504         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3505         if (r)
3506                 return r;
3507
3508         return 0;
3509 }
3510
3511 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
3512 {
3513         uint32_t rlc_setting;
3514
3515         /* if RLC is not enabled, do nothing */
3516         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3517         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3518                 return false;
3519
3520         return true;
3521 }
3522
3523 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
3524 {
3525         uint32_t data;
3526         unsigned i;
3527
3528         data = RLC_SAFE_MODE__CMD_MASK;
3529         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3530         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3531
3532         /* wait for RLC_SAFE_MODE */
3533         for (i = 0; i < adev->usec_timeout; i++) {
3534                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3535                         break;
3536                 udelay(1);
3537         }
3538 }
3539
3540 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
3541 {
3542         uint32_t data;
3543
3544         data = RLC_SAFE_MODE__CMD_MASK;
3545         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3546 }
3547
3548 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3549                                                 bool enable)
3550 {
3551         amdgpu_gfx_rlc_enter_safe_mode(adev);
3552
3553         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3554                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3555                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3556                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3557         } else {
3558                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3559                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3560         }
3561
3562         amdgpu_gfx_rlc_exit_safe_mode(adev);
3563 }
3564
3565 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3566                                                 bool enable)
3567 {
3568         /* TODO: double check if we need to perform under safe mode */
3569         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3570
3571         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3572                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3573         else
3574                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3575
3576         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3577                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3578         else
3579                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3580
3581         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3582 }
3583
3584 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3585                                                       bool enable)
3586 {
3587         uint32_t data, def;
3588
3589         amdgpu_gfx_rlc_enter_safe_mode(adev);
3590
3591         /* It is disabled by HW by default */
3592         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3593                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3594                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3595
3596                 if (adev->asic_type != CHIP_VEGA12)
3597                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3598
3599                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3600                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3601                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3602
3603                 /* only for Vega10 & Raven1 */
3604                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3605
3606                 if (def != data)
3607                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3608
3609                 /* MGLS is a global flag to control all MGLS in GFX */
3610                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3611                         /* 2 - RLC memory Light sleep */
3612                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3613                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3614                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3615                                 if (def != data)
3616                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3617                         }
3618                         /* 3 - CP memory Light sleep */
3619                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3620                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3621                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3622                                 if (def != data)
3623                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3624                         }
3625                 }
3626         } else {
3627                 /* 1 - MGCG_OVERRIDE */
3628                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3629
3630                 if (adev->asic_type != CHIP_VEGA12)
3631                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3632
3633                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3634                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3635                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3636                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3637
3638                 if (def != data)
3639                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3640
3641                 /* 2 - disable MGLS in RLC */
3642                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3643                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3644                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3645                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3646                 }
3647
3648                 /* 3 - disable MGLS in CP */
3649                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3650                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3651                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3652                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3653                 }
3654         }
3655
3656         amdgpu_gfx_rlc_exit_safe_mode(adev);
3657 }
3658
3659 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3660                                            bool enable)
3661 {
3662         uint32_t data, def;
3663
3664         amdgpu_gfx_rlc_enter_safe_mode(adev);
3665
3666         /* Enable 3D CGCG/CGLS */
3667         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3668                 /* write cmd to clear cgcg/cgls ov */
3669                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3670                 /* unset CGCG override */
3671                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3672                 /* update CGCG and CGLS override bits */
3673                 if (def != data)
3674                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3675
3676                 /* enable 3Dcgcg FSM(0x0000363f) */
3677                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3678
3679                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3680                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3681                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3682                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3683                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3684                 if (def != data)
3685                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3686
3687                 /* set IDLE_POLL_COUNT(0x00900100) */
3688                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3689                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3690                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3691                 if (def != data)
3692                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3693         } else {
3694                 /* Disable CGCG/CGLS */
3695                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3696                 /* disable cgcg, cgls should be disabled */
3697                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3698                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3699                 /* disable cgcg and cgls in FSM */
3700                 if (def != data)
3701                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3702         }
3703
3704         amdgpu_gfx_rlc_exit_safe_mode(adev);
3705 }
3706
3707 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3708                                                       bool enable)
3709 {
3710         uint32_t def, data;
3711
3712         amdgpu_gfx_rlc_enter_safe_mode(adev);
3713
3714         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3715                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3716                 /* unset CGCG override */
3717                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3718                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3719                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3720                 else
3721                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3722                 /* update CGCG and CGLS override bits */
3723                 if (def != data)
3724                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3725
3726                 /* enable cgcg FSM(0x0000363F) */
3727                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3728
3729                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3730                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3731                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3732                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3733                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3734                 if (def != data)
3735                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3736
3737                 /* set IDLE_POLL_COUNT(0x00900100) */
3738                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3739                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3740                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3741                 if (def != data)
3742                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3743         } else {
3744                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3745                 /* reset CGCG/CGLS bits */
3746                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3747                 /* disable cgcg and cgls in FSM */
3748                 if (def != data)
3749                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3750         }
3751
3752         amdgpu_gfx_rlc_exit_safe_mode(adev);
3753 }
3754
3755 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3756                                             bool enable)
3757 {
3758         if (enable) {
3759                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3760                  * ===  MGCG + MGLS ===
3761                  */
3762                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3763                 /* ===  CGCG /CGLS for GFX 3D Only === */
3764                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3765                 /* ===  CGCG + CGLS === */
3766                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3767         } else {
3768                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3769                  * ===  CGCG + CGLS ===
3770                  */
3771                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3772                 /* ===  CGCG /CGLS for GFX 3D Only === */
3773                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3774                 /* ===  MGCG + MGLS === */
3775                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3776         }
3777         return 0;
3778 }
3779
3780 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3781         .is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
3782         .set_safe_mode = gfx_v9_0_set_safe_mode,
3783         .unset_safe_mode = gfx_v9_0_unset_safe_mode,
3784         .init = gfx_v9_0_rlc_init,
3785         .get_csb_size = gfx_v9_0_get_csb_size,
3786         .get_csb_buffer = gfx_v9_0_get_csb_buffer,
3787         .get_cp_table_num = gfx_v9_0_cp_jump_table_num,
3788         .resume = gfx_v9_0_rlc_resume,
3789         .stop = gfx_v9_0_rlc_stop,
3790         .reset = gfx_v9_0_rlc_reset,
3791         .start = gfx_v9_0_rlc_start
3792 };
3793
3794 static int gfx_v9_0_set_powergating_state(void *handle,
3795                                           enum amd_powergating_state state)
3796 {
3797         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3798         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3799
3800         switch (adev->asic_type) {
3801         case CHIP_RAVEN:
3802                 if (!enable) {
3803                         amdgpu_gfx_off_ctrl(adev, false);
3804                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3805                 }
3806                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3807                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3808                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3809                 } else {
3810                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3811                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3812                 }
3813
3814                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3815                         gfx_v9_0_enable_cp_power_gating(adev, true);
3816                 else
3817                         gfx_v9_0_enable_cp_power_gating(adev, false);
3818
3819                 /* update gfx cgpg state */
3820                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3821
3822                 /* update mgcg state */
3823                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3824
3825                 if (enable)
3826                         amdgpu_gfx_off_ctrl(adev, true);
3827                 break;
3828         case CHIP_VEGA12:
3829                 if (!enable) {
3830                         amdgpu_gfx_off_ctrl(adev, false);
3831                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3832                 } else {
3833                         amdgpu_gfx_off_ctrl(adev, true);
3834                 }
3835                 break;
3836         default:
3837                 break;
3838         }
3839
3840         return 0;
3841 }
3842
3843 static int gfx_v9_0_set_clockgating_state(void *handle,
3844                                           enum amd_clockgating_state state)
3845 {
3846         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3847
3848         if (amdgpu_sriov_vf(adev))
3849                 return 0;
3850
3851         switch (adev->asic_type) {
3852         case CHIP_VEGA10:
3853         case CHIP_VEGA12:
3854         case CHIP_VEGA20:
3855         case CHIP_RAVEN:
3856                 gfx_v9_0_update_gfx_clock_gating(adev,
3857                                                  state == AMD_CG_STATE_GATE ? true : false);
3858                 break;
3859         default:
3860                 break;
3861         }
3862         return 0;
3863 }
3864
3865 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3866 {
3867         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3868         int data;
3869
3870         if (amdgpu_sriov_vf(adev))
3871                 *flags = 0;
3872
3873         /* AMD_CG_SUPPORT_GFX_MGCG */
3874         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3875         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3876                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3877
3878         /* AMD_CG_SUPPORT_GFX_CGCG */
3879         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3880         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3881                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3882
3883         /* AMD_CG_SUPPORT_GFX_CGLS */
3884         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3885                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3886
3887         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3888         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3889         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3890                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3891
3892         /* AMD_CG_SUPPORT_GFX_CP_LS */
3893         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3894         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3895                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3896
3897         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3898         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3899         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3900                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3901
3902         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3903         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3904                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3905 }
3906
3907 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3908 {
3909         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3910 }
3911
3912 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3913 {
3914         struct amdgpu_device *adev = ring->adev;
3915         u64 wptr;
3916
3917         /* XXX check if swapping is necessary on BE */
3918         if (ring->use_doorbell) {
3919                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3920         } else {
3921                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3922                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3923         }
3924
3925         return wptr;
3926 }
3927
3928 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3929 {
3930         struct amdgpu_device *adev = ring->adev;
3931
3932         if (ring->use_doorbell) {
3933                 /* XXX check if swapping is necessary on BE */
3934                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3935                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3936         } else {
3937                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3938                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3939         }
3940 }
3941
3942 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3943 {
3944         struct amdgpu_device *adev = ring->adev;
3945         u32 ref_and_mask, reg_mem_engine;
3946         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3947
3948         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3949                 switch (ring->me) {
3950                 case 1:
3951                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3952                         break;
3953                 case 2:
3954                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3955                         break;
3956                 default:
3957                         return;
3958                 }
3959                 reg_mem_engine = 0;
3960         } else {
3961                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3962                 reg_mem_engine = 1; /* pfp */
3963         }
3964
3965         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3966                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3967                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3968                               ref_and_mask, ref_and_mask, 0x20);
3969 }
3970
3971 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3972                                         struct amdgpu_job *job,
3973                                         struct amdgpu_ib *ib,
3974                                         uint32_t flags)
3975 {
3976         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
3977         u32 header, control = 0;
3978
3979         if (ib->flags & AMDGPU_IB_FLAG_CE)
3980                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3981         else
3982                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3983
3984         control |= ib->length_dw | (vmid << 24);
3985
3986         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3987                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3988
3989                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3990                         gfx_v9_0_ring_emit_de_meta(ring);
3991         }
3992
3993         amdgpu_ring_write(ring, header);
3994         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3995         amdgpu_ring_write(ring,
3996 #ifdef __BIG_ENDIAN
3997                 (2 << 0) |
3998 #endif
3999                 lower_32_bits(ib->gpu_addr));
4000         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4001         amdgpu_ring_write(ring, control);
4002 }
4003
4004 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4005                                           struct amdgpu_job *job,
4006                                           struct amdgpu_ib *ib,
4007                                           uint32_t flags)
4008 {
4009         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4010         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4011
4012         /* Currently, there is a high possibility to get wave ID mismatch
4013          * between ME and GDS, leading to a hw deadlock, because ME generates
4014          * different wave IDs than the GDS expects. This situation happens
4015          * randomly when at least 5 compute pipes use GDS ordered append.
4016          * The wave IDs generated by ME are also wrong after suspend/resume.
4017          * Those are probably bugs somewhere else in the kernel driver.
4018          *
4019          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4020          * GDS to 0 for this ring (me/pipe).
4021          */
4022         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4023                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4024                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4025                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4026         }
4027
4028         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4029         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4030         amdgpu_ring_write(ring,
4031 #ifdef __BIG_ENDIAN
4032                                 (2 << 0) |
4033 #endif
4034                                 lower_32_bits(ib->gpu_addr));
4035         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4036         amdgpu_ring_write(ring, control);
4037 }
4038
4039 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4040                                      u64 seq, unsigned flags)
4041 {
4042         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4043         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4044         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
4045
4046         /* RELEASE_MEM - flush caches, send int */
4047         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4048         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
4049                                                EOP_TC_NC_ACTION_EN) :
4050                                               (EOP_TCL1_ACTION_EN |
4051                                                EOP_TC_ACTION_EN |
4052                                                EOP_TC_WB_ACTION_EN |
4053                                                EOP_TC_MD_ACTION_EN)) |
4054                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4055                                  EVENT_INDEX(5)));
4056         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4057
4058         /*
4059          * the address should be Qword aligned if 64bit write, Dword
4060          * aligned if only send 32bit data low (discard data high)
4061          */
4062         if (write64bit)
4063                 BUG_ON(addr & 0x7);
4064         else
4065                 BUG_ON(addr & 0x3);
4066         amdgpu_ring_write(ring, lower_32_bits(addr));
4067         amdgpu_ring_write(ring, upper_32_bits(addr));
4068         amdgpu_ring_write(ring, lower_32_bits(seq));
4069         amdgpu_ring_write(ring, upper_32_bits(seq));
4070         amdgpu_ring_write(ring, 0);
4071 }
4072
4073 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4074 {
4075         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4076         uint32_t seq = ring->fence_drv.sync_seq;
4077         uint64_t addr = ring->fence_drv.gpu_addr;
4078
4079         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4080                               lower_32_bits(addr), upper_32_bits(addr),
4081                               seq, 0xffffffff, 4);
4082 }
4083
4084 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4085                                         unsigned vmid, uint64_t pd_addr)
4086 {
4087         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4088
4089         /* compute doesn't have PFP */
4090         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4091                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4092                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4093                 amdgpu_ring_write(ring, 0x0);
4094         }
4095 }
4096
4097 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4098 {
4099         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4100 }
4101
4102 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4103 {
4104         u64 wptr;
4105
4106         /* XXX check if swapping is necessary on BE */
4107         if (ring->use_doorbell)
4108                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4109         else
4110                 BUG();
4111         return wptr;
4112 }
4113
4114 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4115                                            bool acquire)
4116 {
4117         struct amdgpu_device *adev = ring->adev;
4118         int pipe_num, tmp, reg;
4119         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4120
4121         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4122
4123         /* first me only has 2 entries, GFX and HP3D */
4124         if (ring->me > 0)
4125                 pipe_num -= 2;
4126
4127         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4128         tmp = RREG32(reg);
4129         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4130         WREG32(reg, tmp);
4131 }
4132
4133 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4134                                             struct amdgpu_ring *ring,
4135                                             bool acquire)
4136 {
4137         int i, pipe;
4138         bool reserve;
4139         struct amdgpu_ring *iring;
4140
4141         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4142         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4143         if (acquire)
4144                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4145         else
4146                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4147
4148         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4149                 /* Clear all reservations - everyone reacquires all resources */
4150                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4151                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4152                                                        true);
4153
4154                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4155                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4156                                                        true);
4157         } else {
4158                 /* Lower all pipes without a current reservation */
4159                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4160                         iring = &adev->gfx.gfx_ring[i];
4161                         pipe = amdgpu_gfx_queue_to_bit(adev,
4162                                                        iring->me,
4163                                                        iring->pipe,
4164                                                        0);
4165                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4166                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4167                 }
4168
4169                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4170                         iring = &adev->gfx.compute_ring[i];
4171                         pipe = amdgpu_gfx_queue_to_bit(adev,
4172                                                        iring->me,
4173                                                        iring->pipe,
4174                                                        0);
4175                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4176                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4177                 }
4178         }
4179
4180         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4181 }
4182
4183 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4184                                       struct amdgpu_ring *ring,
4185                                       bool acquire)
4186 {
4187         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4188         uint32_t queue_priority = acquire ? 0xf : 0x0;
4189
4190         mutex_lock(&adev->srbm_mutex);
4191         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4192
4193         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4194         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4195
4196         soc15_grbm_select(adev, 0, 0, 0, 0);
4197         mutex_unlock(&adev->srbm_mutex);
4198 }
4199
4200 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4201                                                enum drm_sched_priority priority)
4202 {
4203         struct amdgpu_device *adev = ring->adev;
4204         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4205
4206         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4207                 return;
4208
4209         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4210         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4211 }
4212
4213 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4214 {
4215         struct amdgpu_device *adev = ring->adev;
4216
4217         /* XXX check if swapping is necessary on BE */
4218         if (ring->use_doorbell) {
4219                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4220                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4221         } else{
4222                 BUG(); /* only DOORBELL method supported on gfx9 now */
4223         }
4224 }
4225
4226 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4227                                          u64 seq, unsigned int flags)
4228 {
4229         struct amdgpu_device *adev = ring->adev;
4230
4231         /* we only allocate 32bit for each seq wb address */
4232         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4233
4234         /* write fence seq to the "addr" */
4235         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4236         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4237                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4238         amdgpu_ring_write(ring, lower_32_bits(addr));
4239         amdgpu_ring_write(ring, upper_32_bits(addr));
4240         amdgpu_ring_write(ring, lower_32_bits(seq));
4241
4242         if (flags & AMDGPU_FENCE_FLAG_INT) {
4243                 /* set register to trigger INT */
4244                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4245                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4246                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4247                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4248                 amdgpu_ring_write(ring, 0);
4249                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4250         }
4251 }
4252
4253 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4254 {
4255         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4256         amdgpu_ring_write(ring, 0);
4257 }
4258
4259 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4260 {
4261         struct v9_ce_ib_state ce_payload = {0};
4262         uint64_t csa_addr;
4263         int cnt;
4264
4265         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4266         csa_addr = amdgpu_csa_vaddr(ring->adev);
4267
4268         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4269         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4270                                  WRITE_DATA_DST_SEL(8) |
4271                                  WR_CONFIRM) |
4272                                  WRITE_DATA_CACHE_POLICY(0));
4273         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4274         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4275         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4276 }
4277
4278 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4279 {
4280         struct v9_de_ib_state de_payload = {0};
4281         uint64_t csa_addr, gds_addr;
4282         int cnt;
4283
4284         csa_addr = amdgpu_csa_vaddr(ring->adev);
4285         gds_addr = csa_addr + 4096;
4286         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4287         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4288
4289         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4290         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4291         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4292                                  WRITE_DATA_DST_SEL(8) |
4293                                  WR_CONFIRM) |
4294                                  WRITE_DATA_CACHE_POLICY(0));
4295         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4296         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4297         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4298 }
4299
4300 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4301 {
4302         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4303         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4304 }
4305
4306 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4307 {
4308         uint32_t dw2 = 0;
4309
4310         if (amdgpu_sriov_vf(ring->adev))
4311                 gfx_v9_0_ring_emit_ce_meta(ring);
4312
4313         gfx_v9_0_ring_emit_tmz(ring, true);
4314
4315         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4316         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4317                 /* set load_global_config & load_global_uconfig */
4318                 dw2 |= 0x8001;
4319                 /* set load_cs_sh_regs */
4320                 dw2 |= 0x01000000;
4321                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4322                 dw2 |= 0x10002;
4323
4324                 /* set load_ce_ram if preamble presented */
4325                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4326                         dw2 |= 0x10000000;
4327         } else {
4328                 /* still load_ce_ram if this is the first time preamble presented
4329                  * although there is no context switch happens.
4330                  */
4331                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4332                         dw2 |= 0x10000000;
4333         }
4334
4335         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4336         amdgpu_ring_write(ring, dw2);
4337         amdgpu_ring_write(ring, 0);
4338 }
4339
4340 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4341 {
4342         unsigned ret;
4343         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4344         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4345         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4346         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4347         ret = ring->wptr & ring->buf_mask;
4348         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4349         return ret;
4350 }
4351
4352 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4353 {
4354         unsigned cur;
4355         BUG_ON(offset > ring->buf_mask);
4356         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4357
4358         cur = (ring->wptr & ring->buf_mask) - 1;
4359         if (likely(cur > offset))
4360                 ring->ring[offset] = cur - offset;
4361         else
4362                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4363 }
4364
4365 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4366 {
4367         struct amdgpu_device *adev = ring->adev;
4368
4369         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4370         amdgpu_ring_write(ring, 0 |     /* src: register*/
4371                                 (5 << 8) |      /* dst: memory */
4372                                 (1 << 20));     /* write confirm */
4373         amdgpu_ring_write(ring, reg);
4374         amdgpu_ring_write(ring, 0);
4375         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4376                                 adev->virt.reg_val_offs * 4));
4377         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4378                                 adev->virt.reg_val_offs * 4));
4379 }
4380
4381 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4382                                     uint32_t val)
4383 {
4384         uint32_t cmd = 0;
4385
4386         switch (ring->funcs->type) {
4387         case AMDGPU_RING_TYPE_GFX:
4388                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4389                 break;
4390         case AMDGPU_RING_TYPE_KIQ:
4391                 cmd = (1 << 16); /* no inc addr */
4392                 break;
4393         default:
4394                 cmd = WR_CONFIRM;
4395                 break;
4396         }
4397         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4398         amdgpu_ring_write(ring, cmd);
4399         amdgpu_ring_write(ring, reg);
4400         amdgpu_ring_write(ring, 0);
4401         amdgpu_ring_write(ring, val);
4402 }
4403
4404 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4405                                         uint32_t val, uint32_t mask)
4406 {
4407         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4408 }
4409
4410 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4411                                                   uint32_t reg0, uint32_t reg1,
4412                                                   uint32_t ref, uint32_t mask)
4413 {
4414         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4415         struct amdgpu_device *adev = ring->adev;
4416         bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
4417                 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
4418
4419         if (fw_version_ok)
4420                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4421                                       ref, mask, 0x20);
4422         else
4423                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4424                                                            ref, mask);
4425 }
4426
4427 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4428 {
4429         struct amdgpu_device *adev = ring->adev;
4430         uint32_t value = 0;
4431
4432         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4433         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4434         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4435         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4436         WREG32(mmSQ_CMD, value);
4437 }
4438
4439 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4440                                                  enum amdgpu_interrupt_state state)
4441 {
4442         switch (state) {
4443         case AMDGPU_IRQ_STATE_DISABLE:
4444         case AMDGPU_IRQ_STATE_ENABLE:
4445                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4446                                TIME_STAMP_INT_ENABLE,
4447                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4448                 break;
4449         default:
4450                 break;
4451         }
4452 }
4453
4454 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4455                                                      int me, int pipe,
4456                                                      enum amdgpu_interrupt_state state)
4457 {
4458         u32 mec_int_cntl, mec_int_cntl_reg;
4459
4460         /*
4461          * amdgpu controls only the first MEC. That's why this function only
4462          * handles the setting of interrupts for this specific MEC. All other
4463          * pipes' interrupts are set by amdkfd.
4464          */
4465
4466         if (me == 1) {
4467                 switch (pipe) {
4468                 case 0:
4469                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4470                         break;
4471                 case 1:
4472                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4473                         break;
4474                 case 2:
4475                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4476                         break;
4477                 case 3:
4478                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4479                         break;
4480                 default:
4481                         DRM_DEBUG("invalid pipe %d\n", pipe);
4482                         return;
4483                 }
4484         } else {
4485                 DRM_DEBUG("invalid me %d\n", me);
4486                 return;
4487         }
4488
4489         switch (state) {
4490         case AMDGPU_IRQ_STATE_DISABLE:
4491                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4492                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4493                                              TIME_STAMP_INT_ENABLE, 0);
4494                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4495                 break;
4496         case AMDGPU_IRQ_STATE_ENABLE:
4497                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4498                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4499                                              TIME_STAMP_INT_ENABLE, 1);
4500                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4501                 break;
4502         default:
4503                 break;
4504         }
4505 }
4506
4507 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4508                                              struct amdgpu_irq_src *source,
4509                                              unsigned type,
4510                                              enum amdgpu_interrupt_state state)
4511 {
4512         switch (state) {
4513         case AMDGPU_IRQ_STATE_DISABLE:
4514         case AMDGPU_IRQ_STATE_ENABLE:
4515                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4516                                PRIV_REG_INT_ENABLE,
4517                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4518                 break;
4519         default:
4520                 break;
4521         }
4522
4523         return 0;
4524 }
4525
4526 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4527                                               struct amdgpu_irq_src *source,
4528                                               unsigned type,
4529                                               enum amdgpu_interrupt_state state)
4530 {
4531         switch (state) {
4532         case AMDGPU_IRQ_STATE_DISABLE:
4533         case AMDGPU_IRQ_STATE_ENABLE:
4534                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4535                                PRIV_INSTR_INT_ENABLE,
4536                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4537         default:
4538                 break;
4539         }
4540
4541         return 0;
4542 }
4543
4544 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4545                                             struct amdgpu_irq_src *src,
4546                                             unsigned type,
4547                                             enum amdgpu_interrupt_state state)
4548 {
4549         switch (type) {
4550         case AMDGPU_CP_IRQ_GFX_EOP:
4551                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4552                 break;
4553         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4554                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4555                 break;
4556         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4557                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4558                 break;
4559         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4560                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4561                 break;
4562         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4563                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4564                 break;
4565         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4566                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4567                 break;
4568         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4569                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4570                 break;
4571         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4572                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4573                 break;
4574         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4575                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4576                 break;
4577         default:
4578                 break;
4579         }
4580         return 0;
4581 }
4582
4583 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4584                             struct amdgpu_irq_src *source,
4585                             struct amdgpu_iv_entry *entry)
4586 {
4587         int i;
4588         u8 me_id, pipe_id, queue_id;
4589         struct amdgpu_ring *ring;
4590
4591         DRM_DEBUG("IH: CP EOP\n");
4592         me_id = (entry->ring_id & 0x0c) >> 2;
4593         pipe_id = (entry->ring_id & 0x03) >> 0;
4594         queue_id = (entry->ring_id & 0x70) >> 4;
4595
4596         switch (me_id) {
4597         case 0:
4598                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4599                 break;
4600         case 1:
4601         case 2:
4602                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4603                         ring = &adev->gfx.compute_ring[i];
4604                         /* Per-queue interrupt is supported for MEC starting from VI.
4605                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4606                           */
4607                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4608                                 amdgpu_fence_process(ring);
4609                 }
4610                 break;
4611         }
4612         return 0;
4613 }
4614
4615 static void gfx_v9_0_fault(struct amdgpu_device *adev,
4616                            struct amdgpu_iv_entry *entry)
4617 {
4618         u8 me_id, pipe_id, queue_id;
4619         struct amdgpu_ring *ring;
4620         int i;
4621
4622         me_id = (entry->ring_id & 0x0c) >> 2;
4623         pipe_id = (entry->ring_id & 0x03) >> 0;
4624         queue_id = (entry->ring_id & 0x70) >> 4;
4625
4626         switch (me_id) {
4627         case 0:
4628                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4629                 break;
4630         case 1:
4631         case 2:
4632                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4633                         ring = &adev->gfx.compute_ring[i];
4634                         if (ring->me == me_id && ring->pipe == pipe_id &&
4635                             ring->queue == queue_id)
4636                                 drm_sched_fault(&ring->sched);
4637                 }
4638                 break;
4639         }
4640 }
4641
4642 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4643                                  struct amdgpu_irq_src *source,
4644                                  struct amdgpu_iv_entry *entry)
4645 {
4646         DRM_ERROR("Illegal register access in command stream\n");
4647         gfx_v9_0_fault(adev, entry);
4648         return 0;
4649 }
4650
4651 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4652                                   struct amdgpu_irq_src *source,
4653                                   struct amdgpu_iv_entry *entry)
4654 {
4655         DRM_ERROR("Illegal instruction in command stream\n");
4656         gfx_v9_0_fault(adev, entry);
4657         return 0;
4658 }
4659
4660 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4661         .name = "gfx_v9_0",
4662         .early_init = gfx_v9_0_early_init,
4663         .late_init = gfx_v9_0_late_init,
4664         .sw_init = gfx_v9_0_sw_init,
4665         .sw_fini = gfx_v9_0_sw_fini,
4666         .hw_init = gfx_v9_0_hw_init,
4667         .hw_fini = gfx_v9_0_hw_fini,
4668         .suspend = gfx_v9_0_suspend,
4669         .resume = gfx_v9_0_resume,
4670         .is_idle = gfx_v9_0_is_idle,
4671         .wait_for_idle = gfx_v9_0_wait_for_idle,
4672         .soft_reset = gfx_v9_0_soft_reset,
4673         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4674         .set_powergating_state = gfx_v9_0_set_powergating_state,
4675         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4676 };
4677
4678 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4679         .type = AMDGPU_RING_TYPE_GFX,
4680         .align_mask = 0xff,
4681         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4682         .support_64bit_ptrs = true,
4683         .vmhub = AMDGPU_GFXHUB,
4684         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4685         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4686         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4687         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4688                 5 +  /* COND_EXEC */
4689                 7 +  /* PIPELINE_SYNC */
4690                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4691                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4692                 2 + /* VM_FLUSH */
4693                 8 +  /* FENCE for VM_FLUSH */
4694                 20 + /* GDS switch */
4695                 4 + /* double SWITCH_BUFFER,
4696                        the first COND_EXEC jump to the place just
4697                            prior to this double SWITCH_BUFFER  */
4698                 5 + /* COND_EXEC */
4699                 7 +      /*     HDP_flush */
4700                 4 +      /*     VGT_flush */
4701                 14 + /* CE_META */
4702                 31 + /* DE_META */
4703                 3 + /* CNTX_CTRL */
4704                 5 + /* HDP_INVL */
4705                 8 + 8 + /* FENCE x2 */
4706                 2, /* SWITCH_BUFFER */
4707         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4708         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4709         .emit_fence = gfx_v9_0_ring_emit_fence,
4710         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4711         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4712         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4713         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4714         .test_ring = gfx_v9_0_ring_test_ring,
4715         .test_ib = gfx_v9_0_ring_test_ib,
4716         .insert_nop = amdgpu_ring_insert_nop,
4717         .pad_ib = amdgpu_ring_generic_pad_ib,
4718         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4719         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4720         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4721         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4722         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4723         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4724         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4725         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4726         .soft_recovery = gfx_v9_0_ring_soft_recovery,
4727 };
4728
4729 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4730         .type = AMDGPU_RING_TYPE_COMPUTE,
4731         .align_mask = 0xff,
4732         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4733         .support_64bit_ptrs = true,
4734         .vmhub = AMDGPU_GFXHUB,
4735         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4736         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4737         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4738         .emit_frame_size =
4739                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4740                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4741                 5 + /* hdp invalidate */
4742                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4743                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4744                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4745                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4746                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4747         .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
4748         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4749         .emit_fence = gfx_v9_0_ring_emit_fence,
4750         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4751         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4752         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4753         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4754         .test_ring = gfx_v9_0_ring_test_ring,
4755         .test_ib = gfx_v9_0_ring_test_ib,
4756         .insert_nop = amdgpu_ring_insert_nop,
4757         .pad_ib = amdgpu_ring_generic_pad_ib,
4758         .set_priority = gfx_v9_0_ring_set_priority_compute,
4759         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4760         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4761         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4762 };
4763
4764 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4765         .type = AMDGPU_RING_TYPE_KIQ,
4766         .align_mask = 0xff,
4767         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4768         .support_64bit_ptrs = true,
4769         .vmhub = AMDGPU_GFXHUB,
4770         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4771         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4772         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4773         .emit_frame_size =
4774                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4775                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4776                 5 + /* hdp invalidate */
4777                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4778                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4779                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4780                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4781                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4782         .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
4783         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4784         .test_ring = gfx_v9_0_ring_test_ring,
4785         .insert_nop = amdgpu_ring_insert_nop,
4786         .pad_ib = amdgpu_ring_generic_pad_ib,
4787         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4788         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4789         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4790         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4791 };
4792
4793 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4794 {
4795         int i;
4796
4797         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4798
4799         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4800                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4801
4802         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4803                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4804 }
4805
4806 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4807         .set = gfx_v9_0_set_eop_interrupt_state,
4808         .process = gfx_v9_0_eop_irq,
4809 };
4810
4811 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4812         .set = gfx_v9_0_set_priv_reg_fault_state,
4813         .process = gfx_v9_0_priv_reg_irq,
4814 };
4815
4816 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4817         .set = gfx_v9_0_set_priv_inst_fault_state,
4818         .process = gfx_v9_0_priv_inst_irq,
4819 };
4820
4821 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4822 {
4823         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4824         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4825
4826         adev->gfx.priv_reg_irq.num_types = 1;
4827         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4828
4829         adev->gfx.priv_inst_irq.num_types = 1;
4830         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4831 }
4832
4833 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4834 {
4835         switch (adev->asic_type) {
4836         case CHIP_VEGA10:
4837         case CHIP_VEGA12:
4838         case CHIP_VEGA20:
4839         case CHIP_RAVEN:
4840                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4841                 break;
4842         default:
4843                 break;
4844         }
4845 }
4846
4847 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4848 {
4849         /* init asci gds info */
4850         switch (adev->asic_type) {
4851         case CHIP_VEGA10:
4852         case CHIP_VEGA12:
4853         case CHIP_VEGA20:
4854                 adev->gds.mem.total_size = 0x10000;
4855                 break;
4856         case CHIP_RAVEN:
4857                 adev->gds.mem.total_size = 0x1000;
4858                 break;
4859         default:
4860                 adev->gds.mem.total_size = 0x10000;
4861                 break;
4862         }
4863
4864         switch (adev->asic_type) {
4865         case CHIP_VEGA10:
4866         case CHIP_VEGA20:
4867                 adev->gds.gds_compute_max_wave_id = 0x7ff;
4868                 break;
4869         case CHIP_VEGA12:
4870                 adev->gds.gds_compute_max_wave_id = 0x27f;
4871                 break;
4872         case CHIP_RAVEN:
4873                 if (adev->rev_id >= 0x8)
4874                         adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
4875                 else
4876                         adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
4877                 break;
4878         default:
4879                 /* this really depends on the chip */
4880                 adev->gds.gds_compute_max_wave_id = 0x7ff;
4881                 break;
4882         }
4883
4884         adev->gds.gws.total_size = 64;
4885         adev->gds.oa.total_size = 16;
4886
4887         if (adev->gds.mem.total_size == 64 * 1024) {
4888                 adev->gds.mem.gfx_partition_size = 4096;
4889                 adev->gds.mem.cs_partition_size = 4096;
4890
4891                 adev->gds.gws.gfx_partition_size = 4;
4892                 adev->gds.gws.cs_partition_size = 4;
4893
4894                 adev->gds.oa.gfx_partition_size = 4;
4895                 adev->gds.oa.cs_partition_size = 1;
4896         } else {
4897                 adev->gds.mem.gfx_partition_size = 1024;
4898                 adev->gds.mem.cs_partition_size = 1024;
4899
4900                 adev->gds.gws.gfx_partition_size = 16;
4901                 adev->gds.gws.cs_partition_size = 16;
4902
4903                 adev->gds.oa.gfx_partition_size = 4;
4904                 adev->gds.oa.cs_partition_size = 4;
4905         }
4906 }
4907
4908 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4909                                                  u32 bitmap)
4910 {
4911         u32 data;
4912
4913         if (!bitmap)
4914                 return;
4915
4916         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4917         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4918
4919         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4920 }
4921
4922 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4923 {
4924         u32 data, mask;
4925
4926         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4927         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4928
4929         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4930         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4931
4932         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4933
4934         return (~data) & mask;
4935 }
4936
4937 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4938                                  struct amdgpu_cu_info *cu_info)
4939 {
4940         int i, j, k, counter, active_cu_number = 0;
4941         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4942         unsigned disable_masks[4 * 2];
4943
4944         if (!adev || !cu_info)
4945                 return -EINVAL;
4946
4947         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4948
4949         mutex_lock(&adev->grbm_idx_mutex);
4950         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4951                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4952                         mask = 1;
4953                         ao_bitmap = 0;
4954                         counter = 0;
4955                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4956                         if (i < 4 && j < 2)
4957                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4958                                         adev, disable_masks[i * 2 + j]);
4959                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4960                         cu_info->bitmap[i][j] = bitmap;
4961
4962                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4963                                 if (bitmap & mask) {
4964                                         if (counter < adev->gfx.config.max_cu_per_sh)
4965                                                 ao_bitmap |= mask;
4966                                         counter ++;
4967                                 }
4968                                 mask <<= 1;
4969                         }
4970                         active_cu_number += counter;
4971                         if (i < 2 && j < 2)
4972                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4973                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4974                 }
4975         }
4976         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4977         mutex_unlock(&adev->grbm_idx_mutex);
4978
4979         cu_info->number = active_cu_number;
4980         cu_info->ao_cu_mask = ao_cu_mask;
4981         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4982
4983         return 0;
4984 }
4985
4986 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4987 {
4988         .type = AMD_IP_BLOCK_TYPE_GFX,
4989         .major = 9,
4990         .minor = 0,
4991         .rev = 0,
4992         .funcs = &gfx_v9_0_ip_funcs,
4993 };