drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 /* QLogic qed NIC Driver
   3  * Copyright (c) 2015-2017  QLogic Corporation
   4  * Copyright (c) 2019-2020 Marvell International Ltd.
   5  */
   6
   7 #include <linux/types.h>
   8 #include <asm/byteorder.h>
   9 #include <linux/delay.h>
  10 #include <linux/errno.h>
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/string.h>
  15 #include <linux/etherdevice.h>
  16 #include "qed.h"
  17 #include "qed_cxt.h"
  18 #include "qed_dcbx.h"
  19 #include "qed_hsi.h"
  20 #include "qed_mfw_hsi.h"
  21 #include "qed_hw.h"
  22 #include "qed_mcp.h"
  23 #include "qed_reg_addr.h"
  24 #include "qed_sriov.h"
  25
  26 #define GRCBASE_MCP     0xe00000
  27
  28 #define QED_MCP_RESP_ITER_US    10
  29
  30 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  31 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  32
  33 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  34         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)), \
  35                _val)
  36
  37 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  38         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)))
  39
  40 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  41         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  42                      offsetof(struct public_drv_mb, _field), _val)
  43
  44 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  45         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  46                      offsetof(struct public_drv_mb, _field))
  47
  48 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  49                   DRV_ID_PDA_COMP_VER_SHIFT)
  50
  51 #define MCP_BYTES_PER_MBIT_SHIFT 17
  52
  53 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  54 {
  55         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  56                 return false;
  57         return true;
  58 }
  59
  60 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  61 {
  62         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  63                                         PUBLIC_PORT);
  64         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  65
  66         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  67                                                    MFW_PORT(p_hwfn));
  68         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  69                    "port_addr = 0x%x, port_id 0x%02x\n",
  70                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  71 }
  72
  73 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  74 {
  75         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  76         u32 tmp, i;
  77
  78         if (!p_hwfn->mcp_info->public_base)
  79                 return;
  80
  81         for (i = 0; i < length; i++) {
  82                 tmp = qed_rd(p_hwfn, p_ptt,
  83                              p_hwfn->mcp_info->mfw_mb_addr +
  84                              (i << 2) + sizeof(u32));
  85
  86                 /* The MB data is actually BE; Need to force it to cpu */
  87                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  88                         be32_to_cpu((__force __be32)tmp);
  89         }
  90 }
  91
  92 struct qed_mcp_cmd_elem {
  93         struct list_head list;
  94         struct qed_mcp_mb_params *p_mb_params;
  95         u16 expected_seq_num;
  96         bool b_is_completed;
  97 };
  98
  99 /* Must be called while cmd_lock is acquired */
 100 static struct qed_mcp_cmd_elem *
 101 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 102                      struct qed_mcp_mb_params *p_mb_params,
 103                      u16 expected_seq_num)
 104 {
 105         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 106
 107         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 108         if (!p_cmd_elem)
 109                 goto out;
 110
 111         p_cmd_elem->p_mb_params = p_mb_params;
 112         p_cmd_elem->expected_seq_num = expected_seq_num;
 113         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 114 out:
 115         return p_cmd_elem;
 116 }
 117
 118 /* Must be called while cmd_lock is acquired */
 119 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 120                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 121 {
 122         list_del(&p_cmd_elem->list);
 123         kfree(p_cmd_elem);
 124 }
 125
 126 /* Must be called while cmd_lock is acquired */
 127 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 128                                                      u16 seq_num)
 129 {
 130         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 131
 132         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 133                 if (p_cmd_elem->expected_seq_num == seq_num)
 134                         return p_cmd_elem;
 135         }
 136
 137         return NULL;
 138 }
 139
 140 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 141 {
 142         if (p_hwfn->mcp_info) {
 143                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 144
 145                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 146                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 147
 148                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 149                 list_for_each_entry_safe(p_cmd_elem,
 150                                          p_tmp,
 151                                          &p_hwfn->mcp_info->cmd_list, list) {
 152                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 153                 }
 154                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 155         }
 156
 157         kfree(p_hwfn->mcp_info);
 158         p_hwfn->mcp_info = NULL;
 159
 160         return 0;
 161 }
 162
 163 /* Maximum of 1 sec to wait for the SHMEM ready indication */
 164 #define QED_MCP_SHMEM_RDY_MAX_RETRIES   20
 165 #define QED_MCP_SHMEM_RDY_ITER_MS       50
 166
 167 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 168 {
 169         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 170         u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES;
 171         u8 msec = QED_MCP_SHMEM_RDY_ITER_MS;
 172         u32 drv_mb_offsize, mfw_mb_offsize;
 173         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 174
 175         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 176         if (!p_info->public_base) {
 177                 DP_NOTICE(p_hwfn,
 178                           "The address of the MCP scratch-pad is not configured\n");
 179                 return -EINVAL;
 180         }
 181
 182         p_info->public_base |= GRCBASE_MCP;
 183
 184         /* Get the MFW MB address and number of supported messages */
 185         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 186                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 187                                                      PUBLIC_MFW_MB));
 188         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 189         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt,
 190                                             p_info->mfw_mb_addr +
 191                                             offsetof(struct public_mfw_mb,
 192                                                      sup_msgs));
 193
 194         /* The driver can notify that there was an MCP reset, and might read the
 195          * SHMEM values before the MFW has completed initializing them.
 196          * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a
 197          * data ready indication.
 198          */
 199         while (!p_info->mfw_mb_length && --cnt) {
 200                 msleep(msec);
 201                 p_info->mfw_mb_length =
 202                         (u16)qed_rd(p_hwfn, p_ptt,
 203                                     p_info->mfw_mb_addr +
 204                                     offsetof(struct public_mfw_mb, sup_msgs));
 205         }
 206
 207         if (!cnt) {
 208                 DP_NOTICE(p_hwfn,
 209                           "Failed to get the SHMEM ready notification after %d msec\n",
 210                           QED_MCP_SHMEM_RDY_MAX_RETRIES * msec);
 211                 return -EBUSY;
 212         }
 213
 214         /* Calculate the driver and MFW mailbox address */
 215         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 216                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 217                                                      PUBLIC_DRV_MB));
 218         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 219         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 220                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 221                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 222
 223         /* Get the current driver mailbox sequence before sending
 224          * the first command
 225          */
 226         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 227                              DRV_MSG_SEQ_NUMBER_MASK;
 228
 229         /* Get current FW pulse sequence */
 230         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 231                                 DRV_PULSE_SEQ_MASK;
 232
 233         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 234
 235         return 0;
 236 }
 237
 238 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 239 {
 240         struct qed_mcp_info *p_info;
 241         u32 size;
 242
 243         /* Allocate mcp_info structure */
 244         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 245         if (!p_hwfn->mcp_info)
 246                 goto err;
 247         p_info = p_hwfn->mcp_info;
 248
 249         /* Initialize the MFW spinlock */
 250         spin_lock_init(&p_info->cmd_lock);
 251         spin_lock_init(&p_info->link_lock);
 252
 253         INIT_LIST_HEAD(&p_info->cmd_list);
 254
 255         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 256                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 257                 /* Do not free mcp_info here, since public_base indicate that
 258                  * the MCP is not initialized
 259                  */
 260                 return 0;
 261         }
 262
 263         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 264         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 265         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 266         if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
 267                 goto err;
 268
 269         return 0;
 270
 271 err:
 272         qed_mcp_free(p_hwfn);
 273         return -ENOMEM;
 274 }
 275
 276 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 277                                    struct qed_ptt *p_ptt)
 278 {
 279         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 280
 281         /* Use MCP history register to check if MCP reset occurred between init
 282          * time and now.
 283          */
 284         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 285                 DP_VERBOSE(p_hwfn,
 286                            QED_MSG_SP,
 287                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 288                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 289
 290                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 291                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 292         }
 293 }
 294
 295 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 296 {
 297         u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0;
 298         int rc = 0;
 299
 300         if (p_hwfn->mcp_info->b_block_cmd) {
 301                 DP_NOTICE(p_hwfn,
 302                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 303                 return -EBUSY;
 304         }
 305
 306         /* Ensure that only a single thread is accessing the mailbox */
 307         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 308
 309         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 310
 311         /* Set drv command along with the updated sequence */
 312         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 313         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 314         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 315
 316         do {
 317                 /* Wait for MFW response */
 318                 udelay(delay);
 319                 /* Give the FW up to 500 second (50*1000*10usec) */
 320         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 321                                               MISCS_REG_GENERIC_POR_0)) &&
 322                  (cnt++ < QED_MCP_RESET_RETRIES));
 323
 324         if (org_mcp_reset_seq !=
 325             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 326                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 327                            "MCP was reset after %d usec\n", cnt * delay);
 328         } else {
 329                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 330                 rc = -EAGAIN;
 331         }
 332
 333         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 334
 335         return rc;
 336 }
 337
 338 /* Must be called while cmd_lock is acquired */
 339 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 340 {
 341         struct qed_mcp_cmd_elem *p_cmd_elem;
 342
 343         /* There is at most one pending command at a certain time, and if it
 344          * exists - it is placed at the HEAD of the list.
 345          */
 346         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 347                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 348                                               struct qed_mcp_cmd_elem, list);
 349                 return !p_cmd_elem->b_is_completed;
 350         }
 351
 352         return false;
 353 }
 354
 355 /* Must be called while cmd_lock is acquired */
 356 static int
 357 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 358 {
 359         struct qed_mcp_mb_params *p_mb_params;
 360         struct qed_mcp_cmd_elem *p_cmd_elem;
 361         u32 mcp_resp;
 362         u16 seq_num;
 363
 364         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 365         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 366
 367         /* Return if no new non-handled response has been received */
 368         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 369                 return -EAGAIN;
 370
 371         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 372         if (!p_cmd_elem) {
 373                 DP_ERR(p_hwfn,
 374                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 375                        seq_num);
 376                 return -EINVAL;
 377         }
 378
 379         p_mb_params = p_cmd_elem->p_mb_params;
 380
 381         /* Get the MFW response along with the sequence number */
 382         p_mb_params->mcp_resp = mcp_resp;
 383
 384         /* Get the MFW param */
 385         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 386
 387         /* Get the union data */
 388         if (p_mb_params->p_data_dst && p_mb_params->data_dst_size) {
 389                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 390                                       offsetof(struct public_drv_mb,
 391                                                union_data);
 392                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 393                                 union_data_addr, p_mb_params->data_dst_size);
 394         }
 395
 396         p_cmd_elem->b_is_completed = true;
 397
 398         return 0;
 399 }
 400
 401 /* Must be called while cmd_lock is acquired */
 402 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 403                                     struct qed_ptt *p_ptt,
 404                                     struct qed_mcp_mb_params *p_mb_params,
 405                                     u16 seq_num)
 406 {
 407         union drv_union_data union_data;
 408         u32 union_data_addr;
 409
 410         /* Set the union data */
 411         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 412                           offsetof(struct public_drv_mb, union_data);
 413         memset(&union_data, 0, sizeof(union_data));
 414         if (p_mb_params->p_data_src && p_mb_params->data_src_size)
 415                 memcpy(&union_data, p_mb_params->p_data_src,
 416                        p_mb_params->data_src_size);
 417         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 418                       sizeof(union_data));
 419
 420         /* Set the drv param */
 421         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 422
 423         /* Set the drv command along with the sequence number */
 424         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 425
 426         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 427                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 428                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 429 }
 430
 431 static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd)
 432 {
 433         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 434
 435         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 436                 block_cmd ? "Block" : "Unblock");
 437 }
 438
 439 static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn,
 440                                    struct qed_ptt *p_ptt)
 441 {
 442         u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2;
 443         u32 delay = QED_MCP_RESP_ITER_US;
 444
 445         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
 446         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
 447         cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 448         udelay(delay);
 449         cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 450         udelay(delay);
 451         cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 452
 453         DP_NOTICE(p_hwfn,
 454                   "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n",
 455                   cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2);
 456 }
 457
 458 static int
 459 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 460                        struct qed_ptt *p_ptt,
 461                        struct qed_mcp_mb_params *p_mb_params,
 462                        u32 max_retries, u32 usecs)
 463 {
 464         u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000);
 465         struct qed_mcp_cmd_elem *p_cmd_elem;
 466         u16 seq_num;
 467         int rc = 0;
 468
 469         /* Wait until the mailbox is non-occupied */
 470         do {
 471                 /* Exit the loop if there is no pending command, or if the
 472                  * pending command is completed during this iteration.
 473                  * The spinlock stays locked until the command is sent.
 474                  */
 475
 476                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 477
 478                 if (!qed_mcp_has_pending_cmd(p_hwfn))
 479                         break;
 480
 481                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 482                 if (!rc)
 483                         break;
 484                 else if (rc != -EAGAIN)
 485                         goto err;
 486
 487                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 488
 489                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 490                         msleep(msecs);
 491                 else
 492                         udelay(usecs);
 493         } while (++cnt < max_retries);
 494
 495         if (cnt >= max_retries) {
 496                 DP_NOTICE(p_hwfn,
 497                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 498                           p_mb_params->cmd, p_mb_params->param);
 499                 return -EAGAIN;
 500         }
 501
 502         /* Send the mailbox command */
 503         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 504         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 505         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 506         if (!p_cmd_elem) {
 507                 rc = -ENOMEM;
 508                 goto err;
 509         }
 510
 511         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 512         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 513
 514         /* Wait for the MFW response */
 515         do {
 516                 /* Exit the loop if the command is already completed, or if the
 517                  * command is completed during this iteration.
 518                  * The spinlock stays locked until the list element is removed.
 519                  */
 520
 521                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 522                         msleep(msecs);
 523                 else
 524                         udelay(usecs);
 525
 526                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 527
 528                 if (p_cmd_elem->b_is_completed)
 529                         break;
 530
 531                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 532                 if (!rc)
 533                         break;
 534                 else if (rc != -EAGAIN)
 535                         goto err;
 536
 537                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 538         } while (++cnt < max_retries);
 539
 540         if (cnt >= max_retries) {
 541                 DP_NOTICE(p_hwfn,
 542                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 543                           p_mb_params->cmd, p_mb_params->param);
 544                 qed_mcp_print_cpu_info(p_hwfn, p_ptt);
 545
 546                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 547                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 548                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 549
 550                 if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK))
 551                         qed_mcp_cmd_set_blocking(p_hwfn, true);
 552
 553                 qed_hw_err_notify(p_hwfn, p_ptt,
 554                                   QED_HW_ERR_MFW_RESP_FAIL, NULL);
 555                 return -EAGAIN;
 556         }
 557
 558         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 559         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 560
 561         DP_VERBOSE(p_hwfn,
 562                    QED_MSG_SP,
 563                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 564                    p_mb_params->mcp_resp,
 565                    p_mb_params->mcp_param,
 566                    (cnt * usecs) / 1000, (cnt * usecs) % 1000);
 567
 568         /* Clear the sequence number from the MFW response */
 569         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 570
 571         return 0;
 572
 573 err:
 574         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 575         return rc;
 576 }
 577
 578 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 579                                  struct qed_ptt *p_ptt,
 580                                  struct qed_mcp_mb_params *p_mb_params)
 581 {
 582         size_t union_data_size = sizeof(union drv_union_data);
 583         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 584         u32 usecs = QED_MCP_RESP_ITER_US;
 585
 586         /* MCP not initialized */
 587         if (!qed_mcp_is_init(p_hwfn)) {
 588                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 589                 return -EBUSY;
 590         }
 591
 592         if (p_hwfn->mcp_info->b_block_cmd) {
 593                 DP_NOTICE(p_hwfn,
 594                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 595                           p_mb_params->cmd, p_mb_params->param);
 596                 return -EBUSY;
 597         }
 598
 599         if (p_mb_params->data_src_size > union_data_size ||
 600             p_mb_params->data_dst_size > union_data_size) {
 601                 DP_ERR(p_hwfn,
 602                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 603                        p_mb_params->data_src_size,
 604                        p_mb_params->data_dst_size, union_data_size);
 605                 return -EINVAL;
 606         }
 607
 608         if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) {
 609                 max_retries = DIV_ROUND_UP(max_retries, 1000);
 610                 usecs *= 1000;
 611         }
 612
 613         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 614                                       usecs);
 615 }
 616
 617 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 618                 struct qed_ptt *p_ptt,
 619                 u32 cmd,
 620                 u32 param,
 621                 u32 *o_mcp_resp,
 622                 u32 *o_mcp_param)
 623 {
 624         struct qed_mcp_mb_params mb_params;
 625         int rc;
 626
 627         memset(&mb_params, 0, sizeof(mb_params));
 628         mb_params.cmd = cmd;
 629         mb_params.param = param;
 630
 631         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 632         if (rc)
 633                 return rc;
 634
 635         *o_mcp_resp = mb_params.mcp_resp;
 636         *o_mcp_param = mb_params.mcp_param;
 637
 638         return 0;
 639 }
 640
 641 static int
 642 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
 643                    struct qed_ptt *p_ptt,
 644                    u32 cmd,
 645                    u32 param,
 646                    u32 *o_mcp_resp,
 647                    u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
 648 {
 649         struct qed_mcp_mb_params mb_params;
 650         int rc;
 651
 652         memset(&mb_params, 0, sizeof(mb_params));
 653         mb_params.cmd = cmd;
 654         mb_params.param = param;
 655         mb_params.p_data_src = i_buf;
 656         mb_params.data_src_size = (u8)i_txn_size;
 657         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 658         if (rc)
 659                 return rc;
 660
 661         *o_mcp_resp = mb_params.mcp_resp;
 662         *o_mcp_param = mb_params.mcp_param;
 663
 664         /* nvm_info needs to be updated */
 665         p_hwfn->nvm_info.valid = false;
 666
 667         return 0;
 668 }
 669
 670 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 671                        struct qed_ptt *p_ptt,
 672                        u32 cmd,
 673                        u32 param,
 674                        u32 *o_mcp_resp,
 675                        u32 *o_mcp_param,
 676                        u32 *o_txn_size, u32 *o_buf, bool b_can_sleep)
 677 {
 678         struct qed_mcp_mb_params mb_params;
 679         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 680         int rc;
 681
 682         memset(&mb_params, 0, sizeof(mb_params));
 683         mb_params.cmd = cmd;
 684         mb_params.param = param;
 685         mb_params.p_data_dst = raw_data;
 686
 687         /* Use the maximal value since the actual one is part of the response */
 688         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 689         if (b_can_sleep)
 690                 mb_params.flags = QED_MB_FLAG_CAN_SLEEP;
 691
 692         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 693         if (rc)
 694                 return rc;
 695
 696         *o_mcp_resp = mb_params.mcp_resp;
 697         *o_mcp_param = mb_params.mcp_param;
 698
 699         *o_txn_size = *o_mcp_param;
 700         memcpy(o_buf, raw_data, *o_txn_size);
 701
 702         return 0;
 703 }
 704
 705 static bool
 706 qed_mcp_can_force_load(u8 drv_role,
 707                        u8 exist_drv_role,
 708                        enum qed_override_force_load override_force_load)
 709 {
 710         bool can_force_load = false;
 711
 712         switch (override_force_load) {
 713         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 714                 can_force_load = true;
 715                 break;
 716         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 717                 can_force_load = false;
 718                 break;
 719         default:
 720                 can_force_load = (drv_role == DRV_ROLE_OS &&
 721                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 722                                  (drv_role == DRV_ROLE_KDUMP &&
 723                                   exist_drv_role == DRV_ROLE_OS);
 724                 break;
 725         }
 726
 727         return can_force_load;
 728 }
 729
 730 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 731                                    struct qed_ptt *p_ptt)
 732 {
 733         u32 resp = 0, param = 0;
 734         int rc;
 735
 736         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 737                          &resp, &param);
 738         if (rc)
 739                 DP_NOTICE(p_hwfn,
 740                           "Failed to send cancel load request, rc = %d\n", rc);
 741
 742         return rc;
 743 }
 744
 745 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 746 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 747 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 748 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 749 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 750 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 751
 752 static u32 qed_get_config_bitmap(void)
 753 {
 754         u32 config_bitmap = 0x0;
 755
 756         if (IS_ENABLED(CONFIG_QEDE))
 757                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 758
 759         if (IS_ENABLED(CONFIG_QED_SRIOV))
 760                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 761
 762         if (IS_ENABLED(CONFIG_QED_RDMA))
 763                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 764
 765         if (IS_ENABLED(CONFIG_QED_FCOE))
 766                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 767
 768         if (IS_ENABLED(CONFIG_QED_ISCSI))
 769                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 770
 771         if (IS_ENABLED(CONFIG_QED_LL2))
 772                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 773
 774         return config_bitmap;
 775 }
 776
 777 struct qed_load_req_in_params {
 778         u8 hsi_ver;
 779 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 780 #define QED_LOAD_REQ_HSI_VER_1          1
 781         u32 drv_ver_0;
 782         u32 drv_ver_1;
 783         u32 fw_ver;
 784         u8 drv_role;
 785         u8 timeout_val;
 786         u8 force_cmd;
 787         bool avoid_eng_reset;
 788 };
 789
 790 struct qed_load_req_out_params {
 791         u32 load_code;
 792         u32 exist_drv_ver_0;
 793         u32 exist_drv_ver_1;
 794         u32 exist_fw_ver;
 795         u8 exist_drv_role;
 796         u8 mfw_hsi_ver;
 797         bool drv_exists;
 798 };
 799
 800 static int
 801 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 802                    struct qed_ptt *p_ptt,
 803                    struct qed_load_req_in_params *p_in_params,
 804                    struct qed_load_req_out_params *p_out_params)
 805 {
 806         struct qed_mcp_mb_params mb_params;
 807         struct load_req_stc load_req;
 808         struct load_rsp_stc load_rsp;
 809         u32 hsi_ver;
 810         int rc;
 811
 812         memset(&load_req, 0, sizeof(load_req));
 813         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 814         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 815         load_req.fw_ver = p_in_params->fw_ver;
 816         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 817         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 818                           p_in_params->timeout_val);
 819         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 820                           p_in_params->force_cmd);
 821         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 822                           p_in_params->avoid_eng_reset);
 823
 824         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 825                   DRV_ID_MCP_HSI_VER_CURRENT :
 826                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 827
 828         memset(&mb_params, 0, sizeof(mb_params));
 829         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 830         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 831         mb_params.p_data_src = &load_req;
 832         mb_params.data_src_size = sizeof(load_req);
 833         mb_params.p_data_dst = &load_rsp;
 834         mb_params.data_dst_size = sizeof(load_rsp);
 835         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
 836
 837         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 838                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 839                    mb_params.param,
 840                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 841                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 842                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 843                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 844
 845         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 846                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 847                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 848                            load_req.drv_ver_0,
 849                            load_req.drv_ver_1,
 850                            load_req.fw_ver,
 851                            load_req.misc0,
 852                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 853                            QED_MFW_GET_FIELD(load_req.misc0,
 854                                              LOAD_REQ_LOCK_TO),
 855                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 856                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 857         }
 858
 859         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 860         if (rc) {
 861                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 862                 return rc;
 863         }
 864
 865         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 866                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 867         p_out_params->load_code = mb_params.mcp_resp;
 868
 869         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 870             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 871                 DP_VERBOSE(p_hwfn,
 872                            QED_MSG_SP,
 873                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 874                            load_rsp.drv_ver_0,
 875                            load_rsp.drv_ver_1,
 876                            load_rsp.fw_ver,
 877                            load_rsp.misc0,
 878                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 879                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 880                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 881
 882                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 883                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 884                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 885                 p_out_params->exist_drv_role =
 886                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 887                 p_out_params->mfw_hsi_ver =
 888                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 889                 p_out_params->drv_exists =
 890                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 891                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 898                                   enum qed_drv_role drv_role,
 899                                   u8 *p_mfw_drv_role)
 900 {
 901         switch (drv_role) {
 902         case QED_DRV_ROLE_OS:
 903                 *p_mfw_drv_role = DRV_ROLE_OS;
 904                 break;
 905         case QED_DRV_ROLE_KDUMP:
 906                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 907                 break;
 908         default:
 909                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 910                 return -EINVAL;
 911         }
 912
 913         return 0;
 914 }
 915
 916 enum qed_load_req_force {
 917         QED_LOAD_REQ_FORCE_NONE,
 918         QED_LOAD_REQ_FORCE_PF,
 919         QED_LOAD_REQ_FORCE_ALL,
 920 };
 921
 922 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 923                                   enum qed_load_req_force force_cmd,
 924                                   u8 *p_mfw_force_cmd)
 925 {
 926         switch (force_cmd) {
 927         case QED_LOAD_REQ_FORCE_NONE:
 928                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 929                 break;
 930         case QED_LOAD_REQ_FORCE_PF:
 931                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 932                 break;
 933         case QED_LOAD_REQ_FORCE_ALL:
 934                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 935                 break;
 936         }
 937 }
 938
 939 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 940                      struct qed_ptt *p_ptt,
 941                      struct qed_load_req_params *p_params)
 942 {
 943         struct qed_load_req_out_params out_params;
 944         struct qed_load_req_in_params in_params;
 945         u8 mfw_drv_role, mfw_force_cmd;
 946         int rc;
 947
 948         memset(&in_params, 0, sizeof(in_params));
 949         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 950         in_params.drv_ver_1 = qed_get_config_bitmap();
 951         in_params.fw_ver = STORM_FW_VERSION;
 952         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 953         if (rc)
 954                 return rc;
 955
 956         in_params.drv_role = mfw_drv_role;
 957         in_params.timeout_val = p_params->timeout_val;
 958         qed_get_mfw_force_cmd(p_hwfn,
 959                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 960
 961         in_params.force_cmd = mfw_force_cmd;
 962         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 963
 964         memset(&out_params, 0, sizeof(out_params));
 965         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 966         if (rc)
 967                 return rc;
 968
 969         /* First handle cases where another load request should/might be sent:
 970          * - MFW expects the old interface [HSI version = 1]
 971          * - MFW responds that a force load request is required
 972          */
 973         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 974                 DP_INFO(p_hwfn,
 975                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
 976
 977                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
 978                 memset(&out_params, 0, sizeof(out_params));
 979                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 980                 if (rc)
 981                         return rc;
 982         } else if (out_params.load_code ==
 983                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 984                 if (qed_mcp_can_force_load(in_params.drv_role,
 985                                            out_params.exist_drv_role,
 986                                            p_params->override_force_load)) {
 987                         DP_INFO(p_hwfn,
 988                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
 989                                 in_params.drv_role, in_params.fw_ver,
 990                                 in_params.drv_ver_0, in_params.drv_ver_1,
 991                                 out_params.exist_drv_role,
 992                                 out_params.exist_fw_ver,
 993                                 out_params.exist_drv_ver_0,
 994                                 out_params.exist_drv_ver_1);
 995
 996                         qed_get_mfw_force_cmd(p_hwfn,
 997                                               QED_LOAD_REQ_FORCE_ALL,
 998                                               &mfw_force_cmd);
 999
1000                         in_params.force_cmd = mfw_force_cmd;
1001                         memset(&out_params, 0, sizeof(out_params));
1002                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
1003                                                 &out_params);
1004                         if (rc)
1005                                 return rc;
1006                 } else {
1007                         DP_NOTICE(p_hwfn,
1008                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1009                                   in_params.drv_role, in_params.fw_ver,
1010                                   in_params.drv_ver_0, in_params.drv_ver_1,
1011                                   out_params.exist_drv_role,
1012                                   out_params.exist_fw_ver,
1013                                   out_params.exist_drv_ver_0,
1014                                   out_params.exist_drv_ver_1);
1015                         DP_NOTICE(p_hwfn,
1016                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
1017
1018                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
1019                         return -EBUSY;
1020                 }
1021         }
1022
1023         /* Now handle the other types of responses.
1024          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1025          * expected here after the additional revised load requests were sent.
1026          */
1027         switch (out_params.load_code) {
1028         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1029         case FW_MSG_CODE_DRV_LOAD_PORT:
1030         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1031                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
1032                     out_params.drv_exists) {
1033                         /* The role and fw/driver version match, but the PF is
1034                          * already loaded and has not been unloaded gracefully.
1035                          */
1036                         DP_NOTICE(p_hwfn,
1037                                   "PF is already loaded\n");
1038                         return -EINVAL;
1039                 }
1040                 break;
1041         default:
1042                 DP_NOTICE(p_hwfn,
1043                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1044                           out_params.load_code);
1045                 return -EBUSY;
1046         }
1047
1048         p_params->load_code = out_params.load_code;
1049
1050         return 0;
1051 }
1052
1053 int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1054 {
1055         u32 resp = 0, param = 0;
1056         int rc;
1057
1058         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1059                          &param);
1060         if (rc) {
1061                 DP_NOTICE(p_hwfn,
1062                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1063                 return rc;
1064         }
1065
1066         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1067         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1068                 DP_NOTICE(p_hwfn,
1069                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1070
1071         return 0;
1072 }
1073
1074 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1075 {
1076         struct qed_mcp_mb_params mb_params;
1077         u32 wol_param;
1078
1079         switch (p_hwfn->cdev->wol_config) {
1080         case QED_OV_WOL_DISABLED:
1081                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
1082                 break;
1083         case QED_OV_WOL_ENABLED:
1084                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
1085                 break;
1086         default:
1087                 DP_NOTICE(p_hwfn,
1088                           "Unknown WoL configuration %02x\n",
1089                           p_hwfn->cdev->wol_config);
1090                 fallthrough;
1091         case QED_OV_WOL_DEFAULT:
1092                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1093         }
1094
1095         memset(&mb_params, 0, sizeof(mb_params));
1096         mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ;
1097         mb_params.param = wol_param;
1098         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
1099
1100         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1101 }
1102
1103 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1104 {
1105         struct qed_mcp_mb_params mb_params;
1106         struct mcp_mac wol_mac;
1107
1108         memset(&mb_params, 0, sizeof(mb_params));
1109         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1110
1111         /* Set the primary MAC if WoL is enabled */
1112         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1113                 u8 *p_mac = p_hwfn->cdev->wol_mac;
1114
1115                 memset(&wol_mac, 0, sizeof(wol_mac));
1116                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1117                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1118                                     p_mac[4] << 8 | p_mac[5];
1119
1120                 DP_VERBOSE(p_hwfn,
1121                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
1122                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1123                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1124
1125                 mb_params.p_data_src = &wol_mac;
1126                 mb_params.data_src_size = sizeof(wol_mac);
1127         }
1128
1129         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1130 }
1131
1132 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1133                                   struct qed_ptt *p_ptt)
1134 {
1135         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1136                                         PUBLIC_PATH);
1137         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1138         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1139                                      QED_PATH_ID(p_hwfn));
1140         u32 disabled_vfs[VF_MAX_STATIC / 32];
1141         int i;
1142
1143         DP_VERBOSE(p_hwfn,
1144                    QED_MSG_SP,
1145                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1146                    mfw_path_offsize, path_addr);
1147
1148         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1149                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1150                                          path_addr +
1151                                          offsetof(struct public_path,
1152                                                   mcp_vf_disabled) +
1153                                          sizeof(u32) * i);
1154                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1155                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1156                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1157         }
1158
1159         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1160                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1161 }
1162
1163 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1164                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1165 {
1166         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1167                                         PUBLIC_FUNC);
1168         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1169         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1170                                      MCP_PF_ID(p_hwfn));
1171         struct qed_mcp_mb_params mb_params;
1172         int rc;
1173         int i;
1174
1175         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1176                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1177                            "Acking VFs [%08x,...,%08x] - %08x\n",
1178                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1179
1180         memset(&mb_params, 0, sizeof(mb_params));
1181         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1182         mb_params.p_data_src = vfs_to_ack;
1183         mb_params.data_src_size = VF_MAX_STATIC / 8;
1184         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1185         if (rc) {
1186                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1187                 return -EBUSY;
1188         }
1189
1190         /* Clear the ACK bits */
1191         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1192                 qed_wr(p_hwfn, p_ptt,
1193                        func_addr +
1194                        offsetof(struct public_func, drv_ack_vf_disabled) +
1195                        i * sizeof(u32), 0);
1196
1197         return rc;
1198 }
1199
1200 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1201                                               struct qed_ptt *p_ptt)
1202 {
1203         u32 transceiver_state;
1204
1205         transceiver_state = qed_rd(p_hwfn, p_ptt,
1206                                    p_hwfn->mcp_info->port_addr +
1207                                    offsetof(struct public_port,
1208                                             transceiver_data));
1209
1210         DP_VERBOSE(p_hwfn,
1211                    (NETIF_MSG_HW | QED_MSG_SP),
1212                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1213                    transceiver_state,
1214                    (u32)(p_hwfn->mcp_info->port_addr +
1215                           offsetof(struct public_port, transceiver_data)));
1216
1217         transceiver_state = GET_FIELD(transceiver_state,
1218                                       ETH_TRANSCEIVER_STATE);
1219
1220         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1221                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1222         else
1223                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1224 }
1225
1226 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1227                                     struct qed_ptt *p_ptt,
1228                                     struct qed_mcp_link_state *p_link)
1229 {
1230         u32 eee_status, val;
1231
1232         p_link->eee_adv_caps = 0;
1233         p_link->eee_lp_adv_caps = 0;
1234         eee_status = qed_rd(p_hwfn,
1235                             p_ptt,
1236                             p_hwfn->mcp_info->port_addr +
1237                             offsetof(struct public_port, eee_status));
1238         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1239         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1240         if (val & EEE_1G_ADV)
1241                 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1242         if (val & EEE_10G_ADV)
1243                 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1244         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1245         if (val & EEE_1G_ADV)
1246                 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1247         if (val & EEE_10G_ADV)
1248                 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1249 }
1250
1251 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1252                                   struct qed_ptt *p_ptt,
1253                                   struct public_func *p_data, int pfid)
1254 {
1255         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1256                                         PUBLIC_FUNC);
1257         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1258         u32 func_addr;
1259         u32 i, size;
1260
1261         func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1262         memset(p_data, 0, sizeof(*p_data));
1263
1264         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1265         for (i = 0; i < size / sizeof(u32); i++)
1266                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1267                                             func_addr + (i << 2));
1268         return size;
1269 }
1270
1271 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1272                                   struct public_func *p_shmem_info)
1273 {
1274         struct qed_mcp_function_info *p_info;
1275
1276         p_info = &p_hwfn->mcp_info->func_info;
1277
1278         p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config,
1279                                                   FUNC_MF_CFG_MIN_BW);
1280         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1281                 DP_INFO(p_hwfn,
1282                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1283                         p_info->bandwidth_min);
1284                 p_info->bandwidth_min = 1;
1285         }
1286
1287         p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config,
1288                                                   FUNC_MF_CFG_MAX_BW);
1289         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1290                 DP_INFO(p_hwfn,
1291                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1292                         p_info->bandwidth_max);
1293                 p_info->bandwidth_max = 100;
1294         }
1295 }
1296
1297 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1298                                        struct qed_ptt *p_ptt, bool b_reset)
1299 {
1300         struct qed_mcp_link_state *p_link;
1301         u8 max_bw, min_bw;
1302         u32 status = 0;
1303
1304         /* Prevent SW/attentions from doing this at the same time */
1305         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1306
1307         p_link = &p_hwfn->mcp_info->link_output;
1308         memset(p_link, 0, sizeof(*p_link));
1309         if (!b_reset) {
1310                 status = qed_rd(p_hwfn, p_ptt,
1311                                 p_hwfn->mcp_info->port_addr +
1312                                 offsetof(struct public_port, link_status));
1313                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1314                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1315                            status,
1316                            (u32)(p_hwfn->mcp_info->port_addr +
1317                                  offsetof(struct public_port, link_status)));
1318         } else {
1319                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1320                            "Resetting link indications\n");
1321                 goto out;
1322         }
1323
1324         if (p_hwfn->b_drv_link_init) {
1325                 /* Link indication with modern MFW arrives as per-PF
1326                  * indication.
1327                  */
1328                 if (p_hwfn->mcp_info->capabilities &
1329                     FW_MB_PARAM_FEATURE_SUPPORT_VLINK) {
1330                         struct public_func shmem_info;
1331
1332                         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1333                                                MCP_PF_ID(p_hwfn));
1334                         p_link->link_up = !!(shmem_info.status &
1335                                              FUNC_STATUS_VIRTUAL_LINK_UP);
1336                         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1337                         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1338                                    "Virtual link_up = %d\n", p_link->link_up);
1339                 } else {
1340                         p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1341                         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1342                                    "Physical link_up = %d\n", p_link->link_up);
1343                 }
1344         } else {
1345                 p_link->link_up = false;
1346         }
1347
1348         p_link->full_duplex = true;
1349         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1350         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1351                 p_link->speed = 100000;
1352                 break;
1353         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1354                 p_link->speed = 50000;
1355                 break;
1356         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1357                 p_link->speed = 40000;
1358                 break;
1359         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1360                 p_link->speed = 25000;
1361                 break;
1362         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1363                 p_link->speed = 20000;
1364                 break;
1365         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1366                 p_link->speed = 10000;
1367                 break;
1368         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1369                 p_link->full_duplex = false;
1370                 fallthrough;
1371         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1372                 p_link->speed = 1000;
1373                 break;
1374         default:
1375                 p_link->speed = 0;
1376                 p_link->link_up = 0;
1377         }
1378
1379         if (p_link->link_up && p_link->speed)
1380                 p_link->line_speed = p_link->speed;
1381         else
1382                 p_link->line_speed = 0;
1383
1384         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1385         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1386
1387         /* Max bandwidth configuration */
1388         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1389
1390         /* Min bandwidth configuration */
1391         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1392         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1393                                             p_link->min_pf_rate);
1394
1395         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1396         p_link->an_complete = !!(status &
1397                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1398         p_link->parallel_detection = !!(status &
1399                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1400         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1401
1402         p_link->partner_adv_speed |=
1403                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1404                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1405         p_link->partner_adv_speed |=
1406                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1407                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1408         p_link->partner_adv_speed |=
1409                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1410                 QED_LINK_PARTNER_SPEED_10G : 0;
1411         p_link->partner_adv_speed |=
1412                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1413                 QED_LINK_PARTNER_SPEED_20G : 0;
1414         p_link->partner_adv_speed |=
1415                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1416                 QED_LINK_PARTNER_SPEED_25G : 0;
1417         p_link->partner_adv_speed |=
1418                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1419                 QED_LINK_PARTNER_SPEED_40G : 0;
1420         p_link->partner_adv_speed |=
1421                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1422                 QED_LINK_PARTNER_SPEED_50G : 0;
1423         p_link->partner_adv_speed |=
1424                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1425                 QED_LINK_PARTNER_SPEED_100G : 0;
1426
1427         p_link->partner_tx_flow_ctrl_en =
1428                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1429         p_link->partner_rx_flow_ctrl_en =
1430                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1431
1432         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1433         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1434                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1435                 break;
1436         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1437                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1438                 break;
1439         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1440                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1441                 break;
1442         default:
1443                 p_link->partner_adv_pause = 0;
1444         }
1445
1446         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1447
1448         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1449                 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1450
1451         if (p_hwfn->mcp_info->capabilities &
1452             FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) {
1453                 switch (status & LINK_STATUS_FEC_MODE_MASK) {
1454                 case LINK_STATUS_FEC_MODE_NONE:
1455                         p_link->fec_active = QED_FEC_MODE_NONE;
1456                         break;
1457                 case LINK_STATUS_FEC_MODE_FIRECODE_CL74:
1458                         p_link->fec_active = QED_FEC_MODE_FIRECODE;
1459                         break;
1460                 case LINK_STATUS_FEC_MODE_RS_CL91:
1461                         p_link->fec_active = QED_FEC_MODE_RS;
1462                         break;
1463                 default:
1464                         p_link->fec_active = QED_FEC_MODE_AUTO;
1465                 }
1466         } else {
1467                 p_link->fec_active = QED_FEC_MODE_UNSUPPORTED;
1468         }
1469
1470         qed_link_update(p_hwfn, p_ptt);
1471 out:
1472         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1473 }
1474
1475 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1476 {
1477         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1478         struct qed_mcp_mb_params mb_params;
1479         struct eth_phy_cfg phy_cfg;
1480         u32 cmd, fec_bit = 0;
1481         u32 val, ext_speed;
1482         int rc = 0;
1483
1484         /* Set the shmem configuration according to params */
1485         memset(&phy_cfg, 0, sizeof(phy_cfg));
1486         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1487         if (!params->speed.autoneg)
1488                 phy_cfg.speed = params->speed.forced_speed;
1489         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1490         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1491         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1492         phy_cfg.adv_speed = params->speed.advertised_speeds;
1493         phy_cfg.loopback_mode = params->loopback_mode;
1494
1495         /* There are MFWs that share this capability regardless of whether
1496          * this is feasible or not. And given that at the very least adv_caps
1497          * would be set internally by qed, we want to make sure LFA would
1498          * still work.
1499          */
1500         if ((p_hwfn->mcp_info->capabilities &
1501              FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) {
1502                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1503                 if (params->eee.tx_lpi_enable)
1504                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1505                 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1506                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1507                 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1508                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1509                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1510                                     EEE_TX_TIMER_USEC_OFFSET) &
1511                                    EEE_TX_TIMER_USEC_MASK;
1512         }
1513
1514         if (p_hwfn->mcp_info->capabilities &
1515             FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) {
1516                 if (params->fec & QED_FEC_MODE_NONE)
1517                         fec_bit |= FEC_FORCE_MODE_NONE;
1518                 else if (params->fec & QED_FEC_MODE_FIRECODE)
1519                         fec_bit |= FEC_FORCE_MODE_FIRECODE;
1520                 else if (params->fec & QED_FEC_MODE_RS)
1521                         fec_bit |= FEC_FORCE_MODE_RS;
1522                 else if (params->fec & QED_FEC_MODE_AUTO)
1523                         fec_bit |= FEC_FORCE_MODE_AUTO;
1524
1525                 SET_MFW_FIELD(phy_cfg.fec_mode, FEC_FORCE_MODE, fec_bit);
1526         }
1527
1528         if (p_hwfn->mcp_info->capabilities &
1529             FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) {
1530                 ext_speed = 0;
1531                 if (params->ext_speed.autoneg)
1532                         ext_speed |= ETH_EXT_SPEED_NONE;
1533
1534                 val = params->ext_speed.forced_speed;
1535                 if (val & QED_EXT_SPEED_1G)
1536                         ext_speed |= ETH_EXT_SPEED_1G;
1537                 if (val & QED_EXT_SPEED_10G)
1538                         ext_speed |= ETH_EXT_SPEED_10G;
1539                 if (val & QED_EXT_SPEED_25G)
1540                         ext_speed |= ETH_EXT_SPEED_25G;
1541                 if (val & QED_EXT_SPEED_40G)
1542                         ext_speed |= ETH_EXT_SPEED_40G;
1543                 if (val & QED_EXT_SPEED_50G_R)
1544                         ext_speed |= ETH_EXT_SPEED_50G_BASE_R;
1545                 if (val & QED_EXT_SPEED_50G_R2)
1546                         ext_speed |= ETH_EXT_SPEED_50G_BASE_R2;
1547                 if (val & QED_EXT_SPEED_100G_R2)
1548                         ext_speed |= ETH_EXT_SPEED_100G_BASE_R2;
1549                 if (val & QED_EXT_SPEED_100G_R4)
1550                         ext_speed |= ETH_EXT_SPEED_100G_BASE_R4;
1551                 if (val & QED_EXT_SPEED_100G_P4)
1552                         ext_speed |= ETH_EXT_SPEED_100G_BASE_P4;
1553
1554                 SET_MFW_FIELD(phy_cfg.extended_speed, ETH_EXT_SPEED,
1555                               ext_speed);
1556
1557                 ext_speed = 0;
1558
1559                 val = params->ext_speed.advertised_speeds;
1560                 if (val & QED_EXT_SPEED_MASK_1G)
1561                         ext_speed |= ETH_EXT_ADV_SPEED_1G;
1562                 if (val & QED_EXT_SPEED_MASK_10G)
1563                         ext_speed |= ETH_EXT_ADV_SPEED_10G;
1564                 if (val & QED_EXT_SPEED_MASK_25G)
1565                         ext_speed |= ETH_EXT_ADV_SPEED_25G;
1566                 if (val & QED_EXT_SPEED_MASK_40G)
1567                         ext_speed |= ETH_EXT_ADV_SPEED_40G;
1568                 if (val & QED_EXT_SPEED_MASK_50G_R)
1569                         ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R;
1570                 if (val & QED_EXT_SPEED_MASK_50G_R2)
1571                         ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R2;
1572                 if (val & QED_EXT_SPEED_MASK_100G_R2)
1573                         ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R2;
1574                 if (val & QED_EXT_SPEED_MASK_100G_R4)
1575                         ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R4;
1576                 if (val & QED_EXT_SPEED_MASK_100G_P4)
1577                         ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_P4;
1578
1579                 phy_cfg.extended_speed |= ext_speed;
1580
1581                 SET_MFW_FIELD(phy_cfg.fec_mode, FEC_EXTENDED_MODE,
1582                               params->ext_fec_mode);
1583         }
1584
1585         p_hwfn->b_drv_link_init = b_up;
1586
1587         if (b_up) {
1588                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1589                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, Adv. Speed 0x%08x, Loopback 0x%08x, FEC 0x%08x, Ext. Speed 0x%08x\n",
1590                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1591                            phy_cfg.loopback_mode, phy_cfg.fec_mode,
1592                            phy_cfg.extended_speed);
1593         } else {
1594                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, "Resetting link\n");
1595         }
1596
1597         memset(&mb_params, 0, sizeof(mb_params));
1598         mb_params.cmd = cmd;
1599         mb_params.p_data_src = &phy_cfg;
1600         mb_params.data_src_size = sizeof(phy_cfg);
1601         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1602
1603         /* if mcp fails to respond we must abort */
1604         if (rc) {
1605                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1606                 return rc;
1607         }
1608
1609         /* Mimic link-change attention, done for several reasons:
1610          *  - On reset, there's no guarantee MFW would trigger
1611          *    an attention.
1612          *  - On initialization, older MFWs might not indicate link change
1613          *    during LFA, so we'll never get an UP indication.
1614          */
1615         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1616
1617         return 0;
1618 }
1619
1620 u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn,
1621                                  struct qed_ptt *p_ptt)
1622 {
1623         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1624
1625         if (IS_VF(p_hwfn->cdev))
1626                 return -EINVAL;
1627
1628         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1629                                                  PUBLIC_PATH);
1630         path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr);
1631         path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn));
1632
1633         proc_kill_cnt = qed_rd(p_hwfn, p_ptt,
1634                                path_addr +
1635                                offsetof(struct public_path, process_kill)) &
1636                         PROCESS_KILL_COUNTER_MASK;
1637
1638         return proc_kill_cnt;
1639 }
1640
1641 static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn,
1642                                         struct qed_ptt *p_ptt)
1643 {
1644         struct qed_dev *cdev = p_hwfn->cdev;
1645         u32 proc_kill_cnt;
1646
1647         /* Prevent possible attentions/interrupts during the recovery handling
1648          * and till its load phase, during which they will be re-enabled.
1649          */
1650         qed_int_igu_disable_int(p_hwfn, p_ptt);
1651
1652         DP_NOTICE(p_hwfn, "Received a process kill indication\n");
1653
1654         /* The following operations should be done once, and thus in CMT mode
1655          * are carried out by only the first HW function.
1656          */
1657         if (p_hwfn != QED_LEADING_HWFN(cdev))
1658                 return;
1659
1660         if (cdev->recov_in_prog) {
1661                 DP_NOTICE(p_hwfn,
1662                           "Ignoring the indication since a recovery process is already in progress\n");
1663                 return;
1664         }
1665
1666         cdev->recov_in_prog = true;
1667
1668         proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt);
1669         DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt);
1670
1671         qed_schedule_recovery_handler(p_hwfn);
1672 }
1673
1674 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1675                                         struct qed_ptt *p_ptt,
1676                                         enum MFW_DRV_MSG_TYPE type)
1677 {
1678         enum qed_mcp_protocol_type stats_type;
1679         union qed_mcp_protocol_stats stats;
1680         struct qed_mcp_mb_params mb_params;
1681         u32 hsi_param;
1682
1683         switch (type) {
1684         case MFW_DRV_MSG_GET_LAN_STATS:
1685                 stats_type = QED_MCP_LAN_STATS;
1686                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1687                 break;
1688         case MFW_DRV_MSG_GET_FCOE_STATS:
1689                 stats_type = QED_MCP_FCOE_STATS;
1690                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1691                 break;
1692         case MFW_DRV_MSG_GET_ISCSI_STATS:
1693                 stats_type = QED_MCP_ISCSI_STATS;
1694                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1695                 break;
1696         case MFW_DRV_MSG_GET_RDMA_STATS:
1697                 stats_type = QED_MCP_RDMA_STATS;
1698                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1699                 break;
1700         default:
1701                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1702                 return;
1703         }
1704
1705         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1706
1707         memset(&mb_params, 0, sizeof(mb_params));
1708         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1709         mb_params.param = hsi_param;
1710         mb_params.p_data_src = &stats;
1711         mb_params.data_src_size = sizeof(stats);
1712         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1713 }
1714
1715 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1716 {
1717         struct qed_mcp_function_info *p_info;
1718         struct public_func shmem_info;
1719         u32 resp = 0, param = 0;
1720
1721         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1722
1723         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1724
1725         p_info = &p_hwfn->mcp_info->func_info;
1726
1727         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1728         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1729
1730         /* Acknowledge the MFW */
1731         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1732                     &param);
1733 }
1734
1735 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1736 {
1737         struct public_func shmem_info;
1738         u32 resp = 0, param = 0;
1739
1740         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1741
1742         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1743                                                  FUNC_MF_CFG_OV_STAG_MASK;
1744         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1745         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) {
1746                 if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) {
1747                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
1748                                p_hwfn->hw_info.ovlan);
1749                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
1750
1751                         /* Configure DB to add external vlan to EDPM packets */
1752                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
1753                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
1754                                p_hwfn->hw_info.ovlan);
1755                 } else {
1756                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
1757                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
1758                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
1759                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
1760                 }
1761
1762                 qed_sp_pf_update_stag(p_hwfn);
1763         }
1764
1765         DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n",
1766                    p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
1767
1768         /* Acknowledge the MFW */
1769         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1770                     &resp, &param);
1771 }
1772
1773 static void qed_mcp_handle_fan_failure(struct qed_hwfn *p_hwfn,
1774                                        struct qed_ptt *p_ptt)
1775 {
1776         /* A single notification should be sent to upper driver in CMT mode */
1777         if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev))
1778                 return;
1779
1780         qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_FAN_FAIL,
1781                           "Fan failure was detected on the network interface card and it's going to be shut down.\n");
1782 }
1783
1784 struct qed_mdump_cmd_params {
1785         u32 cmd;
1786         void *p_data_src;
1787         u8 data_src_size;
1788         void *p_data_dst;
1789         u8 data_dst_size;
1790         u32 mcp_resp;
1791 };
1792
1793 static int
1794 qed_mcp_mdump_cmd(struct qed_hwfn *p_hwfn,
1795                   struct qed_ptt *p_ptt,
1796                   struct qed_mdump_cmd_params *p_mdump_cmd_params)
1797 {
1798         struct qed_mcp_mb_params mb_params;
1799         int rc;
1800
1801         memset(&mb_params, 0, sizeof(mb_params));
1802         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1803         mb_params.param = p_mdump_cmd_params->cmd;
1804         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1805         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1806         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1807         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1808         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1809         if (rc)
1810                 return rc;
1811
1812         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1813
1814         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1815                 DP_INFO(p_hwfn,
1816                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1817                         p_mdump_cmd_params->cmd);
1818                 rc = -EOPNOTSUPP;
1819         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1820                 DP_INFO(p_hwfn,
1821                         "The mdump command is not supported by the MFW\n");
1822                 rc = -EOPNOTSUPP;
1823         }
1824
1825         return rc;
1826 }
1827
1828 static int qed_mcp_mdump_ack(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1829 {
1830         struct qed_mdump_cmd_params mdump_cmd_params;
1831
1832         memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params));
1833         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1834
1835         return qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1836 }
1837
1838 int
1839 qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn,
1840                          struct qed_ptt *p_ptt,
1841                          struct mdump_retain_data_stc *p_mdump_retain)
1842 {
1843         struct qed_mdump_cmd_params mdump_cmd_params;
1844         int rc;
1845
1846         memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params));
1847         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1848         mdump_cmd_params.p_data_dst = p_mdump_retain;
1849         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_retain);
1850
1851         rc = qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1852         if (rc)
1853                 return rc;
1854
1855         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1856                 DP_INFO(p_hwfn,
1857                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1858                         mdump_cmd_params.mcp_resp);
1859                 return -EINVAL;
1860         }
1861
1862         return 0;
1863 }
1864
1865 static void qed_mcp_handle_critical_error(struct qed_hwfn *p_hwfn,
1866                                           struct qed_ptt *p_ptt)
1867 {
1868         struct mdump_retain_data_stc mdump_retain;
1869         int rc;
1870
1871         /* In CMT mode - no need for more than a single acknowledgment to the
1872          * MFW, and no more than a single notification to the upper driver.
1873          */
1874         if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev))
1875                 return;
1876
1877         rc = qed_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1878         if (rc == 0 && mdump_retain.valid)
1879                 DP_NOTICE(p_hwfn,
1880                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1881                           mdump_retain.epoch,
1882                           mdump_retain.pf, mdump_retain.status);
1883         else
1884                 DP_NOTICE(p_hwfn,
1885                           "The MFW notified that a critical error occurred in the device\n");
1886
1887         DP_NOTICE(p_hwfn,
1888                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1889         qed_mcp_mdump_ack(p_hwfn, p_ptt);
1890
1891         qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_HW_ATTN, NULL);
1892 }
1893
1894 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1895 {
1896         struct public_func shmem_info;
1897         u32 port_cfg, val;
1898
1899         if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1900                 return;
1901
1902         memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1903         port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1904                           offsetof(struct public_port, oem_cfg_port));
1905         val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >>
1906                 OEM_CFG_CHANNEL_TYPE_OFFSET;
1907         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1908                 DP_NOTICE(p_hwfn,
1909                           "Incorrect UFP Channel type  %d port_id 0x%02x\n",
1910                           val, MFW_PORT(p_hwfn));
1911
1912         val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET;
1913         if (val == OEM_CFG_SCHED_TYPE_ETS) {
1914                 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS;
1915         } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) {
1916                 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW;
1917         } else {
1918                 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN;
1919                 DP_NOTICE(p_hwfn,
1920                           "Unknown UFP scheduling mode %d port_id 0x%02x\n",
1921                           val, MFW_PORT(p_hwfn));
1922         }
1923
1924         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1925         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >>
1926                 OEM_CFG_FUNC_TC_OFFSET;
1927         p_hwfn->ufp_info.tc = (u8)val;
1928         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >>
1929                 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET;
1930         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) {
1931                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC;
1932         } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) {
1933                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS;
1934         } else {
1935                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN;
1936                 DP_NOTICE(p_hwfn,
1937                           "Unknown Host priority control %d port_id 0x%02x\n",
1938                           val, MFW_PORT(p_hwfn));
1939         }
1940
1941         DP_NOTICE(p_hwfn,
1942                   "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n",
1943                   p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1944                   p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn));
1945 }
1946
1947 static int
1948 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1949 {
1950         qed_mcp_read_ufp_config(p_hwfn, p_ptt);
1951
1952         if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) {
1953                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1954                 qed_hw_info_set_offload_tc(&p_hwfn->hw_info,
1955                                            p_hwfn->ufp_info.tc);
1956
1957                 qed_qm_reconf(p_hwfn, p_ptt);
1958         } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) {
1959                 /* Merge UFP TC with the dcbx TC data */
1960                 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1961                                           QED_DCBX_OPERATIONAL_MIB);
1962         } else {
1963                 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n");
1964                 return -EINVAL;
1965         }
1966
1967         /* update storm FW with negotiation results */
1968         qed_sp_pf_update_ufp(p_hwfn);
1969
1970         /* update stag pcp value */
1971         qed_sp_pf_update_stag(p_hwfn);
1972
1973         return 0;
1974 }
1975
1976 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1977                           struct qed_ptt *p_ptt)
1978 {
1979         struct qed_mcp_info *info = p_hwfn->mcp_info;
1980         int rc = 0;
1981         bool found = false;
1982         u16 i;
1983
1984         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1985
1986         /* Read Messages from MFW */
1987         qed_mcp_read_mb(p_hwfn, p_ptt);
1988
1989         /* Compare current messages to old ones */
1990         for (i = 0; i < info->mfw_mb_length; i++) {
1991                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1992                         continue;
1993
1994                 found = true;
1995
1996                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1997                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1998                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1999
2000                 switch (i) {
2001                 case MFW_DRV_MSG_LINK_CHANGE:
2002                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
2003                         break;
2004                 case MFW_DRV_MSG_VF_DISABLED:
2005                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
2006                         break;
2007                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
2008                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
2009                                                   QED_DCBX_REMOTE_LLDP_MIB);
2010                         break;
2011                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
2012                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
2013                                                   QED_DCBX_REMOTE_MIB);
2014                         break;
2015                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
2016                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
2017                                                   QED_DCBX_OPERATIONAL_MIB);
2018                         break;
2019                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
2020                         qed_mcp_handle_ufp_event(p_hwfn, p_ptt);
2021                         break;
2022                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
2023                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
2024                         break;
2025                 case MFW_DRV_MSG_ERROR_RECOVERY:
2026                         qed_mcp_handle_process_kill(p_hwfn, p_ptt);
2027                         break;
2028                 case MFW_DRV_MSG_GET_LAN_STATS:
2029                 case MFW_DRV_MSG_GET_FCOE_STATS:
2030                 case MFW_DRV_MSG_GET_ISCSI_STATS:
2031                 case MFW_DRV_MSG_GET_RDMA_STATS:
2032                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
2033                         break;
2034                 case MFW_DRV_MSG_BW_UPDATE:
2035                         qed_mcp_update_bw(p_hwfn, p_ptt);
2036                         break;
2037                 case MFW_DRV_MSG_S_TAG_UPDATE:
2038                         qed_mcp_update_stag(p_hwfn, p_ptt);
2039                         break;
2040                 case MFW_DRV_MSG_FAILURE_DETECTED:
2041                         qed_mcp_handle_fan_failure(p_hwfn, p_ptt);
2042                         break;
2043                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
2044                         qed_mcp_handle_critical_error(p_hwfn, p_ptt);
2045                         break;
2046                 case MFW_DRV_MSG_GET_TLV_REQ:
2047                         qed_mfw_tlv_req(p_hwfn);
2048                         break;
2049                 default:
2050                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
2051                         rc = -EINVAL;
2052                 }
2053         }
2054
2055         /* ACK everything */
2056         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2057                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
2058
2059                 /* MFW expect answer in BE, so we force write in that format */
2060                 qed_wr(p_hwfn, p_ptt,
2061                        info->mfw_mb_addr + sizeof(u32) +
2062                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2063                        sizeof(u32) + i * sizeof(u32),
2064                        (__force u32)val);
2065         }
2066
2067         if (!found) {
2068                 DP_NOTICE(p_hwfn,
2069                           "Received an MFW message indication but no new message!\n");
2070                 rc = -EINVAL;
2071         }
2072
2073         /* Copy the new mfw messages into the shadow */
2074         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2075
2076         return rc;
2077 }
2078
2079 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
2080                         struct qed_ptt *p_ptt,
2081                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
2082 {
2083         u32 global_offsize, public_base;
2084
2085         if (IS_VF(p_hwfn->cdev)) {
2086                 if (p_hwfn->vf_iov_info) {
2087                         struct pfvf_acquire_resp_tlv *p_resp;
2088
2089                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2090                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2091                         return 0;
2092                 } else {
2093                         DP_VERBOSE(p_hwfn,
2094                                    QED_MSG_IOV,
2095                                    "VF requested MFW version prior to ACQUIRE\n");
2096                         return -EINVAL;
2097                 }
2098         }
2099
2100         public_base = p_hwfn->mcp_info->public_base;
2101         global_offsize = qed_rd(p_hwfn, p_ptt,
2102                                 SECTION_OFFSIZE_ADDR(public_base,
2103                                                      PUBLIC_GLOBAL));
2104         *p_mfw_ver =
2105             qed_rd(p_hwfn, p_ptt,
2106                    SECTION_ADDR(global_offsize,
2107                                 0) + offsetof(struct public_global, mfw_ver));
2108
2109         if (p_running_bundle_id) {
2110                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
2111                                               SECTION_ADDR(global_offsize, 0) +
2112                                               offsetof(struct public_global,
2113                                                        running_bundle_id));
2114         }
2115
2116         return 0;
2117 }
2118
2119 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
2120                         struct qed_ptt *p_ptt, u32 *p_mbi_ver)
2121 {
2122         u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
2123
2124         if (IS_VF(p_hwfn->cdev))
2125                 return -EINVAL;
2126
2127         /* Read the address of the nvm_cfg */
2128         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2129         if (!nvm_cfg_addr) {
2130                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2131                 return -EINVAL;
2132         }
2133
2134         /* Read the offset of nvm_cfg1 */
2135         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2136
2137         mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2138                        offsetof(struct nvm_cfg1, glob) +
2139                        offsetof(struct nvm_cfg1_glob, mbi_version);
2140         *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
2141                             mbi_ver_addr) &
2142                      (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
2143                       NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
2144                       NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
2145
2146         return 0;
2147 }
2148
2149 int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn,
2150                            struct qed_ptt *p_ptt, u32 *p_media_type)
2151 {
2152         *p_media_type = MEDIA_UNSPECIFIED;
2153
2154         if (IS_VF(p_hwfn->cdev))
2155                 return -EINVAL;
2156
2157         if (!qed_mcp_is_init(p_hwfn)) {
2158                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
2159                 return -EBUSY;
2160         }
2161
2162         if (!p_ptt) {
2163                 *p_media_type = MEDIA_UNSPECIFIED;
2164                 return -EINVAL;
2165         }
2166
2167         *p_media_type = qed_rd(p_hwfn, p_ptt,
2168                                p_hwfn->mcp_info->port_addr +
2169                                offsetof(struct public_port,
2170                                         media_type));
2171
2172         return 0;
2173 }
2174
2175 int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn,
2176                                  struct qed_ptt *p_ptt,
2177                                  u32 *p_transceiver_state,
2178                                  u32 *p_transceiver_type)
2179 {
2180         u32 transceiver_info;
2181
2182         *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE;
2183         *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING;
2184
2185         if (IS_VF(p_hwfn->cdev))
2186                 return -EINVAL;
2187
2188         if (!qed_mcp_is_init(p_hwfn)) {
2189                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
2190                 return -EBUSY;
2191         }
2192
2193         transceiver_info = qed_rd(p_hwfn, p_ptt,
2194                                   p_hwfn->mcp_info->port_addr +
2195                                   offsetof(struct public_port,
2196                                            transceiver_data));
2197
2198         *p_transceiver_state = (transceiver_info &
2199                                 ETH_TRANSCEIVER_STATE_MASK) >>
2200                                 ETH_TRANSCEIVER_STATE_OFFSET;
2201
2202         if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
2203                 *p_transceiver_type = (transceiver_info &
2204                                        ETH_TRANSCEIVER_TYPE_MASK) >>
2205                                        ETH_TRANSCEIVER_TYPE_OFFSET;
2206         else
2207                 *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN;
2208
2209         return 0;
2210 }
2211
2212 static bool qed_is_transceiver_ready(u32 transceiver_state,
2213                                      u32 transceiver_type)
2214 {
2215         if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) &&
2216             ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) &&
2217             (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE))
2218                 return true;
2219
2220         return false;
2221 }
2222
2223 int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn,
2224                              struct qed_ptt *p_ptt, u32 *p_speed_mask)
2225 {
2226         u32 transceiver_type, transceiver_state;
2227         int ret;
2228
2229         ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state,
2230                                            &transceiver_type);
2231         if (ret)
2232                 return ret;
2233
2234         if (qed_is_transceiver_ready(transceiver_state, transceiver_type) ==
2235                                      false)
2236                 return -EINVAL;
2237
2238         switch (transceiver_type) {
2239         case ETH_TRANSCEIVER_TYPE_1G_LX:
2240         case ETH_TRANSCEIVER_TYPE_1G_SX:
2241         case ETH_TRANSCEIVER_TYPE_1G_PCC:
2242         case ETH_TRANSCEIVER_TYPE_1G_ACC:
2243         case ETH_TRANSCEIVER_TYPE_1000BASET:
2244                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2245                 break;
2246         case ETH_TRANSCEIVER_TYPE_10G_SR:
2247         case ETH_TRANSCEIVER_TYPE_10G_LR:
2248         case ETH_TRANSCEIVER_TYPE_10G_LRM:
2249         case ETH_TRANSCEIVER_TYPE_10G_ER:
2250         case ETH_TRANSCEIVER_TYPE_10G_PCC:
2251         case ETH_TRANSCEIVER_TYPE_10G_ACC:
2252         case ETH_TRANSCEIVER_TYPE_4x10G:
2253                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2254                 break;
2255         case ETH_TRANSCEIVER_TYPE_40G_LR4:
2256         case ETH_TRANSCEIVER_TYPE_40G_SR4:
2257         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
2258         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
2259                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2260                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2261                 break;
2262         case ETH_TRANSCEIVER_TYPE_100G_AOC:
2263         case ETH_TRANSCEIVER_TYPE_100G_SR4:
2264         case ETH_TRANSCEIVER_TYPE_100G_LR4:
2265         case ETH_TRANSCEIVER_TYPE_100G_ER4:
2266         case ETH_TRANSCEIVER_TYPE_100G_ACC:
2267                 *p_speed_mask =
2268                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2269                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2270                 break;
2271         case ETH_TRANSCEIVER_TYPE_25G_SR:
2272         case ETH_TRANSCEIVER_TYPE_25G_LR:
2273         case ETH_TRANSCEIVER_TYPE_25G_AOC:
2274         case ETH_TRANSCEIVER_TYPE_25G_ACC_S:
2275         case ETH_TRANSCEIVER_TYPE_25G_ACC_M:
2276         case ETH_TRANSCEIVER_TYPE_25G_ACC_L:
2277                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2278                 break;
2279         case ETH_TRANSCEIVER_TYPE_25G_CA_N:
2280         case ETH_TRANSCEIVER_TYPE_25G_CA_S:
2281         case ETH_TRANSCEIVER_TYPE_25G_CA_L:
2282         case ETH_TRANSCEIVER_TYPE_4x25G_CR:
2283                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2284                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2285                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2286                 break;
2287         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
2288         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR:
2289                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2290                                 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2291                 break;
2292         case ETH_TRANSCEIVER_TYPE_40G_CR4:
2293         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
2294                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2295                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2296                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2297                 break;
2298         case ETH_TRANSCEIVER_TYPE_100G_CR4:
2299         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
2300                 *p_speed_mask =
2301                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2302                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G |
2303                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2304                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2305                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G |
2306                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2307                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2308                 break;
2309         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
2310         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
2311         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC:
2312                 *p_speed_mask =
2313                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2314                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2315                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2316                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2317                 break;
2318         case ETH_TRANSCEIVER_TYPE_XLPPI:
2319                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
2320                 break;
2321         case ETH_TRANSCEIVER_TYPE_10G_BASET:
2322         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
2323         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
2324                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2325                                 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2326                 break;
2327         default:
2328                 DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n",
2329                         transceiver_type);
2330                 *p_speed_mask = 0xff;
2331                 break;
2332         }
2333
2334         return 0;
2335 }
2336
2337 int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn,
2338                              struct qed_ptt *p_ptt, u32 *p_board_config)
2339 {
2340         u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr;
2341
2342         if (IS_VF(p_hwfn->cdev))
2343                 return -EINVAL;
2344
2345         if (!qed_mcp_is_init(p_hwfn)) {
2346                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
2347                 return -EBUSY;
2348         }
2349         if (!p_ptt) {
2350                 *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
2351                 return -EINVAL;
2352         }
2353
2354         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2355         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2356         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2357                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2358         *p_board_config = qed_rd(p_hwfn, p_ptt,
2359                                  port_cfg_addr +
2360                                  offsetof(struct nvm_cfg1_port,
2361                                           board_cfg));
2362
2363         return 0;
2364 }
2365
2366 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2367 static void
2368 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
2369                                enum qed_pci_personality *p_proto)
2370 {
2371         /* There wasn't ever a legacy MFW that published iwarp.
2372          * So at this point, this is either plain l2 or RoCE.
2373          */
2374         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
2375                 *p_proto = QED_PCI_ETH_ROCE;
2376         else
2377                 *p_proto = QED_PCI_ETH;
2378
2379         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
2380                    "According to Legacy capabilities, L2 personality is %08x\n",
2381                    (u32)*p_proto);
2382 }
2383
2384 static int
2385 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
2386                             struct qed_ptt *p_ptt,
2387                             enum qed_pci_personality *p_proto)
2388 {
2389         u32 resp = 0, param = 0;
2390         int rc;
2391
2392         rc = qed_mcp_cmd(p_hwfn, p_ptt,
2393                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
2394         if (rc)
2395                 return rc;
2396         if (resp != FW_MSG_CODE_OK) {
2397                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
2398                            "MFW lacks support for command; Returns %08x\n",
2399                            resp);
2400                 return -EINVAL;
2401         }
2402
2403         switch (param) {
2404         case FW_MB_PARAM_GET_PF_RDMA_NONE:
2405                 *p_proto = QED_PCI_ETH;
2406                 break;
2407         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
2408                 *p_proto = QED_PCI_ETH_ROCE;
2409                 break;
2410         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
2411                 *p_proto = QED_PCI_ETH_IWARP;
2412                 break;
2413         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
2414                 *p_proto = QED_PCI_ETH_RDMA;
2415                 break;
2416         default:
2417                 DP_NOTICE(p_hwfn,
2418                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
2419                           param);
2420                 return -EINVAL;
2421         }
2422
2423         DP_VERBOSE(p_hwfn,
2424                    NETIF_MSG_IFUP,
2425                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2426                    (u32)*p_proto, resp, param);
2427         return 0;
2428 }
2429
2430 static int
2431 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
2432                         struct public_func *p_info,
2433                         struct qed_ptt *p_ptt,
2434                         enum qed_pci_personality *p_proto)
2435 {
2436         int rc = 0;
2437
2438         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2439         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2440                 if (!IS_ENABLED(CONFIG_QED_RDMA))
2441                         *p_proto = QED_PCI_ETH;
2442                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
2443                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2444                 break;
2445         case FUNC_MF_CFG_PROTOCOL_ISCSI:
2446                 *p_proto = QED_PCI_ISCSI;
2447                 break;
2448         case FUNC_MF_CFG_PROTOCOL_FCOE:
2449                 *p_proto = QED_PCI_FCOE;
2450                 break;
2451         case FUNC_MF_CFG_PROTOCOL_ROCE:
2452                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
2453                 fallthrough;
2454         default:
2455                 rc = -EINVAL;
2456         }
2457
2458         return rc;
2459 }
2460
2461 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
2462                                  struct qed_ptt *p_ptt)
2463 {
2464         struct qed_mcp_function_info *info;
2465         struct public_func shmem_info;
2466
2467         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2468         info = &p_hwfn->mcp_info->func_info;
2469
2470         info->pause_on_host = (shmem_info.config &
2471                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2472
2473         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2474                                     &info->protocol)) {
2475                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2476                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2477                 return -EINVAL;
2478         }
2479
2480         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
2481
2482         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2483                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2484                 info->mac[1] = (u8)(shmem_info.mac_upper);
2485                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2486                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2487                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2488                 info->mac[5] = (u8)(shmem_info.mac_lower);
2489
2490                 /* Store primary MAC for later possible WoL */
2491                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
2492         } else {
2493                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
2494         }
2495
2496         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
2497                          (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
2498         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
2499                          (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
2500
2501         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2502
2503         info->mtu = (u16)shmem_info.mtu_size;
2504
2505         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
2506         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
2507         if (qed_mcp_is_init(p_hwfn)) {
2508                 u32 resp = 0, param = 0;
2509                 int rc;
2510
2511                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
2512                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
2513                 if (rc)
2514                         return rc;
2515                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
2516                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
2517         }
2518
2519         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
2520                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %pM wwn port %llx node %llx ovlan %04x wol %02x\n",
2521                 info->pause_on_host, info->protocol,
2522                 info->bandwidth_min, info->bandwidth_max,
2523                 info->mac,
2524                 info->wwn_port, info->wwn_node,
2525                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
2526
2527         return 0;
2528 }
2529
2530 struct qed_mcp_link_params
2531 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
2532 {
2533         if (!p_hwfn || !p_hwfn->mcp_info)
2534                 return NULL;
2535         return &p_hwfn->mcp_info->link_input;
2536 }
2537
2538 struct qed_mcp_link_state
2539 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
2540 {
2541         if (!p_hwfn || !p_hwfn->mcp_info)
2542                 return NULL;
2543         return &p_hwfn->mcp_info->link_output;
2544 }
2545
2546 struct qed_mcp_link_capabilities
2547 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
2548 {
2549         if (!p_hwfn || !p_hwfn->mcp_info)
2550                 return NULL;
2551         return &p_hwfn->mcp_info->link_capabilities;
2552 }
2553
2554 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2555 {
2556         u32 resp = 0, param = 0;
2557         int rc;
2558
2559         rc = qed_mcp_cmd(p_hwfn, p_ptt,
2560                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2561
2562         /* Wait for the drain to complete before returning */
2563         msleep(1020);
2564
2565         return rc;
2566 }
2567
2568 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
2569                            struct qed_ptt *p_ptt, u32 *p_flash_size)
2570 {
2571         u32 flash_size;
2572
2573         if (IS_VF(p_hwfn->cdev))
2574                 return -EINVAL;
2575
2576         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2577         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2578                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2579         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2580
2581         *p_flash_size = flash_size;
2582
2583         return 0;
2584 }
2585
2586 int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2587 {
2588         struct qed_dev *cdev = p_hwfn->cdev;
2589
2590         if (cdev->recov_in_prog) {
2591                 DP_NOTICE(p_hwfn,
2592                           "Avoid triggering a recovery since such a process is already in progress\n");
2593                 return -EAGAIN;
2594         }
2595
2596         DP_NOTICE(p_hwfn, "Triggering a recovery process\n");
2597         qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2598
2599         return 0;
2600 }
2601
2602 #define QED_RECOVERY_PROLOG_SLEEP_MS    100
2603
2604 int qed_recovery_prolog(struct qed_dev *cdev)
2605 {
2606         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2607         struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
2608         int rc;
2609
2610         /* Allow ongoing PCIe transactions to complete */
2611         msleep(QED_RECOVERY_PROLOG_SLEEP_MS);
2612
2613         /* Clear the PF's internal FID_enable in the PXP */
2614         rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2615         if (rc)
2616                 DP_NOTICE(p_hwfn,
2617                           "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
2618                           rc);
2619
2620         return rc;
2621 }
2622
2623 static int
2624 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
2625                           struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2626 {
2627         u32 resp = 0, param = 0, rc_param = 0;
2628         int rc;
2629
2630         /* Only Leader can configure MSIX, and need to take CMT into account */
2631         if (!IS_LEAD_HWFN(p_hwfn))
2632                 return 0;
2633         num *= p_hwfn->cdev->num_hwfns;
2634
2635         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2636                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2637         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2638                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2639
2640         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2641                          &resp, &rc_param);
2642
2643         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2644                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
2645                 rc = -EINVAL;
2646         } else {
2647                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2648                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2649                            num, vf_id);
2650         }
2651
2652         return rc;
2653 }
2654
2655 static int
2656 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
2657                           struct qed_ptt *p_ptt, u8 num)
2658 {
2659         u32 resp = 0, param = num, rc_param = 0;
2660         int rc;
2661
2662         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2663                          param, &resp, &rc_param);
2664
2665         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2666                 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
2667                 rc = -EINVAL;
2668         } else {
2669                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2670                            "Requested 0x%02x MSI-x interrupts for VFs\n", num);
2671         }
2672
2673         return rc;
2674 }
2675
2676 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
2677                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2678 {
2679         if (QED_IS_BB(p_hwfn->cdev))
2680                 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2681         else
2682                 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2683 }
2684
2685 int
2686 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
2687                          struct qed_ptt *p_ptt,
2688                          struct qed_mcp_drv_version *p_ver)
2689 {
2690         struct qed_mcp_mb_params mb_params;
2691         struct drv_version_stc drv_version;
2692         __be32 val;
2693         u32 i;
2694         int rc;
2695
2696         memset(&drv_version, 0, sizeof(drv_version));
2697         drv_version.version = p_ver->version;
2698         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
2699                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
2700                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
2701         }
2702
2703         memset(&mb_params, 0, sizeof(mb_params));
2704         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2705         mb_params.p_data_src = &drv_version;
2706         mb_params.data_src_size = sizeof(drv_version);
2707         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2708         if (rc)
2709                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2710
2711         return rc;
2712 }
2713
2714 /* A maximal 100 msec waiting time for the MCP to halt */
2715 #define QED_MCP_HALT_SLEEP_MS           10
2716 #define QED_MCP_HALT_MAX_RETRIES        10
2717
2718 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2719 {
2720         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2721         int rc;
2722
2723         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2724                          &param);
2725         if (rc) {
2726                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2727                 return rc;
2728         }
2729
2730         do {
2731                 msleep(QED_MCP_HALT_SLEEP_MS);
2732                 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2733                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2734                         break;
2735         } while (++cnt < QED_MCP_HALT_MAX_RETRIES);
2736
2737         if (cnt == QED_MCP_HALT_MAX_RETRIES) {
2738                 DP_NOTICE(p_hwfn,
2739                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2740                           qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2741                 return -EBUSY;
2742         }
2743
2744         qed_mcp_cmd_set_blocking(p_hwfn, true);
2745
2746         return 0;
2747 }
2748
2749 #define QED_MCP_RESUME_SLEEP_MS 10
2750
2751 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2752 {
2753         u32 cpu_mode, cpu_state;
2754
2755         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2756
2757         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2758         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2759         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2760         msleep(QED_MCP_RESUME_SLEEP_MS);
2761         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2762
2763         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2764                 DP_NOTICE(p_hwfn,
2765                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2766                           cpu_mode, cpu_state);
2767                 return -EBUSY;
2768         }
2769
2770         qed_mcp_cmd_set_blocking(p_hwfn, false);
2771
2772         return 0;
2773 }
2774
2775 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2776                                      struct qed_ptt *p_ptt,
2777                                      enum qed_ov_client client)
2778 {
2779         u32 resp = 0, param = 0;
2780         u32 drv_mb_param;
2781         int rc;
2782
2783         switch (client) {
2784         case QED_OV_CLIENT_DRV:
2785                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2786                 break;
2787         case QED_OV_CLIENT_USER:
2788                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2789                 break;
2790         case QED_OV_CLIENT_VENDOR_SPEC:
2791                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2792                 break;
2793         default:
2794                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2795                 return -EINVAL;
2796         }
2797
2798         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2799                          drv_mb_param, &resp, &param);
2800         if (rc)
2801                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2802
2803         return rc;
2804 }
2805
2806 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2807                                    struct qed_ptt *p_ptt,
2808                                    enum qed_ov_driver_state drv_state)
2809 {
2810         u32 resp = 0, param = 0;
2811         u32 drv_mb_param;
2812         int rc;
2813
2814         switch (drv_state) {
2815         case QED_OV_DRIVER_STATE_NOT_LOADED:
2816                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2817                 break;
2818         case QED_OV_DRIVER_STATE_DISABLED:
2819                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2820                 break;
2821         case QED_OV_DRIVER_STATE_ACTIVE:
2822                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2823                 break;
2824         default:
2825                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2826                 return -EINVAL;
2827         }
2828
2829         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2830                          drv_mb_param, &resp, &param);
2831         if (rc)
2832                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2833
2834         return rc;
2835 }
2836
2837 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2838                           struct qed_ptt *p_ptt, u16 mtu)
2839 {
2840         u32 resp = 0, param = 0;
2841         u32 drv_mb_param;
2842         int rc;
2843
2844         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2845         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2846                          drv_mb_param, &resp, &param);
2847         if (rc)
2848                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2849
2850         return rc;
2851 }
2852
2853 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2854                           struct qed_ptt *p_ptt, const u8 *mac)
2855 {
2856         struct qed_mcp_mb_params mb_params;
2857         u32 mfw_mac[2];
2858         int rc;
2859
2860         memset(&mb_params, 0, sizeof(mb_params));
2861         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2862         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2863                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2864         mb_params.param |= MCP_PF_ID(p_hwfn);
2865
2866         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2867          * in 32-bit granularity.
2868          * So the MAC has to be set in native order [and not byte order],
2869          * otherwise it would be read incorrectly by MFW after swap.
2870          */
2871         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2872         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2873
2874         mb_params.p_data_src = (u8 *)mfw_mac;
2875         mb_params.data_src_size = 8;
2876         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2877         if (rc)
2878                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2879
2880         /* Store primary MAC for later possible WoL */
2881         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2882
2883         return rc;
2884 }
2885
2886 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2887                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2888 {
2889         u32 resp = 0, param = 0;
2890         u32 drv_mb_param;
2891         int rc;
2892
2893         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2894                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2895                            "Can't change WoL configuration when WoL isn't supported\n");
2896                 return -EINVAL;
2897         }
2898
2899         switch (wol) {
2900         case QED_OV_WOL_DEFAULT:
2901                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2902                 break;
2903         case QED_OV_WOL_DISABLED:
2904                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2905                 break;
2906         case QED_OV_WOL_ENABLED:
2907                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2908                 break;
2909         default:
2910                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2911                 return -EINVAL;
2912         }
2913
2914         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2915                          drv_mb_param, &resp, &param);
2916         if (rc)
2917                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2918
2919         /* Store the WoL update for a future unload */
2920         p_hwfn->cdev->wol_config = (u8)wol;
2921
2922         return rc;
2923 }
2924
2925 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2926                               struct qed_ptt *p_ptt,
2927                               enum qed_ov_eswitch eswitch)
2928 {
2929         u32 resp = 0, param = 0;
2930         u32 drv_mb_param;
2931         int rc;
2932
2933         switch (eswitch) {
2934         case QED_OV_ESWITCH_NONE:
2935                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2936                 break;
2937         case QED_OV_ESWITCH_VEB:
2938                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2939                 break;
2940         case QED_OV_ESWITCH_VEPA:
2941                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2942                 break;
2943         default:
2944                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2945                 return -EINVAL;
2946         }
2947
2948         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2949                          drv_mb_param, &resp, &param);
2950         if (rc)
2951                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2952
2953         return rc;
2954 }
2955
2956 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2957                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2958 {
2959         u32 resp = 0, param = 0, drv_mb_param;
2960         int rc;
2961
2962         switch (mode) {
2963         case QED_LED_MODE_ON:
2964                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2965                 break;
2966         case QED_LED_MODE_OFF:
2967                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2968                 break;
2969         case QED_LED_MODE_RESTORE:
2970                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2971                 break;
2972         default:
2973                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2974                 return -EINVAL;
2975         }
2976
2977         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2978                          drv_mb_param, &resp, &param);
2979
2980         return rc;
2981 }
2982
2983 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2984                           struct qed_ptt *p_ptt, u32 mask_parities)
2985 {
2986         u32 resp = 0, param = 0;
2987         int rc;
2988
2989         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2990                          mask_parities, &resp, &param);
2991
2992         if (rc) {
2993                 DP_ERR(p_hwfn,
2994                        "MCP response failure for mask parities, aborting\n");
2995         } else if (resp != FW_MSG_CODE_OK) {
2996                 DP_ERR(p_hwfn,
2997                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2998                 rc = -EINVAL;
2999         }
3000
3001         return rc;
3002 }
3003
3004 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
3005 {
3006         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
3007         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3008         u32 resp = 0, resp_param = 0;
3009         struct qed_ptt *p_ptt;
3010         int rc = 0;
3011
3012         p_ptt = qed_ptt_acquire(p_hwfn);
3013         if (!p_ptt)
3014                 return -EBUSY;
3015
3016         while (bytes_left > 0) {
3017                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
3018
3019                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3020                                         DRV_MSG_CODE_NVM_READ_NVRAM,
3021                                         addr + offset +
3022                                         (bytes_to_copy <<
3023                                          DRV_MB_PARAM_NVM_LEN_OFFSET),
3024                                         &resp, &resp_param,
3025                                         &read_len,
3026                                         (u32 *)(p_buf + offset), false);
3027
3028                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
3029                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
3030                         break;
3031                 }
3032
3033                 /* This can be a lengthy process, and it's possible scheduler
3034                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
3035                  */
3036                 if (bytes_left % 0x1000 <
3037                     (bytes_left - read_len) % 0x1000)
3038                         usleep_range(1000, 2000);
3039
3040                 offset += read_len;
3041                 bytes_left -= read_len;
3042         }
3043
3044         cdev->mcp_nvm_resp = resp;
3045         qed_ptt_release(p_hwfn, p_ptt);
3046
3047         return rc;
3048 }
3049
3050 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
3051 {
3052         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3053         struct qed_ptt *p_ptt;
3054
3055         p_ptt = qed_ptt_acquire(p_hwfn);
3056         if (!p_ptt)
3057                 return -EBUSY;
3058
3059         memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
3060         qed_ptt_release(p_hwfn, p_ptt);
3061
3062         return 0;
3063 }
3064
3065 int qed_mcp_nvm_write(struct qed_dev *cdev,
3066                       u32 cmd, u32 addr, u8 *p_buf, u32 len)
3067 {
3068         u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
3069         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3070         struct qed_ptt *p_ptt;
3071         int rc = -EINVAL;
3072
3073         p_ptt = qed_ptt_acquire(p_hwfn);
3074         if (!p_ptt)
3075                 return -EBUSY;
3076
3077         switch (cmd) {
3078         case QED_PUT_FILE_BEGIN:
3079                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
3080                 break;
3081         case QED_PUT_FILE_DATA:
3082                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
3083                 break;
3084         case QED_NVM_WRITE_NVRAM:
3085                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
3086                 break;
3087         default:
3088                 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
3089                 rc = -EINVAL;
3090                 goto out;
3091         }
3092
3093         buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
3094         while (buf_idx < len) {
3095                 if (cmd == QED_PUT_FILE_BEGIN)
3096                         nvm_offset = addr;
3097                 else
3098                         nvm_offset = ((buf_size <<
3099                                        DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) +
3100                                        buf_idx;
3101                 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
3102                                         &resp, &param, buf_size,
3103                                         (u32 *)&p_buf[buf_idx]);
3104                 if (rc) {
3105                         DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
3106                         resp = FW_MSG_CODE_ERROR;
3107                         break;
3108                 }
3109
3110                 if (resp != FW_MSG_CODE_OK &&
3111                     resp != FW_MSG_CODE_NVM_OK &&
3112                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
3113                         DP_NOTICE(cdev,
3114                                   "nvm write failed, resp = 0x%08x\n", resp);
3115                         rc = -EINVAL;
3116                         break;
3117                 }
3118
3119                 /* This can be a lengthy process, and it's possible scheduler
3120                  * isn't pre-emptable. Sleep a bit to prevent CPU hogging.
3121                  */
3122                 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
3123                         usleep_range(1000, 2000);
3124
3125                 /* For MBI upgrade, MFW response includes the next buffer offset
3126                  * to be delivered to MFW.
3127                  */
3128                 if (param && cmd == QED_PUT_FILE_DATA) {
3129                         buf_idx =
3130                         QED_MFW_GET_FIELD(param,
3131                                           FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET);
3132                         buf_size =
3133                         QED_MFW_GET_FIELD(param,
3134                                           FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE);
3135                 } else {
3136                         buf_idx += buf_size;
3137                         buf_size = min_t(u32, (len - buf_idx),
3138                                          MCP_DRV_NVM_BUF_LEN);
3139                 }
3140         }
3141
3142         cdev->mcp_nvm_resp = resp;
3143 out:
3144         qed_ptt_release(p_hwfn, p_ptt);
3145
3146         return rc;
3147 }
3148
3149 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3150                          u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf)
3151 {
3152         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0;
3153         u32 resp, param;
3154         int rc;
3155
3156         nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) &
3157                        DRV_MB_PARAM_TRANSCEIVER_PORT_MASK;
3158         nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) &
3159                        DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK;
3160
3161         addr = offset;
3162         offset = 0;
3163         bytes_left = len;
3164         while (bytes_left > 0) {
3165                 bytes_to_copy = min_t(u32, bytes_left,
3166                                       MAX_I2C_TRANSACTION_SIZE);
3167                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
3168                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
3169                 nvm_offset |= ((addr + offset) <<
3170                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) &
3171                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK;
3172                 nvm_offset |= (bytes_to_copy <<
3173                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) &
3174                                DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK;
3175                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3176                                         DRV_MSG_CODE_TRANSCEIVER_READ,
3177                                         nvm_offset, &resp, &param, &buf_size,
3178                                         (u32 *)(p_buf + offset), true);
3179                 if (rc) {
3180                         DP_NOTICE(p_hwfn,
3181                                   "Failed to send a transceiver read command to the MFW. rc = %d.\n",
3182                                   rc);
3183                         return rc;
3184                 }
3185
3186                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
3187                         return -ENODEV;
3188                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
3189                         return -EINVAL;
3190
3191                 offset += buf_size;
3192                 bytes_left -= buf_size;
3193         }
3194
3195         return 0;
3196 }
3197
3198 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3199 {
3200         u32 drv_mb_param = 0, rsp, param;
3201         int rc = 0;
3202
3203         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3204                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
3205
3206         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3207                          drv_mb_param, &rsp, &param);
3208
3209         if (rc)
3210                 return rc;
3211
3212         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3213             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3214                 rc = -EAGAIN;
3215
3216         return rc;
3217 }
3218
3219 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3220 {
3221         u32 drv_mb_param, rsp, param;
3222         int rc = 0;
3223
3224         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3225                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
3226
3227         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3228                          drv_mb_param, &rsp, &param);
3229
3230         if (rc)
3231                 return rc;
3232
3233         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3234             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3235                 rc = -EAGAIN;
3236
3237         return rc;
3238 }
3239
3240 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
3241                                     struct qed_ptt *p_ptt,
3242                                     u32 *num_images)
3243 {
3244         u32 drv_mb_param = 0, rsp;
3245         int rc = 0;
3246
3247         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3248                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
3249
3250         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3251                          drv_mb_param, &rsp, num_images);
3252         if (rc)
3253                 return rc;
3254
3255         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3256                 rc = -EINVAL;
3257
3258         return rc;
3259 }
3260
3261 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
3262                                    struct qed_ptt *p_ptt,
3263                                    struct bist_nvm_image_att *p_image_att,
3264                                    u32 image_index)
3265 {
3266         u32 buf_size = 0, param, resp = 0, resp_param = 0;
3267         int rc;
3268
3269         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3270                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
3271         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
3272
3273         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3274                                 DRV_MSG_CODE_BIST_TEST, param,
3275                                 &resp, &resp_param,
3276                                 &buf_size,
3277                                 (u32 *)p_image_att, false);
3278         if (rc)
3279                 return rc;
3280
3281         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3282             (p_image_att->return_code != 1))
3283                 rc = -EINVAL;
3284
3285         return rc;
3286 }
3287
3288 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
3289 {
3290         struct qed_nvm_image_info nvm_info;
3291         struct qed_ptt *p_ptt;
3292         int rc;
3293         u32 i;
3294
3295         if (p_hwfn->nvm_info.valid)
3296                 return 0;
3297
3298         p_ptt = qed_ptt_acquire(p_hwfn);
3299         if (!p_ptt) {
3300                 DP_ERR(p_hwfn, "failed to acquire ptt\n");
3301                 return -EBUSY;
3302         }
3303
3304         /* Acquire from MFW the amount of available images */
3305         nvm_info.num_images = 0;
3306         rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
3307                                              p_ptt, &nvm_info.num_images);
3308         if (rc == -EOPNOTSUPP) {
3309                 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
3310                 goto out;
3311         } else if (rc || !nvm_info.num_images) {
3312                 DP_ERR(p_hwfn, "Failed getting number of images\n");
3313                 goto err0;
3314         }
3315
3316         nvm_info.image_att = kmalloc_array(nvm_info.num_images,
3317                                            sizeof(struct bist_nvm_image_att),
3318                                            GFP_KERNEL);
3319         if (!nvm_info.image_att) {
3320                 rc = -ENOMEM;
3321                 goto err0;
3322         }
3323
3324         /* Iterate over images and get their attributes */
3325         for (i = 0; i < nvm_info.num_images; i++) {
3326                 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
3327                                                     &nvm_info.image_att[i], i);
3328                 if (rc) {
3329                         DP_ERR(p_hwfn,
3330                                "Failed getting image index %d attributes\n", i);
3331                         goto err1;
3332                 }
3333
3334                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
3335                            nvm_info.image_att[i].len);
3336         }
3337 out:
3338         /* Update hwfn's nvm_info */
3339         if (nvm_info.num_images) {
3340                 p_hwfn->nvm_info.num_images = nvm_info.num_images;
3341                 kfree(p_hwfn->nvm_info.image_att);
3342                 p_hwfn->nvm_info.image_att = nvm_info.image_att;
3343                 p_hwfn->nvm_info.valid = true;
3344         }
3345
3346         qed_ptt_release(p_hwfn, p_ptt);
3347         return 0;
3348
3349 err1:
3350         kfree(nvm_info.image_att);
3351 err0:
3352         qed_ptt_release(p_hwfn, p_ptt);
3353         return rc;
3354 }
3355
3356 void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn)
3357 {
3358         kfree(p_hwfn->nvm_info.image_att);
3359         p_hwfn->nvm_info.image_att = NULL;
3360         p_hwfn->nvm_info.valid = false;
3361 }
3362
3363 int
3364 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
3365                           enum qed_nvm_images image_id,
3366                           struct qed_nvm_image_att *p_image_att)
3367 {
3368         enum nvm_image_type type;
3369         int rc;
3370         u32 i;
3371
3372         /* Translate image_id into MFW definitions */
3373         switch (image_id) {
3374         case QED_NVM_IMAGE_ISCSI_CFG:
3375                 type = NVM_TYPE_ISCSI_CFG;
3376                 break;
3377         case QED_NVM_IMAGE_FCOE_CFG:
3378                 type = NVM_TYPE_FCOE_CFG;
3379                 break;
3380         case QED_NVM_IMAGE_MDUMP:
3381                 type = NVM_TYPE_MDUMP;
3382                 break;
3383         case QED_NVM_IMAGE_NVM_CFG1:
3384                 type = NVM_TYPE_NVM_CFG1;
3385                 break;
3386         case QED_NVM_IMAGE_DEFAULT_CFG:
3387                 type = NVM_TYPE_DEFAULT_CFG;
3388                 break;
3389         case QED_NVM_IMAGE_NVM_META:
3390                 type = NVM_TYPE_NVM_META;
3391                 break;
3392         default:
3393                 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
3394                           image_id);
3395                 return -EINVAL;
3396         }
3397
3398         rc = qed_mcp_nvm_info_populate(p_hwfn);
3399         if (rc)
3400                 return rc;
3401
3402         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
3403                 if (type == p_hwfn->nvm_info.image_att[i].image_type)
3404                         break;
3405         if (i == p_hwfn->nvm_info.num_images) {
3406                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
3407                            "Failed to find nvram image of type %08x\n",
3408                            image_id);
3409                 return -ENOENT;
3410         }
3411
3412         p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
3413         p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
3414
3415         return 0;
3416 }
3417
3418 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
3419                           enum qed_nvm_images image_id,
3420                           u8 *p_buffer, u32 buffer_len)
3421 {
3422         struct qed_nvm_image_att image_att;
3423         int rc;
3424
3425         memset(p_buffer, 0, buffer_len);
3426
3427         rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
3428         if (rc)
3429                 return rc;
3430
3431         /* Validate sizes - both the image's and the supplied buffer's */
3432         if (image_att.length <= 4) {
3433                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
3434                            "Image [%d] is too small - only %d bytes\n",
3435                            image_id, image_att.length);
3436                 return -EINVAL;
3437         }
3438
3439         if (image_att.length > buffer_len) {
3440                 DP_VERBOSE(p_hwfn,
3441                            QED_MSG_STORAGE,
3442                            "Image [%d] is too big - %08x bytes where only %08x are available\n",
3443                            image_id, image_att.length, buffer_len);
3444                 return -ENOMEM;
3445         }
3446
3447         return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
3448                                 p_buffer, image_att.length);
3449 }
3450
3451 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
3452 {
3453         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3454
3455         switch (res_id) {
3456         case QED_SB:
3457                 mfw_res_id = RESOURCE_NUM_SB_E;
3458                 break;
3459         case QED_L2_QUEUE:
3460                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3461                 break;
3462         case QED_VPORT:
3463                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3464                 break;
3465         case QED_RSS_ENG:
3466                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3467                 break;
3468         case QED_PQ:
3469                 mfw_res_id = RESOURCE_NUM_PQ_E;
3470                 break;
3471         case QED_RL:
3472                 mfw_res_id = RESOURCE_NUM_RL_E;
3473                 break;
3474         case QED_MAC:
3475         case QED_VLAN:
3476                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3477                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3478                 break;
3479         case QED_ILT:
3480                 mfw_res_id = RESOURCE_ILT_E;
3481                 break;
3482         case QED_LL2_RAM_QUEUE:
3483                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3484                 break;
3485         case QED_LL2_CTX_QUEUE:
3486                 mfw_res_id = RESOURCE_LL2_CQS_E;
3487                 break;
3488         case QED_RDMA_CNQ_RAM:
3489         case QED_CMDQS_CQS:
3490                 /* CNQ/CMDQS are the same resource */
3491                 mfw_res_id = RESOURCE_CQS_E;
3492                 break;
3493         case QED_RDMA_STATS_QUEUE:
3494                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3495                 break;
3496         case QED_BDQ:
3497                 mfw_res_id = RESOURCE_BDQ_E;
3498                 break;
3499         default:
3500                 break;
3501         }
3502
3503         return mfw_res_id;
3504 }
3505
3506 #define QED_RESC_ALLOC_VERSION_MAJOR    2
3507 #define QED_RESC_ALLOC_VERSION_MINOR    0
3508 #define QED_RESC_ALLOC_VERSION                               \
3509         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
3510           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
3511          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
3512           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
3513
3514 struct qed_resc_alloc_in_params {
3515         u32 cmd;
3516         enum qed_resources res_id;
3517         u32 resc_max_val;
3518 };
3519
3520 struct qed_resc_alloc_out_params {
3521         u32 mcp_resp;
3522         u32 mcp_param;
3523         u32 resc_num;
3524         u32 resc_start;
3525         u32 vf_resc_num;
3526         u32 vf_resc_start;
3527         u32 flags;
3528 };
3529
3530 static int
3531 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
3532                             struct qed_ptt *p_ptt,
3533                             struct qed_resc_alloc_in_params *p_in_params,
3534                             struct qed_resc_alloc_out_params *p_out_params)
3535 {
3536         struct qed_mcp_mb_params mb_params;
3537         struct resource_info mfw_resc_info;
3538         int rc;
3539
3540         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
3541
3542         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
3543         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3544                 DP_ERR(p_hwfn,
3545                        "Failed to match resource %d [%s] with the MFW resources\n",
3546                        p_in_params->res_id,
3547                        qed_hw_get_resc_name(p_in_params->res_id));
3548                 return -EINVAL;
3549         }
3550
3551         switch (p_in_params->cmd) {
3552         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3553                 mfw_resc_info.size = p_in_params->resc_max_val;
3554                 fallthrough;
3555         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3556                 break;
3557         default:
3558                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3559                        p_in_params->cmd);
3560                 return -EINVAL;
3561         }
3562
3563         memset(&mb_params, 0, sizeof(mb_params));
3564         mb_params.cmd = p_in_params->cmd;
3565         mb_params.param = QED_RESC_ALLOC_VERSION;
3566         mb_params.p_data_src = &mfw_resc_info;
3567         mb_params.data_src_size = sizeof(mfw_resc_info);
3568         mb_params.p_data_dst = mb_params.p_data_src;
3569         mb_params.data_dst_size = mb_params.data_src_size;
3570
3571         DP_VERBOSE(p_hwfn,
3572                    QED_MSG_SP,
3573                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3574                    p_in_params->cmd,
3575                    p_in_params->res_id,
3576                    qed_hw_get_resc_name(p_in_params->res_id),
3577                    QED_MFW_GET_FIELD(mb_params.param,
3578                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3579                    QED_MFW_GET_FIELD(mb_params.param,
3580                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3581                    p_in_params->resc_max_val);
3582
3583         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3584         if (rc)
3585                 return rc;
3586
3587         p_out_params->mcp_resp = mb_params.mcp_resp;
3588         p_out_params->mcp_param = mb_params.mcp_param;
3589         p_out_params->resc_num = mfw_resc_info.size;
3590         p_out_params->resc_start = mfw_resc_info.offset;
3591         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3592         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3593         p_out_params->flags = mfw_resc_info.flags;
3594
3595         DP_VERBOSE(p_hwfn,
3596                    QED_MSG_SP,
3597                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3598                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3599                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3600                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3601                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3602                    p_out_params->resc_num,
3603                    p_out_params->resc_start,
3604                    p_out_params->vf_resc_num,
3605                    p_out_params->vf_resc_start, p_out_params->flags);
3606
3607         return 0;
3608 }
3609
3610 int
3611 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
3612                          struct qed_ptt *p_ptt,
3613                          enum qed_resources res_id,
3614                          u32 resc_max_val, u32 *p_mcp_resp)
3615 {
3616         struct qed_resc_alloc_out_params out_params;
3617         struct qed_resc_alloc_in_params in_params;
3618         int rc;
3619
3620         memset(&in_params, 0, sizeof(in_params));
3621         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3622         in_params.res_id = res_id;
3623         in_params.resc_max_val = resc_max_val;
3624         memset(&out_params, 0, sizeof(out_params));
3625         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3626                                          &out_params);
3627         if (rc)
3628                 return rc;
3629
3630         *p_mcp_resp = out_params.mcp_resp;
3631
3632         return 0;
3633 }
3634
3635 int
3636 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
3637                       struct qed_ptt *p_ptt,
3638                       enum qed_resources res_id,
3639                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
3640 {
3641         struct qed_resc_alloc_out_params out_params;
3642         struct qed_resc_alloc_in_params in_params;
3643         int rc;
3644
3645         memset(&in_params, 0, sizeof(in_params));
3646         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3647         in_params.res_id = res_id;
3648         memset(&out_params, 0, sizeof(out_params));
3649         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3650                                          &out_params);
3651         if (rc)
3652                 return rc;
3653
3654         *p_mcp_resp = out_params.mcp_resp;
3655
3656         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3657                 *p_resc_num = out_params.resc_num;
3658                 *p_resc_start = out_params.resc_start;
3659         }
3660
3661         return 0;
3662 }
3663
3664 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3665 {
3666         u32 mcp_resp, mcp_param;
3667
3668         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3669                            &mcp_resp, &mcp_param);
3670 }
3671
3672 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
3673                                 struct qed_ptt *p_ptt,
3674                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
3675 {
3676         int rc;
3677
3678         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3679                          p_mcp_resp, p_mcp_param);
3680         if (rc)
3681                 return rc;
3682
3683         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3684                 DP_INFO(p_hwfn,
3685                         "The resource command is unsupported by the MFW\n");
3686                 return -EINVAL;
3687         }
3688
3689         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3690                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3691
3692                 DP_NOTICE(p_hwfn,
3693                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3694                           param, opcode);
3695                 return -EINVAL;
3696         }
3697
3698         return rc;
3699 }
3700
3701 static int
3702 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3703                     struct qed_ptt *p_ptt,
3704                     struct qed_resc_lock_params *p_params)
3705 {
3706         u32 param = 0, mcp_resp, mcp_param;
3707         u8 opcode;
3708         int rc;
3709
3710         switch (p_params->timeout) {
3711         case QED_MCP_RESC_LOCK_TO_DEFAULT:
3712                 opcode = RESOURCE_OPCODE_REQ;
3713                 p_params->timeout = 0;
3714                 break;
3715         case QED_MCP_RESC_LOCK_TO_NONE:
3716                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3717                 p_params->timeout = 0;
3718                 break;
3719         default:
3720                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3721                 break;
3722         }
3723
3724         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3725         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3726         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3727
3728         DP_VERBOSE(p_hwfn,
3729                    QED_MSG_SP,
3730                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3731                    param, p_params->timeout, opcode, p_params->resource);
3732
3733         /* Attempt to acquire the resource */
3734         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3735         if (rc)
3736                 return rc;
3737
3738         /* Analyze the response */
3739         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3740         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3741
3742         DP_VERBOSE(p_hwfn,
3743                    QED_MSG_SP,
3744                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3745                    mcp_param, opcode, p_params->owner);
3746
3747         switch (opcode) {
3748         case RESOURCE_OPCODE_GNT:
3749                 p_params->b_granted = true;
3750                 break;
3751         case RESOURCE_OPCODE_BUSY:
3752                 p_params->b_granted = false;
3753                 break;
3754         default:
3755                 DP_NOTICE(p_hwfn,
3756                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3757                           mcp_param, opcode);
3758                 return -EINVAL;
3759         }
3760
3761         return 0;
3762 }
3763
3764 int
3765 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3766                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
3767 {
3768         u32 retry_cnt = 0;
3769         int rc;
3770
3771         do {
3772                 /* No need for an interval before the first iteration */
3773                 if (retry_cnt) {
3774                         if (p_params->sleep_b4_retry) {
3775                                 u16 retry_interval_in_ms =
3776                                     DIV_ROUND_UP(p_params->retry_interval,
3777                                                  1000);
3778
3779                                 msleep(retry_interval_in_ms);
3780                         } else {
3781                                 udelay(p_params->retry_interval);
3782                         }
3783                 }
3784
3785                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3786                 if (rc)
3787                         return rc;
3788
3789                 if (p_params->b_granted)
3790                         break;
3791         } while (retry_cnt++ < p_params->retry_num);
3792
3793         return 0;
3794 }
3795
3796 int
3797 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
3798                     struct qed_ptt *p_ptt,
3799                     struct qed_resc_unlock_params *p_params)
3800 {
3801         u32 param = 0, mcp_resp, mcp_param;
3802         u8 opcode;
3803         int rc;
3804
3805         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3806                                    : RESOURCE_OPCODE_RELEASE;
3807         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3808         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3809
3810         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3811                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3812                    param, opcode, p_params->resource);
3813
3814         /* Attempt to release the resource */
3815         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3816         if (rc)
3817                 return rc;
3818
3819         /* Analyze the response */
3820         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3821
3822         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3823                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3824                    mcp_param, opcode);
3825
3826         switch (opcode) {
3827         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3828                 DP_INFO(p_hwfn,
3829                         "Resource unlock request for an already released resource [%d]\n",
3830                         p_params->resource);
3831                 fallthrough;
3832         case RESOURCE_OPCODE_RELEASED:
3833                 p_params->b_released = true;
3834                 break;
3835         case RESOURCE_OPCODE_WRONG_OWNER:
3836                 p_params->b_released = false;
3837                 break;
3838         default:
3839                 DP_NOTICE(p_hwfn,
3840                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3841                           mcp_param, opcode);
3842                 return -EINVAL;
3843         }
3844
3845         return 0;
3846 }
3847
3848 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3849                                     struct qed_resc_unlock_params *p_unlock,
3850                                     enum qed_resc_lock
3851                                     resource, bool b_is_permanent)
3852 {
3853         if (p_lock) {
3854                 memset(p_lock, 0, sizeof(*p_lock));
3855
3856                 /* Permanent resources don't require aging, and there's no
3857                  * point in trying to acquire them more than once since it's
3858                  * unexpected another entity would release them.
3859                  */
3860                 if (b_is_permanent) {
3861                         p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3862                 } else {
3863                         p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3864                         p_lock->retry_interval =
3865                             QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3866                         p_lock->sleep_b4_retry = true;
3867                 }
3868
3869                 p_lock->resource = resource;
3870         }
3871
3872         if (p_unlock) {
3873                 memset(p_unlock, 0, sizeof(*p_unlock));
3874                 p_unlock->resource = resource;
3875         }
3876 }
3877
3878 bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn)
3879 {
3880         return !!(p_hwfn->mcp_info->capabilities &
3881                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3882 }
3883
3884 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3885 {
3886         u32 mcp_resp;
3887         int rc;
3888
3889         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3890                          0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3891         if (!rc)
3892                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3893                            "MFW supported features: %08x\n",
3894                            p_hwfn->mcp_info->capabilities);
3895
3896         return rc;
3897 }
3898
3899 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3900 {
3901         u32 mcp_resp, mcp_param, features;
3902
3903         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE |
3904                    DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK |
3905                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL;
3906
3907         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3908                            features, &mcp_resp, &mcp_param);
3909 }
3910
3911 int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3912 {
3913         struct qed_mcp_mb_params mb_params = {0};
3914         struct qed_dev *cdev = p_hwfn->cdev;
3915         u8 fir_valid, l2_valid;
3916         int rc;
3917
3918         mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG;
3919         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3920         if (rc)
3921                 return rc;
3922
3923         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3924                 DP_INFO(p_hwfn,
3925                         "The get_engine_config command is unsupported by the MFW\n");
3926                 return -EOPNOTSUPP;
3927         }
3928
3929         fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param,
3930                                       FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID);
3931         if (fir_valid)
3932                 cdev->fir_affin =
3933                     QED_MFW_GET_FIELD(mb_params.mcp_param,
3934                                       FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE);
3935
3936         l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param,
3937                                      FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID);
3938         if (l2_valid)
3939                 cdev->l2_affin_hint =
3940                     QED_MFW_GET_FIELD(mb_params.mcp_param,
3941                                       FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE);
3942
3943         DP_INFO(p_hwfn,
3944                 "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n",
3945                 fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint);
3946
3947         return 0;
3948 }
3949
3950 int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3951 {
3952         struct qed_mcp_mb_params mb_params = {0};
3953         struct qed_dev *cdev = p_hwfn->cdev;
3954         int rc;
3955
3956         mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP;
3957         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3958         if (rc)
3959                 return rc;
3960
3961         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3962                 DP_INFO(p_hwfn,
3963                         "The get_ppfid_bitmap command is unsupported by the MFW\n");
3964                 return -EOPNOTSUPP;
3965         }
3966
3967         cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param,
3968                                                FW_MB_PARAM_PPFID_BITMAP);
3969
3970         DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n",
3971                    cdev->ppfid_bitmap);
3972
3973         return 0;
3974 }
3975
3976 int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3977                         u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
3978                         u32 *p_len)
3979 {
3980         u32 mb_param = 0, resp, param;
3981         int rc;
3982
3983         QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
3984         if (flags & QED_NVM_CFG_OPTION_INIT)
3985                 QED_MFW_SET_FIELD(mb_param,
3986                                   DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
3987         if (flags & QED_NVM_CFG_OPTION_FREE)
3988                 QED_MFW_SET_FIELD(mb_param,
3989                                   DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
3990         if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
3991                 QED_MFW_SET_FIELD(mb_param,
3992                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
3993                 QED_MFW_SET_FIELD(mb_param,
3994                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
3995                                   entity_id);
3996         }
3997
3998         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3999                                 DRV_MSG_CODE_GET_NVM_CFG_OPTION,
4000                                 mb_param, &resp, &param, p_len,
4001                                 (u32 *)p_buf, false);
4002
4003         return rc;
4004 }
4005
4006 int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4007                         u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
4008                         u32 len)
4009 {
4010         u32 mb_param = 0, resp, param;
4011
4012         QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
4013         if (flags & QED_NVM_CFG_OPTION_ALL)
4014                 QED_MFW_SET_FIELD(mb_param,
4015                                   DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1);
4016         if (flags & QED_NVM_CFG_OPTION_INIT)
4017                 QED_MFW_SET_FIELD(mb_param,
4018                                   DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
4019         if (flags & QED_NVM_CFG_OPTION_COMMIT)
4020                 QED_MFW_SET_FIELD(mb_param,
4021                                   DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1);
4022         if (flags & QED_NVM_CFG_OPTION_FREE)
4023                 QED_MFW_SET_FIELD(mb_param,
4024                                   DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
4025         if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
4026                 QED_MFW_SET_FIELD(mb_param,
4027                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
4028                 QED_MFW_SET_FIELD(mb_param,
4029                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
4030                                   entity_id);
4031         }
4032
4033         return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
4034                                   DRV_MSG_CODE_SET_NVM_CFG_OPTION,
4035                                   mb_param, &resp, &param, len, (u32 *)p_buf);
4036 }
4037
4038 #define QED_MCP_DBG_DATA_MAX_SIZE               MCP_DRV_NVM_BUF_LEN
4039 #define QED_MCP_DBG_DATA_MAX_HEADER_SIZE        sizeof(u32)
4040 #define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \
4041         (QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE)
4042
4043 static int
4044 __qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn,
4045                           struct qed_ptt *p_ptt, u8 *p_buf, u8 size)
4046 {
4047         struct qed_mcp_mb_params mb_params;
4048         int rc;
4049
4050         if (size > QED_MCP_DBG_DATA_MAX_SIZE) {
4051                 DP_ERR(p_hwfn,
4052                        "Debug data size is %d while it should not exceed %d\n",
4053                        size, QED_MCP_DBG_DATA_MAX_SIZE);
4054                 return -EINVAL;
4055         }
4056
4057         memset(&mb_params, 0, sizeof(mb_params));
4058         mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND;
4059         SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size);
4060         mb_params.p_data_src = p_buf;
4061         mb_params.data_src_size = size;
4062         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
4063         if (rc)
4064                 return rc;
4065
4066         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
4067                 DP_INFO(p_hwfn,
4068                         "The DEBUG_DATA_SEND command is unsupported by the MFW\n");
4069                 return -EOPNOTSUPP;
4070         } else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) {
4071                 DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n");
4072                 return -EBUSY;
4073         } else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) {
4074                 DP_NOTICE(p_hwfn,
4075                           "Failed to send debug data to the MFW [resp 0x%08x]\n",
4076                           mb_params.mcp_resp);
4077                 return -EINVAL;
4078         }
4079
4080         return 0;
4081 }
4082
4083 enum qed_mcp_dbg_data_type {
4084         QED_MCP_DBG_DATA_TYPE_RAW,
4085 };
4086
4087 /* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */
4088 #define QED_MCP_DBG_DATA_HDR_SN_OFFSET  0
4089 #define QED_MCP_DBG_DATA_HDR_SN_MASK            0x00000fff
4090 #define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET        12
4091 #define QED_MCP_DBG_DATA_HDR_TYPE_MASK  0x000ff000
4092 #define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET       20
4093 #define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000
4094 #define QED_MCP_DBG_DATA_HDR_PF_OFFSET  28
4095 #define QED_MCP_DBG_DATA_HDR_PF_MASK            0xf0000000
4096
4097 #define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST        0x1
4098 #define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2
4099
4100 static int
4101 qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn,
4102                         struct qed_ptt *p_ptt,
4103                         enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size)
4104 {
4105         u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf;
4106         u32 tmp_size = size, *p_header, *p_payload;
4107         u8 flags = 0;
4108         u16 seq;
4109         int rc;
4110
4111         p_header = (u32 *)raw_data;
4112         p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE);
4113
4114         seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq);
4115
4116         /* First chunk is marked as 'first' */
4117         flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST;
4118
4119         *p_header = 0;
4120         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq);
4121         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type);
4122         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags);
4123         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id);
4124
4125         while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) {
4126                 memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE);
4127                 rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data,
4128                                                QED_MCP_DBG_DATA_MAX_SIZE);
4129                 if (rc)
4130                         return rc;
4131
4132                 /* Clear the 'first' marking after sending the first chunk */
4133                 if (p_tmp_buf == p_buf) {
4134                         flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST;
4135                         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS,
4136                                       flags);
4137                 }
4138
4139                 p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE;
4140                 tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE;
4141         }
4142
4143         /* Last chunk is marked as 'last' */
4144         flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST;
4145         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags);
4146         memcpy(p_payload, p_tmp_buf, tmp_size);
4147
4148         /* Casting the left size to u8 is ok since at this point it is <= 32 */
4149         return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data,
4150                                          (u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE +
4151                                          tmp_size));
4152 }
4153
4154 int
4155 qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn,
4156                             struct qed_ptt *p_ptt, u8 *p_buf, u32 size)
4157 {
4158         return qed_mcp_send_debug_data(p_hwfn, p_ptt,
4159                                        QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size);
4160 }