drivers/net/ethernet/ni/nixge.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016-2017, National Instruments Corp.
   3  *
   4  * Author: Moritz Fischer <[email protected]>
   5  */
   6
   7 #include <linux/etherdevice.h>
   8 #include <linux/module.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_mdio.h>
  12 #include <linux/of_net.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/phy.h>
  17 #include <linux/mii.h>
  18 #include <linux/nvmem-consumer.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/iopoll.h>
  21
  22 #define TX_BD_NUM               64
  23 #define RX_BD_NUM               128
  24
  25 /* Axi DMA Register definitions */
  26 #define XAXIDMA_TX_CR_OFFSET    0x00 /* Channel control */
  27 #define XAXIDMA_TX_SR_OFFSET    0x04 /* Status */
  28 #define XAXIDMA_TX_CDESC_OFFSET 0x08 /* Current descriptor pointer */
  29 #define XAXIDMA_TX_TDESC_OFFSET 0x10 /* Tail descriptor pointer */
  30
  31 #define XAXIDMA_RX_CR_OFFSET    0x30 /* Channel control */
  32 #define XAXIDMA_RX_SR_OFFSET    0x34 /* Status */
  33 #define XAXIDMA_RX_CDESC_OFFSET 0x38 /* Current descriptor pointer */
  34 #define XAXIDMA_RX_TDESC_OFFSET 0x40 /* Tail descriptor pointer */
  35
  36 #define XAXIDMA_CR_RUNSTOP_MASK 0x1 /* Start/stop DMA channel */
  37 #define XAXIDMA_CR_RESET_MASK   0x4 /* Reset DMA engine */
  38
  39 #define XAXIDMA_BD_CTRL_LENGTH_MASK     0x007FFFFF /* Requested len */
  40 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  41 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  42 #define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
  43
  44 #define XAXIDMA_DELAY_MASK              0xFF000000 /* Delay timeout counter */
  45 #define XAXIDMA_COALESCE_MASK           0x00FF0000 /* Coalesce counter */
  46
  47 #define XAXIDMA_DELAY_SHIFT             24
  48 #define XAXIDMA_COALESCE_SHIFT          16
  49
  50 #define XAXIDMA_IRQ_IOC_MASK            0x00001000 /* Completion intr */
  51 #define XAXIDMA_IRQ_DELAY_MASK          0x00002000 /* Delay interrupt */
  52 #define XAXIDMA_IRQ_ERROR_MASK          0x00004000 /* Error interrupt */
  53 #define XAXIDMA_IRQ_ALL_MASK            0x00007000 /* All interrupts */
  54
  55 /* Default TX/RX Threshold and waitbound values for SGDMA mode */
  56 #define XAXIDMA_DFT_TX_THRESHOLD        24
  57 #define XAXIDMA_DFT_TX_WAITBOUND        254
  58 #define XAXIDMA_DFT_RX_THRESHOLD        24
  59 #define XAXIDMA_DFT_RX_WAITBOUND        254
  60
  61 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */
  62 #define XAXIDMA_BD_STS_COMPLETE_MASK    0x80000000 /* Completed */
  63 #define XAXIDMA_BD_STS_DEC_ERR_MASK     0x40000000 /* Decode error */
  64 #define XAXIDMA_BD_STS_SLV_ERR_MASK     0x20000000 /* Slave error */
  65 #define XAXIDMA_BD_STS_INT_ERR_MASK     0x10000000 /* Internal err */
  66 #define XAXIDMA_BD_STS_ALL_ERR_MASK     0x70000000 /* All errors */
  67 #define XAXIDMA_BD_STS_RXSOF_MASK       0x08000000 /* First rx pkt */
  68 #define XAXIDMA_BD_STS_RXEOF_MASK       0x04000000 /* Last rx pkt */
  69 #define XAXIDMA_BD_STS_ALL_MASK         0xFC000000 /* All status bits */
  70
  71 #define NIXGE_REG_CTRL_OFFSET   0x4000
  72 #define NIXGE_REG_INFO          0x00
  73 #define NIXGE_REG_MAC_CTL       0x04
  74 #define NIXGE_REG_PHY_CTL       0x08
  75 #define NIXGE_REG_LED_CTL       0x0c
  76 #define NIXGE_REG_MDIO_DATA     0x10
  77 #define NIXGE_REG_MDIO_ADDR     0x14
  78 #define NIXGE_REG_MDIO_OP       0x18
  79 #define NIXGE_REG_MDIO_CTRL     0x1c
  80
  81 #define NIXGE_ID_LED_CTL_EN     BIT(0)
  82 #define NIXGE_ID_LED_CTL_VAL    BIT(1)
  83
  84 #define NIXGE_MDIO_CLAUSE45     BIT(12)
  85 #define NIXGE_MDIO_CLAUSE22     0
  86 #define NIXGE_MDIO_OP(n)     (((n) & 0x3) << 10)
  87 #define NIXGE_MDIO_OP_ADDRESS   0
  88 #define NIXGE_MDIO_C45_WRITE    BIT(0)
  89 #define NIXGE_MDIO_C45_READ     (BIT(1) | BIT(0))
  90 #define NIXGE_MDIO_C22_WRITE    BIT(0)
  91 #define NIXGE_MDIO_C22_READ     BIT(1)
  92 #define NIXGE_MDIO_ADDR(n)   (((n) & 0x1f) << 5)
  93 #define NIXGE_MDIO_MMD(n)    (((n) & 0x1f) << 0)
  94
  95 #define NIXGE_REG_MAC_LSB       0x1000
  96 #define NIXGE_REG_MAC_MSB       0x1004
  97
  98 /* Packet size info */
  99 #define NIXGE_HDR_SIZE          14 /* Size of Ethernet header */
 100 #define NIXGE_TRL_SIZE          4 /* Size of Ethernet trailer (FCS) */
 101 #define NIXGE_MTU               1500 /* Max MTU of an Ethernet frame */
 102 #define NIXGE_JUMBO_MTU         9000 /* Max MTU of a jumbo Eth. frame */
 103
 104 #define NIXGE_MAX_FRAME_SIZE     (NIXGE_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
 105 #define NIXGE_MAX_JUMBO_FRAME_SIZE \
 106         (NIXGE_JUMBO_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
 107
 108 enum nixge_version {
 109         NIXGE_V2,
 110         NIXGE_V3,
 111         NIXGE_VERSION_COUNT
 112 };
 113
 114 struct nixge_hw_dma_bd {
 115         u32 next_lo;
 116         u32 next_hi;
 117         u32 phys_lo;
 118         u32 phys_hi;
 119         u32 reserved3;
 120         u32 reserved4;
 121         u32 cntrl;
 122         u32 status;
 123         u32 app0;
 124         u32 app1;
 125         u32 app2;
 126         u32 app3;
 127         u32 app4;
 128         u32 sw_id_offset_lo;
 129         u32 sw_id_offset_hi;
 130         u32 reserved6;
 131 };
 132
 133 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 134 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
 135         do { \
 136                 (bd)->field##_lo = lower_32_bits((addr)); \
 137                 (bd)->field##_hi = upper_32_bits((addr)); \
 138         } while (0)
 139 #else
 140 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
 141         ((bd)->field##_lo = lower_32_bits((addr)))
 142 #endif
 143
 144 #define nixge_hw_dma_bd_set_phys(bd, addr) \
 145         nixge_hw_dma_bd_set_addr((bd), phys, (addr))
 146
 147 #define nixge_hw_dma_bd_set_next(bd, addr) \
 148         nixge_hw_dma_bd_set_addr((bd), next, (addr))
 149
 150 #define nixge_hw_dma_bd_set_offset(bd, addr) \
 151         nixge_hw_dma_bd_set_addr((bd), sw_id_offset, (addr))
 152
 153 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 154 #define nixge_hw_dma_bd_get_addr(bd, field) \
 155         (dma_addr_t)((((u64)(bd)->field##_hi) << 32) | ((bd)->field##_lo))
 156 #else
 157 #define nixge_hw_dma_bd_get_addr(bd, field) \
 158         (dma_addr_t)((bd)->field##_lo)
 159 #endif
 160
 161 struct nixge_tx_skb {
 162         struct sk_buff *skb;
 163         dma_addr_t mapping;
 164         size_t size;
 165         bool mapped_as_page;
 166 };
 167
 168 struct nixge_priv {
 169         struct net_device *ndev;
 170         struct napi_struct napi;
 171         struct device *dev;
 172
 173         /* Connection to PHY device */
 174         struct device_node *phy_node;
 175         phy_interface_t         phy_mode;
 176
 177         int link;
 178         unsigned int speed;
 179         unsigned int duplex;
 180
 181         /* MDIO bus data */
 182         struct mii_bus *mii_bus;        /* MII bus reference */
 183
 184         /* IO registers, dma functions and IRQs */
 185         void __iomem *ctrl_regs;
 186         void __iomem *dma_regs;
 187
 188         struct tasklet_struct dma_err_tasklet;
 189
 190         int tx_irq;
 191         int rx_irq;
 192
 193         /* Buffer descriptors */
 194         struct nixge_hw_dma_bd *tx_bd_v;
 195         struct nixge_tx_skb *tx_skb;
 196         dma_addr_t tx_bd_p;
 197
 198         struct nixge_hw_dma_bd *rx_bd_v;
 199         dma_addr_t rx_bd_p;
 200         u32 tx_bd_ci;
 201         u32 tx_bd_tail;
 202         u32 rx_bd_ci;
 203
 204         u32 coalesce_count_rx;
 205         u32 coalesce_count_tx;
 206 };
 207
 208 static void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
 209 {
 210         writel(val, priv->dma_regs + offset);
 211 }
 212
 213 static void nixge_dma_write_desc_reg(struct nixge_priv *priv, off_t offset,
 214                                      dma_addr_t addr)
 215 {
 216         writel(lower_32_bits(addr), priv->dma_regs + offset);
 217 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 218         writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
 219 #endif
 220 }
 221
 222 static u32 nixge_dma_read_reg(const struct nixge_priv *priv, off_t offset)
 223 {
 224         return readl(priv->dma_regs + offset);
 225 }
 226
 227 static void nixge_ctrl_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
 228 {
 229         writel(val, priv->ctrl_regs + offset);
 230 }
 231
 232 static u32 nixge_ctrl_read_reg(struct nixge_priv *priv, off_t offset)
 233 {
 234         return readl(priv->ctrl_regs + offset);
 235 }
 236
 237 #define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 238         readl_poll_timeout((priv)->ctrl_regs + (addr), (val), (cond), \
 239                            (sleep_us), (timeout_us))
 240
 241 #define nixge_dma_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 242         readl_poll_timeout((priv)->dma_regs + (addr), (val), (cond), \
 243                            (sleep_us), (timeout_us))
 244
 245 static void nixge_hw_dma_bd_release(struct net_device *ndev)
 246 {
 247         struct nixge_priv *priv = netdev_priv(ndev);
 248         dma_addr_t phys_addr;
 249         struct sk_buff *skb;
 250         int i;
 251
 252         for (i = 0; i < RX_BD_NUM; i++) {
 253                 phys_addr = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
 254                                                      phys);
 255
 256                 dma_unmap_single(ndev->dev.parent, phys_addr,
 257                                  NIXGE_MAX_JUMBO_FRAME_SIZE,
 258                                  DMA_FROM_DEVICE);
 259
 260                 skb = (struct sk_buff *)(uintptr_t)
 261                         nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
 262                                                  sw_id_offset);
 263                 dev_kfree_skb(skb);
 264         }
 265
 266         if (priv->rx_bd_v)
 267                 dma_free_coherent(ndev->dev.parent,
 268                                   sizeof(*priv->rx_bd_v) * RX_BD_NUM,
 269                                   priv->rx_bd_v,
 270                                   priv->rx_bd_p);
 271
 272         if (priv->tx_skb)
 273                 devm_kfree(ndev->dev.parent, priv->tx_skb);
 274
 275         if (priv->tx_bd_v)
 276                 dma_free_coherent(ndev->dev.parent,
 277                                   sizeof(*priv->tx_bd_v) * TX_BD_NUM,
 278                                   priv->tx_bd_v,
 279                                   priv->tx_bd_p);
 280 }
 281
 282 static int nixge_hw_dma_bd_init(struct net_device *ndev)
 283 {
 284         struct nixge_priv *priv = netdev_priv(ndev);
 285         struct sk_buff *skb;
 286         dma_addr_t phys;
 287         u32 cr;
 288         int i;
 289
 290         /* Reset the indexes which are used for accessing the BDs */
 291         priv->tx_bd_ci = 0;
 292         priv->tx_bd_tail = 0;
 293         priv->rx_bd_ci = 0;
 294
 295         /* Allocate the Tx and Rx buffer descriptors. */
 296         priv->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 297                                            sizeof(*priv->tx_bd_v) * TX_BD_NUM,
 298                                            &priv->tx_bd_p, GFP_KERNEL);
 299         if (!priv->tx_bd_v)
 300                 goto out;
 301
 302         priv->tx_skb = devm_kcalloc(ndev->dev.parent,
 303                                     TX_BD_NUM, sizeof(*priv->tx_skb),
 304                                     GFP_KERNEL);
 305         if (!priv->tx_skb)
 306                 goto out;
 307
 308         priv->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 309                                            sizeof(*priv->rx_bd_v) * RX_BD_NUM,
 310                                            &priv->rx_bd_p, GFP_KERNEL);
 311         if (!priv->rx_bd_v)
 312                 goto out;
 313
 314         for (i = 0; i < TX_BD_NUM; i++) {
 315                 nixge_hw_dma_bd_set_next(&priv->tx_bd_v[i],
 316                                          priv->tx_bd_p +
 317                                          sizeof(*priv->tx_bd_v) *
 318                                          ((i + 1) % TX_BD_NUM));
 319         }
 320
 321         for (i = 0; i < RX_BD_NUM; i++) {
 322                 nixge_hw_dma_bd_set_next(&priv->rx_bd_v[i],
 323                                          priv->rx_bd_p
 324                                          + sizeof(*priv->rx_bd_v) *
 325                                          ((i + 1) % RX_BD_NUM));
 326
 327                 skb = netdev_alloc_skb_ip_align(ndev,
 328                                                 NIXGE_MAX_JUMBO_FRAME_SIZE);
 329                 if (!skb)
 330                         goto out;
 331
 332                 nixge_hw_dma_bd_set_offset(&priv->rx_bd_v[i], (uintptr_t)skb);
 333                 phys = dma_map_single(ndev->dev.parent, skb->data,
 334                                       NIXGE_MAX_JUMBO_FRAME_SIZE,
 335                                       DMA_FROM_DEVICE);
 336
 337                 nixge_hw_dma_bd_set_phys(&priv->rx_bd_v[i], phys);
 338
 339                 priv->rx_bd_v[i].cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
 340         }
 341
 342         /* Start updating the Rx channel control register */
 343         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 344         /* Update the interrupt coalesce count */
 345         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
 346               ((priv->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
 347         /* Update the delay timer count */
 348         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
 349               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 350         /* Enable coalesce, delay timer and error interrupts */
 351         cr |= XAXIDMA_IRQ_ALL_MASK;
 352         /* Write to the Rx channel control register */
 353         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 354
 355         /* Start updating the Tx channel control register */
 356         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 357         /* Update the interrupt coalesce count */
 358         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
 359               ((priv->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
 360         /* Update the delay timer count */
 361         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
 362               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 363         /* Enable coalesce, delay timer and error interrupts */
 364         cr |= XAXIDMA_IRQ_ALL_MASK;
 365         /* Write to the Tx channel control register */
 366         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 367
 368         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
 369          * halted state. This will make the Rx side ready for reception.
 370          */
 371         nixge_dma_write_desc_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
 372         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 373         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
 374                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 375         nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
 376                             (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
 377
 378         /* Write to the RS (Run-stop) bit in the Tx channel control register.
 379          * Tx channel is now ready to run. But only after we write to the
 380          * tail pointer register that the Tx channel will start transmitting.
 381          */
 382         nixge_dma_write_desc_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
 383         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 384         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
 385                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 386
 387         return 0;
 388 out:
 389         nixge_hw_dma_bd_release(ndev);
 390         return -ENOMEM;
 391 }
 392
 393 static void __nixge_device_reset(struct nixge_priv *priv, off_t offset)
 394 {
 395         u32 status;
 396         int err;
 397
 398         /* Reset Axi DMA. This would reset NIXGE Ethernet core as well.
 399          * The reset process of Axi DMA takes a while to complete as all
 400          * pending commands/transfers will be flushed or completed during
 401          * this reset process.
 402          */
 403         nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
 404         err = nixge_dma_poll_timeout(priv, offset, status,
 405                                      !(status & XAXIDMA_CR_RESET_MASK), 10,
 406                                      1000);
 407         if (err)
 408                 netdev_err(priv->ndev, "%s: DMA reset timeout!\n", __func__);
 409 }
 410
 411 static void nixge_device_reset(struct net_device *ndev)
 412 {
 413         struct nixge_priv *priv = netdev_priv(ndev);
 414
 415         __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET);
 416         __nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET);
 417
 418         if (nixge_hw_dma_bd_init(ndev))
 419                 netdev_err(ndev, "%s: descriptor allocation failed\n",
 420                            __func__);
 421
 422         netif_trans_update(ndev);
 423 }
 424
 425 static void nixge_handle_link_change(struct net_device *ndev)
 426 {
 427         struct nixge_priv *priv = netdev_priv(ndev);
 428         struct phy_device *phydev = ndev->phydev;
 429
 430         if (phydev->link != priv->link || phydev->speed != priv->speed ||
 431             phydev->duplex != priv->duplex) {
 432                 priv->link = phydev->link;
 433                 priv->speed = phydev->speed;
 434                 priv->duplex = phydev->duplex;
 435                 phy_print_status(phydev);
 436         }
 437 }
 438
 439 static void nixge_tx_skb_unmap(struct nixge_priv *priv,
 440                                struct nixge_tx_skb *tx_skb)
 441 {
 442         if (tx_skb->mapping) {
 443                 if (tx_skb->mapped_as_page)
 444                         dma_unmap_page(priv->ndev->dev.parent, tx_skb->mapping,
 445                                        tx_skb->size, DMA_TO_DEVICE);
 446                 else
 447                         dma_unmap_single(priv->ndev->dev.parent,
 448                                          tx_skb->mapping,
 449                                          tx_skb->size, DMA_TO_DEVICE);
 450                 tx_skb->mapping = 0;
 451         }
 452
 453         if (tx_skb->skb) {
 454                 dev_kfree_skb_any(tx_skb->skb);
 455                 tx_skb->skb = NULL;
 456         }
 457 }
 458
 459 static void nixge_start_xmit_done(struct net_device *ndev)
 460 {
 461         struct nixge_priv *priv = netdev_priv(ndev);
 462         struct nixge_hw_dma_bd *cur_p;
 463         struct nixge_tx_skb *tx_skb;
 464         unsigned int status = 0;
 465         u32 packets = 0;
 466         u32 size = 0;
 467
 468         cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
 469         tx_skb = &priv->tx_skb[priv->tx_bd_ci];
 470
 471         status = cur_p->status;
 472
 473         while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
 474                 nixge_tx_skb_unmap(priv, tx_skb);
 475                 cur_p->status = 0;
 476
 477                 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 478                 packets++;
 479
 480                 ++priv->tx_bd_ci;
 481                 priv->tx_bd_ci %= TX_BD_NUM;
 482                 cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
 483                 tx_skb = &priv->tx_skb[priv->tx_bd_ci];
 484                 status = cur_p->status;
 485         }
 486
 487         ndev->stats.tx_packets += packets;
 488         ndev->stats.tx_bytes += size;
 489
 490         if (packets)
 491                 netif_wake_queue(ndev);
 492 }
 493
 494 static int nixge_check_tx_bd_space(struct nixge_priv *priv,
 495                                    int num_frag)
 496 {
 497         struct nixge_hw_dma_bd *cur_p;
 498
 499         cur_p = &priv->tx_bd_v[(priv->tx_bd_tail + num_frag) % TX_BD_NUM];
 500         if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
 501                 return NETDEV_TX_BUSY;
 502         return 0;
 503 }
 504
 505 static netdev_tx_t nixge_start_xmit(struct sk_buff *skb,
 506                                     struct net_device *ndev)
 507 {
 508         struct nixge_priv *priv = netdev_priv(ndev);
 509         struct nixge_hw_dma_bd *cur_p;
 510         struct nixge_tx_skb *tx_skb;
 511         dma_addr_t tail_p, cur_phys;
 512         skb_frag_t *frag;
 513         u32 num_frag;
 514         u32 ii;
 515
 516         num_frag = skb_shinfo(skb)->nr_frags;
 517         cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 518         tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 519
 520         if (nixge_check_tx_bd_space(priv, num_frag)) {
 521                 if (!netif_queue_stopped(ndev))
 522                         netif_stop_queue(ndev);
 523                 return NETDEV_TX_OK;
 524         }
 525
 526         cur_phys = dma_map_single(ndev->dev.parent, skb->data,
 527                                   skb_headlen(skb), DMA_TO_DEVICE);
 528         if (dma_mapping_error(ndev->dev.parent, cur_phys))
 529                 goto drop;
 530         nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 531
 532         cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
 533
 534         tx_skb->skb = NULL;
 535         tx_skb->mapping = cur_phys;
 536         tx_skb->size = skb_headlen(skb);
 537         tx_skb->mapped_as_page = false;
 538
 539         for (ii = 0; ii < num_frag; ii++) {
 540                 ++priv->tx_bd_tail;
 541                 priv->tx_bd_tail %= TX_BD_NUM;
 542                 cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 543                 tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 544                 frag = &skb_shinfo(skb)->frags[ii];
 545
 546                 cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
 547                                             skb_frag_size(frag),
 548                                             DMA_TO_DEVICE);
 549                 if (dma_mapping_error(ndev->dev.parent, cur_phys))
 550                         goto frag_err;
 551                 nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 552
 553                 cur_p->cntrl = skb_frag_size(frag);
 554
 555                 tx_skb->skb = NULL;
 556                 tx_skb->mapping = cur_phys;
 557                 tx_skb->size = skb_frag_size(frag);
 558                 tx_skb->mapped_as_page = true;
 559         }
 560
 561         /* last buffer of the frame */
 562         tx_skb->skb = skb;
 563
 564         cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
 565
 566         tail_p = priv->tx_bd_p + sizeof(*priv->tx_bd_v) * priv->tx_bd_tail;
 567         /* Start the transfer */
 568         nixge_dma_write_desc_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
 569         ++priv->tx_bd_tail;
 570         priv->tx_bd_tail %= TX_BD_NUM;
 571
 572         return NETDEV_TX_OK;
 573 frag_err:
 574         for (; ii > 0; ii--) {
 575                 if (priv->tx_bd_tail)
 576                         priv->tx_bd_tail--;
 577                 else
 578                         priv->tx_bd_tail = TX_BD_NUM - 1;
 579
 580                 tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 581                 nixge_tx_skb_unmap(priv, tx_skb);
 582
 583                 cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 584                 cur_p->status = 0;
 585         }
 586         dma_unmap_single(priv->ndev->dev.parent,
 587                          tx_skb->mapping,
 588                          tx_skb->size, DMA_TO_DEVICE);
 589 drop:
 590         ndev->stats.tx_dropped++;
 591         return NETDEV_TX_OK;
 592 }
 593
 594 static int nixge_recv(struct net_device *ndev, int budget)
 595 {
 596         struct nixge_priv *priv = netdev_priv(ndev);
 597         struct sk_buff *skb, *new_skb;
 598         struct nixge_hw_dma_bd *cur_p;
 599         dma_addr_t tail_p = 0, cur_phys = 0;
 600         u32 packets = 0;
 601         u32 length = 0;
 602         u32 size = 0;
 603
 604         cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
 605
 606         while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK &&
 607                 budget > packets)) {
 608                 tail_p = priv->rx_bd_p + sizeof(*priv->rx_bd_v) *
 609                          priv->rx_bd_ci;
 610
 611                 skb = (struct sk_buff *)(uintptr_t)
 612                         nixge_hw_dma_bd_get_addr(cur_p, sw_id_offset);
 613
 614                 length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 615                 if (length > NIXGE_MAX_JUMBO_FRAME_SIZE)
 616                         length = NIXGE_MAX_JUMBO_FRAME_SIZE;
 617
 618                 dma_unmap_single(ndev->dev.parent,
 619                                  nixge_hw_dma_bd_get_addr(cur_p, phys),
 620                                  NIXGE_MAX_JUMBO_FRAME_SIZE,
 621                                  DMA_FROM_DEVICE);
 622
 623                 skb_put(skb, length);
 624
 625                 skb->protocol = eth_type_trans(skb, ndev);
 626                 skb_checksum_none_assert(skb);
 627
 628                 /* For now mark them as CHECKSUM_NONE since
 629                  * we don't have offload capabilities
 630                  */
 631                 skb->ip_summed = CHECKSUM_NONE;
 632
 633                 napi_gro_receive(&priv->napi, skb);
 634
 635                 size += length;
 636                 packets++;
 637
 638                 new_skb = netdev_alloc_skb_ip_align(ndev,
 639                                                     NIXGE_MAX_JUMBO_FRAME_SIZE);
 640                 if (!new_skb)
 641                         return packets;
 642
 643                 cur_phys = dma_map_single(ndev->dev.parent, new_skb->data,
 644                                           NIXGE_MAX_JUMBO_FRAME_SIZE,
 645                                           DMA_FROM_DEVICE);
 646                 if (dma_mapping_error(ndev->dev.parent, cur_phys)) {
 647                         /* FIXME: bail out and clean up */
 648                         netdev_err(ndev, "Failed to map ...\n");
 649                 }
 650                 nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 651                 cur_p->cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
 652                 cur_p->status = 0;
 653                 nixge_hw_dma_bd_set_offset(cur_p, (uintptr_t)new_skb);
 654
 655                 ++priv->rx_bd_ci;
 656                 priv->rx_bd_ci %= RX_BD_NUM;
 657                 cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
 658         }
 659
 660         ndev->stats.rx_packets += packets;
 661         ndev->stats.rx_bytes += size;
 662
 663         if (tail_p)
 664                 nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
 665
 666         return packets;
 667 }
 668
 669 static int nixge_poll(struct napi_struct *napi, int budget)
 670 {
 671         struct nixge_priv *priv = container_of(napi, struct nixge_priv, napi);
 672         int work_done;
 673         u32 status, cr;
 674
 675         work_done = 0;
 676
 677         work_done = nixge_recv(priv->ndev, budget);
 678         if (work_done < budget) {
 679                 napi_complete_done(napi, work_done);
 680                 status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
 681
 682                 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 683                         /* If there's more, reschedule, but clear */
 684                         nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 685                         napi_reschedule(napi);
 686                 } else {
 687                         /* if not, turn on RX IRQs again ... */
 688                         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 689                         cr |= (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
 690                         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 691                 }
 692         }
 693
 694         return work_done;
 695 }
 696
 697 static irqreturn_t nixge_tx_irq(int irq, void *_ndev)
 698 {
 699         struct nixge_priv *priv = netdev_priv(_ndev);
 700         struct net_device *ndev = _ndev;
 701         unsigned int status;
 702         dma_addr_t phys;
 703         u32 cr;
 704
 705         status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
 706         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 707                 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
 708                 nixge_start_xmit_done(priv->ndev);
 709                 goto out;
 710         }
 711         if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
 712                 netdev_err(ndev, "No interrupts asserted in Tx path\n");
 713                 return IRQ_NONE;
 714         }
 715         if (status & XAXIDMA_IRQ_ERROR_MASK) {
 716                 phys = nixge_hw_dma_bd_get_addr(&priv->tx_bd_v[priv->tx_bd_ci],
 717                                                 phys);
 718
 719                 netdev_err(ndev, "DMA Tx error 0x%x\n", status);
 720                 netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
 721
 722                 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 723                 /* Disable coalesce, delay timer and error interrupts */
 724                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 725                 /* Write to the Tx channel control register */
 726                 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 727
 728                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 729                 /* Disable coalesce, delay timer and error interrupts */
 730                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 731                 /* Write to the Rx channel control register */
 732                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 733
 734                 tasklet_schedule(&priv->dma_err_tasklet);
 735                 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
 736         }
 737 out:
 738         return IRQ_HANDLED;
 739 }
 740
 741 static irqreturn_t nixge_rx_irq(int irq, void *_ndev)
 742 {
 743         struct nixge_priv *priv = netdev_priv(_ndev);
 744         struct net_device *ndev = _ndev;
 745         unsigned int status;
 746         dma_addr_t phys;
 747         u32 cr;
 748
 749         status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
 750         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 751                 /* Turn of IRQs because NAPI */
 752                 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 753                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 754                 cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
 755                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 756
 757                 if (napi_schedule_prep(&priv->napi))
 758                         __napi_schedule(&priv->napi);
 759                 goto out;
 760         }
 761         if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
 762                 netdev_err(ndev, "No interrupts asserted in Rx path\n");
 763                 return IRQ_NONE;
 764         }
 765         if (status & XAXIDMA_IRQ_ERROR_MASK) {
 766                 phys = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[priv->rx_bd_ci],
 767                                                 phys);
 768                 netdev_err(ndev, "DMA Rx error 0x%x\n", status);
 769                 netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
 770
 771                 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 772                 /* Disable coalesce, delay timer and error interrupts */
 773                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 774                 /* Finally write to the Tx channel control register */
 775                 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 776
 777                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 778                 /* Disable coalesce, delay timer and error interrupts */
 779                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 780                 /* write to the Rx channel control register */
 781                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 782
 783                 tasklet_schedule(&priv->dma_err_tasklet);
 784                 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 785         }
 786 out:
 787         return IRQ_HANDLED;
 788 }
 789
 790 static void nixge_dma_err_handler(struct tasklet_struct *t)
 791 {
 792         struct nixge_priv *lp = from_tasklet(lp, t, dma_err_tasklet);
 793         struct nixge_hw_dma_bd *cur_p;
 794         struct nixge_tx_skb *tx_skb;
 795         u32 cr, i;
 796
 797         __nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
 798         __nixge_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
 799
 800         for (i = 0; i < TX_BD_NUM; i++) {
 801                 cur_p = &lp->tx_bd_v[i];
 802                 tx_skb = &lp->tx_skb[i];
 803                 nixge_tx_skb_unmap(lp, tx_skb);
 804
 805                 nixge_hw_dma_bd_set_phys(cur_p, 0);
 806                 cur_p->cntrl = 0;
 807                 cur_p->status = 0;
 808                 nixge_hw_dma_bd_set_offset(cur_p, 0);
 809         }
 810
 811         for (i = 0; i < RX_BD_NUM; i++) {
 812                 cur_p = &lp->rx_bd_v[i];
 813                 cur_p->status = 0;
 814         }
 815
 816         lp->tx_bd_ci = 0;
 817         lp->tx_bd_tail = 0;
 818         lp->rx_bd_ci = 0;
 819
 820         /* Start updating the Rx channel control register */
 821         cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
 822         /* Update the interrupt coalesce count */
 823         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
 824               (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
 825         /* Update the delay timer count */
 826         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
 827               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 828         /* Enable coalesce, delay timer and error interrupts */
 829         cr |= XAXIDMA_IRQ_ALL_MASK;
 830         /* Finally write to the Rx channel control register */
 831         nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr);
 832
 833         /* Start updating the Tx channel control register */
 834         cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
 835         /* Update the interrupt coalesce count */
 836         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
 837               (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
 838         /* Update the delay timer count */
 839         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
 840               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 841         /* Enable coalesce, delay timer and error interrupts */
 842         cr |= XAXIDMA_IRQ_ALL_MASK;
 843         /* Finally write to the Tx channel control register */
 844         nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr);
 845
 846         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
 847          * halted state. This will make the Rx side ready for reception.
 848          */
 849         nixge_dma_write_desc_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
 850         cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
 851         nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
 852                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 853         nixge_dma_write_desc_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
 854                             (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
 855
 856         /* Write to the RS (Run-stop) bit in the Tx channel control register.
 857          * Tx channel is now ready to run. But only after we write to the
 858          * tail pointer register that the Tx channel will start transmitting
 859          */
 860         nixge_dma_write_desc_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
 861         cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
 862         nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
 863                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 864 }
 865
 866 static int nixge_open(struct net_device *ndev)
 867 {
 868         struct nixge_priv *priv = netdev_priv(ndev);
 869         struct phy_device *phy;
 870         int ret;
 871
 872         nixge_device_reset(ndev);
 873
 874         phy = of_phy_connect(ndev, priv->phy_node,
 875                              &nixge_handle_link_change, 0, priv->phy_mode);
 876         if (!phy)
 877                 return -ENODEV;
 878
 879         phy_start(phy);
 880
 881         /* Enable tasklets for Axi DMA error handling */
 882         tasklet_setup(&priv->dma_err_tasklet, nixge_dma_err_handler);
 883
 884         napi_enable(&priv->napi);
 885
 886         /* Enable interrupts for Axi DMA Tx */
 887         ret = request_irq(priv->tx_irq, nixge_tx_irq, 0, ndev->name, ndev);
 888         if (ret)
 889                 goto err_tx_irq;
 890         /* Enable interrupts for Axi DMA Rx */
 891         ret = request_irq(priv->rx_irq, nixge_rx_irq, 0, ndev->name, ndev);
 892         if (ret)
 893                 goto err_rx_irq;
 894
 895         netif_start_queue(ndev);
 896
 897         return 0;
 898
 899 err_rx_irq:
 900         free_irq(priv->tx_irq, ndev);
 901 err_tx_irq:
 902         phy_stop(phy);
 903         phy_disconnect(phy);
 904         tasklet_kill(&priv->dma_err_tasklet);
 905         netdev_err(ndev, "request_irq() failed\n");
 906         return ret;
 907 }
 908
 909 static int nixge_stop(struct net_device *ndev)
 910 {
 911         struct nixge_priv *priv = netdev_priv(ndev);
 912         u32 cr;
 913
 914         netif_stop_queue(ndev);
 915         napi_disable(&priv->napi);
 916
 917         if (ndev->phydev) {
 918                 phy_stop(ndev->phydev);
 919                 phy_disconnect(ndev->phydev);
 920         }
 921
 922         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 923         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
 924                             cr & (~XAXIDMA_CR_RUNSTOP_MASK));
 925         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 926         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
 927                             cr & (~XAXIDMA_CR_RUNSTOP_MASK));
 928
 929         tasklet_kill(&priv->dma_err_tasklet);
 930
 931         free_irq(priv->tx_irq, ndev);
 932         free_irq(priv->rx_irq, ndev);
 933
 934         nixge_hw_dma_bd_release(ndev);
 935
 936         return 0;
 937 }
 938
 939 static int nixge_change_mtu(struct net_device *ndev, int new_mtu)
 940 {
 941         if (netif_running(ndev))
 942                 return -EBUSY;
 943
 944         if ((new_mtu + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE) >
 945              NIXGE_MAX_JUMBO_FRAME_SIZE)
 946                 return -EINVAL;
 947
 948         ndev->mtu = new_mtu;
 949
 950         return 0;
 951 }
 952
 953 static s32 __nixge_hw_set_mac_address(struct net_device *ndev)
 954 {
 955         struct nixge_priv *priv = netdev_priv(ndev);
 956
 957         nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
 958                              (ndev->dev_addr[2]) << 24 |
 959                              (ndev->dev_addr[3] << 16) |
 960                              (ndev->dev_addr[4] << 8) |
 961                              (ndev->dev_addr[5] << 0));
 962
 963         nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,
 964                              (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));
 965
 966         return 0;
 967 }
 968
 969 static int nixge_net_set_mac_address(struct net_device *ndev, void *p)
 970 {
 971         int err;
 972
 973         err = eth_mac_addr(ndev, p);
 974         if (!err)
 975                 __nixge_hw_set_mac_address(ndev);
 976
 977         return err;
 978 }
 979
 980 static const struct net_device_ops nixge_netdev_ops = {
 981         .ndo_open = nixge_open,
 982         .ndo_stop = nixge_stop,
 983         .ndo_start_xmit = nixge_start_xmit,
 984         .ndo_change_mtu = nixge_change_mtu,
 985         .ndo_set_mac_address = nixge_net_set_mac_address,
 986         .ndo_validate_addr = eth_validate_addr,
 987 };
 988
 989 static void nixge_ethtools_get_drvinfo(struct net_device *ndev,
 990                                        struct ethtool_drvinfo *ed)
 991 {
 992         strlcpy(ed->driver, "nixge", sizeof(ed->driver));
 993         strlcpy(ed->bus_info, "platform", sizeof(ed->bus_info));
 994 }
 995
 996 static int
 997 nixge_ethtools_get_coalesce(struct net_device *ndev,
 998                             struct ethtool_coalesce *ecoalesce,
 999                             struct kernel_ethtool_coalesce *kernel_coal,
1000                             struct netlink_ext_ack *extack)
1001 {
1002         struct nixge_priv *priv = netdev_priv(ndev);
1003         u32 regval = 0;
1004
1005         regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
1006         ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1007                                              >> XAXIDMA_COALESCE_SHIFT;
1008         regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
1009         ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1010                                              >> XAXIDMA_COALESCE_SHIFT;
1011         return 0;
1012 }
1013
1014 static int
1015 nixge_ethtools_set_coalesce(struct net_device *ndev,
1016                             struct ethtool_coalesce *ecoalesce,
1017                             struct kernel_ethtool_coalesce *kernel_coal,
1018                             struct netlink_ext_ack *extack)
1019 {
1020         struct nixge_priv *priv = netdev_priv(ndev);
1021
1022         if (netif_running(ndev)) {
1023                 netdev_err(ndev,
1024                            "Please stop netif before applying configuration\n");
1025                 return -EBUSY;
1026         }
1027
1028         if (ecoalesce->rx_max_coalesced_frames)
1029                 priv->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1030         if (ecoalesce->tx_max_coalesced_frames)
1031                 priv->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1032
1033         return 0;
1034 }
1035
1036 static int nixge_ethtools_set_phys_id(struct net_device *ndev,
1037                                       enum ethtool_phys_id_state state)
1038 {
1039         struct nixge_priv *priv = netdev_priv(ndev);
1040         u32 ctrl;
1041
1042         ctrl = nixge_ctrl_read_reg(priv, NIXGE_REG_LED_CTL);
1043         switch (state) {
1044         case ETHTOOL_ID_ACTIVE:
1045                 ctrl |= NIXGE_ID_LED_CTL_EN;
1046                 /* Enable identification LED override*/
1047                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1048                 return 2;
1049
1050         case ETHTOOL_ID_ON:
1051                 ctrl |= NIXGE_ID_LED_CTL_VAL;
1052                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1053                 break;
1054
1055         case ETHTOOL_ID_OFF:
1056                 ctrl &= ~NIXGE_ID_LED_CTL_VAL;
1057                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1058                 break;
1059
1060         case ETHTOOL_ID_INACTIVE:
1061                 /* Restore LED settings */
1062                 ctrl &= ~NIXGE_ID_LED_CTL_EN;
1063                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1064                 break;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static const struct ethtool_ops nixge_ethtool_ops = {
1071         .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES,
1072         .get_drvinfo    = nixge_ethtools_get_drvinfo,
1073         .get_coalesce   = nixge_ethtools_get_coalesce,
1074         .set_coalesce   = nixge_ethtools_set_coalesce,
1075         .set_phys_id    = nixge_ethtools_set_phys_id,
1076         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1077         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1078         .get_link               = ethtool_op_get_link,
1079 };
1080
1081 static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg)
1082 {
1083         struct nixge_priv *priv = bus->priv;
1084         u32 status, tmp;
1085         int err;
1086         u16 device;
1087
1088         if (reg & MII_ADDR_C45) {
1089                 device = (reg >> 16) & 0x1f;
1090
1091                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1092
1093                 tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
1094                         | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1095
1096                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1097                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1098
1099                 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1100                                               !status, 10, 1000);
1101                 if (err) {
1102                         dev_err(priv->dev, "timeout setting address");
1103                         return err;
1104                 }
1105
1106                 tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
1107                         NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1108         } else {
1109                 device = reg & 0x1f;
1110
1111                 tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
1112                         NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1113         }
1114
1115         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1116         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1117
1118         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1119                                       !status, 10, 1000);
1120         if (err) {
1121                 dev_err(priv->dev, "timeout setting read command");
1122                 return err;
1123         }
1124
1125         status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1126
1127         return status;
1128 }
1129
1130 static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
1131 {
1132         struct nixge_priv *priv = bus->priv;
1133         u32 status, tmp;
1134         u16 device;
1135         int err;
1136
1137         if (reg & MII_ADDR_C45) {
1138                 device = (reg >> 16) & 0x1f;
1139
1140                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1141
1142                 tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
1143                         | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1144
1145                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1146                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1147
1148                 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1149                                               !status, 10, 1000);
1150                 if (err) {
1151                         dev_err(priv->dev, "timeout setting address");
1152                         return err;
1153                 }
1154
1155                 tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE)
1156                         | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1157
1158                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1159                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1160                 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1161                                               !status, 10, 1000);
1162                 if (err)
1163                         dev_err(priv->dev, "timeout setting write command");
1164         } else {
1165                 device = reg & 0x1f;
1166
1167                 tmp = NIXGE_MDIO_CLAUSE22 |
1168                         NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
1169                         NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1170
1171                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1172                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1173                 nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1174
1175                 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1176                                               !status, 10, 1000);
1177                 if (err)
1178                         dev_err(priv->dev, "timeout setting write command");
1179         }
1180
1181         return err;
1182 }
1183
1184 static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
1185 {
1186         struct mii_bus *bus;
1187
1188         bus = devm_mdiobus_alloc(priv->dev);
1189         if (!bus)
1190                 return -ENOMEM;
1191
1192         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
1193         bus->priv = priv;
1194         bus->name = "nixge_mii_bus";
1195         bus->read = nixge_mdio_read;
1196         bus->write = nixge_mdio_write;
1197         bus->parent = priv->dev;
1198
1199         priv->mii_bus = bus;
1200
1201         return of_mdiobus_register(bus, np);
1202 }
1203
1204 static void *nixge_get_nvmem_address(struct device *dev)
1205 {
1206         struct nvmem_cell *cell;
1207         size_t cell_size;
1208         char *mac;
1209
1210         cell = nvmem_cell_get(dev, "address");
1211         if (IS_ERR(cell))
1212                 return NULL;
1213
1214         mac = nvmem_cell_read(cell, &cell_size);
1215         nvmem_cell_put(cell);
1216
1217         return mac;
1218 }
1219
1220 /* Match table for of_platform binding */
1221 static const struct of_device_id nixge_dt_ids[] = {
1222         { .compatible = "ni,xge-enet-2.00", .data = (void *)NIXGE_V2 },
1223         { .compatible = "ni,xge-enet-3.00", .data = (void *)NIXGE_V3 },
1224         {},
1225 };
1226 MODULE_DEVICE_TABLE(of, nixge_dt_ids);
1227
1228 static int nixge_of_get_resources(struct platform_device *pdev)
1229 {
1230         const struct of_device_id *of_id;
1231         enum nixge_version version;
1232         struct net_device *ndev;
1233         struct nixge_priv *priv;
1234
1235         ndev = platform_get_drvdata(pdev);
1236         priv = netdev_priv(ndev);
1237         of_id = of_match_node(nixge_dt_ids, pdev->dev.of_node);
1238         if (!of_id)
1239                 return -ENODEV;
1240
1241         version = (enum nixge_version)of_id->data;
1242         if (version <= NIXGE_V2)
1243                 priv->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1244         else
1245                 priv->dma_regs = devm_platform_ioremap_resource_byname(pdev, "dma");
1246         if (IS_ERR(priv->dma_regs)) {
1247                 netdev_err(ndev, "failed to map dma regs\n");
1248                 return PTR_ERR(priv->dma_regs);
1249         }
1250         if (version <= NIXGE_V2)
1251                 priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
1252         else
1253                 priv->ctrl_regs = devm_platform_ioremap_resource_byname(pdev, "ctrl");
1254         if (IS_ERR(priv->ctrl_regs)) {
1255                 netdev_err(ndev, "failed to map ctrl regs\n");
1256                 return PTR_ERR(priv->ctrl_regs);
1257         }
1258         return 0;
1259 }
1260
1261 static int nixge_probe(struct platform_device *pdev)
1262 {
1263         struct device_node *mn, *phy_node;
1264         struct nixge_priv *priv;
1265         struct net_device *ndev;
1266         const u8 *mac_addr;
1267         int err;
1268
1269         ndev = alloc_etherdev(sizeof(*priv));
1270         if (!ndev)
1271                 return -ENOMEM;
1272
1273         platform_set_drvdata(pdev, ndev);
1274         SET_NETDEV_DEV(ndev, &pdev->dev);
1275
1276         ndev->features = NETIF_F_SG;
1277         ndev->netdev_ops = &nixge_netdev_ops;
1278         ndev->ethtool_ops = &nixge_ethtool_ops;
1279
1280         /* MTU range: 64 - 9000 */
1281         ndev->min_mtu = 64;
1282         ndev->max_mtu = NIXGE_JUMBO_MTU;
1283
1284         mac_addr = nixge_get_nvmem_address(&pdev->dev);
1285         if (mac_addr && is_valid_ether_addr(mac_addr)) {
1286                 eth_hw_addr_set(ndev, mac_addr);
1287                 kfree(mac_addr);
1288         } else {
1289                 eth_hw_addr_random(ndev);
1290         }
1291
1292         priv = netdev_priv(ndev);
1293         priv->ndev = ndev;
1294         priv->dev = &pdev->dev;
1295
1296         netif_napi_add(ndev, &priv->napi, nixge_poll, NAPI_POLL_WEIGHT);
1297         err = nixge_of_get_resources(pdev);
1298         if (err)
1299                 goto free_netdev;
1300         __nixge_hw_set_mac_address(ndev);
1301
1302         priv->tx_irq = platform_get_irq_byname(pdev, "tx");
1303         if (priv->tx_irq < 0) {
1304                 netdev_err(ndev, "could not find 'tx' irq");
1305                 err = priv->tx_irq;
1306                 goto free_netdev;
1307         }
1308
1309         priv->rx_irq = platform_get_irq_byname(pdev, "rx");
1310         if (priv->rx_irq < 0) {
1311                 netdev_err(ndev, "could not find 'rx' irq");
1312                 err = priv->rx_irq;
1313                 goto free_netdev;
1314         }
1315
1316         priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1317         priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1318
1319         mn = of_get_child_by_name(pdev->dev.of_node, "mdio");
1320         if (mn) {
1321                 err = nixge_mdio_setup(priv, mn);
1322                 of_node_put(mn);
1323                 if (err) {
1324                         netdev_err(ndev, "error registering mdio bus");
1325                         goto free_netdev;
1326                 }
1327         }
1328
1329         err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode);
1330         if (err) {
1331                 netdev_err(ndev, "not find \"phy-mode\" property\n");
1332                 goto unregister_mdio;
1333         }
1334
1335         phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1336         if (!phy_node && of_phy_is_fixed_link(pdev->dev.of_node)) {
1337                 err = of_phy_register_fixed_link(pdev->dev.of_node);
1338                 if (err < 0) {
1339                         netdev_err(ndev, "broken fixed-link specification\n");
1340                         goto unregister_mdio;
1341                 }
1342                 phy_node = of_node_get(pdev->dev.of_node);
1343         }
1344         priv->phy_node = phy_node;
1345
1346         err = register_netdev(priv->ndev);
1347         if (err) {
1348                 netdev_err(ndev, "register_netdev() error (%i)\n", err);
1349                 goto free_phy;
1350         }
1351
1352         return 0;
1353
1354 free_phy:
1355         if (of_phy_is_fixed_link(pdev->dev.of_node))
1356                 of_phy_deregister_fixed_link(pdev->dev.of_node);
1357         of_node_put(phy_node);
1358
1359 unregister_mdio:
1360         if (priv->mii_bus)
1361                 mdiobus_unregister(priv->mii_bus);
1362
1363 free_netdev:
1364         free_netdev(ndev);
1365
1366         return err;
1367 }
1368
1369 static int nixge_remove(struct platform_device *pdev)
1370 {
1371         struct net_device *ndev = platform_get_drvdata(pdev);
1372         struct nixge_priv *priv = netdev_priv(ndev);
1373
1374         unregister_netdev(ndev);
1375
1376         if (of_phy_is_fixed_link(pdev->dev.of_node))
1377                 of_phy_deregister_fixed_link(pdev->dev.of_node);
1378         of_node_put(priv->phy_node);
1379
1380         if (priv->mii_bus)
1381                 mdiobus_unregister(priv->mii_bus);
1382
1383         free_netdev(ndev);
1384
1385         return 0;
1386 }
1387
1388 static struct platform_driver nixge_driver = {
1389         .probe          = nixge_probe,
1390         .remove         = nixge_remove,
1391         .driver         = {
1392                 .name           = "nixge",
1393                 .of_match_table = of_match_ptr(nixge_dt_ids),
1394         },
1395 };
1396 module_platform_driver(nixge_driver);
1397
1398 MODULE_LICENSE("GPL v2");
1399 MODULE_DESCRIPTION("National Instruments XGE Management MAC");
1400 MODULE_AUTHOR("Moritz Fischer <[email protected]>");