drivers/clocksource/arm_arch_timer.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/clocksource/arm_arch_timer.c
   4  *
   5  *  Copyright (C) 2011 ARM Ltd.
   6  *  All Rights Reserved
   7  */
   8
   9 #define pr_fmt(fmt)     "arch_timer: " fmt
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/device.h>
  14 #include <linux/smp.h>
  15 #include <linux/cpu.h>
  16 #include <linux/cpu_pm.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/clocksource_ids.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_address.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/sched/clock.h>
  26 #include <linux/sched_clock.h>
  27 #include <linux/acpi.h>
  28 #include <linux/arm-smccc.h>
  29 #include <linux/ptp_kvm.h>
  30
  31 #include <asm/arch_timer.h>
  32 #include <asm/virt.h>
  33
  34 #include <clocksource/arm_arch_timer.h>
  35
  36 #define CNTTIDR         0x08
  37 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
  38
  39 #define CNTACR(n)       (0x40 + ((n) * 4))
  40 #define CNTACR_RPCT     BIT(0)
  41 #define CNTACR_RVCT     BIT(1)
  42 #define CNTACR_RFRQ     BIT(2)
  43 #define CNTACR_RVOFF    BIT(3)
  44 #define CNTACR_RWVT     BIT(4)
  45 #define CNTACR_RWPT     BIT(5)
  46
  47 #define CNTVCT_LO       0x00
  48 #define CNTPCT_LO       0x08
  49 #define CNTFRQ          0x10
  50 #define CNTP_CVAL_LO    0x20
  51 #define CNTP_CTL        0x2c
  52 #define CNTV_CVAL_LO    0x30
  53 #define CNTV_CTL        0x3c
  54
  55 /*
  56  * The minimum amount of time a generic counter is guaranteed to not roll over
  57  * (40 years)
  58  */
  59 #define MIN_ROLLOVER_SECS       (40ULL * 365 * 24 * 3600)
  60
  61 static unsigned arch_timers_present __initdata;
  62
  63 struct arch_timer {
  64         void __iomem *base;
  65         struct clock_event_device evt;
  66 };
  67
  68 static struct arch_timer *arch_timer_mem __ro_after_init;
  69
  70 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
  71
  72 static u32 arch_timer_rate __ro_after_init;
  73 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
  74
  75 static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
  76         [ARCH_TIMER_PHYS_SECURE_PPI]    = "sec-phys",
  77         [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
  78         [ARCH_TIMER_VIRT_PPI]           = "virt",
  79         [ARCH_TIMER_HYP_PPI]            = "hyp-phys",
  80         [ARCH_TIMER_HYP_VIRT_PPI]       = "hyp-virt",
  81 };
  82
  83 static struct clock_event_device __percpu *arch_timer_evt;
  84
  85 static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
  86 static bool arch_timer_c3stop __ro_after_init;
  87 static bool arch_timer_mem_use_virtual __ro_after_init;
  88 static bool arch_counter_suspend_stop __ro_after_init;
  89 #ifdef CONFIG_GENERIC_GETTIMEOFDAY
  90 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
  91 #else
  92 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
  93 #endif /* CONFIG_GENERIC_GETTIMEOFDAY */
  94
  95 static cpumask_t evtstrm_available = CPU_MASK_NONE;
  96 static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
  97
  98 static int __init early_evtstrm_cfg(char *buf)
  99 {
 100         return strtobool(buf, &evtstrm_enable);
 101 }
 102 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
 103
 104 /*
 105  * Makes an educated guess at a valid counter width based on the Generic Timer
 106  * specification. Of note:
 107  *   1) the system counter is at least 56 bits wide
 108  *   2) a roll-over time of not less than 40 years
 109  *
 110  * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
 111  */
 112 static int arch_counter_get_width(void)
 113 {
 114         u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_rate;
 115
 116         /* guarantee the returned width is within the valid range */
 117         return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);
 118 }
 119
 120 /*
 121  * Architected system timer support.
 122  */
 123
 124 static __always_inline
 125 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
 126                           struct clock_event_device *clk)
 127 {
 128         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 129                 struct arch_timer *timer = to_arch_timer(clk);
 130                 switch (reg) {
 131                 case ARCH_TIMER_REG_CTRL:
 132                         writel_relaxed((u32)val, timer->base + CNTP_CTL);
 133                         break;
 134                 case ARCH_TIMER_REG_CVAL:
 135                         /*
 136                          * Not guaranteed to be atomic, so the timer
 137                          * must be disabled at this point.
 138                          */
 139                         writeq_relaxed(val, timer->base + CNTP_CVAL_LO);
 140                         break;
 141                 default:
 142                         BUILD_BUG();
 143                 }
 144         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 145                 struct arch_timer *timer = to_arch_timer(clk);
 146                 switch (reg) {
 147                 case ARCH_TIMER_REG_CTRL:
 148                         writel_relaxed((u32)val, timer->base + CNTV_CTL);
 149                         break;
 150                 case ARCH_TIMER_REG_CVAL:
 151                         /* Same restriction as above */
 152                         writeq_relaxed(val, timer->base + CNTV_CVAL_LO);
 153                         break;
 154                 default:
 155                         BUILD_BUG();
 156                 }
 157         } else {
 158                 arch_timer_reg_write_cp15(access, reg, val);
 159         }
 160 }
 161
 162 static __always_inline
 163 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
 164                         struct clock_event_device *clk)
 165 {
 166         u32 val;
 167
 168         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 169                 struct arch_timer *timer = to_arch_timer(clk);
 170                 switch (reg) {
 171                 case ARCH_TIMER_REG_CTRL:
 172                         val = readl_relaxed(timer->base + CNTP_CTL);
 173                         break;
 174                 default:
 175                         BUILD_BUG();
 176                 }
 177         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 178                 struct arch_timer *timer = to_arch_timer(clk);
 179                 switch (reg) {
 180                 case ARCH_TIMER_REG_CTRL:
 181                         val = readl_relaxed(timer->base + CNTV_CTL);
 182                         break;
 183                 default:
 184                         BUILD_BUG();
 185                 }
 186         } else {
 187                 val = arch_timer_reg_read_cp15(access, reg);
 188         }
 189
 190         return val;
 191 }
 192
 193 static notrace u64 arch_counter_get_cntpct_stable(void)
 194 {
 195         return __arch_counter_get_cntpct_stable();
 196 }
 197
 198 static notrace u64 arch_counter_get_cntpct(void)
 199 {
 200         return __arch_counter_get_cntpct();
 201 }
 202
 203 static notrace u64 arch_counter_get_cntvct_stable(void)
 204 {
 205         return __arch_counter_get_cntvct_stable();
 206 }
 207
 208 static notrace u64 arch_counter_get_cntvct(void)
 209 {
 210         return __arch_counter_get_cntvct();
 211 }
 212
 213 /*
 214  * Default to cp15 based access because arm64 uses this function for
 215  * sched_clock() before DT is probed and the cp15 method is guaranteed
 216  * to exist on arm64. arm doesn't use this before DT is probed so even
 217  * if we don't have the cp15 accessors we won't have a problem.
 218  */
 219 u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
 220 EXPORT_SYMBOL_GPL(arch_timer_read_counter);
 221
 222 static u64 arch_counter_read(struct clocksource *cs)
 223 {
 224         return arch_timer_read_counter();
 225 }
 226
 227 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
 228 {
 229         return arch_timer_read_counter();
 230 }
 231
 232 static struct clocksource clocksource_counter = {
 233         .name   = "arch_sys_counter",
 234         .id     = CSID_ARM_ARCH_COUNTER,
 235         .rating = 400,
 236         .read   = arch_counter_read,
 237         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 238 };
 239
 240 static struct cyclecounter cyclecounter __ro_after_init = {
 241         .read   = arch_counter_read_cc,
 242 };
 243
 244 struct ate_acpi_oem_info {
 245         char oem_id[ACPI_OEM_ID_SIZE + 1];
 246         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
 247         u32 oem_revision;
 248 };
 249
 250 #ifdef CONFIG_FSL_ERRATUM_A008585
 251 /*
 252  * The number of retries is an arbitrary value well beyond the highest number
 253  * of iterations the loop has been observed to take.
 254  */
 255 #define __fsl_a008585_read_reg(reg) ({                  \
 256         u64 _old, _new;                                 \
 257         int _retries = 200;                             \
 258                                                         \
 259         do {                                            \
 260                 _old = read_sysreg(reg);                \
 261                 _new = read_sysreg(reg);                \
 262                 _retries--;                             \
 263         } while (unlikely(_old != _new) && _retries);   \
 264                                                         \
 265         WARN_ON_ONCE(!_retries);                        \
 266         _new;                                           \
 267 })
 268
 269 static u64 notrace fsl_a008585_read_cntpct_el0(void)
 270 {
 271         return __fsl_a008585_read_reg(cntpct_el0);
 272 }
 273
 274 static u64 notrace fsl_a008585_read_cntvct_el0(void)
 275 {
 276         return __fsl_a008585_read_reg(cntvct_el0);
 277 }
 278 #endif
 279
 280 #ifdef CONFIG_HISILICON_ERRATUM_161010101
 281 /*
 282  * Verify whether the value of the second read is larger than the first by
 283  * less than 32 is the only way to confirm the value is correct, so clear the
 284  * lower 5 bits to check whether the difference is greater than 32 or not.
 285  * Theoretically the erratum should not occur more than twice in succession
 286  * when reading the system counter, but it is possible that some interrupts
 287  * may lead to more than twice read errors, triggering the warning, so setting
 288  * the number of retries far beyond the number of iterations the loop has been
 289  * observed to take.
 290  */
 291 #define __hisi_161010101_read_reg(reg) ({                               \
 292         u64 _old, _new;                                         \
 293         int _retries = 50;                                      \
 294                                                                 \
 295         do {                                                    \
 296                 _old = read_sysreg(reg);                        \
 297                 _new = read_sysreg(reg);                        \
 298                 _retries--;                                     \
 299         } while (unlikely((_new - _old) >> 5) && _retries);     \
 300                                                                 \
 301         WARN_ON_ONCE(!_retries);                                \
 302         _new;                                                   \
 303 })
 304
 305 static u64 notrace hisi_161010101_read_cntpct_el0(void)
 306 {
 307         return __hisi_161010101_read_reg(cntpct_el0);
 308 }
 309
 310 static u64 notrace hisi_161010101_read_cntvct_el0(void)
 311 {
 312         return __hisi_161010101_read_reg(cntvct_el0);
 313 }
 314
 315 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
 316         /*
 317          * Note that trailing spaces are required to properly match
 318          * the OEM table information.
 319          */
 320         {
 321                 .oem_id         = "HISI  ",
 322                 .oem_table_id   = "HIP05   ",
 323                 .oem_revision   = 0,
 324         },
 325         {
 326                 .oem_id         = "HISI  ",
 327                 .oem_table_id   = "HIP06   ",
 328                 .oem_revision   = 0,
 329         },
 330         {
 331                 .oem_id         = "HISI  ",
 332                 .oem_table_id   = "HIP07   ",
 333                 .oem_revision   = 0,
 334         },
 335         { /* Sentinel indicating the end of the OEM array */ },
 336 };
 337 #endif
 338
 339 #ifdef CONFIG_ARM64_ERRATUM_858921
 340 static u64 notrace arm64_858921_read_cntpct_el0(void)
 341 {
 342         u64 old, new;
 343
 344         old = read_sysreg(cntpct_el0);
 345         new = read_sysreg(cntpct_el0);
 346         return (((old ^ new) >> 32) & 1) ? old : new;
 347 }
 348
 349 static u64 notrace arm64_858921_read_cntvct_el0(void)
 350 {
 351         u64 old, new;
 352
 353         old = read_sysreg(cntvct_el0);
 354         new = read_sysreg(cntvct_el0);
 355         return (((old ^ new) >> 32) & 1) ? old : new;
 356 }
 357 #endif
 358
 359 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
 360 /*
 361  * The low bits of the counter registers are indeterminate while bit 10 or
 362  * greater is rolling over. Since the counter value can jump both backward
 363  * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
 364  * with all ones or all zeros in the low bits. Bound the loop by the maximum
 365  * number of CPU cycles in 3 consecutive 24 MHz counter periods.
 366  */
 367 #define __sun50i_a64_read_reg(reg) ({                                   \
 368         u64 _val;                                                       \
 369         int _retries = 150;                                             \
 370                                                                         \
 371         do {                                                            \
 372                 _val = read_sysreg(reg);                                \
 373                 _retries--;                                             \
 374         } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries);        \
 375                                                                         \
 376         WARN_ON_ONCE(!_retries);                                        \
 377         _val;                                                           \
 378 })
 379
 380 static u64 notrace sun50i_a64_read_cntpct_el0(void)
 381 {
 382         return __sun50i_a64_read_reg(cntpct_el0);
 383 }
 384
 385 static u64 notrace sun50i_a64_read_cntvct_el0(void)
 386 {
 387         return __sun50i_a64_read_reg(cntvct_el0);
 388 }
 389 #endif
 390
 391 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 392 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
 393 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
 394
 395 static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
 396
 397 static void erratum_set_next_event_generic(const int access, unsigned long evt,
 398                                                 struct clock_event_device *clk)
 399 {
 400         unsigned long ctrl;
 401         u64 cval;
 402
 403         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 404         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 405         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 406
 407         if (access == ARCH_TIMER_PHYS_ACCESS) {
 408                 cval = evt + arch_counter_get_cntpct_stable();
 409                 write_sysreg(cval, cntp_cval_el0);
 410         } else {
 411                 cval = evt + arch_counter_get_cntvct_stable();
 412                 write_sysreg(cval, cntv_cval_el0);
 413         }
 414
 415         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 416 }
 417
 418 static __maybe_unused int erratum_set_next_event_virt(unsigned long evt,
 419                                             struct clock_event_device *clk)
 420 {
 421         erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 422         return 0;
 423 }
 424
 425 static __maybe_unused int erratum_set_next_event_phys(unsigned long evt,
 426                                             struct clock_event_device *clk)
 427 {
 428         erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 429         return 0;
 430 }
 431
 432 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
 433 #ifdef CONFIG_FSL_ERRATUM_A008585
 434         {
 435                 .match_type = ate_match_dt,
 436                 .id = "fsl,erratum-a008585",
 437                 .desc = "Freescale erratum a005858",
 438                 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
 439                 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
 440                 .set_next_event_phys = erratum_set_next_event_phys,
 441                 .set_next_event_virt = erratum_set_next_event_virt,
 442         },
 443 #endif
 444 #ifdef CONFIG_HISILICON_ERRATUM_161010101
 445         {
 446                 .match_type = ate_match_dt,
 447                 .id = "hisilicon,erratum-161010101",
 448                 .desc = "HiSilicon erratum 161010101",
 449                 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
 450                 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
 451                 .set_next_event_phys = erratum_set_next_event_phys,
 452                 .set_next_event_virt = erratum_set_next_event_virt,
 453         },
 454         {
 455                 .match_type = ate_match_acpi_oem_info,
 456                 .id = hisi_161010101_oem_info,
 457                 .desc = "HiSilicon erratum 161010101",
 458                 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
 459                 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
 460                 .set_next_event_phys = erratum_set_next_event_phys,
 461                 .set_next_event_virt = erratum_set_next_event_virt,
 462         },
 463 #endif
 464 #ifdef CONFIG_ARM64_ERRATUM_858921
 465         {
 466                 .match_type = ate_match_local_cap_id,
 467                 .id = (void *)ARM64_WORKAROUND_858921,
 468                 .desc = "ARM erratum 858921",
 469                 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
 470                 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
 471         },
 472 #endif
 473 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
 474         {
 475                 .match_type = ate_match_dt,
 476                 .id = "allwinner,erratum-unknown1",
 477                 .desc = "Allwinner erratum UNKNOWN1",
 478                 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
 479                 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
 480                 .set_next_event_phys = erratum_set_next_event_phys,
 481                 .set_next_event_virt = erratum_set_next_event_virt,
 482         },
 483 #endif
 484 #ifdef CONFIG_ARM64_ERRATUM_1418040
 485         {
 486                 .match_type = ate_match_local_cap_id,
 487                 .id = (void *)ARM64_WORKAROUND_1418040,
 488                 .desc = "ARM erratum 1418040",
 489                 .disable_compat_vdso = true,
 490         },
 491 #endif
 492 };
 493
 494 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
 495                                const void *);
 496
 497 static
 498 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
 499                                  const void *arg)
 500 {
 501         const struct device_node *np = arg;
 502
 503         return of_property_read_bool(np, wa->id);
 504 }
 505
 506 static
 507 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
 508                                         const void *arg)
 509 {
 510         return this_cpu_has_cap((uintptr_t)wa->id);
 511 }
 512
 513
 514 static
 515 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
 516                                        const void *arg)
 517 {
 518         static const struct ate_acpi_oem_info empty_oem_info = {};
 519         const struct ate_acpi_oem_info *info = wa->id;
 520         const struct acpi_table_header *table = arg;
 521
 522         /* Iterate over the ACPI OEM info array, looking for a match */
 523         while (memcmp(info, &empty_oem_info, sizeof(*info))) {
 524                 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
 525                     !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
 526                     info->oem_revision == table->oem_revision)
 527                         return true;
 528
 529                 info++;
 530         }
 531
 532         return false;
 533 }
 534
 535 static const struct arch_timer_erratum_workaround *
 536 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
 537                           ate_match_fn_t match_fn,
 538                           void *arg)
 539 {
 540         int i;
 541
 542         for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
 543                 if (ool_workarounds[i].match_type != type)
 544                         continue;
 545
 546                 if (match_fn(&ool_workarounds[i], arg))
 547                         return &ool_workarounds[i];
 548         }
 549
 550         return NULL;
 551 }
 552
 553 static
 554 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
 555                                   bool local)
 556 {
 557         int i;
 558
 559         if (local) {
 560                 __this_cpu_write(timer_unstable_counter_workaround, wa);
 561         } else {
 562                 for_each_possible_cpu(i)
 563                         per_cpu(timer_unstable_counter_workaround, i) = wa;
 564         }
 565
 566         if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
 567                 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
 568
 569         /*
 570          * Don't use the vdso fastpath if errata require using the
 571          * out-of-line counter accessor. We may change our mind pretty
 572          * late in the game (with a per-CPU erratum, for example), so
 573          * change both the default value and the vdso itself.
 574          */
 575         if (wa->read_cntvct_el0) {
 576                 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
 577                 vdso_default = VDSO_CLOCKMODE_NONE;
 578         } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
 579                 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
 580                 clocksource_counter.vdso_clock_mode = vdso_default;
 581         }
 582 }
 583
 584 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
 585                                             void *arg)
 586 {
 587         const struct arch_timer_erratum_workaround *wa, *__wa;
 588         ate_match_fn_t match_fn = NULL;
 589         bool local = false;
 590
 591         switch (type) {
 592         case ate_match_dt:
 593                 match_fn = arch_timer_check_dt_erratum;
 594                 break;
 595         case ate_match_local_cap_id:
 596                 match_fn = arch_timer_check_local_cap_erratum;
 597                 local = true;
 598                 break;
 599         case ate_match_acpi_oem_info:
 600                 match_fn = arch_timer_check_acpi_oem_erratum;
 601                 break;
 602         default:
 603                 WARN_ON(1);
 604                 return;
 605         }
 606
 607         wa = arch_timer_iterate_errata(type, match_fn, arg);
 608         if (!wa)
 609                 return;
 610
 611         __wa = __this_cpu_read(timer_unstable_counter_workaround);
 612         if (__wa && wa != __wa)
 613                 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
 614                         wa->desc, __wa->desc);
 615
 616         if (__wa)
 617                 return;
 618
 619         arch_timer_enable_workaround(wa, local);
 620         pr_info("Enabling %s workaround for %s\n",
 621                 local ? "local" : "global", wa->desc);
 622 }
 623
 624 static bool arch_timer_this_cpu_has_cntvct_wa(void)
 625 {
 626         return has_erratum_handler(read_cntvct_el0);
 627 }
 628
 629 static bool arch_timer_counter_has_wa(void)
 630 {
 631         return atomic_read(&timer_unstable_counter_workaround_in_use);
 632 }
 633 #else
 634 #define arch_timer_check_ool_workaround(t,a)            do { } while(0)
 635 #define arch_timer_this_cpu_has_cntvct_wa()             ({false;})
 636 #define arch_timer_counter_has_wa()                     ({false;})
 637 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 638
 639 static __always_inline irqreturn_t timer_handler(const int access,
 640                                         struct clock_event_device *evt)
 641 {
 642         unsigned long ctrl;
 643
 644         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
 645         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 646                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 647                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 648                 evt->event_handler(evt);
 649                 return IRQ_HANDLED;
 650         }
 651
 652         return IRQ_NONE;
 653 }
 654
 655 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 656 {
 657         struct clock_event_device *evt = dev_id;
 658
 659         return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 660 }
 661
 662 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 663 {
 664         struct clock_event_device *evt = dev_id;
 665
 666         return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 667 }
 668
 669 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
 670 {
 671         struct clock_event_device *evt = dev_id;
 672
 673         return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
 674 }
 675
 676 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
 677 {
 678         struct clock_event_device *evt = dev_id;
 679
 680         return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
 681 }
 682
 683 static __always_inline int timer_shutdown(const int access,
 684                                           struct clock_event_device *clk)
 685 {
 686         unsigned long ctrl;
 687
 688         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 689         ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 690         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 691
 692         return 0;
 693 }
 694
 695 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
 696 {
 697         return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
 698 }
 699
 700 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
 701 {
 702         return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
 703 }
 704
 705 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
 706 {
 707         return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
 708 }
 709
 710 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
 711 {
 712         return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
 713 }
 714
 715 static __always_inline void set_next_event(const int access, unsigned long evt,
 716                                            struct clock_event_device *clk)
 717 {
 718         unsigned long ctrl;
 719         u64 cnt;
 720
 721         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 722         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 723         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 724
 725         if (access == ARCH_TIMER_PHYS_ACCESS)
 726                 cnt = __arch_counter_get_cntpct();
 727         else
 728                 cnt = __arch_counter_get_cntvct();
 729
 730         arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
 731         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 732 }
 733
 734 static int arch_timer_set_next_event_virt(unsigned long evt,
 735                                           struct clock_event_device *clk)
 736 {
 737         set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 738         return 0;
 739 }
 740
 741 static int arch_timer_set_next_event_phys(unsigned long evt,
 742                                           struct clock_event_device *clk)
 743 {
 744         set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 745         return 0;
 746 }
 747
 748 static u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo)
 749 {
 750         u32 cnt_lo, cnt_hi, tmp_hi;
 751
 752         do {
 753                 cnt_hi = readl_relaxed(t->base + offset_lo + 4);
 754                 cnt_lo = readl_relaxed(t->base + offset_lo);
 755                 tmp_hi = readl_relaxed(t->base + offset_lo + 4);
 756         } while (cnt_hi != tmp_hi);
 757
 758         return ((u64) cnt_hi << 32) | cnt_lo;
 759 }
 760
 761 static __always_inline void set_next_event_mem(const int access, unsigned long evt,
 762                                            struct clock_event_device *clk)
 763 {
 764         struct arch_timer *timer = to_arch_timer(clk);
 765         unsigned long ctrl;
 766         u64 cnt;
 767
 768         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 769         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 770         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 771
 772         if (access ==  ARCH_TIMER_MEM_VIRT_ACCESS)
 773                 cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO);
 774         else
 775                 cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO);
 776
 777         arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
 778         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 779 }
 780
 781 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
 782                                               struct clock_event_device *clk)
 783 {
 784         set_next_event_mem(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
 785         return 0;
 786 }
 787
 788 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 789                                               struct clock_event_device *clk)
 790 {
 791         set_next_event_mem(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
 792         return 0;
 793 }
 794
 795 static u64 __arch_timer_check_delta(void)
 796 {
 797 #ifdef CONFIG_ARM64
 798         const struct midr_range broken_cval_midrs[] = {
 799                 /*
 800                  * XGene-1 implements CVAL in terms of TVAL, meaning
 801                  * that the maximum timer range is 32bit. Shame on them.
 802                  */
 803                 MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
 804                                                  APM_CPU_PART_POTENZA)),
 805                 {},
 806         };
 807
 808         if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
 809                 pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 32bits");
 810                 return CLOCKSOURCE_MASK(32);
 811         }
 812 #endif
 813         return CLOCKSOURCE_MASK(arch_counter_get_width());
 814 }
 815
 816 static void __arch_timer_setup(unsigned type,
 817                                struct clock_event_device *clk)
 818 {
 819         u64 max_delta;
 820
 821         clk->features = CLOCK_EVT_FEAT_ONESHOT;
 822
 823         if (type == ARCH_TIMER_TYPE_CP15) {
 824                 typeof(clk->set_next_event) sne;
 825
 826                 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
 827
 828                 if (arch_timer_c3stop)
 829                         clk->features |= CLOCK_EVT_FEAT_C3STOP;
 830                 clk->name = "arch_sys_timer";
 831                 clk->rating = 450;
 832                 clk->cpumask = cpumask_of(smp_processor_id());
 833                 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
 834                 switch (arch_timer_uses_ppi) {
 835                 case ARCH_TIMER_VIRT_PPI:
 836                         clk->set_state_shutdown = arch_timer_shutdown_virt;
 837                         clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
 838                         sne = erratum_handler(set_next_event_virt);
 839                         break;
 840                 case ARCH_TIMER_PHYS_SECURE_PPI:
 841                 case ARCH_TIMER_PHYS_NONSECURE_PPI:
 842                 case ARCH_TIMER_HYP_PPI:
 843                         clk->set_state_shutdown = arch_timer_shutdown_phys;
 844                         clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
 845                         sne = erratum_handler(set_next_event_phys);
 846                         break;
 847                 default:
 848                         BUG();
 849                 }
 850
 851                 clk->set_next_event = sne;
 852                 max_delta = __arch_timer_check_delta();
 853         } else {
 854                 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 855                 clk->name = "arch_mem_timer";
 856                 clk->rating = 400;
 857                 clk->cpumask = cpu_possible_mask;
 858                 if (arch_timer_mem_use_virtual) {
 859                         clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
 860                         clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
 861                         clk->set_next_event =
 862                                 arch_timer_set_next_event_virt_mem;
 863                 } else {
 864                         clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
 865                         clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
 866                         clk->set_next_event =
 867                                 arch_timer_set_next_event_phys_mem;
 868                 }
 869
 870                 max_delta = CLOCKSOURCE_MASK(56);
 871         }
 872
 873         clk->set_state_shutdown(clk);
 874
 875         clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
 876 }
 877
 878 static void arch_timer_evtstrm_enable(int divider)
 879 {
 880         u32 cntkctl = arch_timer_get_cntkctl();
 881
 882         cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
 883         /* Set the divider and enable virtual event stream */
 884         cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
 885                         | ARCH_TIMER_VIRT_EVT_EN;
 886         arch_timer_set_cntkctl(cntkctl);
 887         arch_timer_set_evtstrm_feature();
 888         cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
 889 }
 890
 891 static void arch_timer_configure_evtstream(void)
 892 {
 893         int evt_stream_div, lsb;
 894
 895         /*
 896          * As the event stream can at most be generated at half the frequency
 897          * of the counter, use half the frequency when computing the divider.
 898          */
 899         evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
 900
 901         /*
 902          * Find the closest power of two to the divisor. If the adjacent bit
 903          * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
 904          */
 905         lsb = fls(evt_stream_div) - 1;
 906         if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
 907                 lsb++;
 908
 909         /* enable event stream */
 910         arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
 911 }
 912
 913 static void arch_counter_set_user_access(void)
 914 {
 915         u32 cntkctl = arch_timer_get_cntkctl();
 916
 917         /* Disable user access to the timers and both counters */
 918         /* Also disable virtual event stream */
 919         cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
 920                         | ARCH_TIMER_USR_VT_ACCESS_EN
 921                         | ARCH_TIMER_USR_VCT_ACCESS_EN
 922                         | ARCH_TIMER_VIRT_EVT_EN
 923                         | ARCH_TIMER_USR_PCT_ACCESS_EN);
 924
 925         /*
 926          * Enable user access to the virtual counter if it doesn't
 927          * need to be workaround. The vdso may have been already
 928          * disabled though.
 929          */
 930         if (arch_timer_this_cpu_has_cntvct_wa())
 931                 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
 932         else
 933                 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
 934
 935         arch_timer_set_cntkctl(cntkctl);
 936 }
 937
 938 static bool arch_timer_has_nonsecure_ppi(void)
 939 {
 940         return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
 941                 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
 942 }
 943
 944 static u32 check_ppi_trigger(int irq)
 945 {
 946         u32 flags = irq_get_trigger_type(irq);
 947
 948         if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
 949                 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
 950                 pr_warn("WARNING: Please fix your firmware\n");
 951                 flags = IRQF_TRIGGER_LOW;
 952         }
 953
 954         return flags;
 955 }
 956
 957 static int arch_timer_starting_cpu(unsigned int cpu)
 958 {
 959         struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
 960         u32 flags;
 961
 962         __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
 963
 964         flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
 965         enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
 966
 967         if (arch_timer_has_nonsecure_ppi()) {
 968                 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
 969                 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
 970                                   flags);
 971         }
 972
 973         arch_counter_set_user_access();
 974         if (evtstrm_enable)
 975                 arch_timer_configure_evtstream();
 976
 977         return 0;
 978 }
 979
 980 static int validate_timer_rate(void)
 981 {
 982         if (!arch_timer_rate)
 983                 return -EINVAL;
 984
 985         /* Arch timer frequency < 1MHz can cause trouble */
 986         WARN_ON(arch_timer_rate < 1000000);
 987
 988         return 0;
 989 }
 990
 991 /*
 992  * For historical reasons, when probing with DT we use whichever (non-zero)
 993  * rate was probed first, and don't verify that others match. If the first node
 994  * probed has a clock-frequency property, this overrides the HW register.
 995  */
 996 static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
 997 {
 998         /* Who has more than one independent system counter? */
 999         if (arch_timer_rate)
1000                 return;
1001
1002         if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
1003                 arch_timer_rate = rate;
1004
1005         /* Check the timer frequency. */
1006         if (validate_timer_rate())
1007                 pr_warn("frequency not available\n");
1008 }
1009
1010 static void __init arch_timer_banner(unsigned type)
1011 {
1012         pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
1013                 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
1014                 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
1015                         " and " : "",
1016                 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
1017                 (unsigned long)arch_timer_rate / 1000000,
1018                 (unsigned long)(arch_timer_rate / 10000) % 100,
1019                 type & ARCH_TIMER_TYPE_CP15 ?
1020                         (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
1021                         "",
1022                 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
1023                 type & ARCH_TIMER_TYPE_MEM ?
1024                         arch_timer_mem_use_virtual ? "virt" : "phys" :
1025                         "");
1026 }
1027
1028 u32 arch_timer_get_rate(void)
1029 {
1030         return arch_timer_rate;
1031 }
1032
1033 bool arch_timer_evtstrm_available(void)
1034 {
1035         /*
1036          * We might get called from a preemptible context. This is fine
1037          * because availability of the event stream should be always the same
1038          * for a preemptible context and context where we might resume a task.
1039          */
1040         return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
1041 }
1042
1043 static u64 arch_counter_get_cntvct_mem(void)
1044 {
1045         return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO);
1046 }
1047
1048 static struct arch_timer_kvm_info arch_timer_kvm_info;
1049
1050 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
1051 {
1052         return &arch_timer_kvm_info;
1053 }
1054
1055 static void __init arch_counter_register(unsigned type)
1056 {
1057         u64 start_count;
1058         int width;
1059
1060         /* Register the CP15 based counter if we have one */
1061         if (type & ARCH_TIMER_TYPE_CP15) {
1062                 u64 (*rd)(void);
1063
1064                 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
1065                     arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
1066                         if (arch_timer_counter_has_wa())
1067                                 rd = arch_counter_get_cntvct_stable;
1068                         else
1069                                 rd = arch_counter_get_cntvct;
1070                 } else {
1071                         if (arch_timer_counter_has_wa())
1072                                 rd = arch_counter_get_cntpct_stable;
1073                         else
1074                                 rd = arch_counter_get_cntpct;
1075                 }
1076
1077                 arch_timer_read_counter = rd;
1078                 clocksource_counter.vdso_clock_mode = vdso_default;
1079         } else {
1080                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1081         }
1082
1083         width = arch_counter_get_width();
1084         clocksource_counter.mask = CLOCKSOURCE_MASK(width);
1085         cyclecounter.mask = CLOCKSOURCE_MASK(width);
1086
1087         if (!arch_counter_suspend_stop)
1088                 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1089         start_count = arch_timer_read_counter();
1090         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1091         cyclecounter.mult = clocksource_counter.mult;
1092         cyclecounter.shift = clocksource_counter.shift;
1093         timecounter_init(&arch_timer_kvm_info.timecounter,
1094                          &cyclecounter, start_count);
1095
1096         sched_clock_register(arch_timer_read_counter, width, arch_timer_rate);
1097 }
1098
1099 static void arch_timer_stop(struct clock_event_device *clk)
1100 {
1101         pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1102
1103         disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1104         if (arch_timer_has_nonsecure_ppi())
1105                 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1106
1107         clk->set_state_shutdown(clk);
1108 }
1109
1110 static int arch_timer_dying_cpu(unsigned int cpu)
1111 {
1112         struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1113
1114         cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1115
1116         arch_timer_stop(clk);
1117         return 0;
1118 }
1119
1120 #ifdef CONFIG_CPU_PM
1121 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1122 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1123                                     unsigned long action, void *hcpu)
1124 {
1125         if (action == CPU_PM_ENTER) {
1126                 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1127
1128                 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1129         } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1130                 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1131
1132                 if (arch_timer_have_evtstrm_feature())
1133                         cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1134         }
1135         return NOTIFY_OK;
1136 }
1137
1138 static struct notifier_block arch_timer_cpu_pm_notifier = {
1139         .notifier_call = arch_timer_cpu_pm_notify,
1140 };
1141
1142 static int __init arch_timer_cpu_pm_init(void)
1143 {
1144         return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1145 }
1146
1147 static void __init arch_timer_cpu_pm_deinit(void)
1148 {
1149         WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1150 }
1151
1152 #else
1153 static int __init arch_timer_cpu_pm_init(void)
1154 {
1155         return 0;
1156 }
1157
1158 static void __init arch_timer_cpu_pm_deinit(void)
1159 {
1160 }
1161 #endif
1162
1163 static int __init arch_timer_register(void)
1164 {
1165         int err;
1166         int ppi;
1167
1168         arch_timer_evt = alloc_percpu(struct clock_event_device);
1169         if (!arch_timer_evt) {
1170                 err = -ENOMEM;
1171                 goto out;
1172         }
1173
1174         ppi = arch_timer_ppi[arch_timer_uses_ppi];
1175         switch (arch_timer_uses_ppi) {
1176         case ARCH_TIMER_VIRT_PPI:
1177                 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1178                                          "arch_timer", arch_timer_evt);
1179                 break;
1180         case ARCH_TIMER_PHYS_SECURE_PPI:
1181         case ARCH_TIMER_PHYS_NONSECURE_PPI:
1182                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1183                                          "arch_timer", arch_timer_evt);
1184                 if (!err && arch_timer_has_nonsecure_ppi()) {
1185                         ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1186                         err = request_percpu_irq(ppi, arch_timer_handler_phys,
1187                                                  "arch_timer", arch_timer_evt);
1188                         if (err)
1189                                 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1190                                                 arch_timer_evt);
1191                 }
1192                 break;
1193         case ARCH_TIMER_HYP_PPI:
1194                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1195                                          "arch_timer", arch_timer_evt);
1196                 break;
1197         default:
1198                 BUG();
1199         }
1200
1201         if (err) {
1202                 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1203                 goto out_free;
1204         }
1205
1206         err = arch_timer_cpu_pm_init();
1207         if (err)
1208                 goto out_unreg_notify;
1209
1210         /* Register and immediately configure the timer on the boot CPU */
1211         err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1212                                 "clockevents/arm/arch_timer:starting",
1213                                 arch_timer_starting_cpu, arch_timer_dying_cpu);
1214         if (err)
1215                 goto out_unreg_cpupm;
1216         return 0;
1217
1218 out_unreg_cpupm:
1219         arch_timer_cpu_pm_deinit();
1220
1221 out_unreg_notify:
1222         free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1223         if (arch_timer_has_nonsecure_ppi())
1224                 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1225                                 arch_timer_evt);
1226
1227 out_free:
1228         free_percpu(arch_timer_evt);
1229 out:
1230         return err;
1231 }
1232
1233 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1234 {
1235         int ret;
1236         irq_handler_t func;
1237
1238         arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL);
1239         if (!arch_timer_mem)
1240                 return -ENOMEM;
1241
1242         arch_timer_mem->base = base;
1243         arch_timer_mem->evt.irq = irq;
1244         __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt);
1245
1246         if (arch_timer_mem_use_virtual)
1247                 func = arch_timer_handler_virt_mem;
1248         else
1249                 func = arch_timer_handler_phys_mem;
1250
1251         ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt);
1252         if (ret) {
1253                 pr_err("Failed to request mem timer irq\n");
1254                 kfree(arch_timer_mem);
1255                 arch_timer_mem = NULL;
1256         }
1257
1258         return ret;
1259 }
1260
1261 static const struct of_device_id arch_timer_of_match[] __initconst = {
1262         { .compatible   = "arm,armv7-timer",    },
1263         { .compatible   = "arm,armv8-timer",    },
1264         {},
1265 };
1266
1267 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1268         { .compatible   = "arm,armv7-timer-mem", },
1269         {},
1270 };
1271
1272 static bool __init arch_timer_needs_of_probing(void)
1273 {
1274         struct device_node *dn;
1275         bool needs_probing = false;
1276         unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1277
1278         /* We have two timers, and both device-tree nodes are probed. */
1279         if ((arch_timers_present & mask) == mask)
1280                 return false;
1281
1282         /*
1283          * Only one type of timer is probed,
1284          * check if we have another type of timer node in device-tree.
1285          */
1286         if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1287                 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1288         else
1289                 dn = of_find_matching_node(NULL, arch_timer_of_match);
1290
1291         if (dn && of_device_is_available(dn))
1292                 needs_probing = true;
1293
1294         of_node_put(dn);
1295
1296         return needs_probing;
1297 }
1298
1299 static int __init arch_timer_common_init(void)
1300 {
1301         arch_timer_banner(arch_timers_present);
1302         arch_counter_register(arch_timers_present);
1303         return arch_timer_arch_init();
1304 }
1305
1306 /**
1307  * arch_timer_select_ppi() - Select suitable PPI for the current system.
1308  *
1309  * If HYP mode is available, we know that the physical timer
1310  * has been configured to be accessible from PL1. Use it, so
1311  * that a guest can use the virtual timer instead.
1312  *
1313  * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1314  * accesses to CNTP_*_EL1 registers are silently redirected to
1315  * their CNTHP_*_EL2 counterparts, and use a different PPI
1316  * number.
1317  *
1318  * If no interrupt provided for virtual timer, we'll have to
1319  * stick to the physical timer. It'd better be accessible...
1320  * For arm64 we never use the secure interrupt.
1321  *
1322  * Return: a suitable PPI type for the current system.
1323  */
1324 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1325 {
1326         if (is_kernel_in_hyp_mode())
1327                 return ARCH_TIMER_HYP_PPI;
1328
1329         if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1330                 return ARCH_TIMER_VIRT_PPI;
1331
1332         if (IS_ENABLED(CONFIG_ARM64))
1333                 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1334
1335         return ARCH_TIMER_PHYS_SECURE_PPI;
1336 }
1337
1338 static void __init arch_timer_populate_kvm_info(void)
1339 {
1340         arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1341         if (is_kernel_in_hyp_mode())
1342                 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1343 }
1344
1345 static int __init arch_timer_of_init(struct device_node *np)
1346 {
1347         int i, irq, ret;
1348         u32 rate;
1349         bool has_names;
1350
1351         if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1352                 pr_warn("multiple nodes in dt, skipping\n");
1353                 return 0;
1354         }
1355
1356         arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1357
1358         has_names = of_property_read_bool(np, "interrupt-names");
1359
1360         for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1361                 if (has_names)
1362                         irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1363                 else
1364                         irq = of_irq_get(np, i);
1365                 if (irq > 0)
1366                         arch_timer_ppi[i] = irq;
1367         }
1368
1369         arch_timer_populate_kvm_info();
1370
1371         rate = arch_timer_get_cntfrq();
1372         arch_timer_of_configure_rate(rate, np);
1373
1374         arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1375
1376         /* Check for globally applicable workarounds */
1377         arch_timer_check_ool_workaround(ate_match_dt, np);
1378
1379         /*
1380          * If we cannot rely on firmware initializing the timer registers then
1381          * we should use the physical timers instead.
1382          */
1383         if (IS_ENABLED(CONFIG_ARM) &&
1384             of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1385                 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1386         else
1387                 arch_timer_uses_ppi = arch_timer_select_ppi();
1388
1389         if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1390                 pr_err("No interrupt available, giving up\n");
1391                 return -EINVAL;
1392         }
1393
1394         /* On some systems, the counter stops ticking when in suspend. */
1395         arch_counter_suspend_stop = of_property_read_bool(np,
1396                                                          "arm,no-tick-in-suspend");
1397
1398         ret = arch_timer_register();
1399         if (ret)
1400                 return ret;
1401
1402         if (arch_timer_needs_of_probing())
1403                 return 0;
1404
1405         return arch_timer_common_init();
1406 }
1407 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1408 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1409
1410 static u32 __init
1411 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1412 {
1413         void __iomem *base;
1414         u32 rate;
1415
1416         base = ioremap(frame->cntbase, frame->size);
1417         if (!base) {
1418                 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1419                 return 0;
1420         }
1421
1422         rate = readl_relaxed(base + CNTFRQ);
1423
1424         iounmap(base);
1425
1426         return rate;
1427 }
1428
1429 static struct arch_timer_mem_frame * __init
1430 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1431 {
1432         struct arch_timer_mem_frame *frame, *best_frame = NULL;
1433         void __iomem *cntctlbase;
1434         u32 cnttidr;
1435         int i;
1436
1437         cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1438         if (!cntctlbase) {
1439                 pr_err("Can't map CNTCTLBase @ %pa\n",
1440                         &timer_mem->cntctlbase);
1441                 return NULL;
1442         }
1443
1444         cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1445
1446         /*
1447          * Try to find a virtual capable frame. Otherwise fall back to a
1448          * physical capable frame.
1449          */
1450         for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1451                 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1452                              CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1453
1454                 frame = &timer_mem->frame[i];
1455                 if (!frame->valid)
1456                         continue;
1457
1458                 /* Try enabling everything, and see what sticks */
1459                 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1460                 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1461
1462                 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1463                     !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1464                         best_frame = frame;
1465                         arch_timer_mem_use_virtual = true;
1466                         break;
1467                 }
1468
1469                 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1470                         continue;
1471
1472                 best_frame = frame;
1473         }
1474
1475         iounmap(cntctlbase);
1476
1477         return best_frame;
1478 }
1479
1480 static int __init
1481 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1482 {
1483         void __iomem *base;
1484         int ret, irq = 0;
1485
1486         if (arch_timer_mem_use_virtual)
1487                 irq = frame->virt_irq;
1488         else
1489                 irq = frame->phys_irq;
1490
1491         if (!irq) {
1492                 pr_err("Frame missing %s irq.\n",
1493                        arch_timer_mem_use_virtual ? "virt" : "phys");
1494                 return -EINVAL;
1495         }
1496
1497         if (!request_mem_region(frame->cntbase, frame->size,
1498                                 "arch_mem_timer"))
1499                 return -EBUSY;
1500
1501         base = ioremap(frame->cntbase, frame->size);
1502         if (!base) {
1503                 pr_err("Can't map frame's registers\n");
1504                 return -ENXIO;
1505         }
1506
1507         ret = arch_timer_mem_register(base, irq);
1508         if (ret) {
1509                 iounmap(base);
1510                 return ret;
1511         }
1512
1513         arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1514
1515         return 0;
1516 }
1517
1518 static int __init arch_timer_mem_of_init(struct device_node *np)
1519 {
1520         struct arch_timer_mem *timer_mem;
1521         struct arch_timer_mem_frame *frame;
1522         struct device_node *frame_node;
1523         struct resource res;
1524         int ret = -EINVAL;
1525         u32 rate;
1526
1527         timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1528         if (!timer_mem)
1529                 return -ENOMEM;
1530
1531         if (of_address_to_resource(np, 0, &res))
1532                 goto out;
1533         timer_mem->cntctlbase = res.start;
1534         timer_mem->size = resource_size(&res);
1535
1536         for_each_available_child_of_node(np, frame_node) {
1537                 u32 n;
1538                 struct arch_timer_mem_frame *frame;
1539
1540                 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1541                         pr_err(FW_BUG "Missing frame-number.\n");
1542                         of_node_put(frame_node);
1543                         goto out;
1544                 }
1545                 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1546                         pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1547                                ARCH_TIMER_MEM_MAX_FRAMES - 1);
1548                         of_node_put(frame_node);
1549                         goto out;
1550                 }
1551                 frame = &timer_mem->frame[n];
1552
1553                 if (frame->valid) {
1554                         pr_err(FW_BUG "Duplicated frame-number.\n");
1555                         of_node_put(frame_node);
1556                         goto out;
1557                 }
1558
1559                 if (of_address_to_resource(frame_node, 0, &res)) {
1560                         of_node_put(frame_node);
1561                         goto out;
1562                 }
1563                 frame->cntbase = res.start;
1564                 frame->size = resource_size(&res);
1565
1566                 frame->virt_irq = irq_of_parse_and_map(frame_node,
1567                                                        ARCH_TIMER_VIRT_SPI);
1568                 frame->phys_irq = irq_of_parse_and_map(frame_node,
1569                                                        ARCH_TIMER_PHYS_SPI);
1570
1571                 frame->valid = true;
1572         }
1573
1574         frame = arch_timer_mem_find_best_frame(timer_mem);
1575         if (!frame) {
1576                 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1577                         &timer_mem->cntctlbase);
1578                 ret = -EINVAL;
1579                 goto out;
1580         }
1581
1582         rate = arch_timer_mem_frame_get_cntfrq(frame);
1583         arch_timer_of_configure_rate(rate, np);
1584
1585         ret = arch_timer_mem_frame_register(frame);
1586         if (!ret && !arch_timer_needs_of_probing())
1587                 ret = arch_timer_common_init();
1588 out:
1589         kfree(timer_mem);
1590         return ret;
1591 }
1592 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1593                        arch_timer_mem_of_init);
1594
1595 #ifdef CONFIG_ACPI_GTDT
1596 static int __init
1597 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1598 {
1599         struct arch_timer_mem_frame *frame;
1600         u32 rate;
1601         int i;
1602
1603         for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1604                 frame = &timer_mem->frame[i];
1605
1606                 if (!frame->valid)
1607                         continue;
1608
1609                 rate = arch_timer_mem_frame_get_cntfrq(frame);
1610                 if (rate == arch_timer_rate)
1611                         continue;
1612
1613                 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1614                         &frame->cntbase,
1615                         (unsigned long)rate, (unsigned long)arch_timer_rate);
1616
1617                 return -EINVAL;
1618         }
1619
1620         return 0;
1621 }
1622
1623 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1624 {
1625         struct arch_timer_mem *timers, *timer;
1626         struct arch_timer_mem_frame *frame, *best_frame = NULL;
1627         int timer_count, i, ret = 0;
1628
1629         timers = kcalloc(platform_timer_count, sizeof(*timers),
1630                             GFP_KERNEL);
1631         if (!timers)
1632                 return -ENOMEM;
1633
1634         ret = acpi_arch_timer_mem_init(timers, &timer_count);
1635         if (ret || !timer_count)
1636                 goto out;
1637
1638         /*
1639          * While unlikely, it's theoretically possible that none of the frames
1640          * in a timer expose the combination of feature we want.
1641          */
1642         for (i = 0; i < timer_count; i++) {
1643                 timer = &timers[i];
1644
1645                 frame = arch_timer_mem_find_best_frame(timer);
1646                 if (!best_frame)
1647                         best_frame = frame;
1648
1649                 ret = arch_timer_mem_verify_cntfrq(timer);
1650                 if (ret) {
1651                         pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1652                         goto out;
1653                 }
1654
1655                 if (!best_frame) /* implies !frame */
1656                         /*
1657                          * Only complain about missing suitable frames if we
1658                          * haven't already found one in a previous iteration.
1659                          */
1660                         pr_err("Unable to find a suitable frame in timer @ %pa\n",
1661                                 &timer->cntctlbase);
1662         }
1663
1664         if (best_frame)
1665                 ret = arch_timer_mem_frame_register(best_frame);
1666 out:
1667         kfree(timers);
1668         return ret;
1669 }
1670
1671 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1672 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1673 {
1674         int ret, platform_timer_count;
1675
1676         if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1677                 pr_warn("already initialized, skipping\n");
1678                 return -EINVAL;
1679         }
1680
1681         arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1682
1683         ret = acpi_gtdt_init(table, &platform_timer_count);
1684         if (ret)
1685                 return ret;
1686
1687         arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1688                 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1689
1690         arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1691                 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1692
1693         arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1694                 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1695
1696         arch_timer_populate_kvm_info();
1697
1698         /*
1699          * When probing via ACPI, we have no mechanism to override the sysreg
1700          * CNTFRQ value. This *must* be correct.
1701          */
1702         arch_timer_rate = arch_timer_get_cntfrq();
1703         ret = validate_timer_rate();
1704         if (ret) {
1705                 pr_err(FW_BUG "frequency not available.\n");
1706                 return ret;
1707         }
1708
1709         arch_timer_uses_ppi = arch_timer_select_ppi();
1710         if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1711                 pr_err("No interrupt available, giving up\n");
1712                 return -EINVAL;
1713         }
1714
1715         /* Always-on capability */
1716         arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1717
1718         /* Check for globally applicable workarounds */
1719         arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1720
1721         ret = arch_timer_register();
1722         if (ret)
1723                 return ret;
1724
1725         if (platform_timer_count &&
1726             arch_timer_mem_acpi_init(platform_timer_count))
1727                 pr_err("Failed to initialize memory-mapped timer.\n");
1728
1729         return arch_timer_common_init();
1730 }
1731 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1732 #endif
1733
1734 int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1735                                  struct clocksource **cs)
1736 {
1737         struct arm_smccc_res hvc_res;
1738         u32 ptp_counter;
1739         ktime_t ktime;
1740
1741         if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1742                 return -EOPNOTSUPP;
1743
1744         if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1745                 ptp_counter = KVM_PTP_VIRT_COUNTER;
1746         else
1747                 ptp_counter = KVM_PTP_PHYS_COUNTER;
1748
1749         arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1750                              ptp_counter, &hvc_res);
1751
1752         if ((int)(hvc_res.a0) < 0)
1753                 return -EOPNOTSUPP;
1754
1755         ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1756         *ts = ktime_to_timespec64(ktime);
1757         if (cycle)
1758                 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1759         if (cs)
1760                 *cs = &clocksource_counter;
1761
1762         return 0;
1763 }
1764 EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);