drivers/clk/imx/clk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MACH_IMX_CLK_H
   3 #define __MACH_IMX_CLK_H
   4
   5 #include <linux/bits.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/clk-provider.h>
   8
   9 extern spinlock_t imx_ccm_lock;
  10
  11 void imx_check_clocks(struct clk *clks[], unsigned int count);
  12 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
  13 #ifndef MODULE
  14 void imx_register_uart_clocks(unsigned int clk_count);
  15 #else
  16 static inline void imx_register_uart_clocks(unsigned int clk_count)
  17 {
  18 }
  19 #endif
  20 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
  21 void imx_unregister_clocks(struct clk *clks[], unsigned int count);
  22 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
  23
  24 extern void imx_cscmr1_fixup(u32 *val);
  25
  26 enum imx_pllv1_type {
  27         IMX_PLLV1_IMX1,
  28         IMX_PLLV1_IMX21,
  29         IMX_PLLV1_IMX25,
  30         IMX_PLLV1_IMX27,
  31         IMX_PLLV1_IMX31,
  32         IMX_PLLV1_IMX35,
  33 };
  34
  35 enum imx_sscg_pll_type {
  36         SCCG_PLL1,
  37         SCCG_PLL2,
  38 };
  39
  40 enum imx_pll14xx_type {
  41         PLL_1416X,
  42         PLL_1443X,
  43 };
  44
  45 enum imx_pllv4_type {
  46         IMX_PLLV4_IMX7ULP,
  47         IMX_PLLV4_IMX8ULP,
  48 };
  49
  50 enum imx_pfdv2_type {
  51         IMX_PFDV2_IMX7ULP,
  52         IMX_PFDV2_IMX8ULP,
  53 };
  54
  55 /* NOTE: Rate table should be kept sorted in descending order. */
  56 struct imx_pll14xx_rate_table {
  57         unsigned int rate;
  58         unsigned int pdiv;
  59         unsigned int mdiv;
  60         unsigned int sdiv;
  61         unsigned int kdiv;
  62 };
  63
  64 struct imx_pll14xx_clk {
  65         enum imx_pll14xx_type type;
  66         const struct imx_pll14xx_rate_table *rate_table;
  67         int rate_count;
  68         int flags;
  69 };
  70
  71 extern struct imx_pll14xx_clk imx_1416x_pll;
  72 extern struct imx_pll14xx_clk imx_1443x_pll;
  73 extern struct imx_pll14xx_clk imx_1443x_dram_pll;
  74
  75 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
  76         to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
  77
  78 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
  79                                 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
  80         to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
  81                                 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
  82
  83 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
  84         to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
  85
  86 #define imx_clk_pfd(name, parent_name, reg, idx) \
  87         to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
  88
  89 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
  90         to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
  91
  92 #define imx_clk_fixed(name, rate) \
  93         to_clk(imx_clk_hw_fixed(name, rate))
  94
  95 #define imx_clk_fixed_factor(name, parent, mult, div) \
  96         to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
  97
  98 #define imx_clk_divider(name, parent, reg, shift, width) \
  99         to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
 100
 101 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
 102         to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
 103
 104 #define imx_clk_gate(name, parent, reg, shift) \
 105         to_clk(imx_clk_hw_gate(name, parent, reg, shift))
 106
 107 #define imx_clk_gate_dis(name, parent, reg, shift) \
 108         to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
 109
 110 #define imx_clk_gate2(name, parent, reg, shift) \
 111         to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
 112
 113 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
 114         to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
 115
 116 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
 117         to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
 118
 119 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
 120         to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
 121
 122 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
 123         to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
 124
 125 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
 126         to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
 127
 128 #define imx_clk_pllv1(type, name, parent, base) \
 129         to_clk(imx_clk_hw_pllv1(type, name, parent, base))
 130
 131 #define imx_clk_pllv2(name, parent, base) \
 132         to_clk(imx_clk_hw_pllv2(name, parent, base))
 133
 134 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
 135         to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
 136
 137 #define imx_clk_hw_gate(name, parent, reg, shift) \
 138         imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
 139
 140 #define imx_clk_hw_gate2(name, parent, reg, shift) \
 141         imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
 142
 143 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \
 144         imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
 145
 146 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
 147         __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
 148
 149 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
 150         __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
 151
 152 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
 153         __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
 154
 155 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
 156         __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
 157
 158 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
 159         __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
 160
 161 #define imx_clk_hw_gate3(name, parent, reg, shift) \
 162         imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
 163
 164 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
 165         __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
 166
 167 #define imx_clk_hw_gate4(name, parent, reg, shift) \
 168         imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
 169
 170 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
 171         imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
 172
 173 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
 174         imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
 175
 176 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
 177         __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
 178
 179 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
 180         __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
 181
 182 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
 183         __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
 184
 185 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
 186         __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
 187
 188 #define imx_clk_hw_divider(name, parent, reg, shift, width) \
 189         __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
 190
 191 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \
 192         __imx_clk_hw_divider(name, parent, reg, shift, width, \
 193                                 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
 194
 195 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
 196         __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
 197
 198 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \
 199         imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
 200
 201 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
 202                                 const char *parent_name, void __iomem *base,
 203                                 const struct imx_pll14xx_clk *pll_clk);
 204
 205 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
 206                 const char *parent, void __iomem *base);
 207
 208 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
 209                 void __iomem *base);
 210
 211 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
 212                              void __iomem *base);
 213
 214 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
 215                                 const char * const *parent_names,
 216                                 u8 num_parents,
 217                                 u8 parent, u8 bypass1, u8 bypass2,
 218                                 void __iomem *base,
 219                                 unsigned long flags);
 220
 221 enum imx_pllv3_type {
 222         IMX_PLLV3_GENERIC,
 223         IMX_PLLV3_SYS,
 224         IMX_PLLV3_USB,
 225         IMX_PLLV3_USB_VF610,
 226         IMX_PLLV3_AV,
 227         IMX_PLLV3_ENET,
 228         IMX_PLLV3_ENET_IMX7,
 229         IMX_PLLV3_SYS_VF610,
 230         IMX_PLLV3_DDR_IMX7,
 231         IMX_PLLV3_AV_IMX7,
 232 };
 233
 234 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
 235                 const char *parent_name, void __iomem *base, u32 div_mask);
 236
 237 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
 238         {                                               \
 239                 .rate   =       (_rate),                \
 240                 .mdiv   =       (_m),                   \
 241                 .pdiv   =       (_p),                   \
 242                 .sdiv   =       (_s),                   \
 243         }
 244
 245 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
 246         {                                               \
 247                 .rate   =       (_rate),                \
 248                 .mdiv   =       (_m),                   \
 249                 .pdiv   =       (_p),                   \
 250                 .sdiv   =       (_s),                   \
 251                 .kdiv   =       (_k),                   \
 252         }
 253
 254 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
 255                 const char *parent_name, void __iomem *base);
 256
 257 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
 258                 const char *parent_name, unsigned long flags,
 259                 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
 260                 u8 clk_gate_flags, spinlock_t *lock,
 261                 unsigned int *share_count);
 262
 263 struct clk * imx_obtain_fixed_clock(
 264                         const char *name, unsigned long rate);
 265
 266 struct clk_hw *imx_obtain_fixed_clock_hw(
 267                         const char *name, unsigned long rate);
 268
 269 struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
 270                                        const char *name);
 271
 272 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
 273          void __iomem *reg, u8 shift, u32 exclusive_mask);
 274
 275 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
 276                 void __iomem *reg, u8 idx);
 277
 278 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
 279          const char *parent_name, void __iomem *reg, u8 idx);
 280
 281 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
 282                                  void __iomem *reg, u8 shift, u8 width,
 283                                  void __iomem *busy_reg, u8 busy_shift);
 284
 285 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
 286                              u8 width, void __iomem *busy_reg, u8 busy_shift,
 287                              const char * const *parent_names, int num_parents);
 288
 289 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
 290                                      const char * const *parent_names,
 291                                      int num_parents, bool mux_present,
 292                                      bool rate_present, bool gate_present,
 293                                      void __iomem *reg);
 294
 295 struct clk_hw *imx8ulp_clk_hw_composite(const char *name,
 296                                      const char * const *parent_names,
 297                                      int num_parents, bool mux_present,
 298                                      bool rate_present, bool gate_present,
 299                                      void __iomem *reg, bool has_swrst);
 300
 301 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
 302                                   void __iomem *reg, u8 shift, u8 width,
 303                                   void (*fixup)(u32 *val));
 304
 305 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
 306                               u8 shift, u8 width, const char * const *parents,
 307                               int num_parents, void (*fixup)(u32 *val));
 308
 309 static inline struct clk *to_clk(struct clk_hw *hw)
 310 {
 311         if (IS_ERR_OR_NULL(hw))
 312                 return ERR_CAST(hw);
 313         return hw->clk;
 314 }
 315
 316 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
 317 {
 318         return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
 319 }
 320
 321 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
 322                 const char *parent, unsigned int mult, unsigned int div)
 323 {
 324         return clk_hw_register_fixed_factor(NULL, name, parent,
 325                         CLK_SET_RATE_PARENT, mult, div);
 326 }
 327
 328 static inline struct clk_hw *__imx_clk_hw_divider(const char *name,
 329                                                    const char *parent,
 330                                                    void __iomem *reg, u8 shift,
 331                                                    u8 width, unsigned long flags)
 332 {
 333         return clk_hw_register_divider(NULL, name, parent, flags,
 334                                        reg, shift, width, 0, &imx_ccm_lock);
 335 }
 336
 337 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,
 338                                                 void __iomem *reg, u8 shift,
 339                                                 unsigned long flags,
 340                                                 unsigned long clk_gate_flags)
 341 {
 342         return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 343                                         shift, clk_gate_flags, &imx_ccm_lock);
 344 }
 345
 346 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,
 347                                                 void __iomem *reg, u8 shift, u8 cgr_val,
 348                                                 unsigned long flags,
 349                                                 unsigned int *share_count)
 350 {
 351         return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 352                                         shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count);
 353 }
 354
 355 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,
 356                         u8 shift, u8 width, const char * const *parents,
 357                         int num_parents, unsigned long flags, unsigned long clk_mux_flags)
 358 {
 359         return clk_hw_register_mux(NULL, name, parents, num_parents,
 360                         flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
 361                         width, clk_mux_flags, &imx_ccm_lock);
 362 }
 363
 364 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 365                 struct clk *div, struct clk *mux, struct clk *pll,
 366                 struct clk *step);
 367
 368 #define IMX_COMPOSITE_CORE              BIT(0)
 369 #define IMX_COMPOSITE_BUS               BIT(1)
 370 #define IMX_COMPOSITE_FW_MANAGED        BIT(2)
 371
 372 #define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \
 373         (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 374 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \
 375         (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL)
 376 #define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \
 377         (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE)
 378 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \
 379         (IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL)
 380
 381 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
 382                                             const char * const *parent_names,
 383                                             int num_parents,
 384                                             void __iomem *reg,
 385                                             u32 composite_flags,
 386                                             unsigned long flags);
 387
 388 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
 389         __imx8m_clk_hw_composite(name, parent_names, \
 390                 ARRAY_SIZE(parent_names), reg, composite_flags, flags)
 391
 392 #define imx8m_clk_hw_composite(name, parent_names, reg) \
 393         _imx8m_clk_hw_composite(name, parent_names, reg, \
 394                         IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
 395
 396 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
 397         _imx8m_clk_hw_composite(name, parent_names, reg, \
 398                         IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
 399
 400 #define imx8m_clk_hw_composite_bus(name, parent_names, reg)     \
 401         _imx8m_clk_hw_composite(name, parent_names, reg, \
 402                         IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
 403
 404 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg)    \
 405         _imx8m_clk_hw_composite(name, parent_names, reg, \
 406                         IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
 407
 408 #define imx8m_clk_hw_composite_core(name, parent_names, reg)    \
 409         _imx8m_clk_hw_composite(name, parent_names, reg, \
 410                         IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
 411
 412 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
 413         _imx8m_clk_hw_composite(name, parent_names, reg, \
 414                         IMX_COMPOSITE_FW_MANAGED, \
 415                         IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE)
 416
 417 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
 418         _imx8m_clk_hw_composite(name, parent_names, reg, \
 419                         IMX_COMPOSITE_FW_MANAGED, \
 420                         IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)
 421
 422 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
 423                 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
 424                 u8 clk_divider_flags, const struct clk_div_table *table,
 425                 spinlock_t *lock);
 426 #endif