drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30
  31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
  32 {
  33         DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
  34         DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
  35         DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
  36         DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
  37         DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
  38         DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
  39         DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
  40         DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
  41         DRM_DEBUG("ucode_array_offset_bytes: %u\n",
  42                   le32_to_cpu(hdr->ucode_array_offset_bytes));
  43         DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
  44 }
  45
  46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
  47 {
  48         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  49         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  50
  51         DRM_DEBUG("MC\n");
  52         amdgpu_ucode_print_common_hdr(hdr);
  53
  54         if (version_major == 1) {
  55                 const struct mc_firmware_header_v1_0 *mc_hdr =
  56                         container_of(hdr, struct mc_firmware_header_v1_0, header);
  57
  58                 DRM_DEBUG("io_debug_size_bytes: %u\n",
  59                           le32_to_cpu(mc_hdr->io_debug_size_bytes));
  60                 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
  61                           le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
  62         } else {
  63                 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
  64         }
  65 }
  66
  67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
  68 {
  69         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  70         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  71         const struct smc_firmware_header_v1_0 *v1_0_hdr;
  72         const struct smc_firmware_header_v2_0 *v2_0_hdr;
  73         const struct smc_firmware_header_v2_1 *v2_1_hdr;
  74
  75         DRM_DEBUG("SMC\n");
  76         amdgpu_ucode_print_common_hdr(hdr);
  77
  78         if (version_major == 1) {
  79                 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
  80                 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
  81         } else if (version_major == 2) {
  82                 switch (version_minor) {
  83                 case 0:
  84                         v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
  85                         DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
  86                         DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
  87                         break;
  88                 case 1:
  89                         v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
  90                         DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
  91                         DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
  92                         break;
  93                 default:
  94                         break;
  95                 }
  96
  97         } else {
  98                 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
  99         }
 100 }
 101
 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
 103 {
 104         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 105         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 106
 107         DRM_DEBUG("GFX\n");
 108         amdgpu_ucode_print_common_hdr(hdr);
 109
 110         if (version_major == 1) {
 111                 const struct gfx_firmware_header_v1_0 *gfx_hdr =
 112                         container_of(hdr, struct gfx_firmware_header_v1_0, header);
 113
 114                 DRM_DEBUG("ucode_feature_version: %u\n",
 115                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 116                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
 117                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
 118         } else if (version_major == 2) {
 119                 const struct gfx_firmware_header_v2_0 *gfx_hdr =
 120                         container_of(hdr, struct gfx_firmware_header_v2_0, header);
 121
 122                 DRM_DEBUG("ucode_feature_version: %u\n",
 123                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 124         } else {
 125                 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
 126         }
 127 }
 128
 129 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
 130 {
 131         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 132         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 133
 134         DRM_DEBUG("RLC\n");
 135         amdgpu_ucode_print_common_hdr(hdr);
 136
 137         if (version_major == 1) {
 138                 const struct rlc_firmware_header_v1_0 *rlc_hdr =
 139                         container_of(hdr, struct rlc_firmware_header_v1_0, header);
 140
 141                 DRM_DEBUG("ucode_feature_version: %u\n",
 142                           le32_to_cpu(rlc_hdr->ucode_feature_version));
 143                 DRM_DEBUG("save_and_restore_offset: %u\n",
 144                           le32_to_cpu(rlc_hdr->save_and_restore_offset));
 145                 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 146                           le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 147                 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 148                           le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 149                 DRM_DEBUG("master_pkt_description_offset: %u\n",
 150                           le32_to_cpu(rlc_hdr->master_pkt_description_offset));
 151         } else if (version_major == 2) {
 152                 const struct rlc_firmware_header_v2_0 *rlc_hdr =
 153                         container_of(hdr, struct rlc_firmware_header_v2_0, header);
 154                 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
 155                         container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
 156                 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
 157                         container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
 158                 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
 159                         container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
 160                 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
 161                         container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
 162
 163                 switch (version_minor) {
 164                 case 0:
 165                         /* rlc_hdr v2_0 */
 166                         DRM_DEBUG("ucode_feature_version: %u\n",
 167                                   le32_to_cpu(rlc_hdr->ucode_feature_version));
 168                         DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
 169                         DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
 170                         DRM_DEBUG("save_and_restore_offset: %u\n",
 171                                   le32_to_cpu(rlc_hdr->save_and_restore_offset));
 172                         DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 173                                   le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 174                         DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 175                                   le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 176                         DRM_DEBUG("reg_restore_list_size: %u\n",
 177                                   le32_to_cpu(rlc_hdr->reg_restore_list_size));
 178                         DRM_DEBUG("reg_list_format_start: %u\n",
 179                                   le32_to_cpu(rlc_hdr->reg_list_format_start));
 180                         DRM_DEBUG("reg_list_format_separate_start: %u\n",
 181                                   le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
 182                         DRM_DEBUG("starting_offsets_start: %u\n",
 183                                   le32_to_cpu(rlc_hdr->starting_offsets_start));
 184                         DRM_DEBUG("reg_list_format_size_bytes: %u\n",
 185                                   le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
 186                         DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
 187                                   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 188                         DRM_DEBUG("reg_list_size_bytes: %u\n",
 189                                   le32_to_cpu(rlc_hdr->reg_list_size_bytes));
 190                         DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
 191                                   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 192                         DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
 193                                   le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
 194                         DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
 195                                   le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
 196                         DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
 197                                   le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
 198                         DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
 199                                   le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
 200                         break;
 201                 case 1:
 202                         /* rlc_hdr v2_1 */
 203                         DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
 204                                   le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
 205                         DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
 206                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
 207                         DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
 208                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
 209                         DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
 210                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
 211                         DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
 212                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
 213                         DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
 214                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
 215                         DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
 216                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
 217                         DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
 218                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
 219                         DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
 220                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
 221                         DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
 222                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
 223                         DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
 224                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
 225                         DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
 226                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
 227                         DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
 228                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
 229                         break;
 230                 case 2:
 231                         /* rlc_hdr v2_2 */
 232                         DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
 233                                   le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
 234                         DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
 235                                   le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
 236                         DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
 237                                   le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
 238                         DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
 239                                   le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
 240                         break;
 241                 case 3:
 242                         /* rlc_hdr v2_3 */
 243                         DRM_DEBUG("rlcp_ucode_version: %u\n",
 244                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
 245                         DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
 246                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
 247                         DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
 248                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
 249                         DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
 250                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
 251                         DRM_DEBUG("rlcv_ucode_version: %u\n",
 252                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
 253                         DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
 254                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
 255                         DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
 256                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
 257                         DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
 258                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
 259                         break;
 260                 case 4:
 261                         /* rlc_hdr v2_4 */
 262                         DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
 263                                   le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
 264                         DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
 265                                   le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
 266                         DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
 267                                   le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
 268                         DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
 269                                   le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
 270                         DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
 271                                   le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
 272                         DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
 273                                   le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
 274                         DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
 275                                   le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
 276                         DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
 277                                   le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
 278                         DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
 279                                   le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
 280                         DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
 281                                   le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
 282                         break;
 283                 default:
 284                         DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
 285                         break;
 286                 }
 287         } else {
 288                 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
 289         }
 290 }
 291
 292 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
 293 {
 294         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 295         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 296
 297         DRM_DEBUG("SDMA\n");
 298         amdgpu_ucode_print_common_hdr(hdr);
 299
 300         if (version_major == 1) {
 301                 const struct sdma_firmware_header_v1_0 *sdma_hdr =
 302                         container_of(hdr, struct sdma_firmware_header_v1_0, header);
 303
 304                 DRM_DEBUG("ucode_feature_version: %u\n",
 305                           le32_to_cpu(sdma_hdr->ucode_feature_version));
 306                 DRM_DEBUG("ucode_change_version: %u\n",
 307                           le32_to_cpu(sdma_hdr->ucode_change_version));
 308                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
 309                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
 310                 if (version_minor >= 1) {
 311                         const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
 312                                 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
 313                         DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
 314                 }
 315         } else if (version_major == 2) {
 316                 const struct sdma_firmware_header_v2_0 *sdma_hdr =
 317                         container_of(hdr, struct sdma_firmware_header_v2_0, header);
 318
 319                 DRM_DEBUG("ucode_feature_version: %u\n",
 320                           le32_to_cpu(sdma_hdr->ucode_feature_version));
 321                 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
 322                 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
 323                 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
 324                 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
 325                 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
 326         } else {
 327                 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
 328                           version_major, version_minor);
 329         }
 330 }
 331
 332 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
 333 {
 334         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 335         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 336         uint32_t fw_index;
 337         const struct psp_fw_bin_desc *desc;
 338
 339         DRM_DEBUG("PSP\n");
 340         amdgpu_ucode_print_common_hdr(hdr);
 341
 342         if (version_major == 1) {
 343                 const struct psp_firmware_header_v1_0 *psp_hdr =
 344                         container_of(hdr, struct psp_firmware_header_v1_0, header);
 345
 346                 DRM_DEBUG("ucode_feature_version: %u\n",
 347                           le32_to_cpu(psp_hdr->sos.fw_version));
 348                 DRM_DEBUG("sos_offset_bytes: %u\n",
 349                           le32_to_cpu(psp_hdr->sos.offset_bytes));
 350                 DRM_DEBUG("sos_size_bytes: %u\n",
 351                           le32_to_cpu(psp_hdr->sos.size_bytes));
 352                 if (version_minor == 1) {
 353                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 354                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 355                         DRM_DEBUG("toc_header_version: %u\n",
 356                                   le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
 357                         DRM_DEBUG("toc_offset_bytes: %u\n",
 358                                   le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
 359                         DRM_DEBUG("toc_size_bytes: %u\n",
 360                                   le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
 361                         DRM_DEBUG("kdb_header_version: %u\n",
 362                                   le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
 363                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 364                                   le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
 365                         DRM_DEBUG("kdb_size_bytes: %u\n",
 366                                   le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
 367                 }
 368                 if (version_minor == 2) {
 369                         const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
 370                                 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
 371                         DRM_DEBUG("kdb_header_version: %u\n",
 372                                   le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
 373                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 374                                   le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
 375                         DRM_DEBUG("kdb_size_bytes: %u\n",
 376                                   le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
 377                 }
 378                 if (version_minor == 3) {
 379                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 380                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 381                         const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
 382                                 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
 383                         DRM_DEBUG("toc_header_version: %u\n",
 384                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
 385                         DRM_DEBUG("toc_offset_bytes: %u\n",
 386                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
 387                         DRM_DEBUG("toc_size_bytes: %u\n",
 388                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
 389                         DRM_DEBUG("kdb_header_version: %u\n",
 390                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
 391                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 392                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
 393                         DRM_DEBUG("kdb_size_bytes: %u\n",
 394                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
 395                         DRM_DEBUG("spl_header_version: %u\n",
 396                                   le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
 397                         DRM_DEBUG("spl_offset_bytes: %u\n",
 398                                   le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
 399                         DRM_DEBUG("spl_size_bytes: %u\n",
 400                                   le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
 401                 }
 402         } else if (version_major == 2) {
 403                 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
 404                          container_of(hdr, struct psp_firmware_header_v2_0, header);
 405                 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
 406                         desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
 407                         switch (desc->fw_type) {
 408                         case PSP_FW_TYPE_PSP_SOS:
 409                                 DRM_DEBUG("psp_sos_version: %u\n",
 410                                           le32_to_cpu(desc->fw_version));
 411                                 DRM_DEBUG("psp_sos_size_bytes: %u\n",
 412                                           le32_to_cpu(desc->size_bytes));
 413                                 break;
 414                         case PSP_FW_TYPE_PSP_SYS_DRV:
 415                                 DRM_DEBUG("psp_sys_drv_version: %u\n",
 416                                           le32_to_cpu(desc->fw_version));
 417                                 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
 418                                           le32_to_cpu(desc->size_bytes));
 419                                 break;
 420                         case PSP_FW_TYPE_PSP_KDB:
 421                                 DRM_DEBUG("psp_kdb_version: %u\n",
 422                                           le32_to_cpu(desc->fw_version));
 423                                 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
 424                                           le32_to_cpu(desc->size_bytes));
 425                                 break;
 426                         case PSP_FW_TYPE_PSP_TOC:
 427                                 DRM_DEBUG("psp_toc_version: %u\n",
 428                                           le32_to_cpu(desc->fw_version));
 429                                 DRM_DEBUG("psp_toc_size_bytes: %u\n",
 430                                           le32_to_cpu(desc->size_bytes));
 431                                 break;
 432                         case PSP_FW_TYPE_PSP_SPL:
 433                                 DRM_DEBUG("psp_spl_version: %u\n",
 434                                           le32_to_cpu(desc->fw_version));
 435                                 DRM_DEBUG("psp_spl_size_bytes: %u\n",
 436                                           le32_to_cpu(desc->size_bytes));
 437                                 break;
 438                         case PSP_FW_TYPE_PSP_RL:
 439                                 DRM_DEBUG("psp_rl_version: %u\n",
 440                                           le32_to_cpu(desc->fw_version));
 441                                 DRM_DEBUG("psp_rl_size_bytes: %u\n",
 442                                           le32_to_cpu(desc->size_bytes));
 443                                 break;
 444                         case PSP_FW_TYPE_PSP_SOC_DRV:
 445                                 DRM_DEBUG("psp_soc_drv_version: %u\n",
 446                                           le32_to_cpu(desc->fw_version));
 447                                 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
 448                                           le32_to_cpu(desc->size_bytes));
 449                                 break;
 450                         case PSP_FW_TYPE_PSP_INTF_DRV:
 451                                 DRM_DEBUG("psp_intf_drv_version: %u\n",
 452                                           le32_to_cpu(desc->fw_version));
 453                                 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
 454                                           le32_to_cpu(desc->size_bytes));
 455                                 break;
 456                         case PSP_FW_TYPE_PSP_DBG_DRV:
 457                                 DRM_DEBUG("psp_dbg_drv_version: %u\n",
 458                                           le32_to_cpu(desc->fw_version));
 459                                 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
 460                                           le32_to_cpu(desc->size_bytes));
 461                                 break;
 462                         default:
 463                                 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
 464                                 break;
 465                         }
 466                 }
 467         } else {
 468                 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
 469                           version_major, version_minor);
 470         }
 471 }
 472
 473 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
 474 {
 475         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 476         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 477
 478         DRM_DEBUG("GPU_INFO\n");
 479         amdgpu_ucode_print_common_hdr(hdr);
 480
 481         if (version_major == 1) {
 482                 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
 483                         container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
 484
 485                 DRM_DEBUG("version_major: %u\n",
 486                           le16_to_cpu(gpu_info_hdr->version_major));
 487                 DRM_DEBUG("version_minor: %u\n",
 488                           le16_to_cpu(gpu_info_hdr->version_minor));
 489         } else {
 490                 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
 491         }
 492 }
 493
 494 static int amdgpu_ucode_validate(const struct firmware *fw)
 495 {
 496         const struct common_firmware_header *hdr =
 497                 (const struct common_firmware_header *)fw->data;
 498
 499         if (fw->size == le32_to_cpu(hdr->size_bytes))
 500                 return 0;
 501
 502         return -EINVAL;
 503 }
 504
 505 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 506                                 uint16_t hdr_major, uint16_t hdr_minor)
 507 {
 508         if ((hdr->common.header_version_major == hdr_major) &&
 509                 (hdr->common.header_version_minor == hdr_minor))
 510                 return true;
 511         return false;
 512 }
 513
 514 enum amdgpu_firmware_load_type
 515 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 516 {
 517         switch (adev->asic_type) {
 518 #ifdef CONFIG_DRM_AMDGPU_SI
 519         case CHIP_TAHITI:
 520         case CHIP_PITCAIRN:
 521         case CHIP_VERDE:
 522         case CHIP_OLAND:
 523         case CHIP_HAINAN:
 524                 return AMDGPU_FW_LOAD_DIRECT;
 525 #endif
 526 #ifdef CONFIG_DRM_AMDGPU_CIK
 527         case CHIP_BONAIRE:
 528         case CHIP_KAVERI:
 529         case CHIP_KABINI:
 530         case CHIP_HAWAII:
 531         case CHIP_MULLINS:
 532                 return AMDGPU_FW_LOAD_DIRECT;
 533 #endif
 534         case CHIP_TOPAZ:
 535         case CHIP_TONGA:
 536         case CHIP_FIJI:
 537         case CHIP_CARRIZO:
 538         case CHIP_STONEY:
 539         case CHIP_POLARIS10:
 540         case CHIP_POLARIS11:
 541         case CHIP_POLARIS12:
 542         case CHIP_VEGAM:
 543                 return AMDGPU_FW_LOAD_SMU;
 544         case CHIP_CYAN_SKILLFISH:
 545                 if (!(load_type &&
 546                       adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
 547                         return AMDGPU_FW_LOAD_DIRECT;
 548                 else
 549                         return AMDGPU_FW_LOAD_PSP;
 550         default:
 551                 if (!load_type)
 552                         return AMDGPU_FW_LOAD_DIRECT;
 553                 else
 554                         return AMDGPU_FW_LOAD_PSP;
 555         }
 556 }
 557
 558 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
 559 {
 560         switch (ucode_id) {
 561         case AMDGPU_UCODE_ID_SDMA0:
 562                 return "SDMA0";
 563         case AMDGPU_UCODE_ID_SDMA1:
 564                 return "SDMA1";
 565         case AMDGPU_UCODE_ID_SDMA2:
 566                 return "SDMA2";
 567         case AMDGPU_UCODE_ID_SDMA3:
 568                 return "SDMA3";
 569         case AMDGPU_UCODE_ID_SDMA4:
 570                 return "SDMA4";
 571         case AMDGPU_UCODE_ID_SDMA5:
 572                 return "SDMA5";
 573         case AMDGPU_UCODE_ID_SDMA6:
 574                 return "SDMA6";
 575         case AMDGPU_UCODE_ID_SDMA7:
 576                 return "SDMA7";
 577         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
 578                 return "SDMA_CTX";
 579         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
 580                 return "SDMA_CTL";
 581         case AMDGPU_UCODE_ID_CP_CE:
 582                 return "CP_CE";
 583         case AMDGPU_UCODE_ID_CP_PFP:
 584                 return "CP_PFP";
 585         case AMDGPU_UCODE_ID_CP_ME:
 586                 return "CP_ME";
 587         case AMDGPU_UCODE_ID_CP_MEC1:
 588                 return "CP_MEC1";
 589         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 590                 return "CP_MEC1_JT";
 591         case AMDGPU_UCODE_ID_CP_MEC2:
 592                 return "CP_MEC2";
 593         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 594                 return "CP_MEC2_JT";
 595         case AMDGPU_UCODE_ID_CP_MES:
 596                 return "CP_MES";
 597         case AMDGPU_UCODE_ID_CP_MES_DATA:
 598                 return "CP_MES_DATA";
 599         case AMDGPU_UCODE_ID_CP_MES1:
 600                 return "CP_MES_KIQ";
 601         case AMDGPU_UCODE_ID_CP_MES1_DATA:
 602                 return "CP_MES_KIQ_DATA";
 603         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 604                 return "RLC_RESTORE_LIST_CNTL";
 605         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 606                 return "RLC_RESTORE_LIST_GPM_MEM";
 607         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 608                 return "RLC_RESTORE_LIST_SRM_MEM";
 609         case AMDGPU_UCODE_ID_RLC_IRAM:
 610                 return "RLC_IRAM";
 611         case AMDGPU_UCODE_ID_RLC_DRAM:
 612                 return "RLC_DRAM";
 613         case AMDGPU_UCODE_ID_RLC_G:
 614                 return "RLC_G";
 615         case AMDGPU_UCODE_ID_RLC_P:
 616                 return "RLC_P";
 617         case AMDGPU_UCODE_ID_RLC_V:
 618                 return "RLC_V";
 619         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
 620                 return "GLOBAL_TAP_DELAYS";
 621         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
 622                 return "SE0_TAP_DELAYS";
 623         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
 624                 return "SE1_TAP_DELAYS";
 625         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
 626                 return "SE2_TAP_DELAYS";
 627         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
 628                 return "SE3_TAP_DELAYS";
 629         case AMDGPU_UCODE_ID_IMU_I:
 630                 return "IMU_I";
 631         case AMDGPU_UCODE_ID_IMU_D:
 632                 return "IMU_D";
 633         case AMDGPU_UCODE_ID_STORAGE:
 634                 return "STORAGE";
 635         case AMDGPU_UCODE_ID_SMC:
 636                 return "SMC";
 637         case AMDGPU_UCODE_ID_PPTABLE:
 638                 return "PPTABLE";
 639         case AMDGPU_UCODE_ID_UVD:
 640                 return "UVD";
 641         case AMDGPU_UCODE_ID_UVD1:
 642                 return "UVD1";
 643         case AMDGPU_UCODE_ID_VCE:
 644                 return "VCE";
 645         case AMDGPU_UCODE_ID_VCN:
 646                 return "VCN";
 647         case AMDGPU_UCODE_ID_VCN1:
 648                 return "VCN1";
 649         case AMDGPU_UCODE_ID_DMCU_ERAM:
 650                 return "DMCU_ERAM";
 651         case AMDGPU_UCODE_ID_DMCU_INTV:
 652                 return "DMCU_INTV";
 653         case AMDGPU_UCODE_ID_VCN0_RAM:
 654                 return "VCN0_RAM";
 655         case AMDGPU_UCODE_ID_VCN1_RAM:
 656                 return "VCN1_RAM";
 657         case AMDGPU_UCODE_ID_DMCUB:
 658                 return "DMCUB";
 659         case AMDGPU_UCODE_ID_CAP:
 660                 return "CAP";
 661         default:
 662                 return "UNKNOWN UCODE";
 663         }
 664 }
 665
 666 #define FW_VERSION_ATTR(name, mode, field)                              \
 667 static ssize_t show_##name(struct device *dev,                          \
 668                           struct device_attribute *attr,                \
 669                           char *buf)                                    \
 670 {                                                                       \
 671         struct drm_device *ddev = dev_get_drvdata(dev);                 \
 672         struct amdgpu_device *adev = drm_to_adev(ddev);                 \
 673                                                                         \
 674         return sysfs_emit(buf, "0x%08x\n", adev->field);        \
 675 }                                                                       \
 676 static DEVICE_ATTR(name, mode, show_##name, NULL)
 677
 678 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
 679 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
 680 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
 681 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
 682 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
 683 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
 684 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
 685 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
 686 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
 687 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
 688 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
 689 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
 690 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
 691 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
 692 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
 693 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
 694 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
 695 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
 696 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
 697 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
 698 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
 699 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
 700
 701 static struct attribute *fw_attrs[] = {
 702         &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
 703         &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
 704         &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
 705         &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
 706         &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
 707         &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
 708         &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
 709         &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
 710         &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
 711         &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
 712         &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
 713         NULL
 714 };
 715
 716 static const struct attribute_group fw_attr_group = {
 717         .name = "fw_version",
 718         .attrs = fw_attrs
 719 };
 720
 721 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
 722 {
 723         return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
 724 }
 725
 726 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
 727 {
 728         sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
 729 }
 730
 731 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 732                                        struct amdgpu_firmware_info *ucode,
 733                                        uint64_t mc_addr, void *kptr)
 734 {
 735         const struct common_firmware_header *header = NULL;
 736         const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
 737         const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
 738         const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
 739         const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
 740         const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
 741         const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
 742         const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
 743         u8 *ucode_addr;
 744
 745         if (NULL == ucode->fw)
 746                 return 0;
 747
 748         ucode->mc_addr = mc_addr;
 749         ucode->kaddr = kptr;
 750
 751         if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
 752                 return 0;
 753
 754         header = (const struct common_firmware_header *)ucode->fw->data;
 755         cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 756         cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
 757         dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
 758         dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
 759         mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
 760         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
 761         imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
 762
 763         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 764                 switch (ucode->ucode_id) {
 765                 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
 766                         ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
 767                         ucode_addr = (u8 *)ucode->fw->data +
 768                                 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
 769                         break;
 770                 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
 771                         ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
 772                         ucode_addr = (u8 *)ucode->fw->data +
 773                                 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
 774                         break;
 775                 case AMDGPU_UCODE_ID_CP_MEC1:
 776                 case AMDGPU_UCODE_ID_CP_MEC2:
 777                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 778                                 le32_to_cpu(cp_hdr->jt_size) * 4;
 779                         ucode_addr = (u8 *)ucode->fw->data +
 780                                 le32_to_cpu(header->ucode_array_offset_bytes);
 781                         break;
 782                 case AMDGPU_UCODE_ID_CP_MEC1_JT:
 783                 case AMDGPU_UCODE_ID_CP_MEC2_JT:
 784                         ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
 785                         ucode_addr = (u8 *)ucode->fw->data +
 786                                 le32_to_cpu(header->ucode_array_offset_bytes) +
 787                                 le32_to_cpu(cp_hdr->jt_offset) * 4;
 788                         break;
 789                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 790                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
 791                         ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
 792                         break;
 793                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 794                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
 795                         ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
 796                         break;
 797                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 798                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
 799                         ucode_addr = adev->gfx.rlc.save_restore_list_srm;
 800                         break;
 801                 case AMDGPU_UCODE_ID_RLC_IRAM:
 802                         ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
 803                         ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
 804                         break;
 805                 case AMDGPU_UCODE_ID_RLC_DRAM:
 806                         ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
 807                         ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
 808                         break;
 809                 case AMDGPU_UCODE_ID_RLC_P:
 810                         ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
 811                         ucode_addr = adev->gfx.rlc.rlcp_ucode;
 812                         break;
 813                 case AMDGPU_UCODE_ID_RLC_V:
 814                         ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
 815                         ucode_addr = adev->gfx.rlc.rlcv_ucode;
 816                         break;
 817                 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
 818                         ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
 819                         ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
 820                         break;
 821                 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
 822                         ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
 823                         ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
 824                         break;
 825                 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
 826                         ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
 827                         ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
 828                         break;
 829                 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
 830                         ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
 831                         ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
 832                         break;
 833                 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
 834                         ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
 835                         ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
 836                         break;
 837                 case AMDGPU_UCODE_ID_CP_MES:
 838                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 839                         ucode_addr = (u8 *)ucode->fw->data +
 840                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
 841                         break;
 842                 case AMDGPU_UCODE_ID_CP_MES_DATA:
 843                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 844                         ucode_addr = (u8 *)ucode->fw->data +
 845                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
 846                         break;
 847                 case AMDGPU_UCODE_ID_CP_MES1:
 848                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 849                         ucode_addr = (u8 *)ucode->fw->data +
 850                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
 851                         break;
 852                 case AMDGPU_UCODE_ID_CP_MES1_DATA:
 853                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 854                         ucode_addr = (u8 *)ucode->fw->data +
 855                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
 856                         break;
 857                 case AMDGPU_UCODE_ID_DMCU_ERAM:
 858                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 859                                 le32_to_cpu(dmcu_hdr->intv_size_bytes);
 860                         ucode_addr = (u8 *)ucode->fw->data +
 861                                 le32_to_cpu(header->ucode_array_offset_bytes);
 862                         break;
 863                 case AMDGPU_UCODE_ID_DMCU_INTV:
 864                         ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
 865                         ucode_addr = (u8 *)ucode->fw->data +
 866                                 le32_to_cpu(header->ucode_array_offset_bytes) +
 867                                 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
 868                         break;
 869                 case AMDGPU_UCODE_ID_DMCUB:
 870                         ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
 871                         ucode_addr = (u8 *)ucode->fw->data +
 872                                 le32_to_cpu(header->ucode_array_offset_bytes);
 873                         break;
 874                 case AMDGPU_UCODE_ID_PPTABLE:
 875                         ucode->ucode_size = ucode->fw->size;
 876                         ucode_addr = (u8 *)ucode->fw->data;
 877                         break;
 878                 case AMDGPU_UCODE_ID_IMU_I:
 879                         ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
 880                         ucode_addr = (u8 *)ucode->fw->data +
 881                                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
 882                         break;
 883                 case AMDGPU_UCODE_ID_IMU_D:
 884                         ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
 885                         ucode_addr = (u8 *)ucode->fw->data +
 886                                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
 887                                 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
 888                         break;
 889                 case AMDGPU_UCODE_ID_CP_RS64_PFP:
 890                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
 891                         ucode_addr = (u8 *)ucode->fw->data +
 892                                 le32_to_cpu(header->ucode_array_offset_bytes);
 893                         break;
 894                 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
 895                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 896                         ucode_addr = (u8 *)ucode->fw->data +
 897                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 898                         break;
 899                 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
 900                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 901                         ucode_addr = (u8 *)ucode->fw->data +
 902                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 903                         break;
 904                 case AMDGPU_UCODE_ID_CP_RS64_ME:
 905                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
 906                         ucode_addr = (u8 *)ucode->fw->data +
 907                                 le32_to_cpu(header->ucode_array_offset_bytes);
 908                         break;
 909                 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
 910                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 911                         ucode_addr = (u8 *)ucode->fw->data +
 912                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 913                         break;
 914                 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
 915                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 916                         ucode_addr = (u8 *)ucode->fw->data +
 917                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 918                         break;
 919                 case AMDGPU_UCODE_ID_CP_RS64_MEC:
 920                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
 921                         ucode_addr = (u8 *)ucode->fw->data +
 922                                 le32_to_cpu(header->ucode_array_offset_bytes);
 923                         break;
 924                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
 925                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 926                         ucode_addr = (u8 *)ucode->fw->data +
 927                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 928                         break;
 929                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
 930                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 931                         ucode_addr = (u8 *)ucode->fw->data +
 932                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 933                         break;
 934                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
 935                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 936                         ucode_addr = (u8 *)ucode->fw->data +
 937                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 938                         break;
 939                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
 940                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 941                         ucode_addr = (u8 *)ucode->fw->data +
 942                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 943                         break;
 944                 default:
 945                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 946                         ucode_addr = (u8 *)ucode->fw->data +
 947                                 le32_to_cpu(header->ucode_array_offset_bytes);
 948                         break;
 949                 }
 950         } else {
 951                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 952                 ucode_addr = (u8 *)ucode->fw->data +
 953                         le32_to_cpu(header->ucode_array_offset_bytes);
 954         }
 955
 956         memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
 957
 958         return 0;
 959 }
 960
 961 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
 962                                 uint64_t mc_addr, void *kptr)
 963 {
 964         const struct gfx_firmware_header_v1_0 *header = NULL;
 965         const struct common_firmware_header *comm_hdr = NULL;
 966         uint8_t *src_addr = NULL;
 967         uint8_t *dst_addr = NULL;
 968
 969         if (NULL == ucode->fw)
 970                 return 0;
 971
 972         comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
 973         header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 974         dst_addr = ucode->kaddr +
 975                            ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
 976                            PAGE_SIZE);
 977         src_addr = (uint8_t *)ucode->fw->data +
 978                            le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
 979                            (le32_to_cpu(header->jt_offset) * 4);
 980         memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
 981
 982         return 0;
 983 }
 984
 985 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
 986 {
 987         if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
 988                 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
 989                         amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 990                         &adev->firmware.fw_buf,
 991                         &adev->firmware.fw_buf_mc,
 992                         &adev->firmware.fw_buf_ptr);
 993                 if (!adev->firmware.fw_buf) {
 994                         dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
 995                         return -ENOMEM;
 996                 } else if (amdgpu_sriov_vf(adev)) {
 997                         memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
 998                 }
 999         }
1000         return 0;
1001 }
1002
1003 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
1004 {
1005         amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
1006                 &adev->firmware.fw_buf_mc,
1007                 &adev->firmware.fw_buf_ptr);
1008 }
1009
1010 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
1011 {
1012         uint64_t fw_offset = 0;
1013         int i;
1014         struct amdgpu_firmware_info *ucode = NULL;
1015
1016  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
1017         if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
1018                 return 0;
1019         /*
1020          * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
1021          * ucode info here
1022          */
1023         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1024                 if (amdgpu_sriov_vf(adev))
1025                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
1026                 else
1027                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
1028         } else {
1029                 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
1030         }
1031
1032         for (i = 0; i < adev->firmware.max_ucodes; i++) {
1033                 ucode = &adev->firmware.ucode[i];
1034                 if (ucode->fw) {
1035                         amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
1036                                                     adev->firmware.fw_buf_ptr + fw_offset);
1037                         if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
1038                             adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1039                                 const struct gfx_firmware_header_v1_0 *cp_hdr;
1040                                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1041                                 amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
1042                                                     adev->firmware.fw_buf_ptr + fw_offset);
1043                                 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1044                         }
1045                         fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
1046                 }
1047         }
1048         return 0;
1049 }
1050
1051 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type)
1052 {
1053         if (block_type == MP0_HWIP) {
1054                 switch (adev->ip_versions[MP0_HWIP][0]) {
1055                 case IP_VERSION(9, 0, 0):
1056                         switch (adev->asic_type) {
1057                         case CHIP_VEGA10:
1058                                 return "vega10";
1059                         case CHIP_VEGA12:
1060                                 return "vega12";
1061                         default:
1062                                 return NULL;
1063                         }
1064                 case IP_VERSION(10, 0, 0):
1065                 case IP_VERSION(10, 0, 1):
1066                         if (adev->asic_type == CHIP_RAVEN) {
1067                                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1068                                         return "raven2";
1069                                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1070                                         return "picasso";
1071                                 return "raven";
1072                         }
1073                         break;
1074                 case IP_VERSION(11, 0, 0):
1075                         return "navi10";
1076                 case IP_VERSION(11, 0, 2):
1077                         return "vega20";
1078                 case IP_VERSION(11, 0, 3):
1079                         return "renoir";
1080                 case IP_VERSION(11, 0, 4):
1081                         return "arcturus";
1082                 case IP_VERSION(11, 0, 5):
1083                         return "navi14";
1084                 case IP_VERSION(11, 0, 7):
1085                         return "sienna_cichlid";
1086                 case IP_VERSION(11, 0, 9):
1087                         return "navi12";
1088                 case IP_VERSION(11, 0, 11):
1089                         return "navy_flounder";
1090                 case IP_VERSION(11, 0, 12):
1091                         return "dimgrey_cavefish";
1092                 case IP_VERSION(11, 0, 13):
1093                         return "beige_goby";
1094                 case IP_VERSION(11, 5, 0):
1095                         return "vangogh";
1096                 case IP_VERSION(12, 0, 1):
1097                         return "green_sardine";
1098                 case IP_VERSION(13, 0, 2):
1099                         return "aldebaran";
1100                 case IP_VERSION(13, 0, 1):
1101                 case IP_VERSION(13, 0, 3):
1102                         return "yellow_carp";
1103                 }
1104         } else if (block_type == MP1_HWIP) {
1105                 switch (adev->ip_versions[MP1_HWIP][0]) {
1106                 case IP_VERSION(9, 0, 0):
1107                 case IP_VERSION(10, 0, 0):
1108                 case IP_VERSION(10, 0, 1):
1109                 case IP_VERSION(11, 0, 2):
1110                         if (adev->asic_type == CHIP_ARCTURUS)
1111                                 return "arcturus_smc";
1112                         return NULL;
1113                 case IP_VERSION(11, 0, 0):
1114                         return "navi10_smc";
1115                 case IP_VERSION(11, 0, 5):
1116                         return "navi14_smc";
1117                 case IP_VERSION(11, 0, 9):
1118                         return "navi12_smc";
1119                 case IP_VERSION(11, 0, 7):
1120                         return "sienna_cichlid_smc";
1121                 case IP_VERSION(11, 0, 11):
1122                         return "navy_flounder_smc";
1123                 case IP_VERSION(11, 0, 12):
1124                         return "dimgrey_cavefish_smc";
1125                 case IP_VERSION(11, 0, 13):
1126                         return "beige_goby_smc";
1127                 case IP_VERSION(13, 0, 2):
1128                         return "aldebaran_smc";
1129                 }
1130         } else if (block_type == SDMA0_HWIP) {
1131                 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1132                 case IP_VERSION(4, 0, 0):
1133                         return "vega10_sdma";
1134                 case IP_VERSION(4, 0, 1):
1135                         return "vega12_sdma";
1136                 case IP_VERSION(4, 1, 0):
1137                 case IP_VERSION(4, 1, 1):
1138                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1139                                 return "raven2_sdma";
1140                         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1141                                 return "picasso_sdma";
1142                         return "raven_sdma";
1143                 case IP_VERSION(4, 1, 2):
1144                         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1145                                 return "renoir_sdma";
1146                         return "green_sardine_sdma";
1147                 case IP_VERSION(4, 2, 0):
1148                         return "vega20_sdma";
1149                 case IP_VERSION(4, 2, 2):
1150                         return "arcturus_sdma";
1151                 case IP_VERSION(4, 4, 0):
1152                         return "aldebaran_sdma";
1153                 case IP_VERSION(5, 0, 0):
1154                         return "navi10_sdma";
1155                 case IP_VERSION(5, 0, 1):
1156                         return "cyan_skillfish2_sdma";
1157                 case IP_VERSION(5, 0, 2):
1158                         return "navi14_sdma";
1159                 case IP_VERSION(5, 0, 5):
1160                         return "navi12_sdma";
1161                 case IP_VERSION(5, 2, 0):
1162                         return "sienna_cichlid_sdma";
1163                 case IP_VERSION(5, 2, 2):
1164                         return "navy_flounder_sdma";
1165                 case IP_VERSION(5, 2, 4):
1166                         return "dimgrey_cavefish_sdma";
1167                 case IP_VERSION(5, 2, 5):
1168                         return "beige_goby_sdma";
1169                 case IP_VERSION(5, 2, 3):
1170                         return "yellow_carp_sdma";
1171                 case IP_VERSION(5, 2, 1):
1172                         return "vangogh_sdma";
1173                 }
1174         } else if (block_type == UVD_HWIP) {
1175                 switch (adev->ip_versions[UVD_HWIP][0]) {
1176                 case IP_VERSION(1, 0, 0):
1177                 case IP_VERSION(1, 0, 1):
1178                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1179                                 return "raven2_vcn";
1180                         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1181                                 return "picasso_vcn";
1182                         return "raven_vcn";
1183                 case IP_VERSION(2, 5, 0):
1184                         return "arcturus_vcn";
1185                 case IP_VERSION(2, 2, 0):
1186                         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1187                                 return "renoir_vcn";
1188                         return "green_sardine_vcn";
1189                 case IP_VERSION(2, 6, 0):
1190                         return "aldebaran_vcn";
1191                 case IP_VERSION(2, 0, 0):
1192                         return "navi10_vcn";
1193                 case IP_VERSION(2, 0, 2):
1194                         if (adev->asic_type == CHIP_NAVI12)
1195                                 return "navi12_vcn";
1196                         return "navi14_vcn";
1197                 case IP_VERSION(3, 0, 0):
1198                 case IP_VERSION(3, 0, 64):
1199                 case IP_VERSION(3, 0, 192):
1200                         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
1201                                 return "sienna_cichlid_vcn";
1202                         return "navy_flounder_vcn";
1203                 case IP_VERSION(3, 0, 2):
1204                         return "vangogh_vcn";
1205                 case IP_VERSION(3, 0, 16):
1206                         return "dimgrey_cavefish_vcn";
1207                 case IP_VERSION(3, 0, 33):
1208                         return "beige_goby_vcn";
1209                 case IP_VERSION(3, 1, 1):
1210                         return "yellow_carp_vcn";
1211                 }
1212         } else if (block_type == GC_HWIP) {
1213                 switch (adev->ip_versions[GC_HWIP][0]) {
1214                 case IP_VERSION(9, 0, 1):
1215                         return "vega10";
1216                 case IP_VERSION(9, 2, 1):
1217                         return "vega12";
1218                 case IP_VERSION(9, 4, 0):
1219                         return "vega20";
1220                 case IP_VERSION(9, 2, 2):
1221                 case IP_VERSION(9, 1, 0):
1222                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1223                                 return "raven2";
1224                         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1225                                 return "picasso";
1226                         return "raven";
1227                 case IP_VERSION(9, 4, 1):
1228                         return "arcturus";
1229                 case IP_VERSION(9, 3, 0):
1230                         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1231                                 return "renoir";
1232                         return "green_sardine";
1233                 case IP_VERSION(9, 4, 2):
1234                         return "aldebaran";
1235                 case IP_VERSION(10, 1, 10):
1236                         return "navi10";
1237                 case IP_VERSION(10, 1, 1):
1238                         return "navi14";
1239                 case IP_VERSION(10, 1, 2):
1240                         return "navi12";
1241                 case IP_VERSION(10, 3, 0):
1242                         return "sienna_cichlid";
1243                 case IP_VERSION(10, 3, 2):
1244                         return "navy_flounder";
1245                 case IP_VERSION(10, 3, 1):
1246                         return "vangogh";
1247                 case IP_VERSION(10, 3, 4):
1248                         return "dimgrey_cavefish";
1249                 case IP_VERSION(10, 3, 5):
1250                         return "beige_goby";
1251                 case IP_VERSION(10, 3, 3):
1252                         return "yellow_carp";
1253                 case IP_VERSION(10, 1, 3):
1254                 case IP_VERSION(10, 1, 4):
1255                         return "cyan_skillfish2";
1256                 }
1257         }
1258         return NULL;
1259 }
1260
1261 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
1262 {
1263         int maj, min, rev;
1264         char *ip_name;
1265         const char *legacy;
1266         uint32_t version = adev->ip_versions[block_type][0];
1267
1268         legacy = amdgpu_ucode_legacy_naming(adev, block_type);
1269         if (legacy) {
1270                 snprintf(ucode_prefix, len, "%s", legacy);
1271                 return;
1272         }
1273
1274         switch (block_type) {
1275         case GC_HWIP:
1276                 ip_name = "gc";
1277                 break;
1278         case SDMA0_HWIP:
1279                 ip_name = "sdma";
1280                 break;
1281         case MP0_HWIP:
1282                 ip_name = "psp";
1283                 break;
1284         case MP1_HWIP:
1285                 ip_name = "smu";
1286                 break;
1287         case UVD_HWIP:
1288                 ip_name = "vcn";
1289                 break;
1290         default:
1291                 BUG();
1292         }
1293
1294         maj = IP_VERSION_MAJ(version);
1295         min = IP_VERSION_MIN(version);
1296         rev = IP_VERSION_REV(version);
1297
1298         snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1299 }
1300
1301 /*
1302  * amdgpu_ucode_request - Fetch and validate amdgpu microcode
1303  *
1304  * @adev: amdgpu device
1305  * @fw: pointer to load firmware to
1306  * @fw_name: firmware to load
1307  *
1308  * This is a helper that will use request_firmware and amdgpu_ucode_validate
1309  * to load and run basic validation on firmware. If the load fails, remap
1310  * the error code to -ENODEV, so that early_init functions will fail to load.
1311  */
1312 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
1313                          const char *fw_name)
1314 {
1315         int err = request_firmware(fw, fw_name, adev->dev);
1316
1317         if (err)
1318                 return -ENODEV;
1319         err = amdgpu_ucode_validate(*fw);
1320         if (err)
1321                 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
1322
1323         return err;
1324 }
1325
1326 /*
1327  * amdgpu_ucode_release - Release firmware microcode
1328  *
1329  * @fw: pointer to firmware to release
1330  */
1331 void amdgpu_ucode_release(const struct firmware **fw)
1332 {
1333         release_firmware(*fw);
1334         *fw = NULL;
1335 }