drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include <linux/mmu_context.h>
  23 #include "amdgpu.h"
  24 #include "amdgpu_amdkfd.h"
  25 #include "gc/gc_10_1_0_offset.h"
  26 #include "gc/gc_10_1_0_sh_mask.h"
  27 #include "navi10_enum.h"
  28 #include "athub/athub_2_0_0_offset.h"
  29 #include "athub/athub_2_0_0_sh_mask.h"
  30 #include "oss/osssys_5_0_0_offset.h"
  31 #include "oss/osssys_5_0_0_sh_mask.h"
  32 #include "soc15_common.h"
  33 #include "v10_structs.h"
  34 #include "nv.h"
  35 #include "nvd.h"
  36 #include "gfxhub_v2_0.h"
  37
  38 enum hqd_dequeue_request_type {
  39         NO_ACTION = 0,
  40         DRAIN_PIPE,
  41         RESET_WAVES,
  42         SAVE_WAVES
  43 };
  44
  45 /* Because of REG_GET_FIELD() being used, we put this function in the
  46  * asic specific file.
  47  */
  48 static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
  49                 struct tile_config *config)
  50 {
  51         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
  52
  53         config->gb_addr_config = adev->gfx.config.gb_addr_config;
  54 #if 0
  55 /* TODO - confirm REG_GET_FIELD x2, should be OK as is... but
  56  * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu
  57  * changes commented out related code, doing the same here for now but
  58  * need to sync with Ken et al
  59  */
  60         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
  61                                 MC_ARB_RAMCFG, NOOFBANK);
  62         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
  63                                 MC_ARB_RAMCFG, NOOFRANKS);
  64 #endif
  65
  66         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
  67         config->num_tile_configs =
  68                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
  69         config->macro_tile_config_ptr =
  70                         adev->gfx.config.macrotile_mode_array;
  71         config->num_macro_tile_configs =
  72                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
  73
  74         return 0;
  75 }
  76
  77 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
  78 {
  79         return (struct amdgpu_device *)kgd;
  80 }
  81
  82 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
  83                         uint32_t queue, uint32_t vmid)
  84 {
  85         struct amdgpu_device *adev = get_amdgpu_device(kgd);
  86
  87         mutex_lock(&adev->srbm_mutex);
  88         nv_grbm_select(adev, mec, pipe, queue, vmid);
  89 }
  90
  91 static void unlock_srbm(struct kgd_dev *kgd)
  92 {
  93         struct amdgpu_device *adev = get_amdgpu_device(kgd);
  94
  95         nv_grbm_select(adev, 0, 0, 0, 0);
  96         mutex_unlock(&adev->srbm_mutex);
  97 }
  98
  99 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 100                                 uint32_t queue_id)
 101 {
 102         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 103
 104         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 105         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 106
 107         lock_srbm(kgd, mec, pipe, queue_id, 0);
 108 }
 109
 110 static uint64_t get_queue_mask(struct amdgpu_device *adev,
 111                                uint32_t pipe_id, uint32_t queue_id)
 112 {
 113         unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
 114                         queue_id;
 115
 116         return 1ull << bit;
 117 }
 118
 119 static void release_queue(struct kgd_dev *kgd)
 120 {
 121         unlock_srbm(kgd);
 122 }
 123
 124 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 125                                         uint32_t sh_mem_config,
 126                                         uint32_t sh_mem_ape1_base,
 127                                         uint32_t sh_mem_ape1_limit,
 128                                         uint32_t sh_mem_bases)
 129 {
 130         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 131
 132         lock_srbm(kgd, 0, 0, 0, vmid);
 133
 134         WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
 135         WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
 136         /* APE1 no longer exists on GFX9 */
 137
 138         unlock_srbm(kgd);
 139 }
 140
 141 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 142                                         unsigned int vmid)
 143 {
 144         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 145
 146         /*
 147          * We have to assume that there is no outstanding mapping.
 148          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 149          * a mapping is in progress or because a mapping finished
 150          * and the SW cleared it.
 151          * So the protocol is to always wait & clear.
 152          */
 153         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 154                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 155
 156         pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
 157
 158         pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
 159         WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
 160                pasid_mapping);
 161
 162 #if 0
 163         /* TODO: uncomment this code when the hardware support is ready. */
 164         while (!(RREG32(SOC15_REG_OFFSET(
 165                                 ATHUB, 0,
 166                                 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) &
 167                  (1U << vmid)))
 168                 cpu_relax();
 169
 170         pr_debug("ATHUB mapping update finished\n");
 171         WREG32(SOC15_REG_OFFSET(ATHUB, 0,
 172                                 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS),
 173                1U << vmid);
 174 #endif
 175
 176         /* Mapping vmid to pasid also for IH block */
 177         pr_debug("update mapping for IH block and mmhub");
 178         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
 179                pasid_mapping);
 180
 181         return 0;
 182 }
 183
 184 /* TODO - RING0 form of field is obsolete, seems to date back to SI
 185  * but still works
 186  */
 187
 188 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 189 {
 190         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 191         uint32_t mec;
 192         uint32_t pipe;
 193
 194         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 195         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 196
 197         lock_srbm(kgd, mec, pipe, 0, 0);
 198
 199         WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
 200                 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 201                 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 202
 203         unlock_srbm(kgd);
 204
 205         return 0;
 206 }
 207
 208 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
 209                                 unsigned int engine_id,
 210                                 unsigned int queue_id)
 211 {
 212         uint32_t sdma_engine_reg_base[2] = {
 213                 SOC15_REG_OFFSET(SDMA0, 0,
 214                                  mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
 215                 /* On gfx10, mmSDMA1_xxx registers are defined NOT based
 216                  * on SDMA1 base address (dw 0x1860) but based on SDMA0
 217                  * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL
 218                  * instead of mmSDMA1_RLC0_RB_CNTL for the base address calc
 219                  * below
 220                  */
 221                 SOC15_REG_OFFSET(SDMA1, 0,
 222                                  mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
 223         };
 224
 225         uint32_t retval = sdma_engine_reg_base[engine_id]
 226                 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
 227
 228         pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
 229                         queue_id, retval);
 230
 231         return retval;
 232 }
 233
 234 #if 0
 235 static uint32_t get_watch_base_addr(struct amdgpu_device *adev)
 236 {
 237         uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
 238                         mmTCP_WATCH0_ADDR_H;
 239
 240         pr_debug("kfd: reg watch base address: 0x%x\n", retval);
 241
 242         return retval;
 243 }
 244 #endif
 245
 246 static inline struct v10_compute_mqd *get_mqd(void *mqd)
 247 {
 248         return (struct v10_compute_mqd *)mqd;
 249 }
 250
 251 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
 252 {
 253         return (struct v10_sdma_mqd *)mqd;
 254 }
 255
 256 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 257                         uint32_t queue_id, uint32_t __user *wptr,
 258                         uint32_t wptr_shift, uint32_t wptr_mask,
 259                         struct mm_struct *mm)
 260 {
 261         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 262         struct v10_compute_mqd *m;
 263         uint32_t *mqd_hqd;
 264         uint32_t reg, hqd_base, data;
 265
 266         m = get_mqd(mqd);
 267
 268         pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
 269         acquire_queue(kgd, pipe_id, queue_id);
 270
 271         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
 272         mqd_hqd = &m->cp_mqd_base_addr_lo;
 273         hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
 274
 275         for (reg = hqd_base;
 276              reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
 277                 WREG32(reg, mqd_hqd[reg - hqd_base]);
 278
 279
 280         /* Activate doorbell logic before triggering WPTR poll. */
 281         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 282                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 283         WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
 284
 285         if (wptr) {
 286                 /* Don't read wptr with get_user because the user
 287                  * context may not be accessible (if this function
 288                  * runs in a work queue). Instead trigger a one-shot
 289                  * polling read from memory in the CP. This assumes
 290                  * that wptr is GPU-accessible in the queue's VMID via
 291                  * ATC or SVM. WPTR==RPTR before starting the poll so
 292                  * the CP starts fetching new commands from the right
 293                  * place.
 294                  *
 295                  * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
 296                  * tricky. Assume that the queue didn't overflow. The
 297                  * number of valid bits in the 32-bit RPTR depends on
 298                  * the queue size. The remaining bits are taken from
 299                  * the saved 64-bit WPTR. If the WPTR wrapped, add the
 300                  * queue size.
 301                  */
 302                 uint32_t queue_size =
 303                         2 << REG_GET_FIELD(m->cp_hqd_pq_control,
 304                                            CP_HQD_PQ_CONTROL, QUEUE_SIZE);
 305                 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
 306
 307                 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
 308                         guessed_wptr += queue_size;
 309                 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
 310                 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
 311
 312                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
 313                        lower_32_bits(guessed_wptr));
 314                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
 315                        upper_32_bits(guessed_wptr));
 316                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
 317                        lower_32_bits((uint64_t)wptr));
 318                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
 319                        upper_32_bits((uint64_t)wptr));
 320                 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
 321                          (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 322                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
 323                        (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 324         }
 325
 326         /* Start the EOP fetcher */
 327         WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
 328                REG_SET_FIELD(m->cp_hqd_eop_rptr,
 329                              CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
 330
 331         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 332         WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
 333
 334         release_queue(kgd);
 335
 336         return 0;
 337 }
 338
 339 static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
 340                             uint32_t pipe_id, uint32_t queue_id,
 341                             uint32_t doorbell_off)
 342 {
 343         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 344         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 345         struct v10_compute_mqd *m;
 346         uint32_t mec, pipe;
 347         int r;
 348
 349         m = get_mqd(mqd);
 350
 351         acquire_queue(kgd, pipe_id, queue_id);
 352
 353         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 354         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 355
 356         pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 357                  mec, pipe, queue_id);
 358
 359         spin_lock(&adev->gfx.kiq.ring_lock);
 360         r = amdgpu_ring_alloc(kiq_ring, 7);
 361         if (r) {
 362                 pr_err("Failed to alloc KIQ (%d).\n", r);
 363                 goto out_unlock;
 364         }
 365
 366         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 367         amdgpu_ring_write(kiq_ring,
 368                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 369                           PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
 370                           PACKET3_MAP_QUEUES_QUEUE(queue_id) |
 371                           PACKET3_MAP_QUEUES_PIPE(pipe) |
 372                           PACKET3_MAP_QUEUES_ME((mec - 1)) |
 373                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 374                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 375                           PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
 376                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 377         amdgpu_ring_write(kiq_ring,
 378                           PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
 379         amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
 380         amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
 381         amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
 382         amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
 383         amdgpu_ring_commit(kiq_ring);
 384
 385 out_unlock:
 386         spin_unlock(&adev->gfx.kiq.ring_lock);
 387         release_queue(kgd);
 388
 389         return r;
 390 }
 391
 392 static int kgd_hqd_dump(struct kgd_dev *kgd,
 393                         uint32_t pipe_id, uint32_t queue_id,
 394                         uint32_t (**dump)[2], uint32_t *n_regs)
 395 {
 396         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 397         uint32_t i = 0, reg;
 398 #define HQD_N_REGS 56
 399 #define DUMP_REG(addr) do {                             \
 400                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 401                         break;                          \
 402                 (*dump)[i][0] = (addr) << 2;            \
 403                 (*dump)[i++][1] = RREG32(addr);         \
 404         } while (0)
 405
 406         *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
 407         if (*dump == NULL)
 408                 return -ENOMEM;
 409
 410         acquire_queue(kgd, pipe_id, queue_id);
 411
 412         for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
 413              reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
 414                 DUMP_REG(reg);
 415
 416         release_queue(kgd);
 417
 418         WARN_ON_ONCE(i != HQD_N_REGS);
 419         *n_regs = i;
 420
 421         return 0;
 422 }
 423
 424 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 425                              uint32_t __user *wptr, struct mm_struct *mm)
 426 {
 427         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 428         struct v10_sdma_mqd *m;
 429         uint32_t sdma_rlc_reg_offset;
 430         unsigned long end_jiffies;
 431         uint32_t data;
 432         uint64_t data64;
 433         uint64_t __user *wptr64 = (uint64_t __user *)wptr;
 434
 435         m = get_sdma_mqd(mqd);
 436         sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
 437                                             m->sdma_queue_id);
 438
 439         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
 440                 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 441
 442         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 443         while (true) {
 444                 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
 445                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 446                         break;
 447                 if (time_after(jiffies, end_jiffies)) {
 448                         pr_err("SDMA RLC not idle in %s\n", __func__);
 449                         return -ETIME;
 450                 }
 451                 usleep_range(500, 1000);
 452         }
 453
 454         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
 455                m->sdmax_rlcx_doorbell_offset);
 456
 457         data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
 458                              ENABLE, 1);
 459         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
 460         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
 461                                 m->sdmax_rlcx_rb_rptr);
 462         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
 463                                 m->sdmax_rlcx_rb_rptr_hi);
 464
 465         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
 466         if (read_user_wptr(mm, wptr64, data64)) {
 467                 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
 468                        lower_32_bits(data64));
 469                 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
 470                        upper_32_bits(data64));
 471         } else {
 472                 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
 473                        m->sdmax_rlcx_rb_rptr);
 474                 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
 475                        m->sdmax_rlcx_rb_rptr_hi);
 476         }
 477         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
 478
 479         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
 480         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
 481                         m->sdmax_rlcx_rb_base_hi);
 482         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 483                         m->sdmax_rlcx_rb_rptr_addr_lo);
 484         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 485                         m->sdmax_rlcx_rb_rptr_addr_hi);
 486
 487         data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
 488                              RB_ENABLE, 1);
 489         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
 490
 491         return 0;
 492 }
 493
 494 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 495                              uint32_t engine_id, uint32_t queue_id,
 496                              uint32_t (**dump)[2], uint32_t *n_regs)
 497 {
 498         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 499         uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
 500                         engine_id, queue_id);
 501         uint32_t i = 0, reg;
 502 #undef HQD_N_REGS
 503 #define HQD_N_REGS (19+6+7+10)
 504
 505         *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
 506         if (*dump == NULL)
 507                 return -ENOMEM;
 508
 509         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 510                 DUMP_REG(sdma_rlc_reg_offset + reg);
 511         for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
 512                 DUMP_REG(sdma_rlc_reg_offset + reg);
 513         for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
 514              reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
 515                 DUMP_REG(sdma_rlc_reg_offset + reg);
 516         for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
 517              reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
 518                 DUMP_REG(sdma_rlc_reg_offset + reg);
 519
 520         WARN_ON_ONCE(i != HQD_N_REGS);
 521         *n_regs = i;
 522
 523         return 0;
 524 }
 525
 526 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 527                                 uint32_t pipe_id, uint32_t queue_id)
 528 {
 529         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 530         uint32_t act;
 531         bool retval = false;
 532         uint32_t low, high;
 533
 534         acquire_queue(kgd, pipe_id, queue_id);
 535         act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
 536         if (act) {
 537                 low = lower_32_bits(queue_address >> 8);
 538                 high = upper_32_bits(queue_address >> 8);
 539
 540                 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
 541                    high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
 542                         retval = true;
 543         }
 544         release_queue(kgd);
 545         return retval;
 546 }
 547
 548 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 549 {
 550         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 551         struct v10_sdma_mqd *m;
 552         uint32_t sdma_rlc_reg_offset;
 553         uint32_t sdma_rlc_rb_cntl;
 554
 555         m = get_sdma_mqd(mqd);
 556         sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
 557                                             m->sdma_queue_id);
 558
 559         sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 560
 561         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 562                 return true;
 563
 564         return false;
 565 }
 566
 567 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 568                                 enum kfd_preempt_type reset_type,
 569                                 unsigned int utimeout, uint32_t pipe_id,
 570                                 uint32_t queue_id)
 571 {
 572         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 573         enum hqd_dequeue_request_type type;
 574         unsigned long end_jiffies;
 575         uint32_t temp;
 576         struct v10_compute_mqd *m = get_mqd(mqd);
 577
 578 #if 0
 579         unsigned long flags;
 580         int retry;
 581 #endif
 582
 583         acquire_queue(kgd, pipe_id, queue_id);
 584
 585         if (m->cp_hqd_vmid == 0)
 586                 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
 587
 588         switch (reset_type) {
 589         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 590                 type = DRAIN_PIPE;
 591                 break;
 592         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 593                 type = RESET_WAVES;
 594                 break;
 595         default:
 596                 type = DRAIN_PIPE;
 597                 break;
 598         }
 599
 600 #if 0 /* Is this still needed? */
 601         /* Workaround: If IQ timer is active and the wait time is close to or
 602          * equal to 0, dequeueing is not safe. Wait until either the wait time
 603          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 604          * cleared before continuing. Also, ensure wait times are set to at
 605          * least 0x3.
 606          */
 607         local_irq_save(flags);
 608         preempt_disable();
 609         retry = 5000; /* wait for 500 usecs at maximum */
 610         while (true) {
 611                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 612                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 613                         pr_debug("HW is processing IQ\n");
 614                         goto loop;
 615                 }
 616                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 617                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 618                                         == 3) /* SEM-rearm is safe */
 619                                 break;
 620                         /* Wait time 3 is safe for CP, but our MMIO read/write
 621                          * time is close to 1 microsecond, so check for 10 to
 622                          * leave more buffer room
 623                          */
 624                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 625                                         >= 10)
 626                                 break;
 627                         pr_debug("IQ timer is active\n");
 628                 } else
 629                         break;
 630 loop:
 631                 if (!retry) {
 632                         pr_err("CP HQD IQ timer status time out\n");
 633                         break;
 634                 }
 635                 ndelay(100);
 636                 --retry;
 637         }
 638         retry = 1000;
 639         while (true) {
 640                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 641                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 642                         break;
 643                 pr_debug("Dequeue request is pending\n");
 644
 645                 if (!retry) {
 646                         pr_err("CP HQD dequeue request time out\n");
 647                         break;
 648                 }
 649                 ndelay(100);
 650                 --retry;
 651         }
 652         local_irq_restore(flags);
 653         preempt_enable();
 654 #endif
 655
 656         WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
 657
 658         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 659         while (true) {
 660                 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
 661                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 662                         break;
 663                 if (time_after(jiffies, end_jiffies)) {
 664                         pr_err("cp queue preemption time out.\n");
 665                         release_queue(kgd);
 666                         return -ETIME;
 667                 }
 668                 usleep_range(500, 1000);
 669         }
 670
 671         release_queue(kgd);
 672         return 0;
 673 }
 674
 675 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 676                                 unsigned int utimeout)
 677 {
 678         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 679         struct v10_sdma_mqd *m;
 680         uint32_t sdma_rlc_reg_offset;
 681         uint32_t temp;
 682         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 683
 684         m = get_sdma_mqd(mqd);
 685         sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
 686                                             m->sdma_queue_id);
 687
 688         temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 689         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 690         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
 691
 692         while (true) {
 693                 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
 694                 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 695                         break;
 696                 if (time_after(jiffies, end_jiffies)) {
 697                         pr_err("SDMA RLC not idle in %s\n", __func__);
 698                         return -ETIME;
 699                 }
 700                 usleep_range(500, 1000);
 701         }
 702
 703         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
 704         WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
 705                 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
 706                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 707
 708         m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
 709         m->sdmax_rlcx_rb_rptr_hi =
 710                 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
 711
 712         return 0;
 713 }
 714
 715 static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
 716                                         uint8_t vmid, uint16_t *p_pasid)
 717 {
 718         uint32_t value;
 719         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 720
 721         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 722                      + vmid);
 723         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 724
 725         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 726 }
 727
 728 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 729 {
 730         return 0;
 731 }
 732
 733 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 734                                         unsigned int watch_point_id,
 735                                         uint32_t cntl_val,
 736                                         uint32_t addr_hi,
 737                                         uint32_t addr_lo)
 738 {
 739         return 0;
 740 }
 741
 742 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 743                                         uint32_t gfx_index_val,
 744                                         uint32_t sq_cmd)
 745 {
 746         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 747         uint32_t data = 0;
 748
 749         mutex_lock(&adev->grbm_idx_mutex);
 750
 751         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
 752         WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
 753
 754         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 755                 INSTANCE_BROADCAST_WRITES, 1);
 756         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 757                 SA_BROADCAST_WRITES, 1);
 758         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 759                 SE_BROADCAST_WRITES, 1);
 760
 761         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
 762         mutex_unlock(&adev->grbm_idx_mutex);
 763
 764         return 0;
 765 }
 766
 767 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 768                                         unsigned int watch_point_id,
 769                                         unsigned int reg_offset)
 770 {
 771         return 0;
 772 }
 773
 774 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 775                 uint64_t page_table_base)
 776 {
 777         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 778
 779         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 780                 pr_err("trying to set page table base for wrong VMID %u\n",
 781                        vmid);
 782                 return;
 783         }
 784
 785         /* SDMA is on gfxhub as well for Navi1* series */
 786         gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
 787 }
 788
 789 const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
 790         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 791         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 792         .init_interrupts = kgd_init_interrupts,
 793         .hqd_load = kgd_hqd_load,
 794         .hiq_mqd_load = kgd_hiq_mqd_load,
 795         .hqd_sdma_load = kgd_hqd_sdma_load,
 796         .hqd_dump = kgd_hqd_dump,
 797         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 798         .hqd_is_occupied = kgd_hqd_is_occupied,
 799         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 800         .hqd_destroy = kgd_hqd_destroy,
 801         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 802         .address_watch_disable = kgd_address_watch_disable,
 803         .address_watch_execute = kgd_address_watch_execute,
 804         .wave_control_execute = kgd_wave_control_execute,
 805         .address_watch_get_offset = kgd_address_watch_get_offset,
 806         .get_atc_vmid_pasid_mapping_info =
 807                         get_atc_vmid_pasid_mapping_info,
 808         .get_tile_config = amdgpu_amdkfd_get_tile_config,
 809         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 810         .get_hive_id = amdgpu_amdkfd_get_hive_id,
 811 };