drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 8, .max = 18 },
 158         .m2 = { .min = 3, .max = 7 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 8, .max = 18 },
 172         .m2 = { .min = 3, .max = 7 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 420
 421         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 422                 DRM_ERROR("DPIO idle wait timed out\n");
 423                 return 0;
 424         }
 425
 426         I915_WRITE(DPIO_REG, reg);
 427         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 428                    DPIO_BYTE);
 429         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 430                 DRM_ERROR("DPIO read wait timed out\n");
 431                 return 0;
 432         }
 433
 434         return I915_READ(DPIO_DATA);
 435 }
 436
 437 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 438                              u32 val)
 439 {
 440         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 441
 442         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 443                 DRM_ERROR("DPIO idle wait timed out\n");
 444                 return;
 445         }
 446
 447         I915_WRITE(DPIO_DATA, val);
 448         I915_WRITE(DPIO_REG, reg);
 449         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 450                    DPIO_BYTE);
 451         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 452                 DRM_ERROR("DPIO write wait timed out\n");
 453 }
 454
 455 static void vlv_init_dpio(struct drm_device *dev)
 456 {
 457         struct drm_i915_private *dev_priv = dev->dev_private;
 458
 459         /* Reset the DPIO config */
 460         I915_WRITE(DPIO_CTL, 0);
 461         POSTING_READ(DPIO_CTL);
 462         I915_WRITE(DPIO_CTL, 1);
 463         POSTING_READ(DPIO_CTL);
 464 }
 465
 466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 467                                                 int refclk)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         const intel_limit_t *limit;
 471
 472         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 473                 if (intel_is_dual_link_lvds(dev)) {
 474                         /* LVDS dual channel */
 475                         if (refclk == 100000)
 476                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 477                         else
 478                                 limit = &intel_limits_ironlake_dual_lvds;
 479                 } else {
 480                         if (refclk == 100000)
 481                                 limit = &intel_limits_ironlake_single_lvds_100m;
 482                         else
 483                                 limit = &intel_limits_ironlake_single_lvds;
 484                 }
 485         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 486                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 487                 limit = &intel_limits_ironlake_display_port;
 488         else
 489                 limit = &intel_limits_ironlake_dac;
 490
 491         return limit;
 492 }
 493
 494 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         const intel_limit_t *limit;
 498
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 500                 if (intel_is_dual_link_lvds(dev))
 501                         /* LVDS with dual channel */
 502                         limit = &intel_limits_g4x_dual_channel_lvds;
 503                 else
 504                         /* LVDS with dual channel */
 505                         limit = &intel_limits_g4x_single_channel_lvds;
 506         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 507                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 508                 limit = &intel_limits_g4x_hdmi;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 510                 limit = &intel_limits_g4x_sdvo;
 511         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 512                 limit = &intel_limits_g4x_display_port;
 513         } else /* The option is for other outputs */
 514                 limit = &intel_limits_i9xx_sdvo;
 515
 516         return limit;
 517 }
 518
 519 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         const intel_limit_t *limit;
 523
 524         if (HAS_PCH_SPLIT(dev))
 525                 limit = intel_ironlake_limit(crtc, refclk);
 526         else if (IS_G4X(dev)) {
 527                 limit = intel_g4x_limit(crtc);
 528         } else if (IS_PINEVIEW(dev)) {
 529                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 530                         limit = &intel_limits_pineview_lvds;
 531                 else
 532                         limit = &intel_limits_pineview_sdvo;
 533         } else if (IS_VALLEYVIEW(dev)) {
 534                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 535                         limit = &intel_limits_vlv_dac;
 536                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 537                         limit = &intel_limits_vlv_hdmi;
 538                 else
 539                         limit = &intel_limits_vlv_dp;
 540         } else if (!IS_GEN2(dev)) {
 541                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i9xx_lvds;
 543                 else
 544                         limit = &intel_limits_i9xx_sdvo;
 545         } else {
 546                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits_i8xx_lvds;
 548                 else
 549                         limit = &intel_limits_i8xx_dvo;
 550         }
 551         return limit;
 552 }
 553
 554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 555 static void pineview_clock(int refclk, intel_clock_t *clock)
 556 {
 557         clock->m = clock->m2 + 2;
 558         clock->p = clock->p1 * clock->p2;
 559         clock->vco = refclk * clock->m / clock->n;
 560         clock->dot = clock->vco / clock->p;
 561 }
 562
 563 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 564 {
 565         if (IS_PINEVIEW(dev)) {
 566                 pineview_clock(refclk, clock);
 567                 return;
 568         }
 569         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 570         clock->p = clock->p1 * clock->p2;
 571         clock->vco = refclk * clock->m / (clock->n + 2);
 572         clock->dot = clock->vco / clock->p;
 573 }
 574
 575 /**
 576  * Returns whether any output on the specified pipe is of the specified type
 577  */
 578 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         struct intel_encoder *encoder;
 582
 583         for_each_encoder_on_crtc(dev, crtc, encoder)
 584                 if (encoder->type == type)
 585                         return true;
 586
 587         return false;
 588 }
 589
 590 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 591 /**
 592  * Returns whether the given set of divisors are valid for a given refclk with
 593  * the given connectors.
 594  */
 595
 596 static bool intel_PLL_is_valid(struct drm_device *dev,
 597                                const intel_limit_t *limit,
 598                                const intel_clock_t *clock)
 599 {
 600         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 601                 INTELPllInvalid("p1 out of range\n");
 602         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 603                 INTELPllInvalid("p out of range\n");
 604         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 605                 INTELPllInvalid("m2 out of range\n");
 606         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 607                 INTELPllInvalid("m1 out of range\n");
 608         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 609                 INTELPllInvalid("m1 <= m2\n");
 610         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 611                 INTELPllInvalid("m out of range\n");
 612         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 613                 INTELPllInvalid("n out of range\n");
 614         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 615                 INTELPllInvalid("vco out of range\n");
 616         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 617          * connector, etc., rather than just a single range.
 618          */
 619         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 620                 INTELPllInvalid("dot out of range\n");
 621
 622         return true;
 623 }
 624
 625 static bool
 626 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                     int target, int refclk, intel_clock_t *match_clock,
 628                     intel_clock_t *best_clock)
 629
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int err = target;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 /*
 637                  * For LVDS just rely on its current settings for dual-channel.
 638                  * We haven't figured out how to reliably set up different
 639                  * single/dual channel state, if we even can.
 640                  */
 641                 if (intel_is_dual_link_lvds(dev))
 642                         clock.p2 = limit->p2.p2_fast;
 643                 else
 644                         clock.p2 = limit->p2.p2_slow;
 645         } else {
 646                 if (target < limit->p2.dot_limit)
 647                         clock.p2 = limit->p2.p2_slow;
 648                 else
 649                         clock.p2 = limit->p2.p2_fast;
 650         }
 651
 652         memset(best_clock, 0, sizeof(*best_clock));
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         /* m1 is always 0 in Pineview */
 659                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 660                                 break;
 661                         for (clock.n = limit->n.min;
 662                              clock.n <= limit->n.max; clock.n++) {
 663                                 for (clock.p1 = limit->p1.min;
 664                                         clock.p1 <= limit->p1.max; clock.p1++) {
 665                                         int this_err;
 666
 667                                         intel_clock(dev, refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 static bool
 689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 690                         int target, int refclk, intel_clock_t *match_clock,
 691                         intel_clock_t *best_clock)
 692 {
 693         struct drm_device *dev = crtc->dev;
 694         intel_clock_t clock;
 695         int max_n;
 696         bool found;
 697         /* approximately equals target * 0.00585 */
 698         int err_most = (target >> 8) + (target >> 9);
 699         found = false;
 700
 701         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 702                 int lvds_reg;
 703
 704                 if (HAS_PCH_SPLIT(dev))
 705                         lvds_reg = PCH_LVDS;
 706                 else
 707                         lvds_reg = LVDS;
 708                 if (intel_is_dual_link_lvds(dev))
 709                         clock.p2 = limit->p2.p2_fast;
 710                 else
 711                         clock.p2 = limit->p2.p2_slow;
 712         } else {
 713                 if (target < limit->p2.dot_limit)
 714                         clock.p2 = limit->p2.p2_slow;
 715                 else
 716                         clock.p2 = limit->p2.p2_fast;
 717         }
 718
 719         memset(best_clock, 0, sizeof(*best_clock));
 720         max_n = limit->n.max;
 721         /* based on hardware requirement, prefer smaller n to precision */
 722         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 723                 /* based on hardware requirement, prefere larger m1,m2 */
 724                 for (clock.m1 = limit->m1.max;
 725                      clock.m1 >= limit->m1.min; clock.m1--) {
 726                         for (clock.m2 = limit->m2.max;
 727                              clock.m2 >= limit->m2.min; clock.m2--) {
 728                                 for (clock.p1 = limit->p1.max;
 729                                      clock.p1 >= limit->p1.min; clock.p1--) {
 730                                         int this_err;
 731
 732                                         intel_clock(dev, refclk, &clock);
 733                                         if (!intel_PLL_is_valid(dev, limit,
 734                                                                 &clock))
 735                                                 continue;
 736                                         if (match_clock &&
 737                                             clock.p != match_clock->p)
 738                                                 continue;
 739
 740                                         this_err = abs(clock.dot - target);
 741                                         if (this_err < err_most) {
 742                                                 *best_clock = clock;
 743                                                 err_most = this_err;
 744                                                 max_n = clock.n;
 745                                                 found = true;
 746                                         }
 747                                 }
 748                         }
 749                 }
 750         }
 751         return found;
 752 }
 753
 754 static bool
 755 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 756                            int target, int refclk, intel_clock_t *match_clock,
 757                            intel_clock_t *best_clock)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         intel_clock_t clock;
 761
 762         if (target < 200000) {
 763                 clock.n = 1;
 764                 clock.p1 = 2;
 765                 clock.p2 = 10;
 766                 clock.m1 = 12;
 767                 clock.m2 = 9;
 768         } else {
 769                 clock.n = 2;
 770                 clock.p1 = 1;
 771                 clock.p2 = 10;
 772                 clock.m1 = 14;
 773                 clock.m2 = 8;
 774         }
 775         intel_clock(dev, refclk, &clock);
 776         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 777         return true;
 778 }
 779
 780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 781 static bool
 782 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 783                       int target, int refclk, intel_clock_t *match_clock,
 784                       intel_clock_t *best_clock)
 785 {
 786         intel_clock_t clock;
 787         if (target < 200000) {
 788                 clock.p1 = 2;
 789                 clock.p2 = 10;
 790                 clock.n = 2;
 791                 clock.m1 = 23;
 792                 clock.m2 = 8;
 793         } else {
 794                 clock.p1 = 1;
 795                 clock.p2 = 10;
 796                 clock.n = 1;
 797                 clock.m1 = 14;
 798                 clock.m2 = 2;
 799         }
 800         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 801         clock.p = (clock.p1 * clock.p2);
 802         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 803         clock.vco = 0;
 804         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 805         return true;
 806 }
 807 static bool
 808 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 809                         int target, int refclk, intel_clock_t *match_clock,
 810                         intel_clock_t *best_clock)
 811 {
 812         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 813         u32 m, n, fastclk;
 814         u32 updrate, minupdate, fracbits, p;
 815         unsigned long bestppm, ppm, absppm;
 816         int dotclk, flag;
 817
 818         flag = 0;
 819         dotclk = target * 1000;
 820         bestppm = 1000000;
 821         ppm = absppm = 0;
 822         fastclk = dotclk / (2*100);
 823         updrate = 0;
 824         minupdate = 19200;
 825         fracbits = 1;
 826         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 827         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 828
 829         /* based on hardware requirement, prefer smaller n to precision */
 830         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 831                 updrate = refclk / n;
 832                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 833                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 834                                 if (p2 > 10)
 835                                         p2 = p2 - 1;
 836                                 p = p1 * p2;
 837                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 838                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 839                                         m2 = (((2*(fastclk * p * n / m1 )) +
 840                                                refclk) / (2*refclk));
 841                                         m = m1 * m2;
 842                                         vco = updrate * m;
 843                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 844                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 845                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 846                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 847                                                         bestppm = 0;
 848                                                         flag = 1;
 849                                                 }
 850                                                 if (absppm < bestppm - 10) {
 851                                                         bestppm = absppm;
 852                                                         flag = 1;
 853                                                 }
 854                                                 if (flag) {
 855                                                         bestn = n;
 856                                                         bestm1 = m1;
 857                                                         bestm2 = m2;
 858                                                         bestp1 = p1;
 859                                                         bestp2 = p2;
 860                                                         flag = 0;
 861                                                 }
 862                                         }
 863                                 }
 864                         }
 865                 }
 866         }
 867         best_clock->n = bestn;
 868         best_clock->m1 = bestm1;
 869         best_clock->m2 = bestm2;
 870         best_clock->p1 = bestp1;
 871         best_clock->p2 = bestp2;
 872
 873         return true;
 874 }
 875
 876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 877                                              enum pipe pipe)
 878 {
 879         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 881
 882         return intel_crtc->cpu_transcoder;
 883 }
 884
 885 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 886 {
 887         struct drm_i915_private *dev_priv = dev->dev_private;
 888         u32 frame, frame_reg = PIPEFRAME(pipe);
 889
 890         frame = I915_READ(frame_reg);
 891
 892         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 /**
 897  * intel_wait_for_vblank - wait for vblank on a given pipe
 898  * @dev: drm device
 899  * @pipe: pipe to wait for
 900  *
 901  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 902  * mode setting code.
 903  */
 904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 905 {
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         int pipestat_reg = PIPESTAT(pipe);
 908
 909         if (INTEL_INFO(dev)->gen >= 5) {
 910                 ironlake_wait_for_vblank(dev, pipe);
 911                 return;
 912         }
 913
 914         /* Clear existing vblank status. Note this will clear any other
 915          * sticky status fields as well.
 916          *
 917          * This races with i915_driver_irq_handler() with the result
 918          * that either function could miss a vblank event.  Here it is not
 919          * fatal, as we will either wait upon the next vblank interrupt or
 920          * timeout.  Generally speaking intel_wait_for_vblank() is only
 921          * called during modeset at which time the GPU should be idle and
 922          * should *not* be performing page flips and thus not waiting on
 923          * vblanks...
 924          * Currently, the result of us stealing a vblank from the irq
 925          * handler is that a single frame will be skipped during swapbuffers.
 926          */
 927         I915_WRITE(pipestat_reg,
 928                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 929
 930         /* Wait for vblank interrupt bit to set */
 931         if (wait_for(I915_READ(pipestat_reg) &
 932                      PIPE_VBLANK_INTERRUPT_STATUS,
 933                      50))
 934                 DRM_DEBUG_KMS("vblank wait timed out\n");
 935 }
 936
 937 /*
 938  * intel_wait_for_pipe_off - wait for pipe to turn off
 939  * @dev: drm device
 940  * @pipe: pipe to wait for
 941  *
 942  * After disabling a pipe, we can't wait for vblank in the usual way,
 943  * spinning on the vblank interrupt status bit, since we won't actually
 944  * see an interrupt when the pipe is disabled.
 945  *
 946  * On Gen4 and above:
 947  *   wait for the pipe register state bit to turn off
 948  *
 949  * Otherwise:
 950  *   wait for the display line value to settle (it usually
 951  *   ends up stopping at the start of the next frame).
 952  *
 953  */
 954 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 955 {
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 958                                                                       pipe);
 959
 960         if (INTEL_INFO(dev)->gen >= 4) {
 961                 int reg = PIPECONF(cpu_transcoder);
 962
 963                 /* Wait for the Pipe State to go off */
 964                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 965                              100))
 966                         WARN(1, "pipe_off wait timed out\n");
 967         } else {
 968                 u32 last_line, line_mask;
 969                 int reg = PIPEDSL(pipe);
 970                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 971
 972                 if (IS_GEN2(dev))
 973                         line_mask = DSL_LINEMASK_GEN2;
 974                 else
 975                         line_mask = DSL_LINEMASK_GEN3;
 976
 977                 /* Wait for the display line to settle */
 978                 do {
 979                         last_line = I915_READ(reg) & line_mask;
 980                         mdelay(5);
 981                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 982                          time_after(timeout, jiffies));
 983                 if (time_after(jiffies, timeout))
 984                         WARN(1, "pipe_off wait timed out\n");
 985         }
 986 }
 987
 988 /*
 989  * ibx_digital_port_connected - is the specified port connected?
 990  * @dev_priv: i915 private structure
 991  * @port: the port to test
 992  *
 993  * Returns true if @port is connected, false otherwise.
 994  */
 995 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 996                                 struct intel_digital_port *port)
 997 {
 998         u32 bit;
 999
1000         if (HAS_PCH_IBX(dev_priv->dev)) {
1001                 switch(port->port) {
1002                 case PORT_B:
1003                         bit = SDE_PORTB_HOTPLUG;
1004                         break;
1005                 case PORT_C:
1006                         bit = SDE_PORTC_HOTPLUG;
1007                         break;
1008                 case PORT_D:
1009                         bit = SDE_PORTD_HOTPLUG;
1010                         break;
1011                 default:
1012                         return true;
1013                 }
1014         } else {
1015                 switch(port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG_CPT;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG_CPT;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG_CPT;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         }
1029
1030         return I915_READ(SDEISR) & bit;
1031 }
1032
1033 static const char *state_string(bool enabled)
1034 {
1035         return enabled ? "on" : "off";
1036 }
1037
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = DPLL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & DPLL_VCO_ENABLE);
1049         WARN(cur_state != state,
1050              "PLL state assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
1056 /* For ILK+ */
1057 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058                            struct intel_pch_pll *pll,
1059                            struct intel_crtc *crtc,
1060                            bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         if (HAS_PCH_LPT(dev_priv->dev)) {
1066                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067                 return;
1068         }
1069
1070         if (WARN (!pll,
1071                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072                 return;
1073
1074         val = I915_READ(pll->pll_reg);
1075         cur_state = !!(val & DPLL_VCO_ENABLE);
1076         WARN(cur_state != state,
1077              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078              pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080         /* Make sure the selected PLL is correctly attached to the transcoder */
1081         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082                 u32 pch_dpll;
1083
1084                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1088                           cur_state, crtc->pipe, pch_dpll)) {
1089                         cur_state = !!(val >> (4*crtc->pipe + 3));
1090                         WARN(cur_state != state,
1091                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1092                              pll->pll_reg == _PCH_DPLL_B,
1093                              state_string(state),
1094                              crtc->pipe,
1095                              val);
1096                 }
1097         }
1098 }
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109                                                                       pipe);
1110
1111         if (HAS_DDI(dev_priv->dev)) {
1112                 /* DDI does not have a specific FDI_TX register */
1113                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1116         } else {
1117                 reg = FDI_TX_CTL(pipe);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & FDI_TX_ENABLE);
1120         }
1121         WARN(cur_state != state,
1122              "FDI TX state assertion failure (expected %s, current %s)\n",
1123              state_string(state), state_string(cur_state));
1124 }
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         int reg;
1132         u32 val;
1133         bool cur_state;
1134
1135         reg = FDI_RX_CTL(pipe);
1136         val = I915_READ(reg);
1137         cur_state = !!(val & FDI_RX_ENABLE);
1138         WARN(cur_state != state,
1139              "FDI RX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146                                       enum pipe pipe)
1147 {
1148         int reg;
1149         u32 val;
1150
1151         /* ILK FDI PLL is always enabled */
1152         if (dev_priv->info->gen == 5)
1153                 return;
1154
1155         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156         if (HAS_DDI(dev_priv->dev))
1157                 return;
1158
1159         reg = FDI_TX_CTL(pipe);
1160         val = I915_READ(reg);
1161         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162 }
1163
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165                                       enum pipe pipe)
1166 {
1167         int reg;
1168         u32 val;
1169
1170         reg = FDI_RX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176                                   enum pipe pipe)
1177 {
1178         int pp_reg, lvds_reg;
1179         u32 val;
1180         enum pipe panel_pipe = PIPE_A;
1181         bool locked = true;
1182
1183         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184                 pp_reg = PCH_PP_CONTROL;
1185                 lvds_reg = PCH_LVDS;
1186         } else {
1187                 pp_reg = PP_CONTROL;
1188                 lvds_reg = LVDS;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197                 panel_pipe = PIPE_B;
1198
1199         WARN(panel_pipe == pipe && locked,
1200              "panel assertion failure, pipe %c regs locked\n",
1201              pipe_name(pipe));
1202 }
1203
1204 void assert_pipe(struct drm_i915_private *dev_priv,
1205                  enum pipe pipe, bool state)
1206 {
1207         int reg;
1208         u32 val;
1209         bool cur_state;
1210         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211                                                                       pipe);
1212
1213         /* if we need the pipe A quirk it must be always on */
1214         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215                 state = true;
1216
1217         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219                 cur_state = false;
1220         } else {
1221                 reg = PIPECONF(cpu_transcoder);
1222                 val = I915_READ(reg);
1223                 cur_state = !!(val & PIPECONF_ENABLE);
1224         }
1225
1226         WARN(cur_state != state,
1227              "pipe %c assertion failure (expected %s, current %s)\n",
1228              pipe_name(pipe), state_string(state), state_string(cur_state));
1229 }
1230
1231 static void assert_plane(struct drm_i915_private *dev_priv,
1232                          enum plane plane, bool state)
1233 {
1234         int reg;
1235         u32 val;
1236         bool cur_state;
1237
1238         reg = DSPCNTR(plane);
1239         val = I915_READ(reg);
1240         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241         WARN(cur_state != state,
1242              "plane %c assertion failure (expected %s, current %s)\n",
1243              plane_name(plane), state_string(state), state_string(cur_state));
1244 }
1245
1246 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
1249 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250                                    enum pipe pipe)
1251 {
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Planes are fixed to pipes on ILK+ */
1257         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN((val & DISPLAY_PLANE_ENABLE),
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for (i = 0; i < 2; i++) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279 {
1280         u32 val;
1281         bool enabled;
1282
1283         if (HAS_PCH_LPT(dev_priv->dev)) {
1284                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285                 return;
1286         }
1287
1288         val = I915_READ(PCH_DREF_CONTROL);
1289         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290                             DREF_SUPERSPREAD_SOURCE_MASK));
1291         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292 }
1293
1294 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                        enum pipe pipe)
1296 {
1297         int reg;
1298         u32 val;
1299         bool enabled;
1300
1301         reg = TRANSCONF(pipe);
1302         val = I915_READ(reg);
1303         enabled = !!(val & TRANS_ENABLE);
1304         WARN(enabled,
1305              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310                             enum pipe pipe, u32 port_sel, u32 val)
1311 {
1312         if ((val & DP_PORT_EN) == 0)
1313                 return false;
1314
1315         if (HAS_PCH_CPT(dev_priv->dev)) {
1316                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & PORT_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv->dev)) {
1334                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335                         return false;
1336         } else {
1337                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338                         return false;
1339         }
1340         return true;
1341 }
1342
1343 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344                               enum pipe pipe, u32 val)
1345 {
1346         if ((val & LVDS_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & ADPA_DAC_ENABLE) == 0)
1363                 return false;
1364         if (HAS_PCH_CPT(dev_priv->dev)) {
1365                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366                         return false;
1367         } else {
1368                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369                         return false;
1370         }
1371         return true;
1372 }
1373
1374 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1375                                    enum pipe pipe, int reg, u32 port_sel)
1376 {
1377         u32 val = I915_READ(reg);
1378         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1379              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1380              reg, pipe_name(pipe));
1381
1382         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383              && (val & DP_PIPEB_SELECT),
1384              "IBX PCH dp port still using transcoder B\n");
1385 }
1386
1387 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388                                      enum pipe pipe, int reg)
1389 {
1390         u32 val = I915_READ(reg);
1391         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1392              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1393              reg, pipe_name(pipe));
1394
1395         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396              && (val & SDVO_PIPE_B_SELECT),
1397              "IBX PCH hdmi port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401                                       enum pipe pipe)
1402 {
1403         int reg;
1404         u32 val;
1405
1406         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1409
1410         reg = PCH_ADPA;
1411         val = I915_READ(reg);
1412         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1413              "PCH VGA enabled on transcoder %c, should be disabled\n",
1414              pipe_name(pipe));
1415
1416         reg = PCH_LVDS;
1417         val = I915_READ(reg);
1418         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1420              pipe_name(pipe));
1421
1422         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 }
1426
1427 /**
1428  * intel_enable_pll - enable a PLL
1429  * @dev_priv: i915 private structure
1430  * @pipe: pipe PLL to enable
1431  *
1432  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1433  * make sure the PLL reg is writable first though, since the panel write
1434  * protect mechanism may be enabled.
1435  *
1436  * Note!  This is for pre-ILK only.
1437  *
1438  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1439  */
1440 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441 {
1442         int reg;
1443         u32 val;
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450                 assert_panel_unlocked(dev_priv, pipe);
1451
1452         reg = DPLL(pipe);
1453         val = I915_READ(reg);
1454         val |= DPLL_VCO_ENABLE;
1455
1456         /* We do this three times for luck */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463         I915_WRITE(reg, val);
1464         POSTING_READ(reg);
1465         udelay(150); /* wait for warmup */
1466 }
1467
1468 /**
1469  * intel_disable_pll - disable a PLL
1470  * @dev_priv: i915 private structure
1471  * @pipe: pipe PLL to disable
1472  *
1473  * Disable the PLL for @pipe, making sure the pipe is off first.
1474  *
1475  * Note!  This is for pre-ILK only.
1476  */
1477 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478 {
1479         int reg;
1480         u32 val;
1481
1482         /* Don't disable pipe A or pipe A PLLs if needed */
1483         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484                 return;
1485
1486         /* Make sure the pipe isn't still relying on us */
1487         assert_pipe_disabled(dev_priv, pipe);
1488
1489         reg = DPLL(pipe);
1490         val = I915_READ(reg);
1491         val &= ~DPLL_VCO_ENABLE;
1492         I915_WRITE(reg, val);
1493         POSTING_READ(reg);
1494 }
1495
1496 /* SBI access */
1497 static void
1498 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499                 enum intel_sbi_destination destination)
1500 {
1501         u32 tmp;
1502
1503         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1504
1505         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1506                                 100)) {
1507                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1508                 return;
1509         }
1510
1511         I915_WRITE(SBI_ADDR, (reg << 16));
1512         I915_WRITE(SBI_DATA, value);
1513
1514         if (destination == SBI_ICLK)
1515                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516         else
1517                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1519
1520         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1521                                 100)) {
1522                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1523                 return;
1524         }
1525 }
1526
1527 static u32
1528 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529                enum intel_sbi_destination destination)
1530 {
1531         u32 value = 0;
1532         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1533
1534         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1535                                 100)) {
1536                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537                 return 0;
1538         }
1539
1540         I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542         if (destination == SBI_ICLK)
1543                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544         else
1545                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1547
1548         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1549                                 100)) {
1550                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1551                 return 0;
1552         }
1553
1554         return I915_READ(SBI_DATA);
1555 }
1556
1557 /**
1558  * ironlake_enable_pch_pll - enable PCH PLL
1559  * @dev_priv: i915 private structure
1560  * @pipe: pipe PLL to enable
1561  *
1562  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563  * drives the transcoder clock.
1564  */
1565 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH PLLs only available on ILK, SNB and IVB */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         pll = intel_crtc->pch_pll;
1575         if (pll == NULL)
1576                 return;
1577
1578         if (WARN_ON(pll->refcount == 0))
1579                 return;
1580
1581         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582                       pll->pll_reg, pll->active, pll->on,
1583                       intel_crtc->base.base.id);
1584
1585         /* PCH refclock must be enabled first */
1586         assert_pch_refclk_enabled(dev_priv);
1587
1588         if (pll->active++ && pll->on) {
1589                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590                 return;
1591         }
1592
1593         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595         reg = pll->pll_reg;
1596         val = I915_READ(reg);
1597         val |= DPLL_VCO_ENABLE;
1598         I915_WRITE(reg, val);
1599         POSTING_READ(reg);
1600         udelay(200);
1601
1602         pll->on = true;
1603 }
1604
1605 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 {
1607         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609         int reg;
1610         u32 val;
1611
1612         /* PCH only available on ILK+ */
1613         BUG_ON(dev_priv->info->gen < 5);
1614         if (pll == NULL)
1615                return;
1616
1617         if (WARN_ON(pll->refcount == 0))
1618                 return;
1619
1620         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621                       pll->pll_reg, pll->active, pll->on,
1622                       intel_crtc->base.base.id);
1623
1624         if (WARN_ON(pll->active == 0)) {
1625                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         if (--pll->active) {
1630                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631                 return;
1632         }
1633
1634         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636         /* Make sure transcoder isn't still depending on us */
1637         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1638
1639         reg = pll->pll_reg;
1640         val = I915_READ(reg);
1641         val &= ~DPLL_VCO_ENABLE;
1642         I915_WRITE(reg, val);
1643         POSTING_READ(reg);
1644         udelay(200);
1645
1646         pll->on = false;
1647 }
1648
1649 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650                                            enum pipe pipe)
1651 {
1652         struct drm_device *dev = dev_priv->dev;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654         uint32_t reg, val, pipeconf_val;
1655
1656         /* PCH only available on ILK+ */
1657         BUG_ON(dev_priv->info->gen < 5);
1658
1659         /* Make sure PCH DPLL is enabled */
1660         assert_pch_pll_enabled(dev_priv,
1661                                to_intel_crtc(crtc)->pch_pll,
1662                                to_intel_crtc(crtc));
1663
1664         /* FDI must be feeding us bits for PCH ports */
1665         assert_fdi_tx_enabled(dev_priv, pipe);
1666         assert_fdi_rx_enabled(dev_priv, pipe);
1667
1668         if (HAS_PCH_CPT(dev)) {
1669                 /* Workaround: Set the timing override bit before enabling the
1670                  * pch transcoder. */
1671                 reg = TRANS_CHICKEN2(pipe);
1672                 val = I915_READ(reg);
1673                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674                 I915_WRITE(reg, val);
1675         }
1676
1677         reg = TRANSCONF(pipe);
1678         val = I915_READ(reg);
1679         pipeconf_val = I915_READ(PIPECONF(pipe));
1680
1681         if (HAS_PCH_IBX(dev_priv->dev)) {
1682                 /*
1683                  * make the BPC in transcoder be consistent with
1684                  * that in pipeconf reg.
1685                  */
1686                 val &= ~PIPECONF_BPC_MASK;
1687                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1688         }
1689
1690         val &= ~TRANS_INTERLACE_MASK;
1691         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1692                 if (HAS_PCH_IBX(dev_priv->dev) &&
1693                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694                         val |= TRANS_LEGACY_INTERLACED_ILK;
1695                 else
1696                         val |= TRANS_INTERLACED;
1697         else
1698                 val |= TRANS_PROGRESSIVE;
1699
1700         I915_WRITE(reg, val | TRANS_ENABLE);
1701         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703 }
1704
1705 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706                                       enum transcoder cpu_transcoder)
1707 {
1708         u32 val, pipeconf_val;
1709
1710         /* PCH only available on ILK+ */
1711         BUG_ON(dev_priv->info->gen < 5);
1712
1713         /* FDI must be feeding us bits for PCH ports */
1714         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1716
1717         /* Workaround: set timing override bit. */
1718         val = I915_READ(_TRANSA_CHICKEN2);
1719         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720         I915_WRITE(_TRANSA_CHICKEN2, val);
1721
1722         val = TRANS_ENABLE;
1723         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1724
1725         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726             PIPECONF_INTERLACED_ILK)
1727                 val |= TRANS_INTERLACED;
1728         else
1729                 val |= TRANS_PROGRESSIVE;
1730
1731         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1732         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733                 DRM_ERROR("Failed to enable PCH transcoder\n");
1734 }
1735
1736 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737                                             enum pipe pipe)
1738 {
1739         struct drm_device *dev = dev_priv->dev;
1740         uint32_t reg, val;
1741
1742         /* FDI relies on the transcoder */
1743         assert_fdi_tx_disabled(dev_priv, pipe);
1744         assert_fdi_rx_disabled(dev_priv, pipe);
1745
1746         /* Ports must be off as well */
1747         assert_pch_ports_disabled(dev_priv, pipe);
1748
1749         reg = TRANSCONF(pipe);
1750         val = I915_READ(reg);
1751         val &= ~TRANS_ENABLE;
1752         I915_WRITE(reg, val);
1753         /* wait for PCH transcoder off, transcoder state */
1754         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1755                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1756
1757         if (!HAS_PCH_IBX(dev)) {
1758                 /* Workaround: Clear the timing override chicken bit again. */
1759                 reg = TRANS_CHICKEN2(pipe);
1760                 val = I915_READ(reg);
1761                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762                 I915_WRITE(reg, val);
1763         }
1764 }
1765
1766 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1767 {
1768         u32 val;
1769
1770         val = I915_READ(_TRANSACONF);
1771         val &= ~TRANS_ENABLE;
1772         I915_WRITE(_TRANSACONF, val);
1773         /* wait for PCH transcoder off, transcoder state */
1774         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775                 DRM_ERROR("Failed to disable PCH transcoder\n");
1776
1777         /* Workaround: clear timing override bit. */
1778         val = I915_READ(_TRANSA_CHICKEN2);
1779         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1780         I915_WRITE(_TRANSA_CHICKEN2, val);
1781 }
1782
1783 /**
1784  * intel_enable_pipe - enable a pipe, asserting requirements
1785  * @dev_priv: i915 private structure
1786  * @pipe: pipe to enable
1787  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1788  *
1789  * Enable @pipe, making sure that various hardware specific requirements
1790  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791  *
1792  * @pipe should be %PIPE_A or %PIPE_B.
1793  *
1794  * Will wait until the pipe is actually running (i.e. first vblank) before
1795  * returning.
1796  */
1797 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798                               bool pch_port)
1799 {
1800         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801                                                                       pipe);
1802         enum pipe pch_transcoder;
1803         int reg;
1804         u32 val;
1805
1806         if (HAS_PCH_LPT(dev_priv->dev))
1807                 pch_transcoder = TRANSCODER_A;
1808         else
1809                 pch_transcoder = pipe;
1810
1811         /*
1812          * A pipe without a PLL won't actually be able to drive bits from
1813          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1814          * need the check.
1815          */
1816         if (!HAS_PCH_SPLIT(dev_priv->dev))
1817                 assert_pll_enabled(dev_priv, pipe);
1818         else {
1819                 if (pch_port) {
1820                         /* if driving the PCH, we need FDI enabled */
1821                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1822                         assert_fdi_tx_pll_enabled(dev_priv,
1823                                                   (enum pipe) cpu_transcoder);
1824                 }
1825                 /* FIXME: assert CPU port conditions for SNB+ */
1826         }
1827
1828         reg = PIPECONF(cpu_transcoder);
1829         val = I915_READ(reg);
1830         if (val & PIPECONF_ENABLE)
1831                 return;
1832
1833         I915_WRITE(reg, val | PIPECONF_ENABLE);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_pipe - disable a pipe, asserting requirements
1839  * @dev_priv: i915 private structure
1840  * @pipe: pipe to disable
1841  *
1842  * Disable @pipe, making sure that various hardware specific requirements
1843  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844  *
1845  * @pipe should be %PIPE_A or %PIPE_B.
1846  *
1847  * Will wait until the pipe has shut down before returning.
1848  */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850                                enum pipe pipe)
1851 {
1852         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853                                                                       pipe);
1854         int reg;
1855         u32 val;
1856
1857         /*
1858          * Make sure planes won't keep trying to pump pixels to us,
1859          * or we might hang the display.
1860          */
1861         assert_planes_disabled(dev_priv, pipe);
1862
1863         /* Don't disable pipe A or pipe A PLLs if needed */
1864         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865                 return;
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if ((val & PIPECONF_ENABLE) == 0)
1870                 return;
1871
1872         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877  * Plane regs are double buffered, going from enabled->disabled needs a
1878  * trigger in order to latch.  The display address reg provides this.
1879  */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881                                       enum plane plane)
1882 {
1883         if (dev_priv->info->gen >= 4)
1884                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885         else
1886                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890  * intel_enable_plane - enable a display plane on a given pipe
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to enable
1893  * @pipe: pipe being fed
1894  *
1895  * Enable @plane on @pipe, making sure that @pipe is running first.
1896  */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898                                enum plane plane, enum pipe pipe)
1899 {
1900         int reg;
1901         u32 val;
1902
1903         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904         assert_pipe_enabled(dev_priv, pipe);
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if (val & DISPLAY_PLANE_ENABLE)
1909                 return;
1910
1911         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912         intel_flush_display_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917  * intel_disable_plane - disable a display plane
1918  * @dev_priv: i915 private structure
1919  * @plane: plane to disable
1920  * @pipe: pipe consuming the data
1921  *
1922  * Disable @plane; should be an independent operation.
1923  */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925                                 enum plane plane, enum pipe pipe)
1926 {
1927         int reg;
1928         u32 val;
1929
1930         reg = DSPCNTR(plane);
1931         val = I915_READ(reg);
1932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933                 return;
1934
1935         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936         intel_flush_display_plane(dev_priv, plane);
1937         intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942                            struct drm_i915_gem_object *obj,
1943                            struct intel_ring_buffer *pipelined)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         u32 alignment;
1947         int ret;
1948
1949         switch (obj->tiling_mode) {
1950         case I915_TILING_NONE:
1951                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952                         alignment = 128 * 1024;
1953                 else if (INTEL_INFO(dev)->gen >= 4)
1954                         alignment = 4 * 1024;
1955                 else
1956                         alignment = 64 * 1024;
1957                 break;
1958         case I915_TILING_X:
1959                 /* pin() will align the object as required by fence */
1960                 alignment = 0;
1961                 break;
1962         case I915_TILING_Y:
1963                 /* FIXME: Is this true? */
1964                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965                 return -EINVAL;
1966         default:
1967                 BUG();
1968         }
1969
1970         dev_priv->mm.interruptible = false;
1971         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972         if (ret)
1973                 goto err_interruptible;
1974
1975         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976          * fence, whereas 965+ only requires a fence if using
1977          * framebuffer compression.  For simplicity, we always install
1978          * a fence as the cost is not that onerous.
1979          */
1980         ret = i915_gem_object_get_fence(obj);
1981         if (ret)
1982                 goto err_unpin;
1983
1984         i915_gem_object_pin_fence(obj);
1985
1986         dev_priv->mm.interruptible = true;
1987         return 0;
1988
1989 err_unpin:
1990         i915_gem_object_unpin(obj);
1991 err_interruptible:
1992         dev_priv->mm.interruptible = true;
1993         return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998         i915_gem_object_unpin_fence(obj);
1999         i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003  * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2005                                              unsigned int tiling_mode,
2006                                              unsigned int cpp,
2007                                              unsigned int pitch)
2008 {
2009         if (tiling_mode != I915_TILING_NONE) {
2010                 unsigned int tile_rows, tiles;
2011
2012                 tile_rows = *y / 8;
2013                 *y %= 8;
2014
2015                 tiles = *x / (512/cpp);
2016                 *x %= 512/cpp;
2017
2018                 return tile_rows * pitch * 8 + tiles * 4096;
2019         } else {
2020                 unsigned int offset;
2021
2022                 offset = *y * pitch + *x * cpp;
2023                 *y = 0;
2024                 *x = (offset & 4095) / cpp;
2025                 return offset & -4096;
2026         }
2027 }
2028
2029 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2030                              int x, int y)
2031 {
2032         struct drm_device *dev = crtc->dev;
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2035         struct intel_framebuffer *intel_fb;
2036         struct drm_i915_gem_object *obj;
2037         int plane = intel_crtc->plane;
2038         unsigned long linear_offset;
2039         u32 dspcntr;
2040         u32 reg;
2041
2042         switch (plane) {
2043         case 0:
2044         case 1:
2045                 break;
2046         default:
2047                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2048                 return -EINVAL;
2049         }
2050
2051         intel_fb = to_intel_framebuffer(fb);
2052         obj = intel_fb->obj;
2053
2054         reg = DSPCNTR(plane);
2055         dspcntr = I915_READ(reg);
2056         /* Mask out pixel format bits in case we change it */
2057         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2058         switch (fb->pixel_format) {
2059         case DRM_FORMAT_C8:
2060                 dspcntr |= DISPPLANE_8BPP;
2061                 break;
2062         case DRM_FORMAT_XRGB1555:
2063         case DRM_FORMAT_ARGB1555:
2064                 dspcntr |= DISPPLANE_BGRX555;
2065                 break;
2066         case DRM_FORMAT_RGB565:
2067                 dspcntr |= DISPPLANE_BGRX565;
2068                 break;
2069         case DRM_FORMAT_XRGB8888:
2070         case DRM_FORMAT_ARGB8888:
2071                 dspcntr |= DISPPLANE_BGRX888;
2072                 break;
2073         case DRM_FORMAT_XBGR8888:
2074         case DRM_FORMAT_ABGR8888:
2075                 dspcntr |= DISPPLANE_RGBX888;
2076                 break;
2077         case DRM_FORMAT_XRGB2101010:
2078         case DRM_FORMAT_ARGB2101010:
2079                 dspcntr |= DISPPLANE_BGRX101010;
2080                 break;
2081         case DRM_FORMAT_XBGR2101010:
2082         case DRM_FORMAT_ABGR2101010:
2083                 dspcntr |= DISPPLANE_RGBX101010;
2084                 break;
2085         default:
2086                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2087                 return -EINVAL;
2088         }
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 if (obj->tiling_mode != I915_TILING_NONE)
2092                         dspcntr |= DISPPLANE_TILED;
2093                 else
2094                         dspcntr &= ~DISPPLANE_TILED;
2095         }
2096
2097         I915_WRITE(reg, dspcntr);
2098
2099         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2100
2101         if (INTEL_INFO(dev)->gen >= 4) {
2102                 intel_crtc->dspaddr_offset =
2103                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2104                                                        fb->bits_per_pixel / 8,
2105                                                        fb->pitches[0]);
2106                 linear_offset -= intel_crtc->dspaddr_offset;
2107         } else {
2108                 intel_crtc->dspaddr_offset = linear_offset;
2109         }
2110
2111         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2112                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2113         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2114         if (INTEL_INFO(dev)->gen >= 4) {
2115                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2116                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2117                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2118                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2119         } else
2120                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2121         POSTING_READ(reg);
2122
2123         return 0;
2124 }
2125
2126 static int ironlake_update_plane(struct drm_crtc *crtc,
2127                                  struct drm_framebuffer *fb, int x, int y)
2128 {
2129         struct drm_device *dev = crtc->dev;
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132         struct intel_framebuffer *intel_fb;
2133         struct drm_i915_gem_object *obj;
2134         int plane = intel_crtc->plane;
2135         unsigned long linear_offset;
2136         u32 dspcntr;
2137         u32 reg;
2138
2139         switch (plane) {
2140         case 0:
2141         case 1:
2142         case 2:
2143                 break;
2144         default:
2145                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2146                 return -EINVAL;
2147         }
2148
2149         intel_fb = to_intel_framebuffer(fb);
2150         obj = intel_fb->obj;
2151
2152         reg = DSPCNTR(plane);
2153         dspcntr = I915_READ(reg);
2154         /* Mask out pixel format bits in case we change it */
2155         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2156         switch (fb->pixel_format) {
2157         case DRM_FORMAT_C8:
2158                 dspcntr |= DISPPLANE_8BPP;
2159                 break;
2160         case DRM_FORMAT_RGB565:
2161                 dspcntr |= DISPPLANE_BGRX565;
2162                 break;
2163         case DRM_FORMAT_XRGB8888:
2164         case DRM_FORMAT_ARGB8888:
2165                 dspcntr |= DISPPLANE_BGRX888;
2166                 break;
2167         case DRM_FORMAT_XBGR8888:
2168         case DRM_FORMAT_ABGR8888:
2169                 dspcntr |= DISPPLANE_RGBX888;
2170                 break;
2171         case DRM_FORMAT_XRGB2101010:
2172         case DRM_FORMAT_ARGB2101010:
2173                 dspcntr |= DISPPLANE_BGRX101010;
2174                 break;
2175         case DRM_FORMAT_XBGR2101010:
2176         case DRM_FORMAT_ABGR2101010:
2177                 dspcntr |= DISPPLANE_RGBX101010;
2178                 break;
2179         default:
2180                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2181                 return -EINVAL;
2182         }
2183
2184         if (obj->tiling_mode != I915_TILING_NONE)
2185                 dspcntr |= DISPPLANE_TILED;
2186         else
2187                 dspcntr &= ~DISPPLANE_TILED;
2188
2189         /* must disable */
2190         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2191
2192         I915_WRITE(reg, dspcntr);
2193
2194         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2195         intel_crtc->dspaddr_offset =
2196                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2197                                                fb->bits_per_pixel / 8,
2198                                                fb->pitches[0]);
2199         linear_offset -= intel_crtc->dspaddr_offset;
2200
2201         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2202                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2203         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2204         I915_MODIFY_DISPBASE(DSPSURF(plane),
2205                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2206         if (IS_HASWELL(dev)) {
2207                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208         } else {
2209                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211         }
2212         POSTING_READ(reg);
2213
2214         return 0;
2215 }
2216
2217 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2218 static int
2219 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220                            int x, int y, enum mode_set_atomic state)
2221 {
2222         struct drm_device *dev = crtc->dev;
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224
2225         if (dev_priv->display.disable_fbc)
2226                 dev_priv->display.disable_fbc(dev);
2227         intel_increase_pllclock(crtc);
2228
2229         return dev_priv->display.update_plane(crtc, fb, x, y);
2230 }
2231
2232 static int
2233 intel_finish_fb(struct drm_framebuffer *old_fb)
2234 {
2235         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2236         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2237         bool was_interruptible = dev_priv->mm.interruptible;
2238         int ret;
2239
2240         /* Big Hammer, we also need to ensure that any pending
2241          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2242          * current scanout is retired before unpinning the old
2243          * framebuffer.
2244          *
2245          * This should only fail upon a hung GPU, in which case we
2246          * can safely continue.
2247          */
2248         dev_priv->mm.interruptible = false;
2249         ret = i915_gem_object_finish_gpu(obj);
2250         dev_priv->mm.interruptible = was_interruptible;
2251
2252         return ret;
2253 }
2254
2255 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2256 {
2257         struct drm_device *dev = crtc->dev;
2258         struct drm_i915_master_private *master_priv;
2259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260
2261         if (!dev->primary->master)
2262                 return;
2263
2264         master_priv = dev->primary->master->driver_priv;
2265         if (!master_priv->sarea_priv)
2266                 return;
2267
2268         switch (intel_crtc->pipe) {
2269         case 0:
2270                 master_priv->sarea_priv->pipeA_x = x;
2271                 master_priv->sarea_priv->pipeA_y = y;
2272                 break;
2273         case 1:
2274                 master_priv->sarea_priv->pipeB_x = x;
2275                 master_priv->sarea_priv->pipeB_y = y;
2276                 break;
2277         default:
2278                 break;
2279         }
2280 }
2281
2282 static int
2283 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2284                     struct drm_framebuffer *fb)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         struct drm_framebuffer *old_fb;
2290         int ret;
2291
2292         /* no fb bound */
2293         if (!fb) {
2294                 DRM_ERROR("No FB bound\n");
2295                 return 0;
2296         }
2297
2298         if(intel_crtc->plane > dev_priv->num_pipe) {
2299                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2300                                 intel_crtc->plane,
2301                                 dev_priv->num_pipe);
2302                 return -EINVAL;
2303         }
2304
2305         mutex_lock(&dev->struct_mutex);
2306         ret = intel_pin_and_fence_fb_obj(dev,
2307                                          to_intel_framebuffer(fb)->obj,
2308                                          NULL);
2309         if (ret != 0) {
2310                 mutex_unlock(&dev->struct_mutex);
2311                 DRM_ERROR("pin & fence failed\n");
2312                 return ret;
2313         }
2314
2315         if (crtc->fb)
2316                 intel_finish_fb(crtc->fb);
2317
2318         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2319         if (ret) {
2320                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("failed to update base address\n");
2323                 return ret;
2324         }
2325
2326         old_fb = crtc->fb;
2327         crtc->fb = fb;
2328         crtc->x = x;
2329         crtc->y = y;
2330
2331         if (old_fb) {
2332                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2333                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2334         }
2335
2336         intel_update_fbc(dev);
2337         mutex_unlock(&dev->struct_mutex);
2338
2339         intel_crtc_update_sarea_pos(crtc, x, y);
2340
2341         return 0;
2342 }
2343
2344 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2345 {
2346         struct drm_device *dev = crtc->dev;
2347         struct drm_i915_private *dev_priv = dev->dev_private;
2348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2349         int pipe = intel_crtc->pipe;
2350         u32 reg, temp;
2351
2352         /* enable normal train */
2353         reg = FDI_TX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (IS_IVYBRIDGE(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2357                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2361         }
2362         I915_WRITE(reg, temp);
2363
2364         reg = FDI_RX_CTL(pipe);
2365         temp = I915_READ(reg);
2366         if (HAS_PCH_CPT(dev)) {
2367                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2368                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2369         } else {
2370                 temp &= ~FDI_LINK_TRAIN_NONE;
2371                 temp |= FDI_LINK_TRAIN_NONE;
2372         }
2373         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2374
2375         /* wait one idle pattern time */
2376         POSTING_READ(reg);
2377         udelay(1000);
2378
2379         /* IVB wants error correction enabled */
2380         if (IS_IVYBRIDGE(dev))
2381                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2382                            FDI_FE_ERRC_ENABLE);
2383 }
2384
2385 static void ivb_modeset_global_resources(struct drm_device *dev)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct intel_crtc *pipe_B_crtc =
2389                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2390         struct intel_crtc *pipe_C_crtc =
2391                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2392         uint32_t temp;
2393
2394         /* When everything is off disable fdi C so that we could enable fdi B
2395          * with all lanes. XXX: This misses the case where a pipe is not using
2396          * any pch resources and so doesn't need any fdi lanes. */
2397         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2398                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2399                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2400
2401                 temp = I915_READ(SOUTH_CHICKEN1);
2402                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2403                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2404                 I915_WRITE(SOUTH_CHICKEN1, temp);
2405         }
2406 }
2407
2408 /* The FDI link training functions for ILK/Ibexpeak. */
2409 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2410 {
2411         struct drm_device *dev = crtc->dev;
2412         struct drm_i915_private *dev_priv = dev->dev_private;
2413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414         int pipe = intel_crtc->pipe;
2415         int plane = intel_crtc->plane;
2416         u32 reg, temp, tries;
2417
2418         /* FDI needs bits from pipe & plane first */
2419         assert_pipe_enabled(dev_priv, pipe);
2420         assert_plane_enabled(dev_priv, plane);
2421
2422         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2423            for train result */
2424         reg = FDI_RX_IMR(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_RX_SYMBOL_LOCK;
2427         temp &= ~FDI_RX_BIT_LOCK;
2428         I915_WRITE(reg, temp);
2429         I915_READ(reg);
2430         udelay(150);
2431
2432         /* enable CPU FDI TX and PCH FDI RX */
2433         reg = FDI_TX_CTL(pipe);
2434         temp = I915_READ(reg);
2435         temp &= ~(7 << 19);
2436         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2437         temp &= ~FDI_LINK_TRAIN_NONE;
2438         temp |= FDI_LINK_TRAIN_PATTERN_1;
2439         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_LINK_TRAIN_NONE;
2444         temp |= FDI_LINK_TRAIN_PATTERN_1;
2445         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         /* Ironlake workaround, enable clock pointer after FDI enable*/
2451         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2452         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2453                    FDI_RX_PHASE_SYNC_POINTER_EN);
2454
2455         reg = FDI_RX_IIR(pipe);
2456         for (tries = 0; tries < 5; tries++) {
2457                 temp = I915_READ(reg);
2458                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460                 if ((temp & FDI_RX_BIT_LOCK)) {
2461                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2462                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2463                         break;
2464                 }
2465         }
2466         if (tries == 5)
2467                 DRM_ERROR("FDI train 1 fail!\n");
2468
2469         /* Train 2 */
2470         reg = FDI_TX_CTL(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_LINK_TRAIN_NONE;
2473         temp |= FDI_LINK_TRAIN_PATTERN_2;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_NONE;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         reg = FDI_RX_IIR(pipe);
2486         for (tries = 0; tries < 5; tries++) {
2487                 temp = I915_READ(reg);
2488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490                 if (temp & FDI_RX_SYMBOL_LOCK) {
2491                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2492                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2493                         break;
2494                 }
2495         }
2496         if (tries == 5)
2497                 DRM_ERROR("FDI train 2 fail!\n");
2498
2499         DRM_DEBUG_KMS("FDI train done\n");
2500
2501 }
2502
2503 static const int snb_b_fdi_train_param[] = {
2504         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508 };
2509
2510 /* The FDI link training functions for SNB/Cougarpoint. */
2511 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp, i, retry;
2518
2519         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520            for train result */
2521         reg = FDI_RX_IMR(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_RX_SYMBOL_LOCK;
2524         temp &= ~FDI_RX_BIT_LOCK;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         /* enable CPU FDI TX and PCH FDI RX */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         temp &= ~(7 << 19);
2534         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_1;
2537         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538         /* SNB-B */
2539         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2540         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2541
2542         I915_WRITE(FDI_RX_MISC(pipe),
2543                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
2545         reg = FDI_RX_CTL(pipe);
2546         temp = I915_READ(reg);
2547         if (HAS_PCH_CPT(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550         } else {
2551                 temp &= ~FDI_LINK_TRAIN_NONE;
2552                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553         }
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         for (i = 0; i < 4; i++) {
2560                 reg = FDI_TX_CTL(pipe);
2561                 temp = I915_READ(reg);
2562                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563                 temp |= snb_b_fdi_train_param[i];
2564                 I915_WRITE(reg, temp);
2565
2566                 POSTING_READ(reg);
2567                 udelay(500);
2568
2569                 for (retry = 0; retry < 5; retry++) {
2570                         reg = FDI_RX_IIR(pipe);
2571                         temp = I915_READ(reg);
2572                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2573                         if (temp & FDI_RX_BIT_LOCK) {
2574                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2575                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2576                                 break;
2577                         }
2578                         udelay(50);
2579                 }
2580                 if (retry < 5)
2581                         break;
2582         }
2583         if (i == 4)
2584                 DRM_ERROR("FDI train 1 fail!\n");
2585
2586         /* Train 2 */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~FDI_LINK_TRAIN_NONE;
2590         temp |= FDI_LINK_TRAIN_PATTERN_2;
2591         if (IS_GEN6(dev)) {
2592                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2593                 /* SNB-B */
2594                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595         }
2596         I915_WRITE(reg, temp);
2597
2598         reg = FDI_RX_CTL(pipe);
2599         temp = I915_READ(reg);
2600         if (HAS_PCH_CPT(dev)) {
2601                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2602                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2603         } else {
2604                 temp &= ~FDI_LINK_TRAIN_NONE;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2606         }
2607         I915_WRITE(reg, temp);
2608
2609         POSTING_READ(reg);
2610         udelay(150);
2611
2612         for (i = 0; i < 4; i++) {
2613                 reg = FDI_TX_CTL(pipe);
2614                 temp = I915_READ(reg);
2615                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616                 temp |= snb_b_fdi_train_param[i];
2617                 I915_WRITE(reg, temp);
2618
2619                 POSTING_READ(reg);
2620                 udelay(500);
2621
2622                 for (retry = 0; retry < 5; retry++) {
2623                         reg = FDI_RX_IIR(pipe);
2624                         temp = I915_READ(reg);
2625                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626                         if (temp & FDI_RX_SYMBOL_LOCK) {
2627                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2628                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2629                                 break;
2630                         }
2631                         udelay(50);
2632                 }
2633                 if (retry < 5)
2634                         break;
2635         }
2636         if (i == 4)
2637                 DRM_ERROR("FDI train 2 fail!\n");
2638
2639         DRM_DEBUG_KMS("FDI train done.\n");
2640 }
2641
2642 /* Manual link training for Ivy Bridge A0 parts */
2643 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2644 {
2645         struct drm_device *dev = crtc->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648         int pipe = intel_crtc->pipe;
2649         u32 reg, temp, i;
2650
2651         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2652            for train result */
2653         reg = FDI_RX_IMR(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_RX_SYMBOL_LOCK;
2656         temp &= ~FDI_RX_BIT_LOCK;
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2663                       I915_READ(FDI_RX_IIR(pipe)));
2664
2665         /* enable CPU FDI TX and PCH FDI RX */
2666         reg = FDI_TX_CTL(pipe);
2667         temp = I915_READ(reg);
2668         temp &= ~(7 << 19);
2669         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2670         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2671         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2672         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674         temp |= FDI_COMPOSITE_SYNC;
2675         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2676
2677         I915_WRITE(FDI_RX_MISC(pipe),
2678                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2679
2680         reg = FDI_RX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         temp &= ~FDI_LINK_TRAIN_AUTO;
2683         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2685         temp |= FDI_COMPOSITE_SYNC;
2686         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2687
2688         POSTING_READ(reg);
2689         udelay(150);
2690
2691         for (i = 0; i < 4; i++) {
2692                 reg = FDI_TX_CTL(pipe);
2693                 temp = I915_READ(reg);
2694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695                 temp |= snb_b_fdi_train_param[i];
2696                 I915_WRITE(reg, temp);
2697
2698                 POSTING_READ(reg);
2699                 udelay(500);
2700
2701                 reg = FDI_RX_IIR(pipe);
2702                 temp = I915_READ(reg);
2703                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2704
2705                 if (temp & FDI_RX_BIT_LOCK ||
2706                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2707                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2708                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2709                         break;
2710                 }
2711         }
2712         if (i == 4)
2713                 DRM_ERROR("FDI train 1 fail!\n");
2714
2715         /* Train 2 */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2719         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2720         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2721         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2722         I915_WRITE(reg, temp);
2723
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2727         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2728         I915_WRITE(reg, temp);
2729
2730         POSTING_READ(reg);
2731         udelay(150);
2732
2733         for (i = 0; i < 4; i++) {
2734                 reg = FDI_TX_CTL(pipe);
2735                 temp = I915_READ(reg);
2736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737                 temp |= snb_b_fdi_train_param[i];
2738                 I915_WRITE(reg, temp);
2739
2740                 POSTING_READ(reg);
2741                 udelay(500);
2742
2743                 reg = FDI_RX_IIR(pipe);
2744                 temp = I915_READ(reg);
2745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747                 if (temp & FDI_RX_SYMBOL_LOCK) {
2748                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2749                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2750                         break;
2751                 }
2752         }
2753         if (i == 4)
2754                 DRM_ERROR("FDI train 2 fail!\n");
2755
2756         DRM_DEBUG_KMS("FDI train done.\n");
2757 }
2758
2759 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2760 {
2761         struct drm_device *dev = intel_crtc->base.dev;
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         int pipe = intel_crtc->pipe;
2764         u32 reg, temp;
2765
2766
2767         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         temp &= ~((0x7 << 19) | (0x7 << 16));
2771         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2772         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2773         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2774
2775         POSTING_READ(reg);
2776         udelay(200);
2777
2778         /* Switch from Rawclk to PCDclk */
2779         temp = I915_READ(reg);
2780         I915_WRITE(reg, temp | FDI_PCDCLK);
2781
2782         POSTING_READ(reg);
2783         udelay(200);
2784
2785         /* Enable CPU FDI TX PLL, always on for Ironlake */
2786         reg = FDI_TX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2789                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2790
2791                 POSTING_READ(reg);
2792                 udelay(100);
2793         }
2794 }
2795
2796 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2797 {
2798         struct drm_device *dev = intel_crtc->base.dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         int pipe = intel_crtc->pipe;
2801         u32 reg, temp;
2802
2803         /* Switch from PCDclk to Rawclk */
2804         reg = FDI_RX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2807
2808         /* Disable CPU FDI TX PLL */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2812
2813         POSTING_READ(reg);
2814         udelay(100);
2815
2816         reg = FDI_RX_CTL(pipe);
2817         temp = I915_READ(reg);
2818         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2819
2820         /* Wait for the clocks to turn off. */
2821         POSTING_READ(reg);
2822         udelay(100);
2823 }
2824
2825 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2826 {
2827         struct drm_device *dev = crtc->dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830         int pipe = intel_crtc->pipe;
2831         u32 reg, temp;
2832
2833         /* disable CPU FDI tx and PCH FDI rx */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2837         POSTING_READ(reg);
2838
2839         reg = FDI_RX_CTL(pipe);
2840         temp = I915_READ(reg);
2841         temp &= ~(0x7 << 16);
2842         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2843         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2844
2845         POSTING_READ(reg);
2846         udelay(100);
2847
2848         /* Ironlake workaround, disable clock pointer after downing FDI */
2849         if (HAS_PCH_IBX(dev)) {
2850                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2851         }
2852
2853         /* still set train pattern 1 */
2854         reg = FDI_TX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         temp &= ~FDI_LINK_TRAIN_NONE;
2857         temp |= FDI_LINK_TRAIN_PATTERN_1;
2858         I915_WRITE(reg, temp);
2859
2860         reg = FDI_RX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         if (HAS_PCH_CPT(dev)) {
2863                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2865         } else {
2866                 temp &= ~FDI_LINK_TRAIN_NONE;
2867                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2868         }
2869         /* BPC in FDI rx is consistent with that in PIPECONF */
2870         temp &= ~(0x07 << 16);
2871         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2872         I915_WRITE(reg, temp);
2873
2874         POSTING_READ(reg);
2875         udelay(100);
2876 }
2877
2878 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2879 {
2880         struct drm_device *dev = crtc->dev;
2881         struct drm_i915_private *dev_priv = dev->dev_private;
2882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2883         unsigned long flags;
2884         bool pending;
2885
2886         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2887             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2888                 return false;
2889
2890         spin_lock_irqsave(&dev->event_lock, flags);
2891         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2892         spin_unlock_irqrestore(&dev->event_lock, flags);
2893
2894         return pending;
2895 }
2896
2897 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2898 {
2899         struct drm_device *dev = crtc->dev;
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901
2902         if (crtc->fb == NULL)
2903                 return;
2904
2905         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2906
2907         wait_event(dev_priv->pending_flip_queue,
2908                    !intel_crtc_has_pending_flip(crtc));
2909
2910         mutex_lock(&dev->struct_mutex);
2911         intel_finish_fb(crtc->fb);
2912         mutex_unlock(&dev->struct_mutex);
2913 }
2914
2915 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2916 {
2917         struct drm_device *dev = crtc->dev;
2918         struct intel_encoder *intel_encoder;
2919
2920         /*
2921          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2922          * must be driven by its own crtc; no sharing is possible.
2923          */
2924         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2925                 switch (intel_encoder->type) {
2926                 case INTEL_OUTPUT_EDP:
2927                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2928                                 return false;
2929                         continue;
2930                 }
2931         }
2932
2933         return true;
2934 }
2935
2936 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2937 {
2938         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2939 }
2940
2941 /* Program iCLKIP clock to the desired frequency */
2942 static void lpt_program_iclkip(struct drm_crtc *crtc)
2943 {
2944         struct drm_device *dev = crtc->dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2947         u32 temp;
2948
2949         mutex_lock(&dev_priv->dpio_lock);
2950
2951         /* It is necessary to ungate the pixclk gate prior to programming
2952          * the divisors, and gate it back when it is done.
2953          */
2954         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2955
2956         /* Disable SSCCTL */
2957         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2958                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2959                                 SBI_SSCCTL_DISABLE,
2960                         SBI_ICLK);
2961
2962         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2963         if (crtc->mode.clock == 20000) {
2964                 auxdiv = 1;
2965                 divsel = 0x41;
2966                 phaseinc = 0x20;
2967         } else {
2968                 /* The iCLK virtual clock root frequency is in MHz,
2969                  * but the crtc->mode.clock in in KHz. To get the divisors,
2970                  * it is necessary to divide one by another, so we
2971                  * convert the virtual clock precision to KHz here for higher
2972                  * precision.
2973                  */
2974                 u32 iclk_virtual_root_freq = 172800 * 1000;
2975                 u32 iclk_pi_range = 64;
2976                 u32 desired_divisor, msb_divisor_value, pi_value;
2977
2978                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2979                 msb_divisor_value = desired_divisor / iclk_pi_range;
2980                 pi_value = desired_divisor % iclk_pi_range;
2981
2982                 auxdiv = 0;
2983                 divsel = msb_divisor_value - 2;
2984                 phaseinc = pi_value;
2985         }
2986
2987         /* This should not happen with any sane values */
2988         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2989                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2990         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2991                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2992
2993         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2994                         crtc->mode.clock,
2995                         auxdiv,
2996                         divsel,
2997                         phasedir,
2998                         phaseinc);
2999
3000         /* Program SSCDIVINTPHASE6 */
3001         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3002         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3003         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3004         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3005         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3006         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3007         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3008         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3009
3010         /* Program SSCAUXDIV */
3011         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3012         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3013         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3014         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3015
3016         /* Enable modulator and associated divider */
3017         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3018         temp &= ~SBI_SSCCTL_DISABLE;
3019         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3020
3021         /* Wait for initialization time */
3022         udelay(24);
3023
3024         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3025
3026         mutex_unlock(&dev_priv->dpio_lock);
3027 }
3028
3029 /*
3030  * Enable PCH resources required for PCH ports:
3031  *   - PCH PLLs
3032  *   - FDI training & RX/TX
3033  *   - update transcoder timings
3034  *   - DP transcoding bits
3035  *   - transcoder
3036  */
3037 static void ironlake_pch_enable(struct drm_crtc *crtc)
3038 {
3039         struct drm_device *dev = crtc->dev;
3040         struct drm_i915_private *dev_priv = dev->dev_private;
3041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042         int pipe = intel_crtc->pipe;
3043         u32 reg, temp;
3044
3045         assert_transcoder_disabled(dev_priv, pipe);
3046
3047         /* Write the TU size bits before fdi link training, so that error
3048          * detection works. */
3049         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3050                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3051
3052         /* For PCH output, training FDI link */
3053         dev_priv->display.fdi_link_train(crtc);
3054
3055         /* XXX: pch pll's can be enabled any time before we enable the PCH
3056          * transcoder, and we actually should do this to not upset any PCH
3057          * transcoder that already use the clock when we share it.
3058          *
3059          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3060          * unconditionally resets the pll - we need that to have the right LVDS
3061          * enable sequence. */
3062         ironlake_enable_pch_pll(intel_crtc);
3063
3064         if (HAS_PCH_CPT(dev)) {
3065                 u32 sel;
3066
3067                 temp = I915_READ(PCH_DPLL_SEL);
3068                 switch (pipe) {
3069                 default:
3070                 case 0:
3071                         temp |= TRANSA_DPLL_ENABLE;
3072                         sel = TRANSA_DPLLB_SEL;
3073                         break;
3074                 case 1:
3075                         temp |= TRANSB_DPLL_ENABLE;
3076                         sel = TRANSB_DPLLB_SEL;
3077                         break;
3078                 case 2:
3079                         temp |= TRANSC_DPLL_ENABLE;
3080                         sel = TRANSC_DPLLB_SEL;
3081                         break;
3082                 }
3083                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3084                         temp |= sel;
3085                 else
3086                         temp &= ~sel;
3087                 I915_WRITE(PCH_DPLL_SEL, temp);
3088         }
3089
3090         /* set transcoder timing, panel must allow it */
3091         assert_panel_unlocked(dev_priv, pipe);
3092         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3093         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3094         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3095
3096         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3097         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3098         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3099         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3100
3101         intel_fdi_normal_train(crtc);
3102
3103         /* For PCH DP, enable TRANS_DP_CTL */
3104         if (HAS_PCH_CPT(dev) &&
3105             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3106              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3107                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3108                 reg = TRANS_DP_CTL(pipe);
3109                 temp = I915_READ(reg);
3110                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3111                           TRANS_DP_SYNC_MASK |
3112                           TRANS_DP_BPC_MASK);
3113                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3114                          TRANS_DP_ENH_FRAMING);
3115                 temp |= bpc << 9; /* same format but at 11:9 */
3116
3117                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3118                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3119                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3120                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3121
3122                 switch (intel_trans_dp_port_sel(crtc)) {
3123                 case PCH_DP_B:
3124                         temp |= TRANS_DP_PORT_SEL_B;
3125                         break;
3126                 case PCH_DP_C:
3127                         temp |= TRANS_DP_PORT_SEL_C;
3128                         break;
3129                 case PCH_DP_D:
3130                         temp |= TRANS_DP_PORT_SEL_D;
3131                         break;
3132                 default:
3133                         BUG();
3134                 }
3135
3136                 I915_WRITE(reg, temp);
3137         }
3138
3139         ironlake_enable_pch_transcoder(dev_priv, pipe);
3140 }
3141
3142 static void lpt_pch_enable(struct drm_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3148
3149         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3150
3151         lpt_program_iclkip(crtc);
3152
3153         /* Set transcoder timing. */
3154         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3155         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3156         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3157
3158         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3159         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3160         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3161         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3162
3163         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3164 }
3165
3166 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3167 {
3168         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3169
3170         if (pll == NULL)
3171                 return;
3172
3173         if (pll->refcount == 0) {
3174                 WARN(1, "bad PCH PLL refcount\n");
3175                 return;
3176         }
3177
3178         --pll->refcount;
3179         intel_crtc->pch_pll = NULL;
3180 }
3181
3182 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3183 {
3184         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3185         struct intel_pch_pll *pll;
3186         int i;
3187
3188         pll = intel_crtc->pch_pll;
3189         if (pll) {
3190                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3191                               intel_crtc->base.base.id, pll->pll_reg);
3192                 goto prepare;
3193         }
3194
3195         if (HAS_PCH_IBX(dev_priv->dev)) {
3196                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3197                 i = intel_crtc->pipe;
3198                 pll = &dev_priv->pch_plls[i];
3199
3200                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3201                               intel_crtc->base.base.id, pll->pll_reg);
3202
3203                 goto found;
3204         }
3205
3206         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3207                 pll = &dev_priv->pch_plls[i];
3208
3209                 /* Only want to check enabled timings first */
3210                 if (pll->refcount == 0)
3211                         continue;
3212
3213                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3214                     fp == I915_READ(pll->fp0_reg)) {
3215                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3216                                       intel_crtc->base.base.id,
3217                                       pll->pll_reg, pll->refcount, pll->active);
3218
3219                         goto found;
3220                 }
3221         }
3222
3223         /* Ok no matching timings, maybe there's a free one? */
3224         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3225                 pll = &dev_priv->pch_plls[i];
3226                 if (pll->refcount == 0) {
3227                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3228                                       intel_crtc->base.base.id, pll->pll_reg);
3229                         goto found;
3230                 }
3231         }
3232
3233         return NULL;
3234
3235 found:
3236         intel_crtc->pch_pll = pll;
3237         pll->refcount++;
3238         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3239 prepare: /* separate function? */
3240         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3241
3242         /* Wait for the clocks to stabilize before rewriting the regs */
3243         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3244         POSTING_READ(pll->pll_reg);
3245         udelay(150);
3246
3247         I915_WRITE(pll->fp0_reg, fp);
3248         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3249         pll->on = false;
3250         return pll;
3251 }
3252
3253 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3254 {
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         int dslreg = PIPEDSL(pipe);
3257         u32 temp;
3258
3259         temp = I915_READ(dslreg);
3260         udelay(500);
3261         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3262                 if (wait_for(I915_READ(dslreg) != temp, 5))
3263                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3264         }
3265 }
3266
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268 {
3269         struct drm_device *dev = crtc->dev;
3270         struct drm_i915_private *dev_priv = dev->dev_private;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         struct intel_encoder *encoder;
3273         int pipe = intel_crtc->pipe;
3274         int plane = intel_crtc->plane;
3275         u32 temp;
3276         bool is_pch_port;
3277
3278         WARN_ON(!crtc->enabled);
3279
3280         if (intel_crtc->active)
3281                 return;
3282
3283         intel_crtc->active = true;
3284         intel_update_watermarks(dev);
3285
3286         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3287                 temp = I915_READ(PCH_LVDS);
3288                 if ((temp & LVDS_PORT_EN) == 0)
3289                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3290         }
3291
3292         is_pch_port = ironlake_crtc_driving_pch(crtc);
3293
3294         if (is_pch_port) {
3295                 /* Note: FDI PLL enabling _must_ be done before we enable the
3296                  * cpu pipes, hence this is separate from all the other fdi/pch
3297                  * enabling. */
3298                 ironlake_fdi_pll_enable(intel_crtc);
3299         } else {
3300                 assert_fdi_tx_disabled(dev_priv, pipe);
3301                 assert_fdi_rx_disabled(dev_priv, pipe);
3302         }
3303
3304         for_each_encoder_on_crtc(dev, crtc, encoder)
3305                 if (encoder->pre_enable)
3306                         encoder->pre_enable(encoder);
3307
3308         /* Enable panel fitting for LVDS */
3309         if (dev_priv->pch_pf_size &&
3310             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3311              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3312                 /* Force use of hard-coded filter coefficients
3313                  * as some pre-programmed values are broken,
3314                  * e.g. x201.
3315                  */
3316                 if (IS_IVYBRIDGE(dev))
3317                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3318                                                  PF_PIPE_SEL_IVB(pipe));
3319                 else
3320                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3321                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3322                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3323         }
3324
3325         /*
3326          * On ILK+ LUT must be loaded before the pipe is running but with
3327          * clocks enabled
3328          */
3329         intel_crtc_load_lut(crtc);
3330
3331         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3332         intel_enable_plane(dev_priv, plane, pipe);
3333
3334         if (is_pch_port)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         intel_crtc_update_cursor(crtc, true);
3342
3343         for_each_encoder_on_crtc(dev, crtc, encoder)
3344                 encoder->enable(encoder);
3345
3346         if (HAS_PCH_CPT(dev))
3347                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3348
3349         /*
3350          * There seems to be a race in PCH platform hw (at least on some
3351          * outputs) where an enabled pipe still completes any pageflip right
3352          * away (as if the pipe is off) instead of waiting for vblank. As soon
3353          * as the first vblank happend, everything works as expected. Hence just
3354          * wait for one vblank before returning to avoid strange things
3355          * happening.
3356          */
3357         intel_wait_for_vblank(dev, intel_crtc->pipe);
3358 }
3359
3360 static void haswell_crtc_enable(struct drm_crtc *crtc)
3361 {
3362         struct drm_device *dev = crtc->dev;
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         struct intel_encoder *encoder;
3366         int pipe = intel_crtc->pipe;
3367         int plane = intel_crtc->plane;
3368         bool is_pch_port;
3369
3370         WARN_ON(!crtc->enabled);
3371
3372         if (intel_crtc->active)
3373                 return;
3374
3375         intel_crtc->active = true;
3376         intel_update_watermarks(dev);
3377
3378         is_pch_port = haswell_crtc_driving_pch(crtc);
3379
3380         if (is_pch_port)
3381                 dev_priv->display.fdi_link_train(crtc);
3382
3383         for_each_encoder_on_crtc(dev, crtc, encoder)
3384                 if (encoder->pre_enable)
3385                         encoder->pre_enable(encoder);
3386
3387         intel_ddi_enable_pipe_clock(intel_crtc);
3388
3389         /* Enable panel fitting for eDP */
3390         if (dev_priv->pch_pf_size &&
3391             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3392                 /* Force use of hard-coded filter coefficients
3393                  * as some pre-programmed values are broken,
3394                  * e.g. x201.
3395                  */
3396                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3397                                          PF_PIPE_SEL_IVB(pipe));
3398                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3400         }
3401
3402         /*
3403          * On ILK+ LUT must be loaded before the pipe is running but with
3404          * clocks enabled
3405          */
3406         intel_crtc_load_lut(crtc);
3407
3408         intel_ddi_set_pipe_settings(crtc);
3409         intel_ddi_enable_pipe_func(crtc);
3410
3411         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3412         intel_enable_plane(dev_priv, plane, pipe);
3413
3414         if (is_pch_port)
3415                 lpt_pch_enable(crtc);
3416
3417         mutex_lock(&dev->struct_mutex);
3418         intel_update_fbc(dev);
3419         mutex_unlock(&dev->struct_mutex);
3420
3421         intel_crtc_update_cursor(crtc, true);
3422
3423         for_each_encoder_on_crtc(dev, crtc, encoder)
3424                 encoder->enable(encoder);
3425
3426         /*
3427          * There seems to be a race in PCH platform hw (at least on some
3428          * outputs) where an enabled pipe still completes any pageflip right
3429          * away (as if the pipe is off) instead of waiting for vblank. As soon
3430          * as the first vblank happend, everything works as expected. Hence just
3431          * wait for one vblank before returning to avoid strange things
3432          * happening.
3433          */
3434         intel_wait_for_vblank(dev, intel_crtc->pipe);
3435 }
3436
3437 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442         struct intel_encoder *encoder;
3443         int pipe = intel_crtc->pipe;
3444         int plane = intel_crtc->plane;
3445         u32 reg, temp;
3446
3447
3448         if (!intel_crtc->active)
3449                 return;
3450
3451         for_each_encoder_on_crtc(dev, crtc, encoder)
3452                 encoder->disable(encoder);
3453
3454         intel_crtc_wait_for_pending_flips(crtc);
3455         drm_vblank_off(dev, pipe);
3456         intel_crtc_update_cursor(crtc, false);
3457
3458         intel_disable_plane(dev_priv, plane, pipe);
3459
3460         if (dev_priv->cfb_plane == plane)
3461                 intel_disable_fbc(dev);
3462
3463         intel_disable_pipe(dev_priv, pipe);
3464
3465         /* Disable PF */
3466         I915_WRITE(PF_CTL(pipe), 0);
3467         I915_WRITE(PF_WIN_SZ(pipe), 0);
3468
3469         for_each_encoder_on_crtc(dev, crtc, encoder)
3470                 if (encoder->post_disable)
3471                         encoder->post_disable(encoder);
3472
3473         ironlake_fdi_disable(crtc);
3474
3475         ironlake_disable_pch_transcoder(dev_priv, pipe);
3476
3477         if (HAS_PCH_CPT(dev)) {
3478                 /* disable TRANS_DP_CTL */
3479                 reg = TRANS_DP_CTL(pipe);
3480                 temp = I915_READ(reg);
3481                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3482                 temp |= TRANS_DP_PORT_SEL_NONE;
3483                 I915_WRITE(reg, temp);
3484
3485                 /* disable DPLL_SEL */
3486                 temp = I915_READ(PCH_DPLL_SEL);
3487                 switch (pipe) {
3488                 case 0:
3489                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3490                         break;
3491                 case 1:
3492                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3493                         break;
3494                 case 2:
3495                         /* C shares PLL A or B */
3496                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3497                         break;
3498                 default:
3499                         BUG(); /* wtf */
3500                 }
3501                 I915_WRITE(PCH_DPLL_SEL, temp);
3502         }
3503
3504         /* disable PCH DPLL */
3505         intel_disable_pch_pll(intel_crtc);
3506
3507         ironlake_fdi_pll_disable(intel_crtc);
3508
3509         intel_crtc->active = false;
3510         intel_update_watermarks(dev);
3511
3512         mutex_lock(&dev->struct_mutex);
3513         intel_update_fbc(dev);
3514         mutex_unlock(&dev->struct_mutex);
3515 }
3516
3517 static void haswell_crtc_disable(struct drm_crtc *crtc)
3518 {
3519         struct drm_device *dev = crtc->dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522         struct intel_encoder *encoder;
3523         int pipe = intel_crtc->pipe;
3524         int plane = intel_crtc->plane;
3525         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3526         bool is_pch_port;
3527
3528         if (!intel_crtc->active)
3529                 return;
3530
3531         is_pch_port = haswell_crtc_driving_pch(crtc);
3532
3533         for_each_encoder_on_crtc(dev, crtc, encoder)
3534                 encoder->disable(encoder);
3535
3536         intel_crtc_wait_for_pending_flips(crtc);
3537         drm_vblank_off(dev, pipe);
3538         intel_crtc_update_cursor(crtc, false);
3539
3540         intel_disable_plane(dev_priv, plane, pipe);
3541
3542         if (dev_priv->cfb_plane == plane)
3543                 intel_disable_fbc(dev);
3544
3545         intel_disable_pipe(dev_priv, pipe);
3546
3547         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3548
3549         /* Disable PF */
3550         I915_WRITE(PF_CTL(pipe), 0);
3551         I915_WRITE(PF_WIN_SZ(pipe), 0);
3552
3553         intel_ddi_disable_pipe_clock(intel_crtc);
3554
3555         for_each_encoder_on_crtc(dev, crtc, encoder)
3556                 if (encoder->post_disable)
3557                         encoder->post_disable(encoder);
3558
3559         if (is_pch_port) {
3560                 lpt_disable_pch_transcoder(dev_priv);
3561                 intel_ddi_fdi_disable(crtc);
3562         }
3563
3564         intel_crtc->active = false;
3565         intel_update_watermarks(dev);
3566
3567         mutex_lock(&dev->struct_mutex);
3568         intel_update_fbc(dev);
3569         mutex_unlock(&dev->struct_mutex);
3570 }
3571
3572 static void ironlake_crtc_off(struct drm_crtc *crtc)
3573 {
3574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575         intel_put_pch_pll(intel_crtc);
3576 }
3577
3578 static void haswell_crtc_off(struct drm_crtc *crtc)
3579 {
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581
3582         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3583          * start using it. */
3584         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3585
3586         intel_ddi_put_crtc_pll(crtc);
3587 }
3588
3589 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3590 {
3591         if (!enable && intel_crtc->overlay) {
3592                 struct drm_device *dev = intel_crtc->base.dev;
3593                 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595                 mutex_lock(&dev->struct_mutex);
3596                 dev_priv->mm.interruptible = false;
3597                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3598                 dev_priv->mm.interruptible = true;
3599                 mutex_unlock(&dev->struct_mutex);
3600         }
3601
3602         /* Let userspace switch the overlay on again. In most cases userspace
3603          * has to recompute where to put it anyway.
3604          */
3605 }
3606
3607 /**
3608  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3609  * cursor plane briefly if not already running after enabling the display
3610  * plane.
3611  * This workaround avoids occasional blank screens when self refresh is
3612  * enabled.
3613  */
3614 static void
3615 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3616 {
3617         u32 cntl = I915_READ(CURCNTR(pipe));
3618
3619         if ((cntl & CURSOR_MODE) == 0) {
3620                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3621
3622                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3623                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3624                 intel_wait_for_vblank(dev_priv->dev, pipe);
3625                 I915_WRITE(CURCNTR(pipe), cntl);
3626                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3627                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3628         }
3629 }
3630
3631 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3632 {
3633         struct drm_device *dev = crtc->dev;
3634         struct drm_i915_private *dev_priv = dev->dev_private;
3635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3636         struct intel_encoder *encoder;
3637         int pipe = intel_crtc->pipe;
3638         int plane = intel_crtc->plane;
3639
3640         WARN_ON(!crtc->enabled);
3641
3642         if (intel_crtc->active)
3643                 return;
3644
3645         intel_crtc->active = true;
3646         intel_update_watermarks(dev);
3647
3648         intel_enable_pll(dev_priv, pipe);
3649
3650         for_each_encoder_on_crtc(dev, crtc, encoder)
3651                 if (encoder->pre_enable)
3652                         encoder->pre_enable(encoder);
3653
3654         intel_enable_pipe(dev_priv, pipe, false);
3655         intel_enable_plane(dev_priv, plane, pipe);
3656         if (IS_G4X(dev))
3657                 g4x_fixup_plane(dev_priv, pipe);
3658
3659         intel_crtc_load_lut(crtc);
3660         intel_update_fbc(dev);
3661
3662         /* Give the overlay scaler a chance to enable if it's on this pipe */
3663         intel_crtc_dpms_overlay(intel_crtc, true);
3664         intel_crtc_update_cursor(crtc, true);
3665
3666         for_each_encoder_on_crtc(dev, crtc, encoder)
3667                 encoder->enable(encoder);
3668 }
3669
3670 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3671 {
3672         struct drm_device *dev = crtc->dev;
3673         struct drm_i915_private *dev_priv = dev->dev_private;
3674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675         struct intel_encoder *encoder;
3676         int pipe = intel_crtc->pipe;
3677         int plane = intel_crtc->plane;
3678         u32 pctl;
3679
3680
3681         if (!intel_crtc->active)
3682                 return;
3683
3684         for_each_encoder_on_crtc(dev, crtc, encoder)
3685                 encoder->disable(encoder);
3686
3687         /* Give the overlay scaler a chance to disable if it's on this pipe */
3688         intel_crtc_wait_for_pending_flips(crtc);
3689         drm_vblank_off(dev, pipe);
3690         intel_crtc_dpms_overlay(intel_crtc, false);
3691         intel_crtc_update_cursor(crtc, false);
3692
3693         if (dev_priv->cfb_plane == plane)
3694                 intel_disable_fbc(dev);
3695
3696         intel_disable_plane(dev_priv, plane, pipe);
3697         intel_disable_pipe(dev_priv, pipe);
3698
3699         /* Disable pannel fitter if it is on this pipe. */
3700         pctl = I915_READ(PFIT_CONTROL);
3701         if ((pctl & PFIT_ENABLE) &&
3702             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3703                 I915_WRITE(PFIT_CONTROL, 0);
3704
3705         intel_disable_pll(dev_priv, pipe);
3706
3707         intel_crtc->active = false;
3708         intel_update_fbc(dev);
3709         intel_update_watermarks(dev);
3710 }
3711
3712 static void i9xx_crtc_off(struct drm_crtc *crtc)
3713 {
3714 }
3715
3716 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3717                                     bool enabled)
3718 {
3719         struct drm_device *dev = crtc->dev;
3720         struct drm_i915_master_private *master_priv;
3721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3722         int pipe = intel_crtc->pipe;
3723
3724         if (!dev->primary->master)
3725                 return;
3726
3727         master_priv = dev->primary->master->driver_priv;
3728         if (!master_priv->sarea_priv)
3729                 return;
3730
3731         switch (pipe) {
3732         case 0:
3733                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3734                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3735                 break;
3736         case 1:
3737                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3738                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3739                 break;
3740         default:
3741                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3742                 break;
3743         }
3744 }
3745
3746 /**
3747  * Sets the power management mode of the pipe and plane.
3748  */
3749 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3750 {
3751         struct drm_device *dev = crtc->dev;
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         struct intel_encoder *intel_encoder;
3754         bool enable = false;
3755
3756         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3757                 enable |= intel_encoder->connectors_active;
3758
3759         if (enable)
3760                 dev_priv->display.crtc_enable(crtc);
3761         else
3762                 dev_priv->display.crtc_disable(crtc);
3763
3764         intel_crtc_update_sarea(crtc, enable);
3765 }
3766
3767 static void intel_crtc_noop(struct drm_crtc *crtc)
3768 {
3769 }
3770
3771 static void intel_crtc_disable(struct drm_crtc *crtc)
3772 {
3773         struct drm_device *dev = crtc->dev;
3774         struct drm_connector *connector;
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777
3778         /* crtc should still be enabled when we disable it. */
3779         WARN_ON(!crtc->enabled);
3780
3781         intel_crtc->eld_vld = false;
3782         dev_priv->display.crtc_disable(crtc);
3783         intel_crtc_update_sarea(crtc, false);
3784         dev_priv->display.off(crtc);
3785
3786         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3787         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3788
3789         if (crtc->fb) {
3790                 mutex_lock(&dev->struct_mutex);
3791                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3792                 mutex_unlock(&dev->struct_mutex);
3793                 crtc->fb = NULL;
3794         }
3795
3796         /* Update computed state. */
3797         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3798                 if (!connector->encoder || !connector->encoder->crtc)
3799                         continue;
3800
3801                 if (connector->encoder->crtc != crtc)
3802                         continue;
3803
3804                 connector->dpms = DRM_MODE_DPMS_OFF;
3805                 to_intel_encoder(connector->encoder)->connectors_active = false;
3806         }
3807 }
3808
3809 void intel_modeset_disable(struct drm_device *dev)
3810 {
3811         struct drm_crtc *crtc;
3812
3813         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3814                 if (crtc->enabled)
3815                         intel_crtc_disable(crtc);
3816         }
3817 }
3818
3819 void intel_encoder_noop(struct drm_encoder *encoder)
3820 {
3821 }
3822
3823 void intel_encoder_destroy(struct drm_encoder *encoder)
3824 {
3825         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3826
3827         drm_encoder_cleanup(encoder);
3828         kfree(intel_encoder);
3829 }
3830
3831 /* Simple dpms helper for encodres with just one connector, no cloning and only
3832  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3833  * state of the entire output pipe. */
3834 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3835 {
3836         if (mode == DRM_MODE_DPMS_ON) {
3837                 encoder->connectors_active = true;
3838
3839                 intel_crtc_update_dpms(encoder->base.crtc);
3840         } else {
3841                 encoder->connectors_active = false;
3842
3843                 intel_crtc_update_dpms(encoder->base.crtc);
3844         }
3845 }
3846
3847 /* Cross check the actual hw state with our own modeset state tracking (and it's
3848  * internal consistency). */
3849 static void intel_connector_check_state(struct intel_connector *connector)
3850 {
3851         if (connector->get_hw_state(connector)) {
3852                 struct intel_encoder *encoder = connector->encoder;
3853                 struct drm_crtc *crtc;
3854                 bool encoder_enabled;
3855                 enum pipe pipe;
3856
3857                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3858                               connector->base.base.id,
3859                               drm_get_connector_name(&connector->base));
3860
3861                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3862                      "wrong connector dpms state\n");
3863                 WARN(connector->base.encoder != &encoder->base,
3864                      "active connector not linked to encoder\n");
3865                 WARN(!encoder->connectors_active,
3866                      "encoder->connectors_active not set\n");
3867
3868                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3869                 WARN(!encoder_enabled, "encoder not enabled\n");
3870                 if (WARN_ON(!encoder->base.crtc))
3871                         return;
3872
3873                 crtc = encoder->base.crtc;
3874
3875                 WARN(!crtc->enabled, "crtc not enabled\n");
3876                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3877                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3878                      "encoder active on the wrong pipe\n");
3879         }
3880 }
3881
3882 /* Even simpler default implementation, if there's really no special case to
3883  * consider. */
3884 void intel_connector_dpms(struct drm_connector *connector, int mode)
3885 {
3886         struct intel_encoder *encoder = intel_attached_encoder(connector);
3887
3888         /* All the simple cases only support two dpms states. */
3889         if (mode != DRM_MODE_DPMS_ON)
3890                 mode = DRM_MODE_DPMS_OFF;
3891
3892         if (mode == connector->dpms)
3893                 return;
3894
3895         connector->dpms = mode;
3896
3897         /* Only need to change hw state when actually enabled */
3898         if (encoder->base.crtc)
3899                 intel_encoder_dpms(encoder, mode);
3900         else
3901                 WARN_ON(encoder->connectors_active != false);
3902
3903         intel_modeset_check_state(connector->dev);
3904 }
3905
3906 /* Simple connector->get_hw_state implementation for encoders that support only
3907  * one connector and no cloning and hence the encoder state determines the state
3908  * of the connector. */
3909 bool intel_connector_get_hw_state(struct intel_connector *connector)
3910 {
3911         enum pipe pipe = 0;
3912         struct intel_encoder *encoder = connector->encoder;
3913
3914         return encoder->get_hw_state(encoder, &pipe);
3915 }
3916
3917 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3918                                   const struct drm_display_mode *mode,
3919                                   struct drm_display_mode *adjusted_mode)
3920 {
3921         struct drm_device *dev = crtc->dev;
3922
3923         if (HAS_PCH_SPLIT(dev)) {
3924                 /* FDI link clock is fixed at 2.7G */
3925                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3926                         return false;
3927         }
3928
3929         /* All interlaced capable intel hw wants timings in frames. Note though
3930          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3931          * timings, so we need to be careful not to clobber these.*/
3932         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3933                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3934
3935         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3936          * with a hsync front porch of 0.
3937          */
3938         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3939                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3940                 return false;
3941
3942         return true;
3943 }
3944
3945 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3946 {
3947         return 400000; /* FIXME */
3948 }
3949
3950 static int i945_get_display_clock_speed(struct drm_device *dev)
3951 {
3952         return 400000;
3953 }
3954
3955 static int i915_get_display_clock_speed(struct drm_device *dev)
3956 {
3957         return 333000;
3958 }
3959
3960 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3961 {
3962         return 200000;
3963 }
3964
3965 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3966 {
3967         u16 gcfgc = 0;
3968
3969         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3970
3971         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3972                 return 133000;
3973         else {
3974                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3975                 case GC_DISPLAY_CLOCK_333_MHZ:
3976                         return 333000;
3977                 default:
3978                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3979                         return 190000;
3980                 }
3981         }
3982 }
3983
3984 static int i865_get_display_clock_speed(struct drm_device *dev)
3985 {
3986         return 266000;
3987 }
3988
3989 static int i855_get_display_clock_speed(struct drm_device *dev)
3990 {
3991         u16 hpllcc = 0;
3992         /* Assume that the hardware is in the high speed state.  This
3993          * should be the default.
3994          */
3995         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3996         case GC_CLOCK_133_200:
3997         case GC_CLOCK_100_200:
3998                 return 200000;
3999         case GC_CLOCK_166_250:
4000                 return 250000;
4001         case GC_CLOCK_100_133:
4002                 return 133000;
4003         }
4004
4005         /* Shouldn't happen */
4006         return 0;
4007 }
4008
4009 static int i830_get_display_clock_speed(struct drm_device *dev)
4010 {
4011         return 133000;
4012 }
4013
4014 static void
4015 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4016 {
4017         while (*num > 0xffffff || *den > 0xffffff) {
4018                 *num >>= 1;
4019                 *den >>= 1;
4020         }
4021 }
4022
4023 void
4024 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4025                        int pixel_clock, int link_clock,
4026                        struct intel_link_m_n *m_n)
4027 {
4028         m_n->tu = 64;
4029         m_n->gmch_m = bits_per_pixel * pixel_clock;
4030         m_n->gmch_n = link_clock * nlanes * 8;
4031         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4032         m_n->link_m = pixel_clock;
4033         m_n->link_n = link_clock;
4034         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4035 }
4036
4037 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4038 {
4039         if (i915_panel_use_ssc >= 0)
4040                 return i915_panel_use_ssc != 0;
4041         return dev_priv->lvds_use_ssc
4042                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4043 }
4044
4045 /**
4046  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4047  * @crtc: CRTC structure
4048  * @mode: requested mode
4049  *
4050  * A pipe may be connected to one or more outputs.  Based on the depth of the
4051  * attached framebuffer, choose a good color depth to use on the pipe.
4052  *
4053  * If possible, match the pipe depth to the fb depth.  In some cases, this
4054  * isn't ideal, because the connected output supports a lesser or restricted
4055  * set of depths.  Resolve that here:
4056  *    LVDS typically supports only 6bpc, so clamp down in that case
4057  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4058  *    Displays may support a restricted set as well, check EDID and clamp as
4059  *      appropriate.
4060  *    DP may want to dither down to 6bpc to fit larger modes
4061  *
4062  * RETURNS:
4063  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4064  * true if they don't match).
4065  */
4066 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4067                                          struct drm_framebuffer *fb,
4068                                          unsigned int *pipe_bpp,
4069                                          struct drm_display_mode *mode)
4070 {
4071         struct drm_device *dev = crtc->dev;
4072         struct drm_i915_private *dev_priv = dev->dev_private;
4073         struct drm_connector *connector;
4074         struct intel_encoder *intel_encoder;
4075         unsigned int display_bpc = UINT_MAX, bpc;
4076
4077         /* Walk the encoders & connectors on this crtc, get min bpc */
4078         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4079
4080                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4081                         unsigned int lvds_bpc;
4082
4083                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4084                             LVDS_A3_POWER_UP)
4085                                 lvds_bpc = 8;
4086                         else
4087                                 lvds_bpc = 6;
4088
4089                         if (lvds_bpc < display_bpc) {
4090                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4091                                 display_bpc = lvds_bpc;
4092                         }
4093                         continue;
4094                 }
4095
4096                 /* Not one of the known troublemakers, check the EDID */
4097                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4098                                     head) {
4099                         if (connector->encoder != &intel_encoder->base)
4100                                 continue;
4101
4102                         /* Don't use an invalid EDID bpc value */
4103                         if (connector->display_info.bpc &&
4104                             connector->display_info.bpc < display_bpc) {
4105                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4106                                 display_bpc = connector->display_info.bpc;
4107                         }
4108                 }
4109
4110                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4111                         /* Use VBT settings if we have an eDP panel */
4112                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4113
4114                         if (edp_bpc && edp_bpc < display_bpc) {
4115                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4116                                 display_bpc = edp_bpc;
4117                         }
4118                         continue;
4119                 }
4120
4121                 /*
4122                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4123                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4124                  */
4125                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4126                         if (display_bpc > 8 && display_bpc < 12) {
4127                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4128                                 display_bpc = 12;
4129                         } else {
4130                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4131                                 display_bpc = 8;
4132                         }
4133                 }
4134         }
4135
4136         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4137                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4138                 display_bpc = 6;
4139         }
4140
4141         /*
4142          * We could just drive the pipe at the highest bpc all the time and
4143          * enable dithering as needed, but that costs bandwidth.  So choose
4144          * the minimum value that expresses the full color range of the fb but
4145          * also stays within the max display bpc discovered above.
4146          */
4147
4148         switch (fb->depth) {
4149         case 8:
4150                 bpc = 8; /* since we go through a colormap */
4151                 break;
4152         case 15:
4153         case 16:
4154                 bpc = 6; /* min is 18bpp */
4155                 break;
4156         case 24:
4157                 bpc = 8;
4158                 break;
4159         case 30:
4160                 bpc = 10;
4161                 break;
4162         case 48:
4163                 bpc = 12;
4164                 break;
4165         default:
4166                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4167                 bpc = min((unsigned int)8, display_bpc);
4168                 break;
4169         }
4170
4171         display_bpc = min(display_bpc, bpc);
4172
4173         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4174                       bpc, display_bpc);
4175
4176         *pipe_bpp = display_bpc * 3;
4177
4178         return display_bpc != bpc;
4179 }
4180
4181 static int vlv_get_refclk(struct drm_crtc *crtc)
4182 {
4183         struct drm_device *dev = crtc->dev;
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         int refclk = 27000; /* for DP & HDMI */
4186
4187         return 100000; /* only one validated so far */
4188
4189         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4190                 refclk = 96000;
4191         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4192                 if (intel_panel_use_ssc(dev_priv))
4193                         refclk = 100000;
4194                 else
4195                         refclk = 96000;
4196         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4197                 refclk = 100000;
4198         }
4199
4200         return refclk;
4201 }
4202
4203 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         int refclk;
4208
4209         if (IS_VALLEYVIEW(dev)) {
4210                 refclk = vlv_get_refclk(crtc);
4211         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4212             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4213                 refclk = dev_priv->lvds_ssc_freq * 1000;
4214                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4215                               refclk / 1000);
4216         } else if (!IS_GEN2(dev)) {
4217                 refclk = 96000;
4218         } else {
4219                 refclk = 48000;
4220         }
4221
4222         return refclk;
4223 }
4224
4225 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4226                                       intel_clock_t *clock)
4227 {
4228         /* SDVO TV has fixed PLL values depend on its clock range,
4229            this mirrors vbios setting. */
4230         if (adjusted_mode->clock >= 100000
4231             && adjusted_mode->clock < 140500) {
4232                 clock->p1 = 2;
4233                 clock->p2 = 10;
4234                 clock->n = 3;
4235                 clock->m1 = 16;
4236                 clock->m2 = 8;
4237         } else if (adjusted_mode->clock >= 140500
4238                    && adjusted_mode->clock <= 200000) {
4239                 clock->p1 = 1;
4240                 clock->p2 = 10;
4241                 clock->n = 6;
4242                 clock->m1 = 12;
4243                 clock->m2 = 8;
4244         }
4245 }
4246
4247 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4248                                      intel_clock_t *clock,
4249                                      intel_clock_t *reduced_clock)
4250 {
4251         struct drm_device *dev = crtc->dev;
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4254         int pipe = intel_crtc->pipe;
4255         u32 fp, fp2 = 0;
4256
4257         if (IS_PINEVIEW(dev)) {
4258                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4259                 if (reduced_clock)
4260                         fp2 = (1 << reduced_clock->n) << 16 |
4261                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4262         } else {
4263                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4264                 if (reduced_clock)
4265                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4266                                 reduced_clock->m2;
4267         }
4268
4269         I915_WRITE(FP0(pipe), fp);
4270
4271         intel_crtc->lowfreq_avail = false;
4272         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4273             reduced_clock && i915_powersave) {
4274                 I915_WRITE(FP1(pipe), fp2);
4275                 intel_crtc->lowfreq_avail = true;
4276         } else {
4277                 I915_WRITE(FP1(pipe), fp);
4278         }
4279 }
4280
4281 static void vlv_update_pll(struct drm_crtc *crtc,
4282                            struct drm_display_mode *mode,
4283                            struct drm_display_mode *adjusted_mode,
4284                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4285                            int num_connectors)
4286 {
4287         struct drm_device *dev = crtc->dev;
4288         struct drm_i915_private *dev_priv = dev->dev_private;
4289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4290         int pipe = intel_crtc->pipe;
4291         u32 dpll, mdiv, pdiv;
4292         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4293         bool is_sdvo;
4294         u32 temp;
4295
4296         mutex_lock(&dev_priv->dpio_lock);
4297
4298         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4299                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4300
4301         dpll = DPLL_VGA_MODE_DIS;
4302         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4303         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4304         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4305
4306         I915_WRITE(DPLL(pipe), dpll);
4307         POSTING_READ(DPLL(pipe));
4308
4309         bestn = clock->n;
4310         bestm1 = clock->m1;
4311         bestm2 = clock->m2;
4312         bestp1 = clock->p1;
4313         bestp2 = clock->p2;
4314
4315         /*
4316          * In Valleyview PLL and program lane counter registers are exposed
4317          * through DPIO interface
4318          */
4319         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4320         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4321         mdiv |= ((bestn << DPIO_N_SHIFT));
4322         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4323         mdiv |= (1 << DPIO_K_SHIFT);
4324         mdiv |= DPIO_ENABLE_CALIBRATION;
4325         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4326
4327         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4328
4329         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4330                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4331                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4332                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4333         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4334
4335         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4336
4337         dpll |= DPLL_VCO_ENABLE;
4338         I915_WRITE(DPLL(pipe), dpll);
4339         POSTING_READ(DPLL(pipe));
4340         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4341                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4342
4343         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4344
4345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4346                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4347
4348         I915_WRITE(DPLL(pipe), dpll);
4349
4350         /* Wait for the clocks to stabilize. */
4351         POSTING_READ(DPLL(pipe));
4352         udelay(150);
4353
4354         temp = 0;
4355         if (is_sdvo) {
4356                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4357                 if (temp > 1)
4358                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4359                 else
4360                         temp = 0;
4361         }
4362         I915_WRITE(DPLL_MD(pipe), temp);
4363         POSTING_READ(DPLL_MD(pipe));
4364
4365         /* Now program lane control registers */
4366         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4367                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4368         {
4369                 temp = 0x1000C4;
4370                 if(pipe == 1)
4371                         temp |= (1 << 21);
4372                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4373         }
4374         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4375         {
4376                 temp = 0x1000C4;
4377                 if(pipe == 1)
4378                         temp |= (1 << 21);
4379                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4380         }
4381
4382         mutex_unlock(&dev_priv->dpio_lock);
4383 }
4384
4385 static void i9xx_update_pll(struct drm_crtc *crtc,
4386                             struct drm_display_mode *mode,
4387                             struct drm_display_mode *adjusted_mode,
4388                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4389                             int num_connectors)
4390 {
4391         struct drm_device *dev = crtc->dev;
4392         struct drm_i915_private *dev_priv = dev->dev_private;
4393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4394         struct intel_encoder *encoder;
4395         int pipe = intel_crtc->pipe;
4396         u32 dpll;
4397         bool is_sdvo;
4398
4399         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4400
4401         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4402                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4403
4404         dpll = DPLL_VGA_MODE_DIS;
4405
4406         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4407                 dpll |= DPLLB_MODE_LVDS;
4408         else
4409                 dpll |= DPLLB_MODE_DAC_SERIAL;
4410         if (is_sdvo) {
4411                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4412                 if (pixel_multiplier > 1) {
4413                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4414                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4415                 }
4416                 dpll |= DPLL_DVO_HIGH_SPEED;
4417         }
4418         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4419                 dpll |= DPLL_DVO_HIGH_SPEED;
4420
4421         /* compute bitmask from p1 value */
4422         if (IS_PINEVIEW(dev))
4423                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4424         else {
4425                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4426                 if (IS_G4X(dev) && reduced_clock)
4427                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4428         }
4429         switch (clock->p2) {
4430         case 5:
4431                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4432                 break;
4433         case 7:
4434                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4435                 break;
4436         case 10:
4437                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4438                 break;
4439         case 14:
4440                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4441                 break;
4442         }
4443         if (INTEL_INFO(dev)->gen >= 4)
4444                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4445
4446         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4447                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4448         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4449                 /* XXX: just matching BIOS for now */
4450                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4451                 dpll |= 3;
4452         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4453                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4454                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4455         else
4456                 dpll |= PLL_REF_INPUT_DREFCLK;
4457
4458         dpll |= DPLL_VCO_ENABLE;
4459         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4460         POSTING_READ(DPLL(pipe));
4461         udelay(150);
4462
4463         for_each_encoder_on_crtc(dev, crtc, encoder)
4464                 if (encoder->pre_pll_enable)
4465                         encoder->pre_pll_enable(encoder);
4466
4467         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4468                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4469
4470         I915_WRITE(DPLL(pipe), dpll);
4471
4472         /* Wait for the clocks to stabilize. */
4473         POSTING_READ(DPLL(pipe));
4474         udelay(150);
4475
4476         if (INTEL_INFO(dev)->gen >= 4) {
4477                 u32 temp = 0;
4478                 if (is_sdvo) {
4479                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4480                         if (temp > 1)
4481                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4482                         else
4483                                 temp = 0;
4484                 }
4485                 I915_WRITE(DPLL_MD(pipe), temp);
4486         } else {
4487                 /* The pixel multiplier can only be updated once the
4488                  * DPLL is enabled and the clocks are stable.
4489                  *
4490                  * So write it again.
4491                  */
4492                 I915_WRITE(DPLL(pipe), dpll);
4493         }
4494 }
4495
4496 static void i8xx_update_pll(struct drm_crtc *crtc,
4497                             struct drm_display_mode *adjusted_mode,
4498                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4499                             int num_connectors)
4500 {
4501         struct drm_device *dev = crtc->dev;
4502         struct drm_i915_private *dev_priv = dev->dev_private;
4503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4504         struct intel_encoder *encoder;
4505         int pipe = intel_crtc->pipe;
4506         u32 dpll;
4507
4508         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4509
4510         dpll = DPLL_VGA_MODE_DIS;
4511
4512         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4513                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4514         } else {
4515                 if (clock->p1 == 2)
4516                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4517                 else
4518                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4519                 if (clock->p2 == 4)
4520                         dpll |= PLL_P2_DIVIDE_BY_4;
4521         }
4522
4523         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4524                 /* XXX: just matching BIOS for now */
4525                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4526                 dpll |= 3;
4527         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4528                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4529                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4530         else
4531                 dpll |= PLL_REF_INPUT_DREFCLK;
4532
4533         dpll |= DPLL_VCO_ENABLE;
4534         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4535         POSTING_READ(DPLL(pipe));
4536         udelay(150);
4537
4538         for_each_encoder_on_crtc(dev, crtc, encoder)
4539                 if (encoder->pre_pll_enable)
4540                         encoder->pre_pll_enable(encoder);
4541
4542         I915_WRITE(DPLL(pipe), dpll);
4543
4544         /* Wait for the clocks to stabilize. */
4545         POSTING_READ(DPLL(pipe));
4546         udelay(150);
4547
4548         /* The pixel multiplier can only be updated once the
4549          * DPLL is enabled and the clocks are stable.
4550          *
4551          * So write it again.
4552          */
4553         I915_WRITE(DPLL(pipe), dpll);
4554 }
4555
4556 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4557                                    struct drm_display_mode *mode,
4558                                    struct drm_display_mode *adjusted_mode)
4559 {
4560         struct drm_device *dev = intel_crtc->base.dev;
4561         struct drm_i915_private *dev_priv = dev->dev_private;
4562         enum pipe pipe = intel_crtc->pipe;
4563         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4564         uint32_t vsyncshift;
4565
4566         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4567                 /* the chip adds 2 halflines automatically */
4568                 adjusted_mode->crtc_vtotal -= 1;
4569                 adjusted_mode->crtc_vblank_end -= 1;
4570                 vsyncshift = adjusted_mode->crtc_hsync_start
4571                              - adjusted_mode->crtc_htotal / 2;
4572         } else {
4573                 vsyncshift = 0;
4574         }
4575
4576         if (INTEL_INFO(dev)->gen > 3)
4577                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4578
4579         I915_WRITE(HTOTAL(cpu_transcoder),
4580                    (adjusted_mode->crtc_hdisplay - 1) |
4581                    ((adjusted_mode->crtc_htotal - 1) << 16));
4582         I915_WRITE(HBLANK(cpu_transcoder),
4583                    (adjusted_mode->crtc_hblank_start - 1) |
4584                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4585         I915_WRITE(HSYNC(cpu_transcoder),
4586                    (adjusted_mode->crtc_hsync_start - 1) |
4587                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4588
4589         I915_WRITE(VTOTAL(cpu_transcoder),
4590                    (adjusted_mode->crtc_vdisplay - 1) |
4591                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4592         I915_WRITE(VBLANK(cpu_transcoder),
4593                    (adjusted_mode->crtc_vblank_start - 1) |
4594                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4595         I915_WRITE(VSYNC(cpu_transcoder),
4596                    (adjusted_mode->crtc_vsync_start - 1) |
4597                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4598
4599         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4600          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4601          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4602          * bits. */
4603         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4604             (pipe == PIPE_B || pipe == PIPE_C))
4605                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4606
4607         /* pipesrc controls the size that is scaled from, which should
4608          * always be the user's requested size.
4609          */
4610         I915_WRITE(PIPESRC(pipe),
4611                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4612 }
4613
4614 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4615                               struct drm_display_mode *mode,
4616                               struct drm_display_mode *adjusted_mode,
4617                               int x, int y,
4618                               struct drm_framebuffer *fb)
4619 {
4620         struct drm_device *dev = crtc->dev;
4621         struct drm_i915_private *dev_priv = dev->dev_private;
4622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4623         int pipe = intel_crtc->pipe;
4624         int plane = intel_crtc->plane;
4625         int refclk, num_connectors = 0;
4626         intel_clock_t clock, reduced_clock;
4627         u32 dspcntr, pipeconf;
4628         bool ok, has_reduced_clock = false, is_sdvo = false;
4629         bool is_lvds = false, is_tv = false, is_dp = false;
4630         struct intel_encoder *encoder;
4631         const intel_limit_t *limit;
4632         int ret;
4633
4634         for_each_encoder_on_crtc(dev, crtc, encoder) {
4635                 switch (encoder->type) {
4636                 case INTEL_OUTPUT_LVDS:
4637                         is_lvds = true;
4638                         break;
4639                 case INTEL_OUTPUT_SDVO:
4640                 case INTEL_OUTPUT_HDMI:
4641                         is_sdvo = true;
4642                         if (encoder->needs_tv_clock)
4643                                 is_tv = true;
4644                         break;
4645                 case INTEL_OUTPUT_TVOUT:
4646                         is_tv = true;
4647                         break;
4648                 case INTEL_OUTPUT_DISPLAYPORT:
4649                         is_dp = true;
4650                         break;
4651                 }
4652
4653                 num_connectors++;
4654         }
4655
4656         refclk = i9xx_get_refclk(crtc, num_connectors);
4657
4658         /*
4659          * Returns a set of divisors for the desired target clock with the given
4660          * refclk, or FALSE.  The returned values represent the clock equation:
4661          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4662          */
4663         limit = intel_limit(crtc, refclk);
4664         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4665                              &clock);
4666         if (!ok) {
4667                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4668                 return -EINVAL;
4669         }
4670
4671         /* Ensure that the cursor is valid for the new mode before changing... */
4672         intel_crtc_update_cursor(crtc, true);
4673
4674         if (is_lvds && dev_priv->lvds_downclock_avail) {
4675                 /*
4676                  * Ensure we match the reduced clock's P to the target clock.
4677                  * If the clocks don't match, we can't switch the display clock
4678                  * by using the FP0/FP1. In such case we will disable the LVDS
4679                  * downclock feature.
4680                 */
4681                 has_reduced_clock = limit->find_pll(limit, crtc,
4682                                                     dev_priv->lvds_downclock,
4683                                                     refclk,
4684                                                     &clock,
4685                                                     &reduced_clock);
4686         }
4687
4688         if (is_sdvo && is_tv)
4689                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4690
4691         if (IS_GEN2(dev))
4692                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4693                                 has_reduced_clock ? &reduced_clock : NULL,
4694                                 num_connectors);
4695         else if (IS_VALLEYVIEW(dev))
4696                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4697                                 has_reduced_clock ? &reduced_clock : NULL,
4698                                 num_connectors);
4699         else
4700                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4701                                 has_reduced_clock ? &reduced_clock : NULL,
4702                                 num_connectors);
4703
4704         /* setup pipeconf */
4705         pipeconf = I915_READ(PIPECONF(pipe));
4706
4707         /* Set up the display plane register */
4708         dspcntr = DISPPLANE_GAMMA_ENABLE;
4709
4710         if (pipe == 0)
4711                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4712         else
4713                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4714
4715         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4716                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4717                  * core speed.
4718                  *
4719                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4720                  * pipe == 0 check?
4721                  */
4722                 if (mode->clock >
4723                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4724                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4725                 else
4726                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4727         }
4728
4729         /* default to 8bpc */
4730         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4731         if (is_dp) {
4732                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4733                         pipeconf |= PIPECONF_6BPC |
4734                                     PIPECONF_DITHER_EN |
4735                                     PIPECONF_DITHER_TYPE_SP;
4736                 }
4737         }
4738
4739         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4740                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4741                         pipeconf |= PIPECONF_6BPC |
4742                                         PIPECONF_ENABLE |
4743                                         I965_PIPECONF_ACTIVE;
4744                 }
4745         }
4746
4747         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4748         drm_mode_debug_printmodeline(mode);
4749
4750         if (HAS_PIPE_CXSR(dev)) {
4751                 if (intel_crtc->lowfreq_avail) {
4752                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4753                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4754                 } else {
4755                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4756                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4757                 }
4758         }
4759
4760         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4761         if (!IS_GEN2(dev) &&
4762             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4763                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4764         else
4765                 pipeconf |= PIPECONF_PROGRESSIVE;
4766
4767         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4768
4769         /* pipesrc and dspsize control the size that is scaled from,
4770          * which should always be the user's requested size.
4771          */
4772         I915_WRITE(DSPSIZE(plane),
4773                    ((mode->vdisplay - 1) << 16) |
4774                    (mode->hdisplay - 1));
4775         I915_WRITE(DSPPOS(plane), 0);
4776
4777         I915_WRITE(PIPECONF(pipe), pipeconf);
4778         POSTING_READ(PIPECONF(pipe));
4779         intel_enable_pipe(dev_priv, pipe, false);
4780
4781         intel_wait_for_vblank(dev, pipe);
4782
4783         I915_WRITE(DSPCNTR(plane), dspcntr);
4784         POSTING_READ(DSPCNTR(plane));
4785
4786         ret = intel_pipe_set_base(crtc, x, y, fb);
4787
4788         intel_update_watermarks(dev);
4789
4790         return ret;
4791 }
4792
4793 static void ironlake_init_pch_refclk(struct drm_device *dev)
4794 {
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796         struct drm_mode_config *mode_config = &dev->mode_config;
4797         struct intel_encoder *encoder;
4798         u32 temp;
4799         bool has_lvds = false;
4800         bool has_cpu_edp = false;
4801         bool has_pch_edp = false;
4802         bool has_panel = false;
4803         bool has_ck505 = false;
4804         bool can_ssc = false;
4805
4806         /* We need to take the global config into account */
4807         list_for_each_entry(encoder, &mode_config->encoder_list,
4808                             base.head) {
4809                 switch (encoder->type) {
4810                 case INTEL_OUTPUT_LVDS:
4811                         has_panel = true;
4812                         has_lvds = true;
4813                         break;
4814                 case INTEL_OUTPUT_EDP:
4815                         has_panel = true;
4816                         if (intel_encoder_is_pch_edp(&encoder->base))
4817                                 has_pch_edp = true;
4818                         else
4819                                 has_cpu_edp = true;
4820                         break;
4821                 }
4822         }
4823
4824         if (HAS_PCH_IBX(dev)) {
4825                 has_ck505 = dev_priv->display_clock_mode;
4826                 can_ssc = has_ck505;
4827         } else {
4828                 has_ck505 = false;
4829                 can_ssc = true;
4830         }
4831
4832         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4833                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4834                       has_ck505);
4835
4836         /* Ironlake: try to setup display ref clock before DPLL
4837          * enabling. This is only under driver's control after
4838          * PCH B stepping, previous chipset stepping should be
4839          * ignoring this setting.
4840          */
4841         temp = I915_READ(PCH_DREF_CONTROL);
4842         /* Always enable nonspread source */
4843         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4844
4845         if (has_ck505)
4846                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4847         else
4848                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4849
4850         if (has_panel) {
4851                 temp &= ~DREF_SSC_SOURCE_MASK;
4852                 temp |= DREF_SSC_SOURCE_ENABLE;
4853
4854                 /* SSC must be turned on before enabling the CPU output  */
4855                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4856                         DRM_DEBUG_KMS("Using SSC on panel\n");
4857                         temp |= DREF_SSC1_ENABLE;
4858                 } else
4859                         temp &= ~DREF_SSC1_ENABLE;
4860
4861                 /* Get SSC going before enabling the outputs */
4862                 I915_WRITE(PCH_DREF_CONTROL, temp);
4863                 POSTING_READ(PCH_DREF_CONTROL);
4864                 udelay(200);
4865
4866                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4867
4868                 /* Enable CPU source on CPU attached eDP */
4869                 if (has_cpu_edp) {
4870                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4871                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4872                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4873                         }
4874                         else
4875                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4876                 } else
4877                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4878
4879                 I915_WRITE(PCH_DREF_CONTROL, temp);
4880                 POSTING_READ(PCH_DREF_CONTROL);
4881                 udelay(200);
4882         } else {
4883                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4884
4885                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4886
4887                 /* Turn off CPU output */
4888                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4889
4890                 I915_WRITE(PCH_DREF_CONTROL, temp);
4891                 POSTING_READ(PCH_DREF_CONTROL);
4892                 udelay(200);
4893
4894                 /* Turn off the SSC source */
4895                 temp &= ~DREF_SSC_SOURCE_MASK;
4896                 temp |= DREF_SSC_SOURCE_DISABLE;
4897
4898                 /* Turn off SSC1 */
4899                 temp &= ~ DREF_SSC1_ENABLE;
4900
4901                 I915_WRITE(PCH_DREF_CONTROL, temp);
4902                 POSTING_READ(PCH_DREF_CONTROL);
4903                 udelay(200);
4904         }
4905 }
4906
4907 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4908 static void lpt_init_pch_refclk(struct drm_device *dev)
4909 {
4910         struct drm_i915_private *dev_priv = dev->dev_private;
4911         struct drm_mode_config *mode_config = &dev->mode_config;
4912         struct intel_encoder *encoder;
4913         bool has_vga = false;
4914         bool is_sdv = false;
4915         u32 tmp;
4916
4917         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4918                 switch (encoder->type) {
4919                 case INTEL_OUTPUT_ANALOG:
4920                         has_vga = true;
4921                         break;
4922                 }
4923         }
4924
4925         if (!has_vga)
4926                 return;
4927
4928         mutex_lock(&dev_priv->dpio_lock);
4929
4930         /* XXX: Rip out SDV support once Haswell ships for real. */
4931         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4932                 is_sdv = true;
4933
4934         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4935         tmp &= ~SBI_SSCCTL_DISABLE;
4936         tmp |= SBI_SSCCTL_PATHALT;
4937         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4938
4939         udelay(24);
4940
4941         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4942         tmp &= ~SBI_SSCCTL_PATHALT;
4943         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4944
4945         if (!is_sdv) {
4946                 tmp = I915_READ(SOUTH_CHICKEN2);
4947                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4948                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4949
4950                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4951                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4952                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4953
4954                 tmp = I915_READ(SOUTH_CHICKEN2);
4955                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4956                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4957
4958                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4959                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4960                                        100))
4961                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4962         }
4963
4964         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4965         tmp &= ~(0xFF << 24);
4966         tmp |= (0x12 << 24);
4967         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4968
4969         if (!is_sdv) {
4970                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4971                 tmp &= ~(0x3 << 6);
4972                 tmp |= (1 << 6) | (1 << 0);
4973                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4974         }
4975
4976         if (is_sdv) {
4977                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4978                 tmp |= 0x7FFF;
4979                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4980         }
4981
4982         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4983         tmp |= (1 << 11);
4984         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4985
4986         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4987         tmp |= (1 << 11);
4988         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4989
4990         if (is_sdv) {
4991                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4992                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4993                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4994
4995                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4996                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4997                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4998
4999                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5000                 tmp |= (0x3F << 8);
5001                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5002
5003                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5004                 tmp |= (0x3F << 8);
5005                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5006         }
5007
5008         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5009         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5010         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5011
5012         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5013         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5014         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5015
5016         if (!is_sdv) {
5017                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5018                 tmp &= ~(7 << 13);
5019                 tmp |= (5 << 13);
5020                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5021
5022                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5023                 tmp &= ~(7 << 13);
5024                 tmp |= (5 << 13);
5025                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5026         }
5027
5028         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5029         tmp &= ~0xFF;
5030         tmp |= 0x1C;
5031         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5032
5033         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5034         tmp &= ~0xFF;
5035         tmp |= 0x1C;
5036         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5037
5038         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5039         tmp &= ~(0xFF << 16);
5040         tmp |= (0x1C << 16);
5041         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5042
5043         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5044         tmp &= ~(0xFF << 16);
5045         tmp |= (0x1C << 16);
5046         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5047
5048         if (!is_sdv) {
5049                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5050                 tmp |= (1 << 27);
5051                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5052
5053                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5054                 tmp |= (1 << 27);
5055                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5056
5057                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5058                 tmp &= ~(0xF << 28);
5059                 tmp |= (4 << 28);
5060                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5061
5062                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5063                 tmp &= ~(0xF << 28);
5064                 tmp |= (4 << 28);
5065                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5066         }
5067
5068         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5069         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5070         tmp |= SBI_DBUFF0_ENABLE;
5071         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5072
5073         mutex_unlock(&dev_priv->dpio_lock);
5074 }
5075
5076 /*
5077  * Initialize reference clocks when the driver loads
5078  */
5079 void intel_init_pch_refclk(struct drm_device *dev)
5080 {
5081         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5082                 ironlake_init_pch_refclk(dev);
5083         else if (HAS_PCH_LPT(dev))
5084                 lpt_init_pch_refclk(dev);
5085 }
5086
5087 static int ironlake_get_refclk(struct drm_crtc *crtc)
5088 {
5089         struct drm_device *dev = crtc->dev;
5090         struct drm_i915_private *dev_priv = dev->dev_private;
5091         struct intel_encoder *encoder;
5092         struct intel_encoder *edp_encoder = NULL;
5093         int num_connectors = 0;
5094         bool is_lvds = false;
5095
5096         for_each_encoder_on_crtc(dev, crtc, encoder) {
5097                 switch (encoder->type) {
5098                 case INTEL_OUTPUT_LVDS:
5099                         is_lvds = true;
5100                         break;
5101                 case INTEL_OUTPUT_EDP:
5102                         edp_encoder = encoder;
5103                         break;
5104                 }
5105                 num_connectors++;
5106         }
5107
5108         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5109                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5110                               dev_priv->lvds_ssc_freq);
5111                 return dev_priv->lvds_ssc_freq * 1000;
5112         }
5113
5114         return 120000;
5115 }
5116
5117 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5118                                   struct drm_display_mode *adjusted_mode,
5119                                   bool dither)
5120 {
5121         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5123         int pipe = intel_crtc->pipe;
5124         uint32_t val;
5125
5126         val = I915_READ(PIPECONF(pipe));
5127
5128         val &= ~PIPECONF_BPC_MASK;
5129         switch (intel_crtc->bpp) {
5130         case 18:
5131                 val |= PIPECONF_6BPC;
5132                 break;
5133         case 24:
5134                 val |= PIPECONF_8BPC;
5135                 break;
5136         case 30:
5137                 val |= PIPECONF_10BPC;
5138                 break;
5139         case 36:
5140                 val |= PIPECONF_12BPC;
5141                 break;
5142         default:
5143                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5144                 BUG();
5145         }
5146
5147         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5148         if (dither)
5149                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5150
5151         val &= ~PIPECONF_INTERLACE_MASK;
5152         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5153                 val |= PIPECONF_INTERLACED_ILK;
5154         else
5155                 val |= PIPECONF_PROGRESSIVE;
5156
5157         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5158                 val |= PIPECONF_COLOR_RANGE_SELECT;
5159         else
5160                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5161
5162         I915_WRITE(PIPECONF(pipe), val);
5163         POSTING_READ(PIPECONF(pipe));
5164 }
5165
5166 /*
5167  * Set up the pipe CSC unit.
5168  *
5169  * Currently only full range RGB to limited range RGB conversion
5170  * is supported, but eventually this should handle various
5171  * RGB<->YCbCr scenarios as well.
5172  */
5173 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5174                                const struct drm_display_mode *adjusted_mode)
5175 {
5176         struct drm_device *dev = crtc->dev;
5177         struct drm_i915_private *dev_priv = dev->dev_private;
5178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5179         int pipe = intel_crtc->pipe;
5180         uint16_t coeff = 0x7800; /* 1.0 */
5181
5182         /*
5183          * TODO: Check what kind of values actually come out of the pipe
5184          * with these coeff/postoff values and adjust to get the best
5185          * accuracy. Perhaps we even need to take the bpc value into
5186          * consideration.
5187          */
5188
5189         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5190                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5191
5192         /*
5193          * GY/GU and RY/RU should be the other way around according
5194          * to BSpec, but reality doesn't agree. Just set them up in
5195          * a way that results in the correct picture.
5196          */
5197         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5198         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5199
5200         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5201         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5202
5203         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5204         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5205
5206         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5207         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5208         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5209
5210         if (INTEL_INFO(dev)->gen > 6) {
5211                 uint16_t postoff = 0;
5212
5213                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5214                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5215
5216                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5217                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5218                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5219
5220                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5221         } else {
5222                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5223
5224                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5225                         mode |= CSC_BLACK_SCREEN_OFFSET;
5226
5227                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5228         }
5229 }
5230
5231 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5232                                  struct drm_display_mode *adjusted_mode,
5233                                  bool dither)
5234 {
5235         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5238         uint32_t val;
5239
5240         val = I915_READ(PIPECONF(cpu_transcoder));
5241
5242         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5243         if (dither)
5244                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5245
5246         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5247         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5248                 val |= PIPECONF_INTERLACED_ILK;
5249         else
5250                 val |= PIPECONF_PROGRESSIVE;
5251
5252         I915_WRITE(PIPECONF(cpu_transcoder), val);
5253         POSTING_READ(PIPECONF(cpu_transcoder));
5254 }
5255
5256 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5257                                     struct drm_display_mode *adjusted_mode,
5258                                     intel_clock_t *clock,
5259                                     bool *has_reduced_clock,
5260                                     intel_clock_t *reduced_clock)
5261 {
5262         struct drm_device *dev = crtc->dev;
5263         struct drm_i915_private *dev_priv = dev->dev_private;
5264         struct intel_encoder *intel_encoder;
5265         int refclk;
5266         const intel_limit_t *limit;
5267         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5268
5269         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5270                 switch (intel_encoder->type) {
5271                 case INTEL_OUTPUT_LVDS:
5272                         is_lvds = true;
5273                         break;
5274                 case INTEL_OUTPUT_SDVO:
5275                 case INTEL_OUTPUT_HDMI:
5276                         is_sdvo = true;
5277                         if (intel_encoder->needs_tv_clock)
5278                                 is_tv = true;
5279                         break;
5280                 case INTEL_OUTPUT_TVOUT:
5281                         is_tv = true;
5282                         break;
5283                 }
5284         }
5285
5286         refclk = ironlake_get_refclk(crtc);
5287
5288         /*
5289          * Returns a set of divisors for the desired target clock with the given
5290          * refclk, or FALSE.  The returned values represent the clock equation:
5291          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5292          */
5293         limit = intel_limit(crtc, refclk);
5294         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5295                               clock);
5296         if (!ret)
5297                 return false;
5298
5299         if (is_lvds && dev_priv->lvds_downclock_avail) {
5300                 /*
5301                  * Ensure we match the reduced clock's P to the target clock.
5302                  * If the clocks don't match, we can't switch the display clock
5303                  * by using the FP0/FP1. In such case we will disable the LVDS
5304                  * downclock feature.
5305                 */
5306                 *has_reduced_clock = limit->find_pll(limit, crtc,
5307                                                      dev_priv->lvds_downclock,
5308                                                      refclk,
5309                                                      clock,
5310                                                      reduced_clock);
5311         }
5312
5313         if (is_sdvo && is_tv)
5314                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5315
5316         return true;
5317 }
5318
5319 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5320 {
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322         uint32_t temp;
5323
5324         temp = I915_READ(SOUTH_CHICKEN1);
5325         if (temp & FDI_BC_BIFURCATION_SELECT)
5326                 return;
5327
5328         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5329         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5330
5331         temp |= FDI_BC_BIFURCATION_SELECT;
5332         DRM_DEBUG_KMS("enabling fdi C rx\n");
5333         I915_WRITE(SOUTH_CHICKEN1, temp);
5334         POSTING_READ(SOUTH_CHICKEN1);
5335 }
5336
5337 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5338 {
5339         struct drm_device *dev = intel_crtc->base.dev;
5340         struct drm_i915_private *dev_priv = dev->dev_private;
5341         struct intel_crtc *pipe_B_crtc =
5342                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5343
5344         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5345                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5346         if (intel_crtc->fdi_lanes > 4) {
5347                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5348                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5349                 /* Clamp lanes to avoid programming the hw with bogus values. */
5350                 intel_crtc->fdi_lanes = 4;
5351
5352                 return false;
5353         }
5354
5355         if (dev_priv->num_pipe == 2)
5356                 return true;
5357
5358         switch (intel_crtc->pipe) {
5359         case PIPE_A:
5360                 return true;
5361         case PIPE_B:
5362                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5363                     intel_crtc->fdi_lanes > 2) {
5364                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5365                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5366                         /* Clamp lanes to avoid programming the hw with bogus values. */
5367                         intel_crtc->fdi_lanes = 2;
5368
5369                         return false;
5370                 }
5371
5372                 if (intel_crtc->fdi_lanes > 2)
5373                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5374                 else
5375                         cpt_enable_fdi_bc_bifurcation(dev);
5376
5377                 return true;
5378         case PIPE_C:
5379                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5380                         if (intel_crtc->fdi_lanes > 2) {
5381                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5382                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5383                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5384                                 intel_crtc->fdi_lanes = 2;
5385
5386                                 return false;
5387                         }
5388                 } else {
5389                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5390                         return false;
5391                 }
5392
5393                 cpt_enable_fdi_bc_bifurcation(dev);
5394
5395                 return true;
5396         default:
5397                 BUG();
5398         }
5399 }
5400
5401 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5402 {
5403         /*
5404          * Account for spread spectrum to avoid
5405          * oversubscribing the link. Max center spread
5406          * is 2.5%; use 5% for safety's sake.
5407          */
5408         u32 bps = target_clock * bpp * 21 / 20;
5409         return bps / (link_bw * 8) + 1;
5410 }
5411
5412 static void ironlake_set_m_n(struct drm_crtc *crtc,
5413                              struct drm_display_mode *mode,
5414                              struct drm_display_mode *adjusted_mode)
5415 {
5416         struct drm_device *dev = crtc->dev;
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5420         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5421         struct intel_link_m_n m_n = {0};
5422         int target_clock, pixel_multiplier, lane, link_bw;
5423         bool is_dp = false, is_cpu_edp = false;
5424
5425         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5426                 switch (intel_encoder->type) {
5427                 case INTEL_OUTPUT_DISPLAYPORT:
5428                         is_dp = true;
5429                         break;
5430                 case INTEL_OUTPUT_EDP:
5431                         is_dp = true;
5432                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5433                                 is_cpu_edp = true;
5434                         edp_encoder = intel_encoder;
5435                         break;
5436                 }
5437         }
5438
5439         /* FDI link */
5440         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5441         lane = 0;
5442         /* CPU eDP doesn't require FDI link, so just set DP M/N
5443            according to current link config */
5444         if (is_cpu_edp) {
5445                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5446         } else {
5447                 /* FDI is a binary signal running at ~2.7GHz, encoding
5448                  * each output octet as 10 bits. The actual frequency
5449                  * is stored as a divider into a 100MHz clock, and the
5450                  * mode pixel clock is stored in units of 1KHz.
5451                  * Hence the bw of each lane in terms of the mode signal
5452                  * is:
5453                  */
5454                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5455         }
5456
5457         /* [e]DP over FDI requires target mode clock instead of link clock. */
5458         if (edp_encoder)
5459                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5460         else if (is_dp)
5461                 target_clock = mode->clock;
5462         else
5463                 target_clock = adjusted_mode->clock;
5464
5465         if (!lane)
5466                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5467                                                    intel_crtc->bpp);
5468
5469         intel_crtc->fdi_lanes = lane;
5470
5471         if (pixel_multiplier > 1)
5472                 link_bw *= pixel_multiplier;
5473         intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5474
5475         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5476         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5477         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5478         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5479 }
5480
5481 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5482                                       struct drm_display_mode *adjusted_mode,
5483                                       intel_clock_t *clock, u32 fp)
5484 {
5485         struct drm_crtc *crtc = &intel_crtc->base;
5486         struct drm_device *dev = crtc->dev;
5487         struct drm_i915_private *dev_priv = dev->dev_private;
5488         struct intel_encoder *intel_encoder;
5489         uint32_t dpll;
5490         int factor, pixel_multiplier, num_connectors = 0;
5491         bool is_lvds = false, is_sdvo = false, is_tv = false;
5492         bool is_dp = false, is_cpu_edp = false;
5493
5494         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5495                 switch (intel_encoder->type) {
5496                 case INTEL_OUTPUT_LVDS:
5497                         is_lvds = true;
5498                         break;
5499                 case INTEL_OUTPUT_SDVO:
5500                 case INTEL_OUTPUT_HDMI:
5501                         is_sdvo = true;
5502                         if (intel_encoder->needs_tv_clock)
5503                                 is_tv = true;
5504                         break;
5505                 case INTEL_OUTPUT_TVOUT:
5506                         is_tv = true;
5507                         break;
5508                 case INTEL_OUTPUT_DISPLAYPORT:
5509                         is_dp = true;
5510                         break;
5511                 case INTEL_OUTPUT_EDP:
5512                         is_dp = true;
5513                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5514                                 is_cpu_edp = true;
5515                         break;
5516                 }
5517
5518                 num_connectors++;
5519         }
5520
5521         /* Enable autotuning of the PLL clock (if permissible) */
5522         factor = 21;
5523         if (is_lvds) {
5524                 if ((intel_panel_use_ssc(dev_priv) &&
5525                      dev_priv->lvds_ssc_freq == 100) ||
5526                     intel_is_dual_link_lvds(dev))
5527                         factor = 25;
5528         } else if (is_sdvo && is_tv)
5529                 factor = 20;
5530
5531         if (clock->m < factor * clock->n)
5532                 fp |= FP_CB_TUNE;
5533
5534         dpll = 0;
5535
5536         if (is_lvds)
5537                 dpll |= DPLLB_MODE_LVDS;
5538         else
5539                 dpll |= DPLLB_MODE_DAC_SERIAL;
5540         if (is_sdvo) {
5541                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5542                 if (pixel_multiplier > 1) {
5543                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5544                 }
5545                 dpll |= DPLL_DVO_HIGH_SPEED;
5546         }
5547         if (is_dp && !is_cpu_edp)
5548                 dpll |= DPLL_DVO_HIGH_SPEED;
5549
5550         /* compute bitmask from p1 value */
5551         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5552         /* also FPA1 */
5553         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5554
5555         switch (clock->p2) {
5556         case 5:
5557                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5558                 break;
5559         case 7:
5560                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5561                 break;
5562         case 10:
5563                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5564                 break;
5565         case 14:
5566                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5567                 break;
5568         }
5569
5570         if (is_sdvo && is_tv)
5571                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5572         else if (is_tv)
5573                 /* XXX: just matching BIOS for now */
5574                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5575                 dpll |= 3;
5576         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5577                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5578         else
5579                 dpll |= PLL_REF_INPUT_DREFCLK;
5580
5581         return dpll;
5582 }
5583
5584 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5585                                   struct drm_display_mode *mode,
5586                                   struct drm_display_mode *adjusted_mode,
5587                                   int x, int y,
5588                                   struct drm_framebuffer *fb)
5589 {
5590         struct drm_device *dev = crtc->dev;
5591         struct drm_i915_private *dev_priv = dev->dev_private;
5592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593         int pipe = intel_crtc->pipe;
5594         int plane = intel_crtc->plane;
5595         int num_connectors = 0;
5596         intel_clock_t clock, reduced_clock;
5597         u32 dpll, fp = 0, fp2 = 0;
5598         bool ok, has_reduced_clock = false;
5599         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5600         struct intel_encoder *encoder;
5601         int ret;
5602         bool dither, fdi_config_ok;
5603
5604         for_each_encoder_on_crtc(dev, crtc, encoder) {
5605                 switch (encoder->type) {
5606                 case INTEL_OUTPUT_LVDS:
5607                         is_lvds = true;
5608                         break;
5609                 case INTEL_OUTPUT_DISPLAYPORT:
5610                         is_dp = true;
5611                         break;
5612                 case INTEL_OUTPUT_EDP:
5613                         is_dp = true;
5614                         if (!intel_encoder_is_pch_edp(&encoder->base))
5615                                 is_cpu_edp = true;
5616                         break;
5617                 }
5618
5619                 num_connectors++;
5620         }
5621
5622         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5623              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5624
5625         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5626                                      &has_reduced_clock, &reduced_clock);
5627         if (!ok) {
5628                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5629                 return -EINVAL;
5630         }
5631
5632         /* Ensure that the cursor is valid for the new mode before changing... */
5633         intel_crtc_update_cursor(crtc, true);
5634
5635         /* determine panel color depth */
5636         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5637                                               adjusted_mode);
5638         if (is_lvds && dev_priv->lvds_dither)
5639                 dither = true;
5640
5641         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5642         if (has_reduced_clock)
5643                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5644                         reduced_clock.m2;
5645
5646         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5647
5648         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5649         drm_mode_debug_printmodeline(mode);
5650
5651         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5652         if (!is_cpu_edp) {
5653                 struct intel_pch_pll *pll;
5654
5655                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5656                 if (pll == NULL) {
5657                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5658                                          pipe);
5659                         return -EINVAL;
5660                 }
5661         } else
5662                 intel_put_pch_pll(intel_crtc);
5663
5664         if (is_dp && !is_cpu_edp)
5665                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5666
5667         for_each_encoder_on_crtc(dev, crtc, encoder)
5668                 if (encoder->pre_pll_enable)
5669                         encoder->pre_pll_enable(encoder);
5670
5671         if (intel_crtc->pch_pll) {
5672                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5673
5674                 /* Wait for the clocks to stabilize. */
5675                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5676                 udelay(150);
5677
5678                 /* The pixel multiplier can only be updated once the
5679                  * DPLL is enabled and the clocks are stable.
5680                  *
5681                  * So write it again.
5682                  */
5683                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5684         }
5685
5686         intel_crtc->lowfreq_avail = false;
5687         if (intel_crtc->pch_pll) {
5688                 if (is_lvds && has_reduced_clock && i915_powersave) {
5689                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5690                         intel_crtc->lowfreq_avail = true;
5691                 } else {
5692                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5693                 }
5694         }
5695
5696         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5697
5698         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5699          * ironlake_check_fdi_lanes. */
5700         ironlake_set_m_n(crtc, mode, adjusted_mode);
5701
5702         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5703
5704         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5705
5706         intel_wait_for_vblank(dev, pipe);
5707
5708         /* Set up the display plane register */
5709         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5710         POSTING_READ(DSPCNTR(plane));
5711
5712         ret = intel_pipe_set_base(crtc, x, y, fb);
5713
5714         intel_update_watermarks(dev);
5715
5716         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5717
5718         return fdi_config_ok ? ret : -EINVAL;
5719 }
5720
5721 static void haswell_modeset_global_resources(struct drm_device *dev)
5722 {
5723         struct drm_i915_private *dev_priv = dev->dev_private;
5724         bool enable = false;
5725         struct intel_crtc *crtc;
5726         struct intel_encoder *encoder;
5727
5728         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5729                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5730                         enable = true;
5731                 /* XXX: Should check for edp transcoder here, but thanks to init
5732                  * sequence that's not yet available. Just in case desktop eDP
5733                  * on PORT D is possible on haswell, too. */
5734         }
5735
5736         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5737                             base.head) {
5738                 if (encoder->type != INTEL_OUTPUT_EDP &&
5739                     encoder->connectors_active)
5740                         enable = true;
5741         }
5742
5743         /* Even the eDP panel fitter is outside the always-on well. */
5744         if (dev_priv->pch_pf_size)
5745                 enable = true;
5746
5747         intel_set_power_well(dev, enable);
5748 }
5749
5750 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5751                                  struct drm_display_mode *mode,
5752                                  struct drm_display_mode *adjusted_mode,
5753                                  int x, int y,
5754                                  struct drm_framebuffer *fb)
5755 {
5756         struct drm_device *dev = crtc->dev;
5757         struct drm_i915_private *dev_priv = dev->dev_private;
5758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5759         int pipe = intel_crtc->pipe;
5760         int plane = intel_crtc->plane;
5761         int num_connectors = 0;
5762         bool is_dp = false, is_cpu_edp = false;
5763         struct intel_encoder *encoder;
5764         int ret;
5765         bool dither;
5766
5767         for_each_encoder_on_crtc(dev, crtc, encoder) {
5768                 switch (encoder->type) {
5769                 case INTEL_OUTPUT_DISPLAYPORT:
5770                         is_dp = true;
5771                         break;
5772                 case INTEL_OUTPUT_EDP:
5773                         is_dp = true;
5774                         if (!intel_encoder_is_pch_edp(&encoder->base))
5775                                 is_cpu_edp = true;
5776                         break;
5777                 }
5778
5779                 num_connectors++;
5780         }
5781
5782         /* We are not sure yet this won't happen. */
5783         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5784              INTEL_PCH_TYPE(dev));
5785
5786         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5787              num_connectors, pipe_name(pipe));
5788
5789         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5790                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5791
5792         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5793
5794         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5795                 return -EINVAL;
5796
5797         /* Ensure that the cursor is valid for the new mode before changing... */
5798         intel_crtc_update_cursor(crtc, true);
5799
5800         /* determine panel color depth */
5801         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5802                                               adjusted_mode);
5803
5804         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5805         drm_mode_debug_printmodeline(mode);
5806
5807         if (is_dp && !is_cpu_edp)
5808                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5809
5810         intel_crtc->lowfreq_avail = false;
5811
5812         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5813
5814         if (!is_dp || is_cpu_edp)
5815                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5816
5817         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5818
5819         intel_set_pipe_csc(crtc, adjusted_mode);
5820
5821         /* Set up the display plane register */
5822         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5823         POSTING_READ(DSPCNTR(plane));
5824
5825         ret = intel_pipe_set_base(crtc, x, y, fb);
5826
5827         intel_update_watermarks(dev);
5828
5829         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5830
5831         return ret;
5832 }
5833
5834 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5835                                struct drm_display_mode *mode,
5836                                struct drm_display_mode *adjusted_mode,
5837                                int x, int y,
5838                                struct drm_framebuffer *fb)
5839 {
5840         struct drm_device *dev = crtc->dev;
5841         struct drm_i915_private *dev_priv = dev->dev_private;
5842         struct drm_encoder_helper_funcs *encoder_funcs;
5843         struct intel_encoder *encoder;
5844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5845         int pipe = intel_crtc->pipe;
5846         int ret;
5847
5848         if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5849                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5850         else
5851                 intel_crtc->cpu_transcoder = pipe;
5852
5853         drm_vblank_pre_modeset(dev, pipe);
5854
5855         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5856                                               x, y, fb);
5857         drm_vblank_post_modeset(dev, pipe);
5858
5859         if (ret != 0)
5860                 return ret;
5861
5862         for_each_encoder_on_crtc(dev, crtc, encoder) {
5863                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5864                         encoder->base.base.id,
5865                         drm_get_encoder_name(&encoder->base),
5866                         mode->base.id, mode->name);
5867                 encoder_funcs = encoder->base.helper_private;
5868                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5869         }
5870
5871         return 0;
5872 }
5873
5874 static bool intel_eld_uptodate(struct drm_connector *connector,
5875                                int reg_eldv, uint32_t bits_eldv,
5876                                int reg_elda, uint32_t bits_elda,
5877                                int reg_edid)
5878 {
5879         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5880         uint8_t *eld = connector->eld;
5881         uint32_t i;
5882
5883         i = I915_READ(reg_eldv);
5884         i &= bits_eldv;
5885
5886         if (!eld[0])
5887                 return !i;
5888
5889         if (!i)
5890                 return false;
5891
5892         i = I915_READ(reg_elda);
5893         i &= ~bits_elda;
5894         I915_WRITE(reg_elda, i);
5895
5896         for (i = 0; i < eld[2]; i++)
5897                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5898                         return false;
5899
5900         return true;
5901 }
5902
5903 static void g4x_write_eld(struct drm_connector *connector,
5904                           struct drm_crtc *crtc)
5905 {
5906         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5907         uint8_t *eld = connector->eld;
5908         uint32_t eldv;
5909         uint32_t len;
5910         uint32_t i;
5911
5912         i = I915_READ(G4X_AUD_VID_DID);
5913
5914         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5915                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5916         else
5917                 eldv = G4X_ELDV_DEVCTG;
5918
5919         if (intel_eld_uptodate(connector,
5920                                G4X_AUD_CNTL_ST, eldv,
5921                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5922                                G4X_HDMIW_HDMIEDID))
5923                 return;
5924
5925         i = I915_READ(G4X_AUD_CNTL_ST);
5926         i &= ~(eldv | G4X_ELD_ADDR);
5927         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5928         I915_WRITE(G4X_AUD_CNTL_ST, i);
5929
5930         if (!eld[0])
5931                 return;
5932
5933         len = min_t(uint8_t, eld[2], len);
5934         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5935         for (i = 0; i < len; i++)
5936                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5937
5938         i = I915_READ(G4X_AUD_CNTL_ST);
5939         i |= eldv;
5940         I915_WRITE(G4X_AUD_CNTL_ST, i);
5941 }
5942
5943 static void haswell_write_eld(struct drm_connector *connector,
5944                                      struct drm_crtc *crtc)
5945 {
5946         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5947         uint8_t *eld = connector->eld;
5948         struct drm_device *dev = crtc->dev;
5949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5950         uint32_t eldv;
5951         uint32_t i;
5952         int len;
5953         int pipe = to_intel_crtc(crtc)->pipe;
5954         int tmp;
5955
5956         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5957         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5958         int aud_config = HSW_AUD_CFG(pipe);
5959         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5960
5961
5962         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5963
5964         /* Audio output enable */
5965         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5966         tmp = I915_READ(aud_cntrl_st2);
5967         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5968         I915_WRITE(aud_cntrl_st2, tmp);
5969
5970         /* Wait for 1 vertical blank */
5971         intel_wait_for_vblank(dev, pipe);
5972
5973         /* Set ELD valid state */
5974         tmp = I915_READ(aud_cntrl_st2);
5975         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5976         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5977         I915_WRITE(aud_cntrl_st2, tmp);
5978         tmp = I915_READ(aud_cntrl_st2);
5979         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5980
5981         /* Enable HDMI mode */
5982         tmp = I915_READ(aud_config);
5983         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5984         /* clear N_programing_enable and N_value_index */
5985         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5986         I915_WRITE(aud_config, tmp);
5987
5988         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5989
5990         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5991         intel_crtc->eld_vld = true;
5992
5993         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5994                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5995                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5996                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5997         } else
5998                 I915_WRITE(aud_config, 0);
5999
6000         if (intel_eld_uptodate(connector,
6001                                aud_cntrl_st2, eldv,
6002                                aud_cntl_st, IBX_ELD_ADDRESS,
6003                                hdmiw_hdmiedid))
6004                 return;
6005
6006         i = I915_READ(aud_cntrl_st2);
6007         i &= ~eldv;
6008         I915_WRITE(aud_cntrl_st2, i);
6009
6010         if (!eld[0])
6011                 return;
6012
6013         i = I915_READ(aud_cntl_st);
6014         i &= ~IBX_ELD_ADDRESS;
6015         I915_WRITE(aud_cntl_st, i);
6016         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6017         DRM_DEBUG_DRIVER("port num:%d\n", i);
6018
6019         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6020         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6021         for (i = 0; i < len; i++)
6022                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6023
6024         i = I915_READ(aud_cntrl_st2);
6025         i |= eldv;
6026         I915_WRITE(aud_cntrl_st2, i);
6027
6028 }
6029
6030 static void ironlake_write_eld(struct drm_connector *connector,
6031                                      struct drm_crtc *crtc)
6032 {
6033         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6034         uint8_t *eld = connector->eld;
6035         uint32_t eldv;
6036         uint32_t i;
6037         int len;
6038         int hdmiw_hdmiedid;
6039         int aud_config;
6040         int aud_cntl_st;
6041         int aud_cntrl_st2;
6042         int pipe = to_intel_crtc(crtc)->pipe;
6043
6044         if (HAS_PCH_IBX(connector->dev)) {
6045                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6046                 aud_config = IBX_AUD_CFG(pipe);
6047                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6048                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6049         } else {
6050                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6051                 aud_config = CPT_AUD_CFG(pipe);
6052                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6053                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6054         }
6055
6056         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6057
6058         i = I915_READ(aud_cntl_st);
6059         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6060         if (!i) {
6061                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6062                 /* operate blindly on all ports */
6063                 eldv = IBX_ELD_VALIDB;
6064                 eldv |= IBX_ELD_VALIDB << 4;
6065                 eldv |= IBX_ELD_VALIDB << 8;
6066         } else {
6067                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6068                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6069         }
6070
6071         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6072                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6073                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6074                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6075         } else
6076                 I915_WRITE(aud_config, 0);
6077
6078         if (intel_eld_uptodate(connector,
6079                                aud_cntrl_st2, eldv,
6080                                aud_cntl_st, IBX_ELD_ADDRESS,
6081                                hdmiw_hdmiedid))
6082                 return;
6083
6084         i = I915_READ(aud_cntrl_st2);
6085         i &= ~eldv;
6086         I915_WRITE(aud_cntrl_st2, i);
6087
6088         if (!eld[0])
6089                 return;
6090
6091         i = I915_READ(aud_cntl_st);
6092         i &= ~IBX_ELD_ADDRESS;
6093         I915_WRITE(aud_cntl_st, i);
6094
6095         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6096         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6097         for (i = 0; i < len; i++)
6098                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6099
6100         i = I915_READ(aud_cntrl_st2);
6101         i |= eldv;
6102         I915_WRITE(aud_cntrl_st2, i);
6103 }
6104
6105 void intel_write_eld(struct drm_encoder *encoder,
6106                      struct drm_display_mode *mode)
6107 {
6108         struct drm_crtc *crtc = encoder->crtc;
6109         struct drm_connector *connector;
6110         struct drm_device *dev = encoder->dev;
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112
6113         connector = drm_select_eld(encoder, mode);
6114         if (!connector)
6115                 return;
6116
6117         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6118                          connector->base.id,
6119                          drm_get_connector_name(connector),
6120                          connector->encoder->base.id,
6121                          drm_get_encoder_name(connector->encoder));
6122
6123         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6124
6125         if (dev_priv->display.write_eld)
6126                 dev_priv->display.write_eld(connector, crtc);
6127 }
6128
6129 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6130 void intel_crtc_load_lut(struct drm_crtc *crtc)
6131 {
6132         struct drm_device *dev = crtc->dev;
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135         int palreg = PALETTE(intel_crtc->pipe);
6136         int i;
6137
6138         /* The clocks have to be on to load the palette. */
6139         if (!crtc->enabled || !intel_crtc->active)
6140                 return;
6141
6142         /* use legacy palette for Ironlake */
6143         if (HAS_PCH_SPLIT(dev))
6144                 palreg = LGC_PALETTE(intel_crtc->pipe);
6145
6146         for (i = 0; i < 256; i++) {
6147                 I915_WRITE(palreg + 4 * i,
6148                            (intel_crtc->lut_r[i] << 16) |
6149                            (intel_crtc->lut_g[i] << 8) |
6150                            intel_crtc->lut_b[i]);
6151         }
6152 }
6153
6154 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6155 {
6156         struct drm_device *dev = crtc->dev;
6157         struct drm_i915_private *dev_priv = dev->dev_private;
6158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159         bool visible = base != 0;
6160         u32 cntl;
6161
6162         if (intel_crtc->cursor_visible == visible)
6163                 return;
6164
6165         cntl = I915_READ(_CURACNTR);
6166         if (visible) {
6167                 /* On these chipsets we can only modify the base whilst
6168                  * the cursor is disabled.
6169                  */
6170                 I915_WRITE(_CURABASE, base);
6171
6172                 cntl &= ~(CURSOR_FORMAT_MASK);
6173                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6174                 cntl |= CURSOR_ENABLE |
6175                         CURSOR_GAMMA_ENABLE |
6176                         CURSOR_FORMAT_ARGB;
6177         } else
6178                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6179         I915_WRITE(_CURACNTR, cntl);
6180
6181         intel_crtc->cursor_visible = visible;
6182 }
6183
6184 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6185 {
6186         struct drm_device *dev = crtc->dev;
6187         struct drm_i915_private *dev_priv = dev->dev_private;
6188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6189         int pipe = intel_crtc->pipe;
6190         bool visible = base != 0;
6191
6192         if (intel_crtc->cursor_visible != visible) {
6193                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6194                 if (base) {
6195                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6196                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6197                         cntl |= pipe << 28; /* Connect to correct pipe */
6198                 } else {
6199                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6200                         cntl |= CURSOR_MODE_DISABLE;
6201                 }
6202                 I915_WRITE(CURCNTR(pipe), cntl);
6203
6204                 intel_crtc->cursor_visible = visible;
6205         }
6206         /* and commit changes on next vblank */
6207         I915_WRITE(CURBASE(pipe), base);
6208 }
6209
6210 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6211 {
6212         struct drm_device *dev = crtc->dev;
6213         struct drm_i915_private *dev_priv = dev->dev_private;
6214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6215         int pipe = intel_crtc->pipe;
6216         bool visible = base != 0;
6217
6218         if (intel_crtc->cursor_visible != visible) {
6219                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6220                 if (base) {
6221                         cntl &= ~CURSOR_MODE;
6222                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6223                 } else {
6224                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6225                         cntl |= CURSOR_MODE_DISABLE;
6226                 }
6227                 if (IS_HASWELL(dev))
6228                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6229                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6230
6231                 intel_crtc->cursor_visible = visible;
6232         }
6233         /* and commit changes on next vblank */
6234         I915_WRITE(CURBASE_IVB(pipe), base);
6235 }
6236
6237 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6238 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6239                                      bool on)
6240 {
6241         struct drm_device *dev = crtc->dev;
6242         struct drm_i915_private *dev_priv = dev->dev_private;
6243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6244         int pipe = intel_crtc->pipe;
6245         int x = intel_crtc->cursor_x;
6246         int y = intel_crtc->cursor_y;
6247         u32 base, pos;
6248         bool visible;
6249
6250         pos = 0;
6251
6252         if (on && crtc->enabled && crtc->fb) {
6253                 base = intel_crtc->cursor_addr;
6254                 if (x > (int) crtc->fb->width)
6255                         base = 0;
6256
6257                 if (y > (int) crtc->fb->height)
6258                         base = 0;
6259         } else
6260                 base = 0;
6261
6262         if (x < 0) {
6263                 if (x + intel_crtc->cursor_width < 0)
6264                         base = 0;
6265
6266                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6267                 x = -x;
6268         }
6269         pos |= x << CURSOR_X_SHIFT;
6270
6271         if (y < 0) {
6272                 if (y + intel_crtc->cursor_height < 0)
6273                         base = 0;
6274
6275                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6276                 y = -y;
6277         }
6278         pos |= y << CURSOR_Y_SHIFT;
6279
6280         visible = base != 0;
6281         if (!visible && !intel_crtc->cursor_visible)
6282                 return;
6283
6284         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6285                 I915_WRITE(CURPOS_IVB(pipe), pos);
6286                 ivb_update_cursor(crtc, base);
6287         } else {
6288                 I915_WRITE(CURPOS(pipe), pos);
6289                 if (IS_845G(dev) || IS_I865G(dev))
6290                         i845_update_cursor(crtc, base);
6291                 else
6292                         i9xx_update_cursor(crtc, base);
6293         }
6294 }
6295
6296 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6297                                  struct drm_file *file,
6298                                  uint32_t handle,
6299                                  uint32_t width, uint32_t height)
6300 {
6301         struct drm_device *dev = crtc->dev;
6302         struct drm_i915_private *dev_priv = dev->dev_private;
6303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304         struct drm_i915_gem_object *obj;
6305         uint32_t addr;
6306         int ret;
6307
6308         /* if we want to turn off the cursor ignore width and height */
6309         if (!handle) {
6310                 DRM_DEBUG_KMS("cursor off\n");
6311                 addr = 0;
6312                 obj = NULL;
6313                 mutex_lock(&dev->struct_mutex);
6314                 goto finish;
6315         }
6316
6317         /* Currently we only support 64x64 cursors */
6318         if (width != 64 || height != 64) {
6319                 DRM_ERROR("we currently only support 64x64 cursors\n");
6320                 return -EINVAL;
6321         }
6322
6323         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6324         if (&obj->base == NULL)
6325                 return -ENOENT;
6326
6327         if (obj->base.size < width * height * 4) {
6328                 DRM_ERROR("buffer is to small\n");
6329                 ret = -ENOMEM;
6330                 goto fail;
6331         }
6332
6333         /* we only need to pin inside GTT if cursor is non-phy */
6334         mutex_lock(&dev->struct_mutex);
6335         if (!dev_priv->info->cursor_needs_physical) {
6336                 if (obj->tiling_mode) {
6337                         DRM_ERROR("cursor cannot be tiled\n");
6338                         ret = -EINVAL;
6339                         goto fail_locked;
6340                 }
6341
6342                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6343                 if (ret) {
6344                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6345                         goto fail_locked;
6346                 }
6347
6348                 ret = i915_gem_object_put_fence(obj);
6349                 if (ret) {
6350                         DRM_ERROR("failed to release fence for cursor");
6351                         goto fail_unpin;
6352                 }
6353
6354                 addr = obj->gtt_offset;
6355         } else {
6356                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6357                 ret = i915_gem_attach_phys_object(dev, obj,
6358                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6359                                                   align);
6360                 if (ret) {
6361                         DRM_ERROR("failed to attach phys object\n");
6362                         goto fail_locked;
6363                 }
6364                 addr = obj->phys_obj->handle->busaddr;
6365         }
6366
6367         if (IS_GEN2(dev))
6368                 I915_WRITE(CURSIZE, (height << 12) | width);
6369
6370  finish:
6371         if (intel_crtc->cursor_bo) {
6372                 if (dev_priv->info->cursor_needs_physical) {
6373                         if (intel_crtc->cursor_bo != obj)
6374                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6375                 } else
6376                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6377                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6378         }
6379
6380         mutex_unlock(&dev->struct_mutex);
6381
6382         intel_crtc->cursor_addr = addr;
6383         intel_crtc->cursor_bo = obj;
6384         intel_crtc->cursor_width = width;
6385         intel_crtc->cursor_height = height;
6386
6387         intel_crtc_update_cursor(crtc, true);
6388
6389         return 0;
6390 fail_unpin:
6391         i915_gem_object_unpin(obj);
6392 fail_locked:
6393         mutex_unlock(&dev->struct_mutex);
6394 fail:
6395         drm_gem_object_unreference_unlocked(&obj->base);
6396         return ret;
6397 }
6398
6399 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6400 {
6401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402
6403         intel_crtc->cursor_x = x;
6404         intel_crtc->cursor_y = y;
6405
6406         intel_crtc_update_cursor(crtc, true);
6407
6408         return 0;
6409 }
6410
6411 /** Sets the color ramps on behalf of RandR */
6412 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6413                                  u16 blue, int regno)
6414 {
6415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416
6417         intel_crtc->lut_r[regno] = red >> 8;
6418         intel_crtc->lut_g[regno] = green >> 8;
6419         intel_crtc->lut_b[regno] = blue >> 8;
6420 }
6421
6422 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6423                              u16 *blue, int regno)
6424 {
6425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6426
6427         *red = intel_crtc->lut_r[regno] << 8;
6428         *green = intel_crtc->lut_g[regno] << 8;
6429         *blue = intel_crtc->lut_b[regno] << 8;
6430 }
6431
6432 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6433                                  u16 *blue, uint32_t start, uint32_t size)
6434 {
6435         int end = (start + size > 256) ? 256 : start + size, i;
6436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437
6438         for (i = start; i < end; i++) {
6439                 intel_crtc->lut_r[i] = red[i] >> 8;
6440                 intel_crtc->lut_g[i] = green[i] >> 8;
6441                 intel_crtc->lut_b[i] = blue[i] >> 8;
6442         }
6443
6444         intel_crtc_load_lut(crtc);
6445 }
6446
6447 /**
6448  * Get a pipe with a simple mode set on it for doing load-based monitor
6449  * detection.
6450  *
6451  * It will be up to the load-detect code to adjust the pipe as appropriate for
6452  * its requirements.  The pipe will be connected to no other encoders.
6453  *
6454  * Currently this code will only succeed if there is a pipe with no encoders
6455  * configured for it.  In the future, it could choose to temporarily disable
6456  * some outputs to free up a pipe for its use.
6457  *
6458  * \return crtc, or NULL if no pipes are available.
6459  */
6460
6461 /* VESA 640x480x72Hz mode to set on the pipe */
6462 static struct drm_display_mode load_detect_mode = {
6463         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6464                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6465 };
6466
6467 static struct drm_framebuffer *
6468 intel_framebuffer_create(struct drm_device *dev,
6469                          struct drm_mode_fb_cmd2 *mode_cmd,
6470                          struct drm_i915_gem_object *obj)
6471 {
6472         struct intel_framebuffer *intel_fb;
6473         int ret;
6474
6475         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6476         if (!intel_fb) {
6477                 drm_gem_object_unreference_unlocked(&obj->base);
6478                 return ERR_PTR(-ENOMEM);
6479         }
6480
6481         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6482         if (ret) {
6483                 drm_gem_object_unreference_unlocked(&obj->base);
6484                 kfree(intel_fb);
6485                 return ERR_PTR(ret);
6486         }
6487
6488         return &intel_fb->base;
6489 }
6490
6491 static u32
6492 intel_framebuffer_pitch_for_width(int width, int bpp)
6493 {
6494         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6495         return ALIGN(pitch, 64);
6496 }
6497
6498 static u32
6499 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6500 {
6501         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6502         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6503 }
6504
6505 static struct drm_framebuffer *
6506 intel_framebuffer_create_for_mode(struct drm_device *dev,
6507                                   struct drm_display_mode *mode,
6508                                   int depth, int bpp)
6509 {
6510         struct drm_i915_gem_object *obj;
6511         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6512
6513         obj = i915_gem_alloc_object(dev,
6514                                     intel_framebuffer_size_for_mode(mode, bpp));
6515         if (obj == NULL)
6516                 return ERR_PTR(-ENOMEM);
6517
6518         mode_cmd.width = mode->hdisplay;
6519         mode_cmd.height = mode->vdisplay;
6520         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6521                                                                 bpp);
6522         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6523
6524         return intel_framebuffer_create(dev, &mode_cmd, obj);
6525 }
6526
6527 static struct drm_framebuffer *
6528 mode_fits_in_fbdev(struct drm_device *dev,
6529                    struct drm_display_mode *mode)
6530 {
6531         struct drm_i915_private *dev_priv = dev->dev_private;
6532         struct drm_i915_gem_object *obj;
6533         struct drm_framebuffer *fb;
6534
6535         if (dev_priv->fbdev == NULL)
6536                 return NULL;
6537
6538         obj = dev_priv->fbdev->ifb.obj;
6539         if (obj == NULL)
6540                 return NULL;
6541
6542         fb = &dev_priv->fbdev->ifb.base;
6543         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6544                                                                fb->bits_per_pixel))
6545                 return NULL;
6546
6547         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6548                 return NULL;
6549
6550         return fb;
6551 }
6552
6553 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6554                                 struct drm_display_mode *mode,
6555                                 struct intel_load_detect_pipe *old)
6556 {
6557         struct intel_crtc *intel_crtc;
6558         struct intel_encoder *intel_encoder =
6559                 intel_attached_encoder(connector);
6560         struct drm_crtc *possible_crtc;
6561         struct drm_encoder *encoder = &intel_encoder->base;
6562         struct drm_crtc *crtc = NULL;
6563         struct drm_device *dev = encoder->dev;
6564         struct drm_framebuffer *fb;
6565         int i = -1;
6566
6567         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6568                       connector->base.id, drm_get_connector_name(connector),
6569                       encoder->base.id, drm_get_encoder_name(encoder));
6570
6571         /*
6572          * Algorithm gets a little messy:
6573          *
6574          *   - if the connector already has an assigned crtc, use it (but make
6575          *     sure it's on first)
6576          *
6577          *   - try to find the first unused crtc that can drive this connector,
6578          *     and use that if we find one
6579          */
6580
6581         /* See if we already have a CRTC for this connector */
6582         if (encoder->crtc) {
6583                 crtc = encoder->crtc;
6584
6585                 mutex_lock(&crtc->mutex);
6586
6587                 old->dpms_mode = connector->dpms;
6588                 old->load_detect_temp = false;
6589
6590                 /* Make sure the crtc and connector are running */
6591                 if (connector->dpms != DRM_MODE_DPMS_ON)
6592                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6593
6594                 return true;
6595         }
6596
6597         /* Find an unused one (if possible) */
6598         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6599                 i++;
6600                 if (!(encoder->possible_crtcs & (1 << i)))
6601                         continue;
6602                 if (!possible_crtc->enabled) {
6603                         crtc = possible_crtc;
6604                         break;
6605                 }
6606         }
6607
6608         /*
6609          * If we didn't find an unused CRTC, don't use any.
6610          */
6611         if (!crtc) {
6612                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6613                 return false;
6614         }
6615
6616         mutex_lock(&crtc->mutex);
6617         intel_encoder->new_crtc = to_intel_crtc(crtc);
6618         to_intel_connector(connector)->new_encoder = intel_encoder;
6619
6620         intel_crtc = to_intel_crtc(crtc);
6621         old->dpms_mode = connector->dpms;
6622         old->load_detect_temp = true;
6623         old->release_fb = NULL;
6624
6625         if (!mode)
6626                 mode = &load_detect_mode;
6627
6628         /* We need a framebuffer large enough to accommodate all accesses
6629          * that the plane may generate whilst we perform load detection.
6630          * We can not rely on the fbcon either being present (we get called
6631          * during its initialisation to detect all boot displays, or it may
6632          * not even exist) or that it is large enough to satisfy the
6633          * requested mode.
6634          */
6635         fb = mode_fits_in_fbdev(dev, mode);
6636         if (fb == NULL) {
6637                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6638                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6639                 old->release_fb = fb;
6640         } else
6641                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6642         if (IS_ERR(fb)) {
6643                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6644                 mutex_unlock(&crtc->mutex);
6645                 return false;
6646         }
6647
6648         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6649                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6650                 if (old->release_fb)
6651                         old->release_fb->funcs->destroy(old->release_fb);
6652                 mutex_unlock(&crtc->mutex);
6653                 return false;
6654         }
6655
6656         /* let the connector get through one full cycle before testing */
6657         intel_wait_for_vblank(dev, intel_crtc->pipe);
6658         return true;
6659 }
6660
6661 void intel_release_load_detect_pipe(struct drm_connector *connector,
6662                                     struct intel_load_detect_pipe *old)
6663 {
6664         struct intel_encoder *intel_encoder =
6665                 intel_attached_encoder(connector);
6666         struct drm_encoder *encoder = &intel_encoder->base;
6667         struct drm_crtc *crtc = encoder->crtc;
6668
6669         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6670                       connector->base.id, drm_get_connector_name(connector),
6671                       encoder->base.id, drm_get_encoder_name(encoder));
6672
6673         if (old->load_detect_temp) {
6674                 to_intel_connector(connector)->new_encoder = NULL;
6675                 intel_encoder->new_crtc = NULL;
6676                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6677
6678                 if (old->release_fb) {
6679                         drm_framebuffer_unregister_private(old->release_fb);
6680                         drm_framebuffer_unreference(old->release_fb);
6681                 }
6682
6683                 mutex_unlock(&crtc->mutex);
6684                 return;
6685         }
6686
6687         /* Switch crtc and encoder back off if necessary */
6688         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6689                 connector->funcs->dpms(connector, old->dpms_mode);
6690
6691         mutex_unlock(&crtc->mutex);
6692 }
6693
6694 /* Returns the clock of the currently programmed mode of the given pipe. */
6695 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6696 {
6697         struct drm_i915_private *dev_priv = dev->dev_private;
6698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6699         int pipe = intel_crtc->pipe;
6700         u32 dpll = I915_READ(DPLL(pipe));
6701         u32 fp;
6702         intel_clock_t clock;
6703
6704         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6705                 fp = I915_READ(FP0(pipe));
6706         else
6707                 fp = I915_READ(FP1(pipe));
6708
6709         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6710         if (IS_PINEVIEW(dev)) {
6711                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6712                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6713         } else {
6714                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6715                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6716         }
6717
6718         if (!IS_GEN2(dev)) {
6719                 if (IS_PINEVIEW(dev))
6720                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6721                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6722                 else
6723                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6724                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6725
6726                 switch (dpll & DPLL_MODE_MASK) {
6727                 case DPLLB_MODE_DAC_SERIAL:
6728                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6729                                 5 : 10;
6730                         break;
6731                 case DPLLB_MODE_LVDS:
6732                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6733                                 7 : 14;
6734                         break;
6735                 default:
6736                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6737                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6738                         return 0;
6739                 }
6740
6741                 /* XXX: Handle the 100Mhz refclk */
6742                 intel_clock(dev, 96000, &clock);
6743         } else {
6744                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6745
6746                 if (is_lvds) {
6747                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6748                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6749                         clock.p2 = 14;
6750
6751                         if ((dpll & PLL_REF_INPUT_MASK) ==
6752                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6753                                 /* XXX: might not be 66MHz */
6754                                 intel_clock(dev, 66000, &clock);
6755                         } else
6756                                 intel_clock(dev, 48000, &clock);
6757                 } else {
6758                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6759                                 clock.p1 = 2;
6760                         else {
6761                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6762                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6763                         }
6764                         if (dpll & PLL_P2_DIVIDE_BY_4)
6765                                 clock.p2 = 4;
6766                         else
6767                                 clock.p2 = 2;
6768
6769                         intel_clock(dev, 48000, &clock);
6770                 }
6771         }
6772
6773         /* XXX: It would be nice to validate the clocks, but we can't reuse
6774          * i830PllIsValid() because it relies on the xf86_config connector
6775          * configuration being accurate, which it isn't necessarily.
6776          */
6777
6778         return clock.dot;
6779 }
6780
6781 /** Returns the currently programmed mode of the given pipe. */
6782 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6783                                              struct drm_crtc *crtc)
6784 {
6785         struct drm_i915_private *dev_priv = dev->dev_private;
6786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6787         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6788         struct drm_display_mode *mode;
6789         int htot = I915_READ(HTOTAL(cpu_transcoder));
6790         int hsync = I915_READ(HSYNC(cpu_transcoder));
6791         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6792         int vsync = I915_READ(VSYNC(cpu_transcoder));
6793
6794         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6795         if (!mode)
6796                 return NULL;
6797
6798         mode->clock = intel_crtc_clock_get(dev, crtc);
6799         mode->hdisplay = (htot & 0xffff) + 1;
6800         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6801         mode->hsync_start = (hsync & 0xffff) + 1;
6802         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6803         mode->vdisplay = (vtot & 0xffff) + 1;
6804         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6805         mode->vsync_start = (vsync & 0xffff) + 1;
6806         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6807
6808         drm_mode_set_name(mode);
6809
6810         return mode;
6811 }
6812
6813 static void intel_increase_pllclock(struct drm_crtc *crtc)
6814 {
6815         struct drm_device *dev = crtc->dev;
6816         drm_i915_private_t *dev_priv = dev->dev_private;
6817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6818         int pipe = intel_crtc->pipe;
6819         int dpll_reg = DPLL(pipe);
6820         int dpll;
6821
6822         if (HAS_PCH_SPLIT(dev))
6823                 return;
6824
6825         if (!dev_priv->lvds_downclock_avail)
6826                 return;
6827
6828         dpll = I915_READ(dpll_reg);
6829         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6830                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6831
6832                 assert_panel_unlocked(dev_priv, pipe);
6833
6834                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6835                 I915_WRITE(dpll_reg, dpll);
6836                 intel_wait_for_vblank(dev, pipe);
6837
6838                 dpll = I915_READ(dpll_reg);
6839                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6840                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6841         }
6842 }
6843
6844 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6845 {
6846         struct drm_device *dev = crtc->dev;
6847         drm_i915_private_t *dev_priv = dev->dev_private;
6848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6849
6850         if (HAS_PCH_SPLIT(dev))
6851                 return;
6852
6853         if (!dev_priv->lvds_downclock_avail)
6854                 return;
6855
6856         /*
6857          * Since this is called by a timer, we should never get here in
6858          * the manual case.
6859          */
6860         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6861                 int pipe = intel_crtc->pipe;
6862                 int dpll_reg = DPLL(pipe);
6863                 int dpll;
6864
6865                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6866
6867                 assert_panel_unlocked(dev_priv, pipe);
6868
6869                 dpll = I915_READ(dpll_reg);
6870                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6871                 I915_WRITE(dpll_reg, dpll);
6872                 intel_wait_for_vblank(dev, pipe);
6873                 dpll = I915_READ(dpll_reg);
6874                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6875                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6876         }
6877
6878 }
6879
6880 void intel_mark_busy(struct drm_device *dev)
6881 {
6882         i915_update_gfx_val(dev->dev_private);
6883 }
6884
6885 void intel_mark_idle(struct drm_device *dev)
6886 {
6887         struct drm_crtc *crtc;
6888
6889         if (!i915_powersave)
6890                 return;
6891
6892         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6893                 if (!crtc->fb)
6894                         continue;
6895
6896                 intel_decrease_pllclock(crtc);
6897         }
6898 }
6899
6900 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6901 {
6902         struct drm_device *dev = obj->base.dev;
6903         struct drm_crtc *crtc;
6904
6905         if (!i915_powersave)
6906                 return;
6907
6908         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6909                 if (!crtc->fb)
6910                         continue;
6911
6912                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6913                         intel_increase_pllclock(crtc);
6914         }
6915 }
6916
6917 static void intel_crtc_destroy(struct drm_crtc *crtc)
6918 {
6919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920         struct drm_device *dev = crtc->dev;
6921         struct intel_unpin_work *work;
6922         unsigned long flags;
6923
6924         spin_lock_irqsave(&dev->event_lock, flags);
6925         work = intel_crtc->unpin_work;
6926         intel_crtc->unpin_work = NULL;
6927         spin_unlock_irqrestore(&dev->event_lock, flags);
6928
6929         if (work) {
6930                 cancel_work_sync(&work->work);
6931                 kfree(work);
6932         }
6933
6934         drm_crtc_cleanup(crtc);
6935
6936         kfree(intel_crtc);
6937 }
6938
6939 static void intel_unpin_work_fn(struct work_struct *__work)
6940 {
6941         struct intel_unpin_work *work =
6942                 container_of(__work, struct intel_unpin_work, work);
6943         struct drm_device *dev = work->crtc->dev;
6944
6945         mutex_lock(&dev->struct_mutex);
6946         intel_unpin_fb_obj(work->old_fb_obj);
6947         drm_gem_object_unreference(&work->pending_flip_obj->base);
6948         drm_gem_object_unreference(&work->old_fb_obj->base);
6949
6950         intel_update_fbc(dev);
6951         mutex_unlock(&dev->struct_mutex);
6952
6953         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6954         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6955
6956         kfree(work);
6957 }
6958
6959 static void do_intel_finish_page_flip(struct drm_device *dev,
6960                                       struct drm_crtc *crtc)
6961 {
6962         drm_i915_private_t *dev_priv = dev->dev_private;
6963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6964         struct intel_unpin_work *work;
6965         struct drm_i915_gem_object *obj;
6966         unsigned long flags;
6967
6968         /* Ignore early vblank irqs */
6969         if (intel_crtc == NULL)
6970                 return;
6971
6972         spin_lock_irqsave(&dev->event_lock, flags);
6973         work = intel_crtc->unpin_work;
6974
6975         /* Ensure we don't miss a work->pending update ... */
6976         smp_rmb();
6977
6978         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6979                 spin_unlock_irqrestore(&dev->event_lock, flags);
6980                 return;
6981         }
6982
6983         /* and that the unpin work is consistent wrt ->pending. */
6984         smp_rmb();
6985
6986         intel_crtc->unpin_work = NULL;
6987
6988         if (work->event)
6989                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6990
6991         drm_vblank_put(dev, intel_crtc->pipe);
6992
6993         spin_unlock_irqrestore(&dev->event_lock, flags);
6994
6995         obj = work->old_fb_obj;
6996
6997         wake_up_all(&dev_priv->pending_flip_queue);
6998
6999         queue_work(dev_priv->wq, &work->work);
7000
7001         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7002 }
7003
7004 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7005 {
7006         drm_i915_private_t *dev_priv = dev->dev_private;
7007         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7008
7009         do_intel_finish_page_flip(dev, crtc);
7010 }
7011
7012 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7013 {
7014         drm_i915_private_t *dev_priv = dev->dev_private;
7015         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7016
7017         do_intel_finish_page_flip(dev, crtc);
7018 }
7019
7020 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7021 {
7022         drm_i915_private_t *dev_priv = dev->dev_private;
7023         struct intel_crtc *intel_crtc =
7024                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7025         unsigned long flags;
7026
7027         /* NB: An MMIO update of the plane base pointer will also
7028          * generate a page-flip completion irq, i.e. every modeset
7029          * is also accompanied by a spurious intel_prepare_page_flip().
7030          */
7031         spin_lock_irqsave(&dev->event_lock, flags);
7032         if (intel_crtc->unpin_work)
7033                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7034         spin_unlock_irqrestore(&dev->event_lock, flags);
7035 }
7036
7037 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7038 {
7039         /* Ensure that the work item is consistent when activating it ... */
7040         smp_wmb();
7041         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7042         /* and that it is marked active as soon as the irq could fire. */
7043         smp_wmb();
7044 }
7045
7046 static int intel_gen2_queue_flip(struct drm_device *dev,
7047                                  struct drm_crtc *crtc,
7048                                  struct drm_framebuffer *fb,
7049                                  struct drm_i915_gem_object *obj)
7050 {
7051         struct drm_i915_private *dev_priv = dev->dev_private;
7052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7053         u32 flip_mask;
7054         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7055         int ret;
7056
7057         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7058         if (ret)
7059                 goto err;
7060
7061         ret = intel_ring_begin(ring, 6);
7062         if (ret)
7063                 goto err_unpin;
7064
7065         /* Can't queue multiple flips, so wait for the previous
7066          * one to finish before executing the next.
7067          */
7068         if (intel_crtc->plane)
7069                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7070         else
7071                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7072         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7073         intel_ring_emit(ring, MI_NOOP);
7074         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7075                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7076         intel_ring_emit(ring, fb->pitches[0]);
7077         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7078         intel_ring_emit(ring, 0); /* aux display base address, unused */
7079
7080         intel_mark_page_flip_active(intel_crtc);
7081         intel_ring_advance(ring);
7082         return 0;
7083
7084 err_unpin:
7085         intel_unpin_fb_obj(obj);
7086 err:
7087         return ret;
7088 }
7089
7090 static int intel_gen3_queue_flip(struct drm_device *dev,
7091                                  struct drm_crtc *crtc,
7092                                  struct drm_framebuffer *fb,
7093                                  struct drm_i915_gem_object *obj)
7094 {
7095         struct drm_i915_private *dev_priv = dev->dev_private;
7096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7097         u32 flip_mask;
7098         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7099         int ret;
7100
7101         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7102         if (ret)
7103                 goto err;
7104
7105         ret = intel_ring_begin(ring, 6);
7106         if (ret)
7107                 goto err_unpin;
7108
7109         if (intel_crtc->plane)
7110                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7111         else
7112                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7113         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7114         intel_ring_emit(ring, MI_NOOP);
7115         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7116                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7117         intel_ring_emit(ring, fb->pitches[0]);
7118         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7119         intel_ring_emit(ring, MI_NOOP);
7120
7121         intel_mark_page_flip_active(intel_crtc);
7122         intel_ring_advance(ring);
7123         return 0;
7124
7125 err_unpin:
7126         intel_unpin_fb_obj(obj);
7127 err:
7128         return ret;
7129 }
7130
7131 static int intel_gen4_queue_flip(struct drm_device *dev,
7132                                  struct drm_crtc *crtc,
7133                                  struct drm_framebuffer *fb,
7134                                  struct drm_i915_gem_object *obj)
7135 {
7136         struct drm_i915_private *dev_priv = dev->dev_private;
7137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138         uint32_t pf, pipesrc;
7139         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7140         int ret;
7141
7142         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7143         if (ret)
7144                 goto err;
7145
7146         ret = intel_ring_begin(ring, 4);
7147         if (ret)
7148                 goto err_unpin;
7149
7150         /* i965+ uses the linear or tiled offsets from the
7151          * Display Registers (which do not change across a page-flip)
7152          * so we need only reprogram the base address.
7153          */
7154         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7155                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7156         intel_ring_emit(ring, fb->pitches[0]);
7157         intel_ring_emit(ring,
7158                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7159                         obj->tiling_mode);
7160
7161         /* XXX Enabling the panel-fitter across page-flip is so far
7162          * untested on non-native modes, so ignore it for now.
7163          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7164          */
7165         pf = 0;
7166         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7167         intel_ring_emit(ring, pf | pipesrc);
7168
7169         intel_mark_page_flip_active(intel_crtc);
7170         intel_ring_advance(ring);
7171         return 0;
7172
7173 err_unpin:
7174         intel_unpin_fb_obj(obj);
7175 err:
7176         return ret;
7177 }
7178
7179 static int intel_gen6_queue_flip(struct drm_device *dev,
7180                                  struct drm_crtc *crtc,
7181                                  struct drm_framebuffer *fb,
7182                                  struct drm_i915_gem_object *obj)
7183 {
7184         struct drm_i915_private *dev_priv = dev->dev_private;
7185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7187         uint32_t pf, pipesrc;
7188         int ret;
7189
7190         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7191         if (ret)
7192                 goto err;
7193
7194         ret = intel_ring_begin(ring, 4);
7195         if (ret)
7196                 goto err_unpin;
7197
7198         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7199                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7200         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7201         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7202
7203         /* Contrary to the suggestions in the documentation,
7204          * "Enable Panel Fitter" does not seem to be required when page
7205          * flipping with a non-native mode, and worse causes a normal
7206          * modeset to fail.
7207          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7208          */
7209         pf = 0;
7210         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7211         intel_ring_emit(ring, pf | pipesrc);
7212
7213         intel_mark_page_flip_active(intel_crtc);
7214         intel_ring_advance(ring);
7215         return 0;
7216
7217 err_unpin:
7218         intel_unpin_fb_obj(obj);
7219 err:
7220         return ret;
7221 }
7222
7223 /*
7224  * On gen7 we currently use the blit ring because (in early silicon at least)
7225  * the render ring doesn't give us interrpts for page flip completion, which
7226  * means clients will hang after the first flip is queued.  Fortunately the
7227  * blit ring generates interrupts properly, so use it instead.
7228  */
7229 static int intel_gen7_queue_flip(struct drm_device *dev,
7230                                  struct drm_crtc *crtc,
7231                                  struct drm_framebuffer *fb,
7232                                  struct drm_i915_gem_object *obj)
7233 {
7234         struct drm_i915_private *dev_priv = dev->dev_private;
7235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7236         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7237         uint32_t plane_bit = 0;
7238         int ret;
7239
7240         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7241         if (ret)
7242                 goto err;
7243
7244         switch(intel_crtc->plane) {
7245         case PLANE_A:
7246                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7247                 break;
7248         case PLANE_B:
7249                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7250                 break;
7251         case PLANE_C:
7252                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7253                 break;
7254         default:
7255                 WARN_ONCE(1, "unknown plane in flip command\n");
7256                 ret = -ENODEV;
7257                 goto err_unpin;
7258         }
7259
7260         ret = intel_ring_begin(ring, 4);
7261         if (ret)
7262                 goto err_unpin;
7263
7264         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7265         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7266         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7267         intel_ring_emit(ring, (MI_NOOP));
7268
7269         intel_mark_page_flip_active(intel_crtc);
7270         intel_ring_advance(ring);
7271         return 0;
7272
7273 err_unpin:
7274         intel_unpin_fb_obj(obj);
7275 err:
7276         return ret;
7277 }
7278
7279 static int intel_default_queue_flip(struct drm_device *dev,
7280                                     struct drm_crtc *crtc,
7281                                     struct drm_framebuffer *fb,
7282                                     struct drm_i915_gem_object *obj)
7283 {
7284         return -ENODEV;
7285 }
7286
7287 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7288                                 struct drm_framebuffer *fb,
7289                                 struct drm_pending_vblank_event *event)
7290 {
7291         struct drm_device *dev = crtc->dev;
7292         struct drm_i915_private *dev_priv = dev->dev_private;
7293         struct drm_framebuffer *old_fb = crtc->fb;
7294         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7296         struct intel_unpin_work *work;
7297         unsigned long flags;
7298         int ret;
7299
7300         /* Can't change pixel format via MI display flips. */
7301         if (fb->pixel_format != crtc->fb->pixel_format)
7302                 return -EINVAL;
7303
7304         /*
7305          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7306          * Note that pitch changes could also affect these register.
7307          */
7308         if (INTEL_INFO(dev)->gen > 3 &&
7309             (fb->offsets[0] != crtc->fb->offsets[0] ||
7310              fb->pitches[0] != crtc->fb->pitches[0]))
7311                 return -EINVAL;
7312
7313         work = kzalloc(sizeof *work, GFP_KERNEL);
7314         if (work == NULL)
7315                 return -ENOMEM;
7316
7317         work->event = event;
7318         work->crtc = crtc;
7319         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7320         INIT_WORK(&work->work, intel_unpin_work_fn);
7321
7322         ret = drm_vblank_get(dev, intel_crtc->pipe);
7323         if (ret)
7324                 goto free_work;
7325
7326         /* We borrow the event spin lock for protecting unpin_work */
7327         spin_lock_irqsave(&dev->event_lock, flags);
7328         if (intel_crtc->unpin_work) {
7329                 spin_unlock_irqrestore(&dev->event_lock, flags);
7330                 kfree(work);
7331                 drm_vblank_put(dev, intel_crtc->pipe);
7332
7333                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7334                 return -EBUSY;
7335         }
7336         intel_crtc->unpin_work = work;
7337         spin_unlock_irqrestore(&dev->event_lock, flags);
7338
7339         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7340                 flush_workqueue(dev_priv->wq);
7341
7342         ret = i915_mutex_lock_interruptible(dev);
7343         if (ret)
7344                 goto cleanup;
7345
7346         /* Reference the objects for the scheduled work. */
7347         drm_gem_object_reference(&work->old_fb_obj->base);
7348         drm_gem_object_reference(&obj->base);
7349
7350         crtc->fb = fb;
7351
7352         work->pending_flip_obj = obj;
7353
7354         work->enable_stall_check = true;
7355
7356         atomic_inc(&intel_crtc->unpin_work_count);
7357         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7358
7359         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7360         if (ret)
7361                 goto cleanup_pending;
7362
7363         intel_disable_fbc(dev);
7364         intel_mark_fb_busy(obj);
7365         mutex_unlock(&dev->struct_mutex);
7366
7367         trace_i915_flip_request(intel_crtc->plane, obj);
7368
7369         return 0;
7370
7371 cleanup_pending:
7372         atomic_dec(&intel_crtc->unpin_work_count);
7373         crtc->fb = old_fb;
7374         drm_gem_object_unreference(&work->old_fb_obj->base);
7375         drm_gem_object_unreference(&obj->base);
7376         mutex_unlock(&dev->struct_mutex);
7377
7378 cleanup:
7379         spin_lock_irqsave(&dev->event_lock, flags);
7380         intel_crtc->unpin_work = NULL;
7381         spin_unlock_irqrestore(&dev->event_lock, flags);
7382
7383         drm_vblank_put(dev, intel_crtc->pipe);
7384 free_work:
7385         kfree(work);
7386
7387         return ret;
7388 }
7389
7390 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7391         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7392         .load_lut = intel_crtc_load_lut,
7393         .disable = intel_crtc_noop,
7394 };
7395
7396 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7397 {
7398         struct intel_encoder *other_encoder;
7399         struct drm_crtc *crtc = &encoder->new_crtc->base;
7400
7401         if (WARN_ON(!crtc))
7402                 return false;
7403
7404         list_for_each_entry(other_encoder,
7405                             &crtc->dev->mode_config.encoder_list,
7406                             base.head) {
7407
7408                 if (&other_encoder->new_crtc->base != crtc ||
7409                     encoder == other_encoder)
7410                         continue;
7411                 else
7412                         return true;
7413         }
7414
7415         return false;
7416 }
7417
7418 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7419                                   struct drm_crtc *crtc)
7420 {
7421         struct drm_device *dev;
7422         struct drm_crtc *tmp;
7423         int crtc_mask = 1;
7424
7425         WARN(!crtc, "checking null crtc?\n");
7426
7427         dev = crtc->dev;
7428
7429         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7430                 if (tmp == crtc)
7431                         break;
7432                 crtc_mask <<= 1;
7433         }
7434
7435         if (encoder->possible_crtcs & crtc_mask)
7436                 return true;
7437         return false;
7438 }
7439
7440 /**
7441  * intel_modeset_update_staged_output_state
7442  *
7443  * Updates the staged output configuration state, e.g. after we've read out the
7444  * current hw state.
7445  */
7446 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7447 {
7448         struct intel_encoder *encoder;
7449         struct intel_connector *connector;
7450
7451         list_for_each_entry(connector, &dev->mode_config.connector_list,
7452                             base.head) {
7453                 connector->new_encoder =
7454                         to_intel_encoder(connector->base.encoder);
7455         }
7456
7457         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7458                             base.head) {
7459                 encoder->new_crtc =
7460                         to_intel_crtc(encoder->base.crtc);
7461         }
7462 }
7463
7464 /**
7465  * intel_modeset_commit_output_state
7466  *
7467  * This function copies the stage display pipe configuration to the real one.
7468  */
7469 static void intel_modeset_commit_output_state(struct drm_device *dev)
7470 {
7471         struct intel_encoder *encoder;
7472         struct intel_connector *connector;
7473
7474         list_for_each_entry(connector, &dev->mode_config.connector_list,
7475                             base.head) {
7476                 connector->base.encoder = &connector->new_encoder->base;
7477         }
7478
7479         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7480                             base.head) {
7481                 encoder->base.crtc = &encoder->new_crtc->base;
7482         }
7483 }
7484
7485 static struct drm_display_mode *
7486 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7487                             struct drm_display_mode *mode)
7488 {
7489         struct drm_device *dev = crtc->dev;
7490         struct drm_display_mode *adjusted_mode;
7491         struct drm_encoder_helper_funcs *encoder_funcs;
7492         struct intel_encoder *encoder;
7493
7494         adjusted_mode = drm_mode_duplicate(dev, mode);
7495         if (!adjusted_mode)
7496                 return ERR_PTR(-ENOMEM);
7497
7498         /* Pass our mode to the connectors and the CRTC to give them a chance to
7499          * adjust it according to limitations or connector properties, and also
7500          * a chance to reject the mode entirely.
7501          */
7502         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7503                             base.head) {
7504
7505                 if (&encoder->new_crtc->base != crtc)
7506                         continue;
7507                 encoder_funcs = encoder->base.helper_private;
7508                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7509                                                 adjusted_mode))) {
7510                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7511                         goto fail;
7512                 }
7513         }
7514
7515         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7516                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7517                 goto fail;
7518         }
7519         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7520
7521         return adjusted_mode;
7522 fail:
7523         drm_mode_destroy(dev, adjusted_mode);
7524         return ERR_PTR(-EINVAL);
7525 }
7526
7527 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7528  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7529 static void
7530 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7531                              unsigned *prepare_pipes, unsigned *disable_pipes)
7532 {
7533         struct intel_crtc *intel_crtc;
7534         struct drm_device *dev = crtc->dev;
7535         struct intel_encoder *encoder;
7536         struct intel_connector *connector;
7537         struct drm_crtc *tmp_crtc;
7538
7539         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7540
7541         /* Check which crtcs have changed outputs connected to them, these need
7542          * to be part of the prepare_pipes mask. We don't (yet) support global
7543          * modeset across multiple crtcs, so modeset_pipes will only have one
7544          * bit set at most. */
7545         list_for_each_entry(connector, &dev->mode_config.connector_list,
7546                             base.head) {
7547                 if (connector->base.encoder == &connector->new_encoder->base)
7548                         continue;
7549
7550                 if (connector->base.encoder) {
7551                         tmp_crtc = connector->base.encoder->crtc;
7552
7553                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7554                 }
7555
7556                 if (connector->new_encoder)
7557                         *prepare_pipes |=
7558                                 1 << connector->new_encoder->new_crtc->pipe;
7559         }
7560
7561         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7562                             base.head) {
7563                 if (encoder->base.crtc == &encoder->new_crtc->base)
7564                         continue;
7565
7566                 if (encoder->base.crtc) {
7567                         tmp_crtc = encoder->base.crtc;
7568
7569                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7570                 }
7571
7572                 if (encoder->new_crtc)
7573                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7574         }
7575
7576         /* Check for any pipes that will be fully disabled ... */
7577         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7578                             base.head) {
7579                 bool used = false;
7580
7581                 /* Don't try to disable disabled crtcs. */
7582                 if (!intel_crtc->base.enabled)
7583                         continue;
7584
7585                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7586                                     base.head) {
7587                         if (encoder->new_crtc == intel_crtc)
7588                                 used = true;
7589                 }
7590
7591                 if (!used)
7592                         *disable_pipes |= 1 << intel_crtc->pipe;
7593         }
7594
7595
7596         /* set_mode is also used to update properties on life display pipes. */
7597         intel_crtc = to_intel_crtc(crtc);
7598         if (crtc->enabled)
7599                 *prepare_pipes |= 1 << intel_crtc->pipe;
7600
7601         /* We only support modeset on one single crtc, hence we need to do that
7602          * only for the passed in crtc iff we change anything else than just
7603          * disable crtcs.
7604          *
7605          * This is actually not true, to be fully compatible with the old crtc
7606          * helper we automatically disable _any_ output (i.e. doesn't need to be
7607          * connected to the crtc we're modesetting on) if it's disconnected.
7608          * Which is a rather nutty api (since changed the output configuration
7609          * without userspace's explicit request can lead to confusion), but
7610          * alas. Hence we currently need to modeset on all pipes we prepare. */
7611         if (*prepare_pipes)
7612                 *modeset_pipes = *prepare_pipes;
7613
7614         /* ... and mask these out. */
7615         *modeset_pipes &= ~(*disable_pipes);
7616         *prepare_pipes &= ~(*disable_pipes);
7617 }
7618
7619 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7620 {
7621         struct drm_encoder *encoder;
7622         struct drm_device *dev = crtc->dev;
7623
7624         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7625                 if (encoder->crtc == crtc)
7626                         return true;
7627
7628         return false;
7629 }
7630
7631 static void
7632 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7633 {
7634         struct intel_encoder *intel_encoder;
7635         struct intel_crtc *intel_crtc;
7636         struct drm_connector *connector;
7637
7638         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7639                             base.head) {
7640                 if (!intel_encoder->base.crtc)
7641                         continue;
7642
7643                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7644
7645                 if (prepare_pipes & (1 << intel_crtc->pipe))
7646                         intel_encoder->connectors_active = false;
7647         }
7648
7649         intel_modeset_commit_output_state(dev);
7650
7651         /* Update computed state. */
7652         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7653                             base.head) {
7654                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7655         }
7656
7657         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7658                 if (!connector->encoder || !connector->encoder->crtc)
7659                         continue;
7660
7661                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7662
7663                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7664                         struct drm_property *dpms_property =
7665                                 dev->mode_config.dpms_property;
7666
7667                         connector->dpms = DRM_MODE_DPMS_ON;
7668                         drm_object_property_set_value(&connector->base,
7669                                                          dpms_property,
7670                                                          DRM_MODE_DPMS_ON);
7671
7672                         intel_encoder = to_intel_encoder(connector->encoder);
7673                         intel_encoder->connectors_active = true;
7674                 }
7675         }
7676
7677 }
7678
7679 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7680         list_for_each_entry((intel_crtc), \
7681                             &(dev)->mode_config.crtc_list, \
7682                             base.head) \
7683                 if (mask & (1 <<(intel_crtc)->pipe)) \
7684
7685 void
7686 intel_modeset_check_state(struct drm_device *dev)
7687 {
7688         struct intel_crtc *crtc;
7689         struct intel_encoder *encoder;
7690         struct intel_connector *connector;
7691
7692         list_for_each_entry(connector, &dev->mode_config.connector_list,
7693                             base.head) {
7694                 /* This also checks the encoder/connector hw state with the
7695                  * ->get_hw_state callbacks. */
7696                 intel_connector_check_state(connector);
7697
7698                 WARN(&connector->new_encoder->base != connector->base.encoder,
7699                      "connector's staged encoder doesn't match current encoder\n");
7700         }
7701
7702         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7703                             base.head) {
7704                 bool enabled = false;
7705                 bool active = false;
7706                 enum pipe pipe, tracked_pipe;
7707
7708                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7709                               encoder->base.base.id,
7710                               drm_get_encoder_name(&encoder->base));
7711
7712                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7713                      "encoder's stage crtc doesn't match current crtc\n");
7714                 WARN(encoder->connectors_active && !encoder->base.crtc,
7715                      "encoder's active_connectors set, but no crtc\n");
7716
7717                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7718                                     base.head) {
7719                         if (connector->base.encoder != &encoder->base)
7720                                 continue;
7721                         enabled = true;
7722                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7723                                 active = true;
7724                 }
7725                 WARN(!!encoder->base.crtc != enabled,
7726                      "encoder's enabled state mismatch "
7727                      "(expected %i, found %i)\n",
7728                      !!encoder->base.crtc, enabled);
7729                 WARN(active && !encoder->base.crtc,
7730                      "active encoder with no crtc\n");
7731
7732                 WARN(encoder->connectors_active != active,
7733                      "encoder's computed active state doesn't match tracked active state "
7734                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7735
7736                 active = encoder->get_hw_state(encoder, &pipe);
7737                 WARN(active != encoder->connectors_active,
7738                      "encoder's hw state doesn't match sw tracking "
7739                      "(expected %i, found %i)\n",
7740                      encoder->connectors_active, active);
7741
7742                 if (!encoder->base.crtc)
7743                         continue;
7744
7745                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7746                 WARN(active && pipe != tracked_pipe,
7747                      "active encoder's pipe doesn't match"
7748                      "(expected %i, found %i)\n",
7749                      tracked_pipe, pipe);
7750
7751         }
7752
7753         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7754                             base.head) {
7755                 bool enabled = false;
7756                 bool active = false;
7757
7758                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7759                               crtc->base.base.id);
7760
7761                 WARN(crtc->active && !crtc->base.enabled,
7762                      "active crtc, but not enabled in sw tracking\n");
7763
7764                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7765                                     base.head) {
7766                         if (encoder->base.crtc != &crtc->base)
7767                                 continue;
7768                         enabled = true;
7769                         if (encoder->connectors_active)
7770                                 active = true;
7771                 }
7772                 WARN(active != crtc->active,
7773                      "crtc's computed active state doesn't match tracked active state "
7774                      "(expected %i, found %i)\n", active, crtc->active);
7775                 WARN(enabled != crtc->base.enabled,
7776                      "crtc's computed enabled state doesn't match tracked enabled state "
7777                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7778
7779                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7780         }
7781 }
7782
7783 int intel_set_mode(struct drm_crtc *crtc,
7784                    struct drm_display_mode *mode,
7785                    int x, int y, struct drm_framebuffer *fb)
7786 {
7787         struct drm_device *dev = crtc->dev;
7788         drm_i915_private_t *dev_priv = dev->dev_private;
7789         struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7790         struct intel_crtc *intel_crtc;
7791         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7792         int ret = 0;
7793
7794         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7795         if (!saved_mode)
7796                 return -ENOMEM;
7797         saved_hwmode = saved_mode + 1;
7798
7799         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7800                                      &prepare_pipes, &disable_pipes);
7801
7802         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7803                       modeset_pipes, prepare_pipes, disable_pipes);
7804
7805         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7806                 intel_crtc_disable(&intel_crtc->base);
7807
7808         *saved_hwmode = crtc->hwmode;
7809         *saved_mode = crtc->mode;
7810
7811         /* Hack: Because we don't (yet) support global modeset on multiple
7812          * crtcs, we don't keep track of the new mode for more than one crtc.
7813          * Hence simply check whether any bit is set in modeset_pipes in all the
7814          * pieces of code that are not yet converted to deal with mutliple crtcs
7815          * changing their mode at the same time. */
7816         adjusted_mode = NULL;
7817         if (modeset_pipes) {
7818                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7819                 if (IS_ERR(adjusted_mode)) {
7820                         ret = PTR_ERR(adjusted_mode);
7821                         goto out;
7822                 }
7823         }
7824
7825         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7826                 if (intel_crtc->base.enabled)
7827                         dev_priv->display.crtc_disable(&intel_crtc->base);
7828         }
7829
7830         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7831          * to set it here already despite that we pass it down the callchain.
7832          */
7833         if (modeset_pipes)
7834                 crtc->mode = *mode;
7835
7836         /* Only after disabling all output pipelines that will be changed can we
7837          * update the the output configuration. */
7838         intel_modeset_update_state(dev, prepare_pipes);
7839
7840         if (dev_priv->display.modeset_global_resources)
7841                 dev_priv->display.modeset_global_resources(dev);
7842
7843         /* Set up the DPLL and any encoders state that needs to adjust or depend
7844          * on the DPLL.
7845          */
7846         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7847                 ret = intel_crtc_mode_set(&intel_crtc->base,
7848                                           mode, adjusted_mode,
7849                                           x, y, fb);
7850                 if (ret)
7851                         goto done;
7852         }
7853
7854         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7855         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7856                 dev_priv->display.crtc_enable(&intel_crtc->base);
7857
7858         if (modeset_pipes) {
7859                 /* Store real post-adjustment hardware mode. */
7860                 crtc->hwmode = *adjusted_mode;
7861
7862                 /* Calculate and store various constants which
7863                  * are later needed by vblank and swap-completion
7864                  * timestamping. They are derived from true hwmode.
7865                  */
7866                 drm_calc_timestamping_constants(crtc);
7867         }
7868
7869         /* FIXME: add subpixel order */
7870 done:
7871         drm_mode_destroy(dev, adjusted_mode);
7872         if (ret && crtc->enabled) {
7873                 crtc->hwmode = *saved_hwmode;
7874                 crtc->mode = *saved_mode;
7875         } else {
7876                 intel_modeset_check_state(dev);
7877         }
7878
7879 out:
7880         kfree(saved_mode);
7881         return ret;
7882 }
7883
7884 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7885 {
7886         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7887 }
7888
7889 #undef for_each_intel_crtc_masked
7890
7891 static void intel_set_config_free(struct intel_set_config *config)
7892 {
7893         if (!config)
7894                 return;
7895
7896         kfree(config->save_connector_encoders);
7897         kfree(config->save_encoder_crtcs);
7898         kfree(config);
7899 }
7900
7901 static int intel_set_config_save_state(struct drm_device *dev,
7902                                        struct intel_set_config *config)
7903 {
7904         struct drm_encoder *encoder;
7905         struct drm_connector *connector;
7906         int count;
7907
7908         config->save_encoder_crtcs =
7909                 kcalloc(dev->mode_config.num_encoder,
7910                         sizeof(struct drm_crtc *), GFP_KERNEL);
7911         if (!config->save_encoder_crtcs)
7912                 return -ENOMEM;
7913
7914         config->save_connector_encoders =
7915                 kcalloc(dev->mode_config.num_connector,
7916                         sizeof(struct drm_encoder *), GFP_KERNEL);
7917         if (!config->save_connector_encoders)
7918                 return -ENOMEM;
7919
7920         /* Copy data. Note that driver private data is not affected.
7921          * Should anything bad happen only the expected state is
7922          * restored, not the drivers personal bookkeeping.
7923          */
7924         count = 0;
7925         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7926                 config->save_encoder_crtcs[count++] = encoder->crtc;
7927         }
7928
7929         count = 0;
7930         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7931                 config->save_connector_encoders[count++] = connector->encoder;
7932         }
7933
7934         return 0;
7935 }
7936
7937 static void intel_set_config_restore_state(struct drm_device *dev,
7938                                            struct intel_set_config *config)
7939 {
7940         struct intel_encoder *encoder;
7941         struct intel_connector *connector;
7942         int count;
7943
7944         count = 0;
7945         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7946                 encoder->new_crtc =
7947                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7948         }
7949
7950         count = 0;
7951         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7952                 connector->new_encoder =
7953                         to_intel_encoder(config->save_connector_encoders[count++]);
7954         }
7955 }
7956
7957 static void
7958 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7959                                       struct intel_set_config *config)
7960 {
7961
7962         /* We should be able to check here if the fb has the same properties
7963          * and then just flip_or_move it */
7964         if (set->crtc->fb != set->fb) {
7965                 /* If we have no fb then treat it as a full mode set */
7966                 if (set->crtc->fb == NULL) {
7967                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7968                         config->mode_changed = true;
7969                 } else if (set->fb == NULL) {
7970                         config->mode_changed = true;
7971                 } else if (set->fb->depth != set->crtc->fb->depth) {
7972                         config->mode_changed = true;
7973                 } else if (set->fb->bits_per_pixel !=
7974                            set->crtc->fb->bits_per_pixel) {
7975                         config->mode_changed = true;
7976                 } else
7977                         config->fb_changed = true;
7978         }
7979
7980         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7981                 config->fb_changed = true;
7982
7983         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7984                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7985                 drm_mode_debug_printmodeline(&set->crtc->mode);
7986                 drm_mode_debug_printmodeline(set->mode);
7987                 config->mode_changed = true;
7988         }
7989 }
7990
7991 static int
7992 intel_modeset_stage_output_state(struct drm_device *dev,
7993                                  struct drm_mode_set *set,
7994                                  struct intel_set_config *config)
7995 {
7996         struct drm_crtc *new_crtc;
7997         struct intel_connector *connector;
7998         struct intel_encoder *encoder;
7999         int count, ro;
8000
8001         /* The upper layers ensure that we either disable a crtc or have a list
8002          * of connectors. For paranoia, double-check this. */
8003         WARN_ON(!set->fb && (set->num_connectors != 0));
8004         WARN_ON(set->fb && (set->num_connectors == 0));
8005
8006         count = 0;
8007         list_for_each_entry(connector, &dev->mode_config.connector_list,
8008                             base.head) {
8009                 /* Otherwise traverse passed in connector list and get encoders
8010                  * for them. */
8011                 for (ro = 0; ro < set->num_connectors; ro++) {
8012                         if (set->connectors[ro] == &connector->base) {
8013                                 connector->new_encoder = connector->encoder;
8014                                 break;
8015                         }
8016                 }
8017
8018                 /* If we disable the crtc, disable all its connectors. Also, if
8019                  * the connector is on the changing crtc but not on the new
8020                  * connector list, disable it. */
8021                 if ((!set->fb || ro == set->num_connectors) &&
8022                     connector->base.encoder &&
8023                     connector->base.encoder->crtc == set->crtc) {
8024                         connector->new_encoder = NULL;
8025
8026                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8027                                 connector->base.base.id,
8028                                 drm_get_connector_name(&connector->base));
8029                 }
8030
8031
8032                 if (&connector->new_encoder->base != connector->base.encoder) {
8033                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8034                         config->mode_changed = true;
8035                 }
8036         }
8037         /* connector->new_encoder is now updated for all connectors. */
8038
8039         /* Update crtc of enabled connectors. */
8040         count = 0;
8041         list_for_each_entry(connector, &dev->mode_config.connector_list,
8042                             base.head) {
8043                 if (!connector->new_encoder)
8044                         continue;
8045
8046                 new_crtc = connector->new_encoder->base.crtc;
8047
8048                 for (ro = 0; ro < set->num_connectors; ro++) {
8049                         if (set->connectors[ro] == &connector->base)
8050                                 new_crtc = set->crtc;
8051                 }
8052
8053                 /* Make sure the new CRTC will work with the encoder */
8054                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8055                                            new_crtc)) {
8056                         return -EINVAL;
8057                 }
8058                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8059
8060                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8061                         connector->base.base.id,
8062                         drm_get_connector_name(&connector->base),
8063                         new_crtc->base.id);
8064         }
8065
8066         /* Check for any encoders that needs to be disabled. */
8067         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8068                             base.head) {
8069                 list_for_each_entry(connector,
8070                                     &dev->mode_config.connector_list,
8071                                     base.head) {
8072                         if (connector->new_encoder == encoder) {
8073                                 WARN_ON(!connector->new_encoder->new_crtc);
8074
8075                                 goto next_encoder;
8076                         }
8077                 }
8078                 encoder->new_crtc = NULL;
8079 next_encoder:
8080                 /* Only now check for crtc changes so we don't miss encoders
8081                  * that will be disabled. */
8082                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8083                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8084                         config->mode_changed = true;
8085                 }
8086         }
8087         /* Now we've also updated encoder->new_crtc for all encoders. */
8088
8089         return 0;
8090 }
8091
8092 static int intel_crtc_set_config(struct drm_mode_set *set)
8093 {
8094         struct drm_device *dev;
8095         struct drm_mode_set save_set;
8096         struct intel_set_config *config;
8097         int ret;
8098
8099         BUG_ON(!set);
8100         BUG_ON(!set->crtc);
8101         BUG_ON(!set->crtc->helper_private);
8102
8103         if (!set->mode)
8104                 set->fb = NULL;
8105
8106         /* The fb helper likes to play gross jokes with ->mode_set_config.
8107          * Unfortunately the crtc helper doesn't do much at all for this case,
8108          * so we have to cope with this madness until the fb helper is fixed up. */
8109         if (set->fb && set->num_connectors == 0)
8110                 return 0;
8111
8112         if (set->fb) {
8113                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8114                                 set->crtc->base.id, set->fb->base.id,
8115                                 (int)set->num_connectors, set->x, set->y);
8116         } else {
8117                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8118         }
8119
8120         dev = set->crtc->dev;
8121
8122         ret = -ENOMEM;
8123         config = kzalloc(sizeof(*config), GFP_KERNEL);
8124         if (!config)
8125                 goto out_config;
8126
8127         ret = intel_set_config_save_state(dev, config);
8128         if (ret)
8129                 goto out_config;
8130
8131         save_set.crtc = set->crtc;
8132         save_set.mode = &set->crtc->mode;
8133         save_set.x = set->crtc->x;
8134         save_set.y = set->crtc->y;
8135         save_set.fb = set->crtc->fb;
8136
8137         /* Compute whether we need a full modeset, only an fb base update or no
8138          * change at all. In the future we might also check whether only the
8139          * mode changed, e.g. for LVDS where we only change the panel fitter in
8140          * such cases. */
8141         intel_set_config_compute_mode_changes(set, config);
8142
8143         ret = intel_modeset_stage_output_state(dev, set, config);
8144         if (ret)
8145                 goto fail;
8146
8147         if (config->mode_changed) {
8148                 if (set->mode) {
8149                         DRM_DEBUG_KMS("attempting to set mode from"
8150                                         " userspace\n");
8151                         drm_mode_debug_printmodeline(set->mode);
8152                 }
8153
8154                 ret = intel_set_mode(set->crtc, set->mode,
8155                                      set->x, set->y, set->fb);
8156                 if (ret) {
8157                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8158                                   set->crtc->base.id, ret);
8159                         goto fail;
8160                 }
8161         } else if (config->fb_changed) {
8162                 ret = intel_pipe_set_base(set->crtc,
8163                                           set->x, set->y, set->fb);
8164         }
8165
8166         intel_set_config_free(config);
8167
8168         return 0;
8169
8170 fail:
8171         intel_set_config_restore_state(dev, config);
8172
8173         /* Try to restore the config */
8174         if (config->mode_changed &&
8175             intel_set_mode(save_set.crtc, save_set.mode,
8176                            save_set.x, save_set.y, save_set.fb))
8177                 DRM_ERROR("failed to restore config after modeset failure\n");
8178
8179 out_config:
8180         intel_set_config_free(config);
8181         return ret;
8182 }
8183
8184 static const struct drm_crtc_funcs intel_crtc_funcs = {
8185         .cursor_set = intel_crtc_cursor_set,
8186         .cursor_move = intel_crtc_cursor_move,
8187         .gamma_set = intel_crtc_gamma_set,
8188         .set_config = intel_crtc_set_config,
8189         .destroy = intel_crtc_destroy,
8190         .page_flip = intel_crtc_page_flip,
8191 };
8192
8193 static void intel_cpu_pll_init(struct drm_device *dev)
8194 {
8195         if (HAS_DDI(dev))
8196                 intel_ddi_pll_init(dev);
8197 }
8198
8199 static void intel_pch_pll_init(struct drm_device *dev)
8200 {
8201         drm_i915_private_t *dev_priv = dev->dev_private;
8202         int i;
8203
8204         if (dev_priv->num_pch_pll == 0) {
8205                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8206                 return;
8207         }
8208
8209         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8210                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8211                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8212                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8213         }
8214 }
8215
8216 static void intel_crtc_init(struct drm_device *dev, int pipe)
8217 {
8218         drm_i915_private_t *dev_priv = dev->dev_private;
8219         struct intel_crtc *intel_crtc;
8220         int i;
8221
8222         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8223         if (intel_crtc == NULL)
8224                 return;
8225
8226         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8227
8228         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8229         for (i = 0; i < 256; i++) {
8230                 intel_crtc->lut_r[i] = i;
8231                 intel_crtc->lut_g[i] = i;
8232                 intel_crtc->lut_b[i] = i;
8233         }
8234
8235         /* Swap pipes & planes for FBC on pre-965 */
8236         intel_crtc->pipe = pipe;
8237         intel_crtc->plane = pipe;
8238         intel_crtc->cpu_transcoder = pipe;
8239         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8240                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8241                 intel_crtc->plane = !pipe;
8242         }
8243
8244         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8245                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8246         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8247         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8248
8249         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8250
8251         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8252 }
8253
8254 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8255                                 struct drm_file *file)
8256 {
8257         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8258         struct drm_mode_object *drmmode_obj;
8259         struct intel_crtc *crtc;
8260
8261         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8262                 return -ENODEV;
8263
8264         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8265                         DRM_MODE_OBJECT_CRTC);
8266
8267         if (!drmmode_obj) {
8268                 DRM_ERROR("no such CRTC id\n");
8269                 return -EINVAL;
8270         }
8271
8272         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8273         pipe_from_crtc_id->pipe = crtc->pipe;
8274
8275         return 0;
8276 }
8277
8278 static int intel_encoder_clones(struct intel_encoder *encoder)
8279 {
8280         struct drm_device *dev = encoder->base.dev;
8281         struct intel_encoder *source_encoder;
8282         int index_mask = 0;
8283         int entry = 0;
8284
8285         list_for_each_entry(source_encoder,
8286                             &dev->mode_config.encoder_list, base.head) {
8287
8288                 if (encoder == source_encoder)
8289                         index_mask |= (1 << entry);
8290
8291                 /* Intel hw has only one MUX where enocoders could be cloned. */
8292                 if (encoder->cloneable && source_encoder->cloneable)
8293                         index_mask |= (1 << entry);
8294
8295                 entry++;
8296         }
8297
8298         return index_mask;
8299 }
8300
8301 static bool has_edp_a(struct drm_device *dev)
8302 {
8303         struct drm_i915_private *dev_priv = dev->dev_private;
8304
8305         if (!IS_MOBILE(dev))
8306                 return false;
8307
8308         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8309                 return false;
8310
8311         if (IS_GEN5(dev) &&
8312             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8313                 return false;
8314
8315         return true;
8316 }
8317
8318 static void intel_setup_outputs(struct drm_device *dev)
8319 {
8320         struct drm_i915_private *dev_priv = dev->dev_private;
8321         struct intel_encoder *encoder;
8322         bool dpd_is_edp = false;
8323         bool has_lvds;
8324
8325         has_lvds = intel_lvds_init(dev);
8326         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8327                 /* disable the panel fitter on everything but LVDS */
8328                 I915_WRITE(PFIT_CONTROL, 0);
8329         }
8330
8331         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8332                 intel_crt_init(dev);
8333
8334         if (HAS_DDI(dev)) {
8335                 int found;
8336
8337                 /* Haswell uses DDI functions to detect digital outputs */
8338                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8339                 /* DDI A only supports eDP */
8340                 if (found)
8341                         intel_ddi_init(dev, PORT_A);
8342
8343                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8344                  * register */
8345                 found = I915_READ(SFUSE_STRAP);
8346
8347                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8348                         intel_ddi_init(dev, PORT_B);
8349                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8350                         intel_ddi_init(dev, PORT_C);
8351                 if (found & SFUSE_STRAP_DDID_DETECTED)
8352                         intel_ddi_init(dev, PORT_D);
8353         } else if (HAS_PCH_SPLIT(dev)) {
8354                 int found;
8355                 dpd_is_edp = intel_dpd_is_edp(dev);
8356
8357                 if (has_edp_a(dev))
8358                         intel_dp_init(dev, DP_A, PORT_A);
8359
8360                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8361                         /* PCH SDVOB multiplex with HDMIB */
8362                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8363                         if (!found)
8364                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8365                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8366                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8367                 }
8368
8369                 if (I915_READ(HDMIC) & PORT_DETECTED)
8370                         intel_hdmi_init(dev, HDMIC, PORT_C);
8371
8372                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8373                         intel_hdmi_init(dev, HDMID, PORT_D);
8374
8375                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8376                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8377
8378                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8379                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8380         } else if (IS_VALLEYVIEW(dev)) {
8381                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8382                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8383                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8384
8385                 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8386                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8387                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8388                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8389                 }
8390
8391                 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8392                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8393
8394         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8395                 bool found = false;
8396
8397                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8398                         DRM_DEBUG_KMS("probing SDVOB\n");
8399                         found = intel_sdvo_init(dev, SDVOB, true);
8400                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8401                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8402                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8403                         }
8404
8405                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8406                                 DRM_DEBUG_KMS("probing DP_B\n");
8407                                 intel_dp_init(dev, DP_B, PORT_B);
8408                         }
8409                 }
8410
8411                 /* Before G4X SDVOC doesn't have its own detect register */
8412
8413                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8414                         DRM_DEBUG_KMS("probing SDVOC\n");
8415                         found = intel_sdvo_init(dev, SDVOC, false);
8416                 }
8417
8418                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8419
8420                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8421                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8422                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8423                         }
8424                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8425                                 DRM_DEBUG_KMS("probing DP_C\n");
8426                                 intel_dp_init(dev, DP_C, PORT_C);
8427                         }
8428                 }
8429
8430                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8431                     (I915_READ(DP_D) & DP_DETECTED)) {
8432                         DRM_DEBUG_KMS("probing DP_D\n");
8433                         intel_dp_init(dev, DP_D, PORT_D);
8434                 }
8435         } else if (IS_GEN2(dev))
8436                 intel_dvo_init(dev);
8437
8438         if (SUPPORTS_TV(dev))
8439                 intel_tv_init(dev);
8440
8441         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8442                 encoder->base.possible_crtcs = encoder->crtc_mask;
8443                 encoder->base.possible_clones =
8444                         intel_encoder_clones(encoder);
8445         }
8446
8447         intel_init_pch_refclk(dev);
8448
8449         drm_helper_move_panel_connectors_to_head(dev);
8450 }
8451
8452 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8453 {
8454         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8455
8456         drm_framebuffer_cleanup(fb);
8457         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8458
8459         kfree(intel_fb);
8460 }
8461
8462 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8463                                                 struct drm_file *file,
8464                                                 unsigned int *handle)
8465 {
8466         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8467         struct drm_i915_gem_object *obj = intel_fb->obj;
8468
8469         return drm_gem_handle_create(file, &obj->base, handle);
8470 }
8471
8472 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8473         .destroy = intel_user_framebuffer_destroy,
8474         .create_handle = intel_user_framebuffer_create_handle,
8475 };
8476
8477 int intel_framebuffer_init(struct drm_device *dev,
8478                            struct intel_framebuffer *intel_fb,
8479                            struct drm_mode_fb_cmd2 *mode_cmd,
8480                            struct drm_i915_gem_object *obj)
8481 {
8482         int ret;
8483
8484         if (obj->tiling_mode == I915_TILING_Y) {
8485                 DRM_DEBUG("hardware does not support tiling Y\n");
8486                 return -EINVAL;
8487         }
8488
8489         if (mode_cmd->pitches[0] & 63) {
8490                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8491                           mode_cmd->pitches[0]);
8492                 return -EINVAL;
8493         }
8494
8495         /* FIXME <= Gen4 stride limits are bit unclear */
8496         if (mode_cmd->pitches[0] > 32768) {
8497                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8498                           mode_cmd->pitches[0]);
8499                 return -EINVAL;
8500         }
8501
8502         if (obj->tiling_mode != I915_TILING_NONE &&
8503             mode_cmd->pitches[0] != obj->stride) {
8504                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8505                           mode_cmd->pitches[0], obj->stride);
8506                 return -EINVAL;
8507         }
8508
8509         /* Reject formats not supported by any plane early. */
8510         switch (mode_cmd->pixel_format) {
8511         case DRM_FORMAT_C8:
8512         case DRM_FORMAT_RGB565:
8513         case DRM_FORMAT_XRGB8888:
8514         case DRM_FORMAT_ARGB8888:
8515                 break;
8516         case DRM_FORMAT_XRGB1555:
8517         case DRM_FORMAT_ARGB1555:
8518                 if (INTEL_INFO(dev)->gen > 3) {
8519                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8520                         return -EINVAL;
8521                 }
8522                 break;
8523         case DRM_FORMAT_XBGR8888:
8524         case DRM_FORMAT_ABGR8888:
8525         case DRM_FORMAT_XRGB2101010:
8526         case DRM_FORMAT_ARGB2101010:
8527         case DRM_FORMAT_XBGR2101010:
8528         case DRM_FORMAT_ABGR2101010:
8529                 if (INTEL_INFO(dev)->gen < 4) {
8530                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8531                         return -EINVAL;
8532                 }
8533                 break;
8534         case DRM_FORMAT_YUYV:
8535         case DRM_FORMAT_UYVY:
8536         case DRM_FORMAT_YVYU:
8537         case DRM_FORMAT_VYUY:
8538                 if (INTEL_INFO(dev)->gen < 5) {
8539                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8540                         return -EINVAL;
8541                 }
8542                 break;
8543         default:
8544                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8545                 return -EINVAL;
8546         }
8547
8548         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8549         if (mode_cmd->offsets[0] != 0)
8550                 return -EINVAL;
8551
8552         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8553         intel_fb->obj = obj;
8554
8555         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8556         if (ret) {
8557                 DRM_ERROR("framebuffer init failed %d\n", ret);
8558                 return ret;
8559         }
8560
8561         return 0;
8562 }
8563
8564 static struct drm_framebuffer *
8565 intel_user_framebuffer_create(struct drm_device *dev,
8566                               struct drm_file *filp,
8567                               struct drm_mode_fb_cmd2 *mode_cmd)
8568 {
8569         struct drm_i915_gem_object *obj;
8570
8571         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8572                                                 mode_cmd->handles[0]));
8573         if (&obj->base == NULL)
8574                 return ERR_PTR(-ENOENT);
8575
8576         return intel_framebuffer_create(dev, mode_cmd, obj);
8577 }
8578
8579 static const struct drm_mode_config_funcs intel_mode_funcs = {
8580         .fb_create = intel_user_framebuffer_create,
8581         .output_poll_changed = intel_fb_output_poll_changed,
8582 };
8583
8584 /* Set up chip specific display functions */
8585 static void intel_init_display(struct drm_device *dev)
8586 {
8587         struct drm_i915_private *dev_priv = dev->dev_private;
8588
8589         /* We always want a DPMS function */
8590         if (HAS_DDI(dev)) {
8591                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8592                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8593                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8594                 dev_priv->display.off = haswell_crtc_off;
8595                 dev_priv->display.update_plane = ironlake_update_plane;
8596         } else if (HAS_PCH_SPLIT(dev)) {
8597                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8598                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8599                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8600                 dev_priv->display.off = ironlake_crtc_off;
8601                 dev_priv->display.update_plane = ironlake_update_plane;
8602         } else {
8603                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8604                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8605                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8606                 dev_priv->display.off = i9xx_crtc_off;
8607                 dev_priv->display.update_plane = i9xx_update_plane;
8608         }
8609
8610         /* Returns the core display clock speed */
8611         if (IS_VALLEYVIEW(dev))
8612                 dev_priv->display.get_display_clock_speed =
8613                         valleyview_get_display_clock_speed;
8614         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8615                 dev_priv->display.get_display_clock_speed =
8616                         i945_get_display_clock_speed;
8617         else if (IS_I915G(dev))
8618                 dev_priv->display.get_display_clock_speed =
8619                         i915_get_display_clock_speed;
8620         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8621                 dev_priv->display.get_display_clock_speed =
8622                         i9xx_misc_get_display_clock_speed;
8623         else if (IS_I915GM(dev))
8624                 dev_priv->display.get_display_clock_speed =
8625                         i915gm_get_display_clock_speed;
8626         else if (IS_I865G(dev))
8627                 dev_priv->display.get_display_clock_speed =
8628                         i865_get_display_clock_speed;
8629         else if (IS_I85X(dev))
8630                 dev_priv->display.get_display_clock_speed =
8631                         i855_get_display_clock_speed;
8632         else /* 852, 830 */
8633                 dev_priv->display.get_display_clock_speed =
8634                         i830_get_display_clock_speed;
8635
8636         if (HAS_PCH_SPLIT(dev)) {
8637                 if (IS_GEN5(dev)) {
8638                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8639                         dev_priv->display.write_eld = ironlake_write_eld;
8640                 } else if (IS_GEN6(dev)) {
8641                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8642                         dev_priv->display.write_eld = ironlake_write_eld;
8643                 } else if (IS_IVYBRIDGE(dev)) {
8644                         /* FIXME: detect B0+ stepping and use auto training */
8645                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8646                         dev_priv->display.write_eld = ironlake_write_eld;
8647                         dev_priv->display.modeset_global_resources =
8648                                 ivb_modeset_global_resources;
8649                 } else if (IS_HASWELL(dev)) {
8650                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8651                         dev_priv->display.write_eld = haswell_write_eld;
8652                         dev_priv->display.modeset_global_resources =
8653                                 haswell_modeset_global_resources;
8654                 }
8655         } else if (IS_G4X(dev)) {
8656                 dev_priv->display.write_eld = g4x_write_eld;
8657         }
8658
8659         /* Default just returns -ENODEV to indicate unsupported */
8660         dev_priv->display.queue_flip = intel_default_queue_flip;
8661
8662         switch (INTEL_INFO(dev)->gen) {
8663         case 2:
8664                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8665                 break;
8666
8667         case 3:
8668                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8669                 break;
8670
8671         case 4:
8672         case 5:
8673                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8674                 break;
8675
8676         case 6:
8677                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8678                 break;
8679         case 7:
8680                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8681                 break;
8682         }
8683 }
8684
8685 /*
8686  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8687  * resume, or other times.  This quirk makes sure that's the case for
8688  * affected systems.
8689  */
8690 static void quirk_pipea_force(struct drm_device *dev)
8691 {
8692         struct drm_i915_private *dev_priv = dev->dev_private;
8693
8694         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8695         DRM_INFO("applying pipe a force quirk\n");
8696 }
8697
8698 /*
8699  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8700  */
8701 static void quirk_ssc_force_disable(struct drm_device *dev)
8702 {
8703         struct drm_i915_private *dev_priv = dev->dev_private;
8704         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8705         DRM_INFO("applying lvds SSC disable quirk\n");
8706 }
8707
8708 /*
8709  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8710  * brightness value
8711  */
8712 static void quirk_invert_brightness(struct drm_device *dev)
8713 {
8714         struct drm_i915_private *dev_priv = dev->dev_private;
8715         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8716         DRM_INFO("applying inverted panel brightness quirk\n");
8717 }
8718
8719 struct intel_quirk {
8720         int device;
8721         int subsystem_vendor;
8722         int subsystem_device;
8723         void (*hook)(struct drm_device *dev);
8724 };
8725
8726 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8727 struct intel_dmi_quirk {
8728         void (*hook)(struct drm_device *dev);
8729         const struct dmi_system_id (*dmi_id_list)[];
8730 };
8731
8732 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8733 {
8734         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8735         return 1;
8736 }
8737
8738 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8739         {
8740                 .dmi_id_list = &(const struct dmi_system_id[]) {
8741                         {
8742                                 .callback = intel_dmi_reverse_brightness,
8743                                 .ident = "NCR Corporation",
8744                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8745                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8746                                 },
8747                         },
8748                         { }  /* terminating entry */
8749                 },
8750                 .hook = quirk_invert_brightness,
8751         },
8752 };
8753
8754 static struct intel_quirk intel_quirks[] = {
8755         /* HP Mini needs pipe A force quirk (LP: #322104) */
8756         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8757
8758         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8759         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8760
8761         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8762         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8763
8764         /* 830/845 need to leave pipe A & dpll A up */
8765         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8766         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8767
8768         /* Lenovo U160 cannot use SSC on LVDS */
8769         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8770
8771         /* Sony Vaio Y cannot use SSC on LVDS */
8772         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8773
8774         /* Acer Aspire 5734Z must invert backlight brightness */
8775         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8776
8777         /* Acer/eMachines G725 */
8778         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8779
8780         /* Acer/eMachines e725 */
8781         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8782
8783         /* Acer/Packard Bell NCL20 */
8784         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8785
8786         /* Acer Aspire 4736Z */
8787         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8788 };
8789
8790 static void intel_init_quirks(struct drm_device *dev)
8791 {
8792         struct pci_dev *d = dev->pdev;
8793         int i;
8794
8795         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8796                 struct intel_quirk *q = &intel_quirks[i];
8797
8798                 if (d->device == q->device &&
8799                     (d->subsystem_vendor == q->subsystem_vendor ||
8800                      q->subsystem_vendor == PCI_ANY_ID) &&
8801                     (d->subsystem_device == q->subsystem_device ||
8802                      q->subsystem_device == PCI_ANY_ID))
8803                         q->hook(dev);
8804         }
8805         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8806                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8807                         intel_dmi_quirks[i].hook(dev);
8808         }
8809 }
8810
8811 /* Disable the VGA plane that we never use */
8812 static void i915_disable_vga(struct drm_device *dev)
8813 {
8814         struct drm_i915_private *dev_priv = dev->dev_private;
8815         u8 sr1;
8816         u32 vga_reg = i915_vgacntrl_reg(dev);
8817
8818         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8819         outb(SR01, VGA_SR_INDEX);
8820         sr1 = inb(VGA_SR_DATA);
8821         outb(sr1 | 1<<5, VGA_SR_DATA);
8822         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8823         udelay(300);
8824
8825         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8826         POSTING_READ(vga_reg);
8827 }
8828
8829 void intel_modeset_init_hw(struct drm_device *dev)
8830 {
8831         intel_init_power_well(dev);
8832
8833         intel_prepare_ddi(dev);
8834
8835         intel_init_clock_gating(dev);
8836
8837         mutex_lock(&dev->struct_mutex);
8838         intel_enable_gt_powersave(dev);
8839         mutex_unlock(&dev->struct_mutex);
8840 }
8841
8842 void intel_modeset_init(struct drm_device *dev)
8843 {
8844         struct drm_i915_private *dev_priv = dev->dev_private;
8845         int i, ret;
8846
8847         drm_mode_config_init(dev);
8848
8849         dev->mode_config.min_width = 0;
8850         dev->mode_config.min_height = 0;
8851
8852         dev->mode_config.preferred_depth = 24;
8853         dev->mode_config.prefer_shadow = 1;
8854
8855         dev->mode_config.funcs = &intel_mode_funcs;
8856
8857         intel_init_quirks(dev);
8858
8859         intel_init_pm(dev);
8860
8861         intel_init_display(dev);
8862
8863         if (IS_GEN2(dev)) {
8864                 dev->mode_config.max_width = 2048;
8865                 dev->mode_config.max_height = 2048;
8866         } else if (IS_GEN3(dev)) {
8867                 dev->mode_config.max_width = 4096;
8868                 dev->mode_config.max_height = 4096;
8869         } else {
8870                 dev->mode_config.max_width = 8192;
8871                 dev->mode_config.max_height = 8192;
8872         }
8873         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8874
8875         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8876                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8877
8878         for (i = 0; i < dev_priv->num_pipe; i++) {
8879                 intel_crtc_init(dev, i);
8880                 ret = intel_plane_init(dev, i);
8881                 if (ret)
8882                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8883         }
8884
8885         intel_cpu_pll_init(dev);
8886         intel_pch_pll_init(dev);
8887
8888         /* Just disable it once at startup */
8889         i915_disable_vga(dev);
8890         intel_setup_outputs(dev);
8891
8892         /* Just in case the BIOS is doing something questionable. */
8893         intel_disable_fbc(dev);
8894 }
8895
8896 static void
8897 intel_connector_break_all_links(struct intel_connector *connector)
8898 {
8899         connector->base.dpms = DRM_MODE_DPMS_OFF;
8900         connector->base.encoder = NULL;
8901         connector->encoder->connectors_active = false;
8902         connector->encoder->base.crtc = NULL;
8903 }
8904
8905 static void intel_enable_pipe_a(struct drm_device *dev)
8906 {
8907         struct intel_connector *connector;
8908         struct drm_connector *crt = NULL;
8909         struct intel_load_detect_pipe load_detect_temp;
8910
8911         /* We can't just switch on the pipe A, we need to set things up with a
8912          * proper mode and output configuration. As a gross hack, enable pipe A
8913          * by enabling the load detect pipe once. */
8914         list_for_each_entry(connector,
8915                             &dev->mode_config.connector_list,
8916                             base.head) {
8917                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8918                         crt = &connector->base;
8919                         break;
8920                 }
8921         }
8922
8923         if (!crt)
8924                 return;
8925
8926         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8927                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8928
8929
8930 }
8931
8932 static bool
8933 intel_check_plane_mapping(struct intel_crtc *crtc)
8934 {
8935         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8936         u32 reg, val;
8937
8938         if (dev_priv->num_pipe == 1)
8939                 return true;
8940
8941         reg = DSPCNTR(!crtc->plane);
8942         val = I915_READ(reg);
8943
8944         if ((val & DISPLAY_PLANE_ENABLE) &&
8945             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8946                 return false;
8947
8948         return true;
8949 }
8950
8951 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8952 {
8953         struct drm_device *dev = crtc->base.dev;
8954         struct drm_i915_private *dev_priv = dev->dev_private;
8955         u32 reg;
8956
8957         /* Clear any frame start delays used for debugging left by the BIOS */
8958         reg = PIPECONF(crtc->cpu_transcoder);
8959         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8960
8961         /* We need to sanitize the plane -> pipe mapping first because this will
8962          * disable the crtc (and hence change the state) if it is wrong. Note
8963          * that gen4+ has a fixed plane -> pipe mapping.  */
8964         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8965                 struct intel_connector *connector;
8966                 bool plane;
8967
8968                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8969                               crtc->base.base.id);
8970
8971                 /* Pipe has the wrong plane attached and the plane is active.
8972                  * Temporarily change the plane mapping and disable everything
8973                  * ...  */
8974                 plane = crtc->plane;
8975                 crtc->plane = !plane;
8976                 dev_priv->display.crtc_disable(&crtc->base);
8977                 crtc->plane = plane;
8978
8979                 /* ... and break all links. */
8980                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8981                                     base.head) {
8982                         if (connector->encoder->base.crtc != &crtc->base)
8983                                 continue;
8984
8985                         intel_connector_break_all_links(connector);
8986                 }
8987
8988                 WARN_ON(crtc->active);
8989                 crtc->base.enabled = false;
8990         }
8991
8992         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8993             crtc->pipe == PIPE_A && !crtc->active) {
8994                 /* BIOS forgot to enable pipe A, this mostly happens after
8995                  * resume. Force-enable the pipe to fix this, the update_dpms
8996                  * call below we restore the pipe to the right state, but leave
8997                  * the required bits on. */
8998                 intel_enable_pipe_a(dev);
8999         }
9000
9001         /* Adjust the state of the output pipe according to whether we
9002          * have active connectors/encoders. */
9003         intel_crtc_update_dpms(&crtc->base);
9004
9005         if (crtc->active != crtc->base.enabled) {
9006                 struct intel_encoder *encoder;
9007
9008                 /* This can happen either due to bugs in the get_hw_state
9009                  * functions or because the pipe is force-enabled due to the
9010                  * pipe A quirk. */
9011                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9012                               crtc->base.base.id,
9013                               crtc->base.enabled ? "enabled" : "disabled",
9014                               crtc->active ? "enabled" : "disabled");
9015
9016                 crtc->base.enabled = crtc->active;
9017
9018                 /* Because we only establish the connector -> encoder ->
9019                  * crtc links if something is active, this means the
9020                  * crtc is now deactivated. Break the links. connector
9021                  * -> encoder links are only establish when things are
9022                  *  actually up, hence no need to break them. */
9023                 WARN_ON(crtc->active);
9024
9025                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9026                         WARN_ON(encoder->connectors_active);
9027                         encoder->base.crtc = NULL;
9028                 }
9029         }
9030 }
9031
9032 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9033 {
9034         struct intel_connector *connector;
9035         struct drm_device *dev = encoder->base.dev;
9036
9037         /* We need to check both for a crtc link (meaning that the
9038          * encoder is active and trying to read from a pipe) and the
9039          * pipe itself being active. */
9040         bool has_active_crtc = encoder->base.crtc &&
9041                 to_intel_crtc(encoder->base.crtc)->active;
9042
9043         if (encoder->connectors_active && !has_active_crtc) {
9044                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9045                               encoder->base.base.id,
9046                               drm_get_encoder_name(&encoder->base));
9047
9048                 /* Connector is active, but has no active pipe. This is
9049                  * fallout from our resume register restoring. Disable
9050                  * the encoder manually again. */
9051                 if (encoder->base.crtc) {
9052                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9053                                       encoder->base.base.id,
9054                                       drm_get_encoder_name(&encoder->base));
9055                         encoder->disable(encoder);
9056                 }
9057
9058                 /* Inconsistent output/port/pipe state happens presumably due to
9059                  * a bug in one of the get_hw_state functions. Or someplace else
9060                  * in our code, like the register restore mess on resume. Clamp
9061                  * things to off as a safer default. */
9062                 list_for_each_entry(connector,
9063                                     &dev->mode_config.connector_list,
9064                                     base.head) {
9065                         if (connector->encoder != encoder)
9066                                 continue;
9067
9068                         intel_connector_break_all_links(connector);
9069                 }
9070         }
9071         /* Enabled encoders without active connectors will be fixed in
9072          * the crtc fixup. */
9073 }
9074
9075 void i915_redisable_vga(struct drm_device *dev)
9076 {
9077         struct drm_i915_private *dev_priv = dev->dev_private;
9078         u32 vga_reg = i915_vgacntrl_reg(dev);
9079
9080         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9081                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9082                 i915_disable_vga(dev);
9083         }
9084 }
9085
9086 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9087  * and i915 state tracking structures. */
9088 void intel_modeset_setup_hw_state(struct drm_device *dev,
9089                                   bool force_restore)
9090 {
9091         struct drm_i915_private *dev_priv = dev->dev_private;
9092         enum pipe pipe;
9093         u32 tmp;
9094         struct intel_crtc *crtc;
9095         struct intel_encoder *encoder;
9096         struct intel_connector *connector;
9097
9098         if (HAS_DDI(dev)) {
9099                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9100
9101                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9102                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9103                         case TRANS_DDI_EDP_INPUT_A_ON:
9104                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9105                                 pipe = PIPE_A;
9106                                 break;
9107                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9108                                 pipe = PIPE_B;
9109                                 break;
9110                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9111                                 pipe = PIPE_C;
9112                                 break;
9113                         }
9114
9115                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9116                         crtc->cpu_transcoder = TRANSCODER_EDP;
9117
9118                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9119                                       pipe_name(pipe));
9120                 }
9121         }
9122
9123         for_each_pipe(pipe) {
9124                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9125
9126                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9127                 if (tmp & PIPECONF_ENABLE)
9128                         crtc->active = true;
9129                 else
9130                         crtc->active = false;
9131
9132                 crtc->base.enabled = crtc->active;
9133
9134                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9135                               crtc->base.base.id,
9136                               crtc->active ? "enabled" : "disabled");
9137         }
9138
9139         if (HAS_DDI(dev))
9140                 intel_ddi_setup_hw_pll_state(dev);
9141
9142         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9143                             base.head) {
9144                 pipe = 0;
9145
9146                 if (encoder->get_hw_state(encoder, &pipe)) {
9147                         encoder->base.crtc =
9148                                 dev_priv->pipe_to_crtc_mapping[pipe];
9149                 } else {
9150                         encoder->base.crtc = NULL;
9151                 }
9152
9153                 encoder->connectors_active = false;
9154                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9155                               encoder->base.base.id,
9156                               drm_get_encoder_name(&encoder->base),
9157                               encoder->base.crtc ? "enabled" : "disabled",
9158                               pipe);
9159         }
9160
9161         list_for_each_entry(connector, &dev->mode_config.connector_list,
9162                             base.head) {
9163                 if (connector->get_hw_state(connector)) {
9164                         connector->base.dpms = DRM_MODE_DPMS_ON;
9165                         connector->encoder->connectors_active = true;
9166                         connector->base.encoder = &connector->encoder->base;
9167                 } else {
9168                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9169                         connector->base.encoder = NULL;
9170                 }
9171                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9172                               connector->base.base.id,
9173                               drm_get_connector_name(&connector->base),
9174                               connector->base.encoder ? "enabled" : "disabled");
9175         }
9176
9177         /* HW state is read out, now we need to sanitize this mess. */
9178         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9179                             base.head) {
9180                 intel_sanitize_encoder(encoder);
9181         }
9182
9183         for_each_pipe(pipe) {
9184                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9185                 intel_sanitize_crtc(crtc);
9186         }
9187
9188         if (force_restore) {
9189                 for_each_pipe(pipe) {
9190                         intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9191                 }
9192
9193                 i915_redisable_vga(dev);
9194         } else {
9195                 intel_modeset_update_staged_output_state(dev);
9196         }
9197
9198         intel_modeset_check_state(dev);
9199
9200         drm_mode_config_reset(dev);
9201 }
9202
9203 void intel_modeset_gem_init(struct drm_device *dev)
9204 {
9205         intel_modeset_init_hw(dev);
9206
9207         intel_setup_overlay(dev);
9208
9209         intel_modeset_setup_hw_state(dev, false);
9210 }
9211
9212 void intel_modeset_cleanup(struct drm_device *dev)
9213 {
9214         struct drm_i915_private *dev_priv = dev->dev_private;
9215         struct drm_crtc *crtc;
9216         struct intel_crtc *intel_crtc;
9217
9218         drm_kms_helper_poll_fini(dev);
9219         mutex_lock(&dev->struct_mutex);
9220
9221         intel_unregister_dsm_handler();
9222
9223
9224         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9225                 /* Skip inactive CRTCs */
9226                 if (!crtc->fb)
9227                         continue;
9228
9229                 intel_crtc = to_intel_crtc(crtc);
9230                 intel_increase_pllclock(crtc);
9231         }
9232
9233         intel_disable_fbc(dev);
9234
9235         intel_disable_gt_powersave(dev);
9236
9237         ironlake_teardown_rc6(dev);
9238
9239         if (IS_VALLEYVIEW(dev))
9240                 vlv_init_dpio(dev);
9241
9242         mutex_unlock(&dev->struct_mutex);
9243
9244         /* Disable the irq before mode object teardown, for the irq might
9245          * enqueue unpin/hotplug work. */
9246         drm_irq_uninstall(dev);
9247         cancel_work_sync(&dev_priv->hotplug_work);
9248         cancel_work_sync(&dev_priv->rps.work);
9249
9250         /* flush any delayed tasks or pending work */
9251         flush_scheduled_work();
9252
9253         drm_mode_config_cleanup(dev);
9254
9255         intel_cleanup_overlay(dev);
9256 }
9257
9258 /*
9259  * Return which encoder is currently attached for connector.
9260  */
9261 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9262 {
9263         return &intel_attached_encoder(connector)->base;
9264 }
9265
9266 void intel_connector_attach_encoder(struct intel_connector *connector,
9267                                     struct intel_encoder *encoder)
9268 {
9269         connector->encoder = encoder;
9270         drm_mode_connector_attach_encoder(&connector->base,
9271                                           &encoder->base);
9272 }
9273
9274 /*
9275  * set vga decode state - true == enable VGA decode
9276  */
9277 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9278 {
9279         struct drm_i915_private *dev_priv = dev->dev_private;
9280         u16 gmch_ctrl;
9281
9282         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9283         if (state)
9284                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9285         else
9286                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9287         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9288         return 0;
9289 }
9290
9291 #ifdef CONFIG_DEBUG_FS
9292 #include <linux/seq_file.h>
9293
9294 struct intel_display_error_state {
9295         struct intel_cursor_error_state {
9296                 u32 control;
9297                 u32 position;
9298                 u32 base;
9299                 u32 size;
9300         } cursor[I915_MAX_PIPES];
9301
9302         struct intel_pipe_error_state {
9303                 u32 conf;
9304                 u32 source;
9305
9306                 u32 htotal;
9307                 u32 hblank;
9308                 u32 hsync;
9309                 u32 vtotal;
9310                 u32 vblank;
9311                 u32 vsync;
9312         } pipe[I915_MAX_PIPES];
9313
9314         struct intel_plane_error_state {
9315                 u32 control;
9316                 u32 stride;
9317                 u32 size;
9318                 u32 pos;
9319                 u32 addr;
9320                 u32 surface;
9321                 u32 tile_offset;
9322         } plane[I915_MAX_PIPES];
9323 };
9324
9325 struct intel_display_error_state *
9326 intel_display_capture_error_state(struct drm_device *dev)
9327 {
9328         drm_i915_private_t *dev_priv = dev->dev_private;
9329         struct intel_display_error_state *error;
9330         enum transcoder cpu_transcoder;
9331         int i;
9332
9333         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9334         if (error == NULL)
9335                 return NULL;
9336
9337         for_each_pipe(i) {
9338                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9339
9340                 error->cursor[i].control = I915_READ(CURCNTR(i));
9341                 error->cursor[i].position = I915_READ(CURPOS(i));
9342                 error->cursor[i].base = I915_READ(CURBASE(i));
9343
9344                 error->plane[i].control = I915_READ(DSPCNTR(i));
9345                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9346                 error->plane[i].size = I915_READ(DSPSIZE(i));
9347                 error->plane[i].pos = I915_READ(DSPPOS(i));
9348                 error->plane[i].addr = I915_READ(DSPADDR(i));
9349                 if (INTEL_INFO(dev)->gen >= 4) {
9350                         error->plane[i].surface = I915_READ(DSPSURF(i));
9351                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9352                 }
9353
9354                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9355                 error->pipe[i].source = I915_READ(PIPESRC(i));
9356                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9357                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9358                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9359                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9360                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9361                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9362         }
9363
9364         return error;
9365 }
9366
9367 void
9368 intel_display_print_error_state(struct seq_file *m,
9369                                 struct drm_device *dev,
9370                                 struct intel_display_error_state *error)
9371 {
9372         drm_i915_private_t *dev_priv = dev->dev_private;
9373         int i;
9374
9375         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9376         for_each_pipe(i) {
9377                 seq_printf(m, "Pipe [%d]:\n", i);
9378                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9379                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9380                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9381                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9382                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9383                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9384                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9385                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9386
9387                 seq_printf(m, "Plane [%d]:\n", i);
9388                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9389                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9390                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9391                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9392                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9393                 if (INTEL_INFO(dev)->gen >= 4) {
9394                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9395                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9396                 }
9397
9398                 seq_printf(m, "Cursor [%d]:\n", i);
9399                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9400                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9401                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9402         }
9403 }
9404 #endif