drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 103                                         size_t size, loff_t *pos)
 104 {
 105         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 106         struct ras_query_if info = {
 107                 .head = obj->head,
 108         };
 109         ssize_t s;
 110         char val[128];
 111
 112         if (amdgpu_ras_error_query(obj->adev, &info))
 113                 return -EINVAL;
 114
 115         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 116                         "ue", info.ue_count,
 117                         "ce", info.ce_count);
 118         if (*pos >= s)
 119                 return 0;
 120
 121         s -= *pos;
 122         s = min_t(u64, s, size);
 123
 124
 125         if (copy_to_user(buf, &val[*pos], s))
 126                 return -EINVAL;
 127
 128         *pos += s;
 129
 130         return s;
 131 }
 132
 133 static const struct file_operations amdgpu_ras_debugfs_ops = {
 134         .owner = THIS_MODULE,
 135         .read = amdgpu_ras_debugfs_read,
 136         .write = NULL,
 137         .llseek = default_llseek
 138 };
 139
 140 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 141 {
 142         int i;
 143
 144         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 145                 *block_id = i;
 146                 if (strcmp(name, ras_block_str(i)) == 0)
 147                         return 0;
 148         }
 149         return -EINVAL;
 150 }
 151
 152 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 153                 const char __user *buf, size_t size,
 154                 loff_t *pos, struct ras_debug_if *data)
 155 {
 156         ssize_t s = min_t(u64, 64, size);
 157         char str[65];
 158         char block_name[33];
 159         char err[9] = "ue";
 160         int op = -1;
 161         int block_id;
 162         uint32_t sub_block;
 163         u64 address, value;
 164
 165         if (*pos)
 166                 return -EINVAL;
 167         *pos = size;
 168
 169         memset(str, 0, sizeof(str));
 170         memset(data, 0, sizeof(*data));
 171
 172         if (copy_from_user(str, buf, s))
 173                 return -EINVAL;
 174
 175         if (sscanf(str, "disable %32s", block_name) == 1)
 176                 op = 0;
 177         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 178                 op = 1;
 179         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 180                 op = 2;
 181         else if (str[0] && str[1] && str[2] && str[3])
 182                 /* ascii string, but commands are not matched. */
 183                 return -EINVAL;
 184
 185         if (op != -1) {
 186                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 187                         return -EINVAL;
 188
 189                 data->head.block = block_id;
 190                 /* only ue and ce errors are supported */
 191                 if (!memcmp("ue", err, 2))
 192                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 193                 else if (!memcmp("ce", err, 2))
 194                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 195                 else
 196                         return -EINVAL;
 197
 198                 data->op = op;
 199
 200                 if (op == 2) {
 201                         if (sscanf(str, "%*s %*s %*s %u %llu %llu",
 202                                                 &sub_block, &address, &value) != 3)
 203                                 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 204                                                         &sub_block, &address, &value) != 3)
 205                                         return -EINVAL;
 206                         data->head.sub_block_index = sub_block;
 207                         data->inject.address = address;
 208                         data->inject.value = value;
 209                 }
 210         } else {
 211                 if (size < sizeof(*data))
 212                         return -EINVAL;
 213
 214                 if (copy_from_user(data, buf, sizeof(*data)))
 215                         return -EINVAL;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * DOC: AMDGPU RAS debugfs control interface
 223  *
 224  * It accepts struct ras_debug_if who has two members.
 225  *
 226  * First member: ras_debug_if::head or ras_debug_if::inject.
 227  *
 228  * head is used to indicate which IP block will be under control.
 229  *
 230  * head has four members, they are block, type, sub_block_index, name.
 231  * block: which IP will be under control.
 232  * type: what kind of error will be enabled/disabled/injected.
 233  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 234  * name: the name of IP.
 235  *
 236  * inject has two more members than head, they are address, value.
 237  * As their names indicate, inject operation will write the
 238  * value to the address.
 239  *
 240  * The second member: struct ras_debug_if::op.
 241  * It has three kinds of operations.
 242  *
 243  * - 0: disable RAS on the block. Take ::head as its data.
 244  * - 1: enable RAS on the block. Take ::head as its data.
 245  * - 2: inject errors on the block. Take ::inject as its data.
 246  *
 247  * How to use the interface?
 248  *
 249  * Programs
 250  *
 251  * Copy the struct ras_debug_if in your codes and initialize it.
 252  * Write the struct to the control node.
 253  *
 254  * Shells
 255  *
 256  * .. code-block:: bash
 257  *
 258  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 259  *
 260  * Parameters:
 261  *
 262  * op: disable, enable, inject
 263  *      disable: only block is needed
 264  *      enable: block and error are needed
 265  *      inject: error, address, value are needed
 266  * block: umc, sdma, gfx, .........
 267  *      see ras_block_string[] for details
 268  * error: ue, ce
 269  *      ue: multi_uncorrectable
 270  *      ce: single_correctable
 271  * sub_block:
 272  *      sub block index, pass 0 if there is no sub block
 273  *
 274  * here are some examples for bash commands:
 275  *
 276  * .. code-block:: bash
 277  *
 278  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 279  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 280  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 281  *
 282  * How to check the result?
 283  *
 284  * For disable/enable, please check ras features at
 285  * /sys/class/drm/card[0/1/2...]/device/ras/features
 286  *
 287  * For inject, please check corresponding err count at
 288  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 289  *
 290  * .. note::
 291  *      Operations are only allowed on blocks which are supported.
 292  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 293  *      to see which blocks support RAS on a particular asic.
 294  *
 295  */
 296 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 297                 size_t size, loff_t *pos)
 298 {
 299         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 300         struct ras_debug_if data;
 301         int ret = 0;
 302
 303         if (!amdgpu_ras_get_error_query_ready(adev)) {
 304                 dev_warn(adev->dev, "RAS WARN: error injection "
 305                                 "currently inaccessible\n");
 306                 return size;
 307         }
 308
 309         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 310         if (ret)
 311                 return -EINVAL;
 312
 313         if (!amdgpu_ras_is_supported(adev, data.head.block))
 314                 return -EINVAL;
 315
 316         switch (data.op) {
 317         case 0:
 318                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 319                 break;
 320         case 1:
 321                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 322                 break;
 323         case 2:
 324                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 325                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 326                         dev_warn(adev->dev, "RAS WARN: input address "
 327                                         "0x%llx is invalid.",
 328                                         data.inject.address);
 329                         ret = -EINVAL;
 330                         break;
 331                 }
 332
 333                 /* umc ce/ue error injection for a bad page is not allowed */
 334                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 335                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 336                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 337                                         "as bad before error injection!\n",
 338                                         data.inject.address);
 339                         break;
 340                 }
 341
 342                 /* data.inject.address is offset instead of absolute gpu address */
 343                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 344                 break;
 345         default:
 346                 ret = -EINVAL;
 347                 break;
 348         }
 349
 350         if (ret)
 351                 return -EINVAL;
 352
 353         return size;
 354 }
 355
 356 /**
 357  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 358  *
 359  * Some boards contain an EEPROM which is used to persistently store a list of
 360  * bad pages which experiences ECC errors in vram.  This interface provides
 361  * a way to reset the EEPROM, e.g., after testing error injection.
 362  *
 363  * Usage:
 364  *
 365  * .. code-block:: bash
 366  *
 367  *      echo 1 > ../ras/ras_eeprom_reset
 368  *
 369  * will reset EEPROM table to 0 entries.
 370  *
 371  */
 372 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 373                 size_t size, loff_t *pos)
 374 {
 375         struct amdgpu_device *adev =
 376                 (struct amdgpu_device *)file_inode(f)->i_private;
 377         int ret;
 378
 379         ret = amdgpu_ras_eeprom_reset_table(
 380                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 381
 382         if (ret == 1) {
 383                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 384                 return size;
 385         } else {
 386                 return -EIO;
 387         }
 388 }
 389
 390 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 391         .owner = THIS_MODULE,
 392         .read = NULL,
 393         .write = amdgpu_ras_debugfs_ctrl_write,
 394         .llseek = default_llseek
 395 };
 396
 397 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 398         .owner = THIS_MODULE,
 399         .read = NULL,
 400         .write = amdgpu_ras_debugfs_eeprom_write,
 401         .llseek = default_llseek
 402 };
 403
 404 /**
 405  * DOC: AMDGPU RAS sysfs Error Count Interface
 406  *
 407  * It allows the user to read the error count for each IP block on the gpu through
 408  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 409  *
 410  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 411  * (ce) error counts.
 412  *
 413  * The format of one line is below,
 414  *
 415  * [ce|ue]: count
 416  *
 417  * Example:
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      ue: 0
 422  *      ce: 1
 423  *
 424  */
 425 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 426                 struct device_attribute *attr, char *buf)
 427 {
 428         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 429         struct ras_query_if info = {
 430                 .head = obj->head,
 431         };
 432
 433         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 434                 return snprintf(buf, PAGE_SIZE,
 435                                 "Query currently inaccessible\n");
 436
 437         if (amdgpu_ras_error_query(obj->adev, &info))
 438                 return -EINVAL;
 439
 440         return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
 441                         "ue", info.ue_count,
 442                         "ce", info.ce_count);
 443 }
 444
 445 /* obj begin */
 446
 447 #define get_obj(obj) do { (obj)->use++; } while (0)
 448 #define alive_obj(obj) ((obj)->use)
 449
 450 static inline void put_obj(struct ras_manager *obj)
 451 {
 452         if (obj && --obj->use == 0)
 453                 list_del(&obj->node);
 454         if (obj && obj->use < 0) {
 455                  DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 456         }
 457 }
 458
 459 /* make one obj and return it. */
 460 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 461                 struct ras_common_if *head)
 462 {
 463         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 464         struct ras_manager *obj;
 465
 466         if (!con)
 467                 return NULL;
 468
 469         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 470                 return NULL;
 471
 472         obj = &con->objs[head->block];
 473         /* already exist. return obj? */
 474         if (alive_obj(obj))
 475                 return NULL;
 476
 477         obj->head = *head;
 478         obj->adev = adev;
 479         list_add(&obj->node, &con->head);
 480         get_obj(obj);
 481
 482         return obj;
 483 }
 484
 485 /* return an obj equal to head, or the first when head is NULL */
 486 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 487                 struct ras_common_if *head)
 488 {
 489         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 490         struct ras_manager *obj;
 491         int i;
 492
 493         if (!con)
 494                 return NULL;
 495
 496         if (head) {
 497                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 498                         return NULL;
 499
 500                 obj = &con->objs[head->block];
 501
 502                 if (alive_obj(obj)) {
 503                         WARN_ON(head->block != obj->head.block);
 504                         return obj;
 505                 }
 506         } else {
 507                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 508                         obj = &con->objs[i];
 509                         if (alive_obj(obj)) {
 510                                 WARN_ON(i != obj->head.block);
 511                                 return obj;
 512                         }
 513                 }
 514         }
 515
 516         return NULL;
 517 }
 518 /* obj end */
 519
 520 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 521                                          const char* invoke_type,
 522                                          const char* block_name,
 523                                          enum ta_ras_status ret)
 524 {
 525         switch (ret) {
 526         case TA_RAS_STATUS__SUCCESS:
 527                 return;
 528         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 529                 dev_warn(adev->dev,
 530                         "RAS WARN: %s %s currently unavailable\n",
 531                         invoke_type,
 532                         block_name);
 533                 break;
 534         default:
 535                 dev_err(adev->dev,
 536                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 537                         invoke_type,
 538                         block_name,
 539                         ret);
 540         }
 541 }
 542
 543 /* feature ctl begin */
 544 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 545                 struct ras_common_if *head)
 546 {
 547         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 548
 549         return con->hw_supported & BIT(head->block);
 550 }
 551
 552 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 553                 struct ras_common_if *head)
 554 {
 555         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 556
 557         return con->features & BIT(head->block);
 558 }
 559
 560 /*
 561  * if obj is not created, then create one.
 562  * set feature enable flag.
 563  */
 564 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 565                 struct ras_common_if *head, int enable)
 566 {
 567         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 568         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 569
 570         /* If hardware does not support ras, then do not create obj.
 571          * But if hardware support ras, we can create the obj.
 572          * Ras framework checks con->hw_supported to see if it need do
 573          * corresponding initialization.
 574          * IP checks con->support to see if it need disable ras.
 575          */
 576         if (!amdgpu_ras_is_feature_allowed(adev, head))
 577                 return 0;
 578         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 579                 return 0;
 580
 581         if (enable) {
 582                 if (!obj) {
 583                         obj = amdgpu_ras_create_obj(adev, head);
 584                         if (!obj)
 585                                 return -EINVAL;
 586                 } else {
 587                         /* In case we create obj somewhere else */
 588                         get_obj(obj);
 589                 }
 590                 con->features |= BIT(head->block);
 591         } else {
 592                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 593                         con->features &= ~BIT(head->block);
 594                         put_obj(obj);
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 /* wrapper of psp_ras_enable_features */
 602 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 603                 struct ras_common_if *head, bool enable)
 604 {
 605         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 606         union ta_ras_cmd_input *info;
 607         int ret;
 608
 609         if (!con)
 610                 return -EINVAL;
 611
 612         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 613         if (!info)
 614                 return -ENOMEM;
 615
 616         if (!enable) {
 617                 info->disable_features = (struct ta_ras_disable_features_input) {
 618                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 619                         .error_type = amdgpu_ras_error_to_ta(head->type),
 620                 };
 621         } else {
 622                 info->enable_features = (struct ta_ras_enable_features_input) {
 623                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 624                         .error_type = amdgpu_ras_error_to_ta(head->type),
 625                 };
 626         }
 627
 628         /* Do not enable if it is not allowed. */
 629         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 630         /* Are we alerady in that state we are going to set? */
 631         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 632                 ret = 0;
 633                 goto out;
 634         }
 635
 636         if (!amdgpu_ras_intr_triggered()) {
 637                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 638                 if (ret) {
 639                         amdgpu_ras_parse_status_code(adev,
 640                                                      enable ? "enable":"disable",
 641                                                      ras_block_str(head->block),
 642                                                     (enum ta_ras_status)ret);
 643                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 644                                 ret = -EAGAIN;
 645                         else
 646                                 ret = -EINVAL;
 647
 648                         goto out;
 649                 }
 650         }
 651
 652         /* setup the obj */
 653         __amdgpu_ras_feature_enable(adev, head, enable);
 654         ret = 0;
 655 out:
 656         kfree(info);
 657         return ret;
 658 }
 659
 660 /* Only used in device probe stage and called only once. */
 661 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 662                 struct ras_common_if *head, bool enable)
 663 {
 664         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 665         int ret;
 666
 667         if (!con)
 668                 return -EINVAL;
 669
 670         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 671                 if (enable) {
 672                         /* There is no harm to issue a ras TA cmd regardless of
 673                          * the currecnt ras state.
 674                          * If current state == target state, it will do nothing
 675                          * But sometimes it requests driver to reset and repost
 676                          * with error code -EAGAIN.
 677                          */
 678                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 679                         /* With old ras TA, we might fail to enable ras.
 680                          * Log it and just setup the object.
 681                          * TODO need remove this WA in the future.
 682                          */
 683                         if (ret == -EINVAL) {
 684                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 685                                 if (!ret)
 686                                         dev_info(adev->dev,
 687                                                 "RAS INFO: %s setup object\n",
 688                                                 ras_block_str(head->block));
 689                         }
 690                 } else {
 691                         /* setup the object then issue a ras TA disable cmd.*/
 692                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 693                         if (ret)
 694                                 return ret;
 695
 696                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 697                 }
 698         } else
 699                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 700
 701         return ret;
 702 }
 703
 704 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 705                 bool bypass)
 706 {
 707         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 708         struct ras_manager *obj, *tmp;
 709
 710         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 711                 /* bypass psp.
 712                  * aka just release the obj and corresponding flags
 713                  */
 714                 if (bypass) {
 715                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 716                                 break;
 717                 } else {
 718                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 719                                 break;
 720                 }
 721         }
 722
 723         return con->features;
 724 }
 725
 726 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 727                 bool bypass)
 728 {
 729         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 730         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 731         int i;
 732         const enum amdgpu_ras_error_type default_ras_type =
 733                 AMDGPU_RAS_ERROR__NONE;
 734
 735         for (i = 0; i < ras_block_count; i++) {
 736                 struct ras_common_if head = {
 737                         .block = i,
 738                         .type = default_ras_type,
 739                         .sub_block_index = 0,
 740                 };
 741                 strcpy(head.name, ras_block_str(i));
 742                 if (bypass) {
 743                         /*
 744                          * bypass psp. vbios enable ras for us.
 745                          * so just create the obj
 746                          */
 747                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 748                                 break;
 749                 } else {
 750                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 751                                 break;
 752                 }
 753         }
 754
 755         return con->features;
 756 }
 757 /* feature ctl end */
 758
 759 /* query/inject/cure begin */
 760 int amdgpu_ras_error_query(struct amdgpu_device *adev,
 761                 struct ras_query_if *info)
 762 {
 763         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 764         struct ras_err_data err_data = {0, 0, 0, NULL};
 765         int i;
 766
 767         if (!obj)
 768                 return -EINVAL;
 769
 770         switch (info->head.block) {
 771         case AMDGPU_RAS_BLOCK__UMC:
 772                 if (adev->umc.funcs->query_ras_error_count)
 773                         adev->umc.funcs->query_ras_error_count(adev, &err_data);
 774                 /* umc query_ras_error_address is also responsible for clearing
 775                  * error status
 776                  */
 777                 if (adev->umc.funcs->query_ras_error_address)
 778                         adev->umc.funcs->query_ras_error_address(adev, &err_data);
 779                 break;
 780         case AMDGPU_RAS_BLOCK__SDMA:
 781                 if (adev->sdma.funcs->query_ras_error_count) {
 782                         for (i = 0; i < adev->sdma.num_instances; i++)
 783                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 784                                                                         &err_data);
 785                 }
 786                 break;
 787         case AMDGPU_RAS_BLOCK__GFX:
 788                 if (adev->gfx.funcs->query_ras_error_count)
 789                         adev->gfx.funcs->query_ras_error_count(adev, &err_data);
 790                 break;
 791         case AMDGPU_RAS_BLOCK__MMHUB:
 792                 if (adev->mmhub.funcs->query_ras_error_count)
 793                         adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
 794                 break;
 795         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 796                 if (adev->nbio.funcs->query_ras_error_count)
 797                         adev->nbio.funcs->query_ras_error_count(adev, &err_data);
 798                 break;
 799         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 800                 amdgpu_xgmi_query_ras_error_count(adev, &err_data);
 801                 break;
 802         default:
 803                 break;
 804         }
 805
 806         obj->err_data.ue_count += err_data.ue_count;
 807         obj->err_data.ce_count += err_data.ce_count;
 808
 809         info->ue_count = obj->err_data.ue_count;
 810         info->ce_count = obj->err_data.ce_count;
 811
 812         if (err_data.ce_count) {
 813                 dev_info(adev->dev, "%ld correctable hardware errors "
 814                                         "detected in %s block, no user "
 815                                         "action is needed.\n",
 816                                         obj->err_data.ce_count,
 817                                         ras_block_str(info->head.block));
 818         }
 819         if (err_data.ue_count) {
 820                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 821                                         "detected in %s block\n",
 822                                         obj->err_data.ue_count,
 823                                         ras_block_str(info->head.block));
 824         }
 825
 826         return 0;
 827 }
 828
 829 /* Trigger XGMI/WAFL error */
 830 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 831                                  struct ta_ras_trigger_error_input *block_info)
 832 {
 833         int ret;
 834
 835         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 836                 dev_warn(adev->dev, "Failed to disallow df cstate");
 837
 838         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 839                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 840
 841         ret = psp_ras_trigger_error(&adev->psp, block_info);
 842
 843         if (amdgpu_ras_intr_triggered())
 844                 return ret;
 845
 846         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 847                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 848
 849         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 850                 dev_warn(adev->dev, "Failed to allow df cstate");
 851
 852         return ret;
 853 }
 854
 855 /* wrapper of psp_ras_trigger_error */
 856 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 857                 struct ras_inject_if *info)
 858 {
 859         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 860         struct ta_ras_trigger_error_input block_info = {
 861                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 862                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 863                 .sub_block_index = info->head.sub_block_index,
 864                 .address = info->address,
 865                 .value = info->value,
 866         };
 867         int ret = 0;
 868
 869         if (!obj)
 870                 return -EINVAL;
 871
 872         /* Calculate XGMI relative offset */
 873         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 874                 block_info.address =
 875                         amdgpu_xgmi_get_relative_phy_addr(adev,
 876                                                           block_info.address);
 877         }
 878
 879         switch (info->head.block) {
 880         case AMDGPU_RAS_BLOCK__GFX:
 881                 if (adev->gfx.funcs->ras_error_inject)
 882                         ret = adev->gfx.funcs->ras_error_inject(adev, info);
 883                 else
 884                         ret = -EINVAL;
 885                 break;
 886         case AMDGPU_RAS_BLOCK__UMC:
 887         case AMDGPU_RAS_BLOCK__MMHUB:
 888         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 889                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
 890                 break;
 891         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 892                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
 893                 break;
 894         default:
 895                 dev_info(adev->dev, "%s error injection is not supported yet\n",
 896                          ras_block_str(info->head.block));
 897                 ret = -EINVAL;
 898         }
 899
 900         amdgpu_ras_parse_status_code(adev,
 901                                      "inject",
 902                                      ras_block_str(info->head.block),
 903                                      (enum ta_ras_status)ret);
 904
 905         return ret;
 906 }
 907
 908 int amdgpu_ras_error_cure(struct amdgpu_device *adev,
 909                 struct ras_cure_if *info)
 910 {
 911         /* psp fw has no cure interface for now. */
 912         return 0;
 913 }
 914
 915 /* get the total error counts on all IPs */
 916 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 917                 bool is_ce)
 918 {
 919         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 920         struct ras_manager *obj;
 921         struct ras_err_data data = {0, 0};
 922
 923         if (!con)
 924                 return 0;
 925
 926         list_for_each_entry(obj, &con->head, node) {
 927                 struct ras_query_if info = {
 928                         .head = obj->head,
 929                 };
 930
 931                 if (amdgpu_ras_error_query(adev, &info))
 932                         return 0;
 933
 934                 data.ce_count += info.ce_count;
 935                 data.ue_count += info.ue_count;
 936         }
 937
 938         return is_ce ? data.ce_count : data.ue_count;
 939 }
 940 /* query/inject/cure end */
 941
 942
 943 /* sysfs begin */
 944
 945 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
 946                 struct ras_badpage **bps, unsigned int *count);
 947
 948 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
 949 {
 950         switch (flags) {
 951         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
 952                 return "R";
 953         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
 954                 return "P";
 955         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
 956         default:
 957                 return "F";
 958         }
 959 }
 960
 961 /**
 962  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
 963  *
 964  * It allows user to read the bad pages of vram on the gpu through
 965  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
 966  *
 967  * It outputs multiple lines, and each line stands for one gpu page.
 968  *
 969  * The format of one line is below,
 970  * gpu pfn : gpu page size : flags
 971  *
 972  * gpu pfn and gpu page size are printed in hex format.
 973  * flags can be one of below character,
 974  *
 975  * R: reserved, this gpu page is reserved and not able to use.
 976  *
 977  * P: pending for reserve, this gpu page is marked as bad, will be reserved
 978  * in next window of page_reserve.
 979  *
 980  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
 981  *
 982  * Examples:
 983  *
 984  * .. code-block:: bash
 985  *
 986  *      0x00000001 : 0x00001000 : R
 987  *      0x00000002 : 0x00001000 : P
 988  *
 989  */
 990
 991 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
 992                 struct kobject *kobj, struct bin_attribute *attr,
 993                 char *buf, loff_t ppos, size_t count)
 994 {
 995         struct amdgpu_ras *con =
 996                 container_of(attr, struct amdgpu_ras, badpages_attr);
 997         struct amdgpu_device *adev = con->adev;
 998         const unsigned int element_size =
 999                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1000         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1001         unsigned int end = div64_ul(ppos + count - 1, element_size);
1002         ssize_t s = 0;
1003         struct ras_badpage *bps = NULL;
1004         unsigned int bps_count = 0;
1005
1006         memset(buf, 0, count);
1007
1008         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1009                 return 0;
1010
1011         for (; start < end && start < bps_count; start++)
1012                 s += scnprintf(&buf[s], element_size + 1,
1013                                 "0x%08x : 0x%08x : %1s\n",
1014                                 bps[start].bp,
1015                                 bps[start].size,
1016                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1017
1018         kfree(bps);
1019
1020         return s;
1021 }
1022
1023 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1024                 struct device_attribute *attr, char *buf)
1025 {
1026         struct amdgpu_ras *con =
1027                 container_of(attr, struct amdgpu_ras, features_attr);
1028
1029         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1030 }
1031
1032 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1033 {
1034         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1035
1036         sysfs_remove_file_from_group(&adev->dev->kobj,
1037                                 &con->badpages_attr.attr,
1038                                 RAS_FS_NAME);
1039 }
1040
1041 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1042 {
1043         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1044         struct attribute *attrs[] = {
1045                 &con->features_attr.attr,
1046                 NULL
1047         };
1048         struct attribute_group group = {
1049                 .name = RAS_FS_NAME,
1050                 .attrs = attrs,
1051         };
1052
1053         sysfs_remove_group(&adev->dev->kobj, &group);
1054
1055         return 0;
1056 }
1057
1058 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1059                 struct ras_fs_if *head)
1060 {
1061         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1062
1063         if (!obj || obj->attr_inuse)
1064                 return -EINVAL;
1065
1066         get_obj(obj);
1067
1068         memcpy(obj->fs_data.sysfs_name,
1069                         head->sysfs_name,
1070                         sizeof(obj->fs_data.sysfs_name));
1071
1072         obj->sysfs_attr = (struct device_attribute){
1073                 .attr = {
1074                         .name = obj->fs_data.sysfs_name,
1075                         .mode = S_IRUGO,
1076                 },
1077                         .show = amdgpu_ras_sysfs_read,
1078         };
1079         sysfs_attr_init(&obj->sysfs_attr.attr);
1080
1081         if (sysfs_add_file_to_group(&adev->dev->kobj,
1082                                 &obj->sysfs_attr.attr,
1083                                 RAS_FS_NAME)) {
1084                 put_obj(obj);
1085                 return -EINVAL;
1086         }
1087
1088         obj->attr_inuse = 1;
1089
1090         return 0;
1091 }
1092
1093 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1094                 struct ras_common_if *head)
1095 {
1096         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1097
1098         if (!obj || !obj->attr_inuse)
1099                 return -EINVAL;
1100
1101         sysfs_remove_file_from_group(&adev->dev->kobj,
1102                                 &obj->sysfs_attr.attr,
1103                                 RAS_FS_NAME);
1104         obj->attr_inuse = 0;
1105         put_obj(obj);
1106
1107         return 0;
1108 }
1109
1110 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1111 {
1112         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1113         struct ras_manager *obj, *tmp;
1114
1115         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1116                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1117         }
1118
1119         if (amdgpu_bad_page_threshold != 0)
1120                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1121
1122         amdgpu_ras_sysfs_remove_feature_node(adev);
1123
1124         return 0;
1125 }
1126 /* sysfs end */
1127
1128 /**
1129  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1130  *
1131  * Normally when there is an uncorrectable error, the driver will reset
1132  * the GPU to recover.  However, in the event of an unrecoverable error,
1133  * the driver provides an interface to reboot the system automatically
1134  * in that event.
1135  *
1136  * The following file in debugfs provides that interface:
1137  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1138  *
1139  * Usage:
1140  *
1141  * .. code-block:: bash
1142  *
1143  *      echo true > .../ras/auto_reboot
1144  *
1145  */
1146 /* debugfs begin */
1147 static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1148 {
1149         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1150         struct drm_minor *minor = adev_to_drm(adev)->primary;
1151
1152         con->dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1153         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
1154                                 adev, &amdgpu_ras_debugfs_ctrl_ops);
1155         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
1156                                 adev, &amdgpu_ras_debugfs_eeprom_ops);
1157
1158         /*
1159          * After one uncorrectable error happens, usually GPU recovery will
1160          * be scheduled. But due to the known problem in GPU recovery failing
1161          * to bring GPU back, below interface provides one direct way to
1162          * user to reboot system automatically in such case within
1163          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1164          * will never be called.
1165          */
1166         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir,
1167                                 &con->reboot);
1168
1169         /*
1170          * User could set this not to clean up hardware's error count register
1171          * of RAS IPs during ras recovery.
1172          */
1173         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644,
1174                         con->dir, &con->disable_ras_err_cnt_harvest);
1175 }
1176
1177 void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1178                 struct ras_fs_if *head)
1179 {
1180         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1181         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1182
1183         if (!obj || obj->ent)
1184                 return;
1185
1186         get_obj(obj);
1187
1188         memcpy(obj->fs_data.debugfs_name,
1189                         head->debugfs_name,
1190                         sizeof(obj->fs_data.debugfs_name));
1191
1192         obj->ent = debugfs_create_file(obj->fs_data.debugfs_name,
1193                                        S_IWUGO | S_IRUGO, con->dir, obj,
1194                                        &amdgpu_ras_debugfs_ops);
1195 }
1196
1197 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1198 {
1199 #if defined(CONFIG_DEBUG_FS)
1200         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1201         struct ras_manager *obj;
1202         struct ras_fs_if fs_info;
1203
1204         /*
1205          * it won't be called in resume path, no need to check
1206          * suspend and gpu reset status
1207          */
1208         if (!con)
1209                 return;
1210
1211         amdgpu_ras_debugfs_create_ctrl_node(adev);
1212
1213         list_for_each_entry(obj, &con->head, node) {
1214                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1215                         (obj->attr_inuse == 1)) {
1216                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1217                                         ras_block_str(obj->head.block));
1218                         fs_info.head = obj->head;
1219                         amdgpu_ras_debugfs_create(adev, &fs_info);
1220                 }
1221         }
1222 #endif
1223 }
1224
1225 void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
1226                 struct ras_common_if *head)
1227 {
1228         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1229
1230         if (!obj || !obj->ent)
1231                 return;
1232
1233         obj->ent = NULL;
1234         put_obj(obj);
1235 }
1236
1237 static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
1238 {
1239 #if defined(CONFIG_DEBUG_FS)
1240         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1241         struct ras_manager *obj, *tmp;
1242
1243         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1244                 amdgpu_ras_debugfs_remove(adev, &obj->head);
1245         }
1246
1247         con->dir = NULL;
1248 #endif
1249 }
1250 /* debugfs end */
1251
1252 /* ras fs */
1253 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1254                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1255 static DEVICE_ATTR(features, S_IRUGO,
1256                 amdgpu_ras_sysfs_features_read, NULL);
1257 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1258 {
1259         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1260         struct attribute_group group = {
1261                 .name = RAS_FS_NAME,
1262         };
1263         struct attribute *attrs[] = {
1264                 &con->features_attr.attr,
1265                 NULL
1266         };
1267         struct bin_attribute *bin_attrs[] = {
1268                 NULL,
1269                 NULL,
1270         };
1271         int r;
1272
1273         /* add features entry */
1274         con->features_attr = dev_attr_features;
1275         group.attrs = attrs;
1276         sysfs_attr_init(attrs[0]);
1277
1278         if (amdgpu_bad_page_threshold != 0) {
1279                 /* add bad_page_features entry */
1280                 bin_attr_gpu_vram_bad_pages.private = NULL;
1281                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1282                 bin_attrs[0] = &con->badpages_attr;
1283                 group.bin_attrs = bin_attrs;
1284                 sysfs_bin_attr_init(bin_attrs[0]);
1285         }
1286
1287         r = sysfs_create_group(&adev->dev->kobj, &group);
1288         if (r)
1289                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1290
1291         return 0;
1292 }
1293
1294 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1295 {
1296         amdgpu_ras_debugfs_remove_all(adev);
1297         amdgpu_ras_sysfs_remove_all(adev);
1298         return 0;
1299 }
1300 /* ras fs end */
1301
1302 /* ih begin */
1303 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1304 {
1305         struct ras_ih_data *data = &obj->ih_data;
1306         struct amdgpu_iv_entry entry;
1307         int ret;
1308         struct ras_err_data err_data = {0, 0, 0, NULL};
1309
1310         while (data->rptr != data->wptr) {
1311                 rmb();
1312                 memcpy(&entry, &data->ring[data->rptr],
1313                                 data->element_size);
1314
1315                 wmb();
1316                 data->rptr = (data->aligned_element_size +
1317                                 data->rptr) % data->ring_size;
1318
1319                 /* Let IP handle its data, maybe we need get the output
1320                  * from the callback to udpate the error type/count, etc
1321                  */
1322                 if (data->cb) {
1323                         ret = data->cb(obj->adev, &err_data, &entry);
1324                         /* ue will trigger an interrupt, and in that case
1325                          * we need do a reset to recovery the whole system.
1326                          * But leave IP do that recovery, here we just dispatch
1327                          * the error.
1328                          */
1329                         if (ret == AMDGPU_RAS_SUCCESS) {
1330                                 /* these counts could be left as 0 if
1331                                  * some blocks do not count error number
1332                                  */
1333                                 obj->err_data.ue_count += err_data.ue_count;
1334                                 obj->err_data.ce_count += err_data.ce_count;
1335                         }
1336                 }
1337         }
1338 }
1339
1340 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1341 {
1342         struct ras_ih_data *data =
1343                 container_of(work, struct ras_ih_data, ih_work);
1344         struct ras_manager *obj =
1345                 container_of(data, struct ras_manager, ih_data);
1346
1347         amdgpu_ras_interrupt_handler(obj);
1348 }
1349
1350 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1351                 struct ras_dispatch_if *info)
1352 {
1353         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1354         struct ras_ih_data *data = &obj->ih_data;
1355
1356         if (!obj)
1357                 return -EINVAL;
1358
1359         if (data->inuse == 0)
1360                 return 0;
1361
1362         /* Might be overflow... */
1363         memcpy(&data->ring[data->wptr], info->entry,
1364                         data->element_size);
1365
1366         wmb();
1367         data->wptr = (data->aligned_element_size +
1368                         data->wptr) % data->ring_size;
1369
1370         schedule_work(&data->ih_work);
1371
1372         return 0;
1373 }
1374
1375 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1376                 struct ras_ih_if *info)
1377 {
1378         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1379         struct ras_ih_data *data;
1380
1381         if (!obj)
1382                 return -EINVAL;
1383
1384         data = &obj->ih_data;
1385         if (data->inuse == 0)
1386                 return 0;
1387
1388         cancel_work_sync(&data->ih_work);
1389
1390         kfree(data->ring);
1391         memset(data, 0, sizeof(*data));
1392         put_obj(obj);
1393
1394         return 0;
1395 }
1396
1397 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1398                 struct ras_ih_if *info)
1399 {
1400         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1401         struct ras_ih_data *data;
1402
1403         if (!obj) {
1404                 /* in case we registe the IH before enable ras feature */
1405                 obj = amdgpu_ras_create_obj(adev, &info->head);
1406                 if (!obj)
1407                         return -EINVAL;
1408         } else
1409                 get_obj(obj);
1410
1411         data = &obj->ih_data;
1412         /* add the callback.etc */
1413         *data = (struct ras_ih_data) {
1414                 .inuse = 0,
1415                 .cb = info->cb,
1416                 .element_size = sizeof(struct amdgpu_iv_entry),
1417                 .rptr = 0,
1418                 .wptr = 0,
1419         };
1420
1421         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1422
1423         data->aligned_element_size = ALIGN(data->element_size, 8);
1424         /* the ring can store 64 iv entries. */
1425         data->ring_size = 64 * data->aligned_element_size;
1426         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1427         if (!data->ring) {
1428                 put_obj(obj);
1429                 return -ENOMEM;
1430         }
1431
1432         /* IH is ready */
1433         data->inuse = 1;
1434
1435         return 0;
1436 }
1437
1438 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1439 {
1440         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1441         struct ras_manager *obj, *tmp;
1442
1443         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1444                 struct ras_ih_if info = {
1445                         .head = obj->head,
1446                 };
1447                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1448         }
1449
1450         return 0;
1451 }
1452 /* ih end */
1453
1454 /* traversal all IPs except NBIO to query error counter */
1455 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1456 {
1457         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1458         struct ras_manager *obj;
1459
1460         if (!con)
1461                 return;
1462
1463         list_for_each_entry(obj, &con->head, node) {
1464                 struct ras_query_if info = {
1465                         .head = obj->head,
1466                 };
1467
1468                 /*
1469                  * PCIE_BIF IP has one different isr by ras controller
1470                  * interrupt, the specific ras counter query will be
1471                  * done in that isr. So skip such block from common
1472                  * sync flood interrupt isr calling.
1473                  */
1474                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1475                         continue;
1476
1477                 amdgpu_ras_error_query(adev, &info);
1478         }
1479 }
1480
1481 /* Parse RdRspStatus and WrRspStatus */
1482 void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1483                 struct ras_query_if *info)
1484 {
1485         /*
1486          * Only two block need to query read/write
1487          * RspStatus at current state
1488          */
1489         switch (info->head.block) {
1490         case AMDGPU_RAS_BLOCK__GFX:
1491                 if (adev->gfx.funcs->query_ras_error_status)
1492                         adev->gfx.funcs->query_ras_error_status(adev);
1493                 break;
1494         case AMDGPU_RAS_BLOCK__MMHUB:
1495                 if (adev->mmhub.funcs->query_ras_error_status)
1496                         adev->mmhub.funcs->query_ras_error_status(adev);
1497                 break;
1498         default:
1499                 break;
1500         }
1501 }
1502
1503 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1504 {
1505         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1506         struct ras_manager *obj;
1507
1508         if (!con)
1509                 return;
1510
1511         list_for_each_entry(obj, &con->head, node) {
1512                 struct ras_query_if info = {
1513                         .head = obj->head,
1514                 };
1515
1516                 amdgpu_ras_error_status_query(adev, &info);
1517         }
1518 }
1519
1520 /* recovery begin */
1521
1522 /* return 0 on success.
1523  * caller need free bps.
1524  */
1525 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1526                 struct ras_badpage **bps, unsigned int *count)
1527 {
1528         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1529         struct ras_err_handler_data *data;
1530         int i = 0;
1531         int ret = 0;
1532
1533         if (!con || !con->eh_data || !bps || !count)
1534                 return -EINVAL;
1535
1536         mutex_lock(&con->recovery_lock);
1537         data = con->eh_data;
1538         if (!data || data->count == 0) {
1539                 *bps = NULL;
1540                 ret = -EINVAL;
1541                 goto out;
1542         }
1543
1544         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1545         if (!*bps) {
1546                 ret = -ENOMEM;
1547                 goto out;
1548         }
1549
1550         for (; i < data->count; i++) {
1551                 (*bps)[i] = (struct ras_badpage){
1552                         .bp = data->bps[i].retired_page,
1553                         .size = AMDGPU_GPU_PAGE_SIZE,
1554                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1555                 };
1556                 ret = amdgpu_vram_mgr_query_page_status(
1557                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1558                                 data->bps[i].retired_page);
1559                 if (ret == -EBUSY)
1560                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1561                 else if (ret == -ENOENT)
1562                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1563         }
1564
1565         *count = data->count;
1566 out:
1567         mutex_unlock(&con->recovery_lock);
1568         return ret;
1569 }
1570
1571 static void amdgpu_ras_do_recovery(struct work_struct *work)
1572 {
1573         struct amdgpu_ras *ras =
1574                 container_of(work, struct amdgpu_ras, recovery_work);
1575         struct amdgpu_device *remote_adev = NULL;
1576         struct amdgpu_device *adev = ras->adev;
1577         struct list_head device_list, *device_list_handle =  NULL;
1578
1579         if (!ras->disable_ras_err_cnt_harvest) {
1580                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1581
1582                 /* Build list of devices to query RAS related errors */
1583                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1584                         device_list_handle = &hive->device_list;
1585                 } else {
1586                         INIT_LIST_HEAD(&device_list);
1587                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1588                         device_list_handle = &device_list;
1589                 }
1590
1591                 list_for_each_entry(remote_adev,
1592                                 device_list_handle, gmc.xgmi.head) {
1593                         amdgpu_ras_query_err_status(remote_adev);
1594                         amdgpu_ras_log_on_err_counter(remote_adev);
1595                 }
1596
1597                 amdgpu_put_xgmi_hive(hive);
1598         }
1599
1600         if (amdgpu_device_should_recover_gpu(ras->adev))
1601                 amdgpu_device_gpu_recover(ras->adev, NULL);
1602         atomic_set(&ras->in_recovery, 0);
1603 }
1604
1605 /* alloc/realloc bps array */
1606 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1607                 struct ras_err_handler_data *data, int pages)
1608 {
1609         unsigned int old_space = data->count + data->space_left;
1610         unsigned int new_space = old_space + pages;
1611         unsigned int align_space = ALIGN(new_space, 512);
1612         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1613
1614         if (!bps) {
1615                 kfree(bps);
1616                 return -ENOMEM;
1617         }
1618
1619         if (data->bps) {
1620                 memcpy(bps, data->bps,
1621                                 data->count * sizeof(*data->bps));
1622                 kfree(data->bps);
1623         }
1624
1625         data->bps = bps;
1626         data->space_left += align_space - old_space;
1627         return 0;
1628 }
1629
1630 /* it deal with vram only. */
1631 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1632                 struct eeprom_table_record *bps, int pages)
1633 {
1634         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1635         struct ras_err_handler_data *data;
1636         int ret = 0;
1637         uint32_t i;
1638
1639         if (!con || !con->eh_data || !bps || pages <= 0)
1640                 return 0;
1641
1642         mutex_lock(&con->recovery_lock);
1643         data = con->eh_data;
1644         if (!data)
1645                 goto out;
1646
1647         for (i = 0; i < pages; i++) {
1648                 if (amdgpu_ras_check_bad_page_unlock(con,
1649                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1650                         continue;
1651
1652                 if (!data->space_left &&
1653                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1654                         ret = -ENOMEM;
1655                         goto out;
1656                 }
1657
1658                 amdgpu_vram_mgr_reserve_range(
1659                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1660                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1661                         AMDGPU_GPU_PAGE_SIZE);
1662
1663                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1664                 data->count++;
1665                 data->space_left--;
1666         }
1667 out:
1668         mutex_unlock(&con->recovery_lock);
1669
1670         return ret;
1671 }
1672
1673 /*
1674  * write error record array to eeprom, the function should be
1675  * protected by recovery_lock
1676  */
1677 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1678 {
1679         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1680         struct ras_err_handler_data *data;
1681         struct amdgpu_ras_eeprom_control *control;
1682         int save_count;
1683
1684         if (!con || !con->eh_data)
1685                 return 0;
1686
1687         control = &con->eeprom_control;
1688         data = con->eh_data;
1689         save_count = data->count - control->num_recs;
1690         /* only new entries are saved */
1691         if (save_count > 0) {
1692                 if (amdgpu_ras_eeprom_process_recods(control,
1693                                                         &data->bps[control->num_recs],
1694                                                         true,
1695                                                         save_count)) {
1696                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1697                         return -EIO;
1698                 }
1699
1700                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1701         }
1702
1703         return 0;
1704 }
1705
1706 /*
1707  * read error record array in eeprom and reserve enough space for
1708  * storing new bad pages
1709  */
1710 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1711 {
1712         struct amdgpu_ras_eeprom_control *control =
1713                                         &adev->psp.ras.ras->eeprom_control;
1714         struct eeprom_table_record *bps = NULL;
1715         int ret = 0;
1716
1717         /* no bad page record, skip eeprom access */
1718         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1719                 return ret;
1720
1721         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1722         if (!bps)
1723                 return -ENOMEM;
1724
1725         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1726                 control->num_recs)) {
1727                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1728                 ret = -EIO;
1729                 goto out;
1730         }
1731
1732         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1733
1734 out:
1735         kfree(bps);
1736         return ret;
1737 }
1738
1739 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1740                                 uint64_t addr)
1741 {
1742         struct ras_err_handler_data *data = con->eh_data;
1743         int i;
1744
1745         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1746         for (i = 0; i < data->count; i++)
1747                 if (addr == data->bps[i].retired_page)
1748                         return true;
1749
1750         return false;
1751 }
1752
1753 /*
1754  * check if an address belongs to bad page
1755  *
1756  * Note: this check is only for umc block
1757  */
1758 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1759                                 uint64_t addr)
1760 {
1761         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1762         bool ret = false;
1763
1764         if (!con || !con->eh_data)
1765                 return ret;
1766
1767         mutex_lock(&con->recovery_lock);
1768         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1769         mutex_unlock(&con->recovery_lock);
1770         return ret;
1771 }
1772
1773 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1774                                         uint32_t max_length)
1775 {
1776         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1777         int tmp_threshold = amdgpu_bad_page_threshold;
1778         u64 val;
1779
1780         /*
1781          * Justification of value bad_page_cnt_threshold in ras structure
1782          *
1783          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1784          * in eeprom, and introduce two scenarios accordingly.
1785          *
1786          * Bad page retirement enablement:
1787          *    - If amdgpu_bad_page_threshold = -1,
1788          *      bad_page_cnt_threshold = typical value by formula.
1789          *
1790          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1791          *      max record length in eeprom, use it directly.
1792          *
1793          * Bad page retirement disablement:
1794          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1795          *      functionality is disabled, and bad_page_cnt_threshold will
1796          *      take no effect.
1797          */
1798
1799         if (tmp_threshold < -1)
1800                 tmp_threshold = -1;
1801         else if (tmp_threshold > max_length)
1802                 tmp_threshold = max_length;
1803
1804         if (tmp_threshold == -1) {
1805                 val = adev->gmc.mc_vram_size;
1806                 do_div(val, RAS_BAD_PAGE_RATE);
1807                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1808                                                 max_length);
1809         } else {
1810                 con->bad_page_cnt_threshold = tmp_threshold;
1811         }
1812 }
1813
1814 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1815 {
1816         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1817         struct ras_err_handler_data **data;
1818         uint32_t max_eeprom_records_len = 0;
1819         bool exc_err_limit = false;
1820         int ret;
1821
1822         if (con)
1823                 data = &con->eh_data;
1824         else
1825                 return 0;
1826
1827         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1828         if (!*data) {
1829                 ret = -ENOMEM;
1830                 goto out;
1831         }
1832
1833         mutex_init(&con->recovery_lock);
1834         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1835         atomic_set(&con->in_recovery, 0);
1836         con->adev = adev;
1837
1838         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1839         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1840
1841         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1842         /*
1843          * This calling fails when exc_err_limit is true or
1844          * ret != 0.
1845          */
1846         if (exc_err_limit || ret)
1847                 goto free;
1848
1849         if (con->eeprom_control.num_recs) {
1850                 ret = amdgpu_ras_load_bad_pages(adev);
1851                 if (ret)
1852                         goto free;
1853         }
1854
1855         return 0;
1856
1857 free:
1858         kfree((*data)->bps);
1859         kfree(*data);
1860         con->eh_data = NULL;
1861 out:
1862         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1863
1864         /*
1865          * Except error threshold exceeding case, other failure cases in this
1866          * function would not fail amdgpu driver init.
1867          */
1868         if (!exc_err_limit)
1869                 ret = 0;
1870         else
1871                 ret = -EINVAL;
1872
1873         return ret;
1874 }
1875
1876 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1877 {
1878         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1879         struct ras_err_handler_data *data = con->eh_data;
1880
1881         /* recovery_init failed to init it, fini is useless */
1882         if (!data)
1883                 return 0;
1884
1885         cancel_work_sync(&con->recovery_work);
1886
1887         mutex_lock(&con->recovery_lock);
1888         con->eh_data = NULL;
1889         kfree(data->bps);
1890         kfree(data);
1891         mutex_unlock(&con->recovery_lock);
1892
1893         return 0;
1894 }
1895 /* recovery end */
1896
1897 /* return 0 if ras will reset gpu and repost.*/
1898 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1899                 unsigned int block)
1900 {
1901         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1902
1903         if (!ras)
1904                 return -EINVAL;
1905
1906         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1907         return 0;
1908 }
1909
1910 static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev)
1911 {
1912         if (adev->asic_type != CHIP_VEGA10 &&
1913                 adev->asic_type != CHIP_VEGA20 &&
1914                 adev->asic_type != CHIP_ARCTURUS &&
1915                 adev->asic_type != CHIP_SIENNA_CICHLID)
1916                 return 1;
1917         else
1918                 return 0;
1919 }
1920
1921 /*
1922  * check hardware's ras ability which will be saved in hw_supported.
1923  * if hardware does not support ras, we can skip some ras initializtion and
1924  * forbid some ras operations from IP.
1925  * if software itself, say boot parameter, limit the ras ability. We still
1926  * need allow IP do some limited operations, like disable. In such case,
1927  * we have to initialize ras as normal. but need check if operation is
1928  * allowed or not in each function.
1929  */
1930 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1931                 uint32_t *hw_supported, uint32_t *supported)
1932 {
1933         *hw_supported = 0;
1934         *supported = 0;
1935
1936         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
1937                 amdgpu_ras_check_asic_type(adev))
1938                 return;
1939
1940         if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
1941                 dev_info(adev->dev, "HBM ECC is active.\n");
1942                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
1943                                 1 << AMDGPU_RAS_BLOCK__DF);
1944         } else
1945                 dev_info(adev->dev, "HBM ECC is not presented.\n");
1946
1947         if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
1948                 dev_info(adev->dev, "SRAM ECC is active.\n");
1949                 *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
1950                                 1 << AMDGPU_RAS_BLOCK__DF);
1951         } else
1952                 dev_info(adev->dev, "SRAM ECC is not presented.\n");
1953
1954         /* hw_supported needs to be aligned with RAS block mask. */
1955         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
1956
1957         *supported = amdgpu_ras_enable == 0 ?
1958                         0 : *hw_supported & amdgpu_ras_mask;
1959         adev->ras_features = *supported;
1960 }
1961
1962 int amdgpu_ras_init(struct amdgpu_device *adev)
1963 {
1964         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1965         int r;
1966
1967         if (con)
1968                 return 0;
1969
1970         con = kmalloc(sizeof(struct amdgpu_ras) +
1971                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1972                         GFP_KERNEL|__GFP_ZERO);
1973         if (!con)
1974                 return -ENOMEM;
1975
1976         con->objs = (struct ras_manager *)(con + 1);
1977
1978         amdgpu_ras_set_context(adev, con);
1979
1980         amdgpu_ras_check_supported(adev, &con->hw_supported,
1981                         &con->supported);
1982         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
1983                 r = 0;
1984                 goto release_con;
1985         }
1986
1987         con->features = 0;
1988         INIT_LIST_HEAD(&con->head);
1989         /* Might need get this flag from vbios. */
1990         con->flags = RAS_DEFAULT_FLAGS;
1991
1992         if (adev->nbio.funcs->init_ras_controller_interrupt) {
1993                 r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
1994                 if (r)
1995                         goto release_con;
1996         }
1997
1998         if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
1999                 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
2000                 if (r)
2001                         goto release_con;
2002         }
2003
2004         if (amdgpu_ras_fs_init(adev)) {
2005                 r = -EINVAL;
2006                 goto release_con;
2007         }
2008
2009         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2010                         "hardware ability[%x] ras_mask[%x]\n",
2011                         con->hw_supported, con->supported);
2012         return 0;
2013 release_con:
2014         amdgpu_ras_set_context(adev, NULL);
2015         kfree(con);
2016
2017         return r;
2018 }
2019
2020 /* helper function to handle common stuff in ip late init phase */
2021 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2022                          struct ras_common_if *ras_block,
2023                          struct ras_fs_if *fs_info,
2024                          struct ras_ih_if *ih_info)
2025 {
2026         int r;
2027
2028         /* disable RAS feature per IP block if it is not supported */
2029         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2030                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2031                 return 0;
2032         }
2033
2034         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2035         if (r) {
2036                 if (r == -EAGAIN) {
2037                         /* request gpu reset. will run again */
2038                         amdgpu_ras_request_reset_on_boot(adev,
2039                                         ras_block->block);
2040                         return 0;
2041                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2042                         /* in resume phase, if fail to enable ras,
2043                          * clean up all ras fs nodes, and disable ras */
2044                         goto cleanup;
2045                 } else
2046                         return r;
2047         }
2048
2049         /* in resume phase, no need to create ras fs node */
2050         if (adev->in_suspend || amdgpu_in_reset(adev))
2051                 return 0;
2052
2053         if (ih_info->cb) {
2054                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2055                 if (r)
2056                         goto interrupt;
2057         }
2058
2059         r = amdgpu_ras_sysfs_create(adev, fs_info);
2060         if (r)
2061                 goto sysfs;
2062
2063         return 0;
2064 cleanup:
2065         amdgpu_ras_sysfs_remove(adev, ras_block);
2066 sysfs:
2067         if (ih_info->cb)
2068                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2069 interrupt:
2070         amdgpu_ras_feature_enable(adev, ras_block, 0);
2071         return r;
2072 }
2073
2074 /* helper function to remove ras fs node and interrupt handler */
2075 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2076                           struct ras_common_if *ras_block,
2077                           struct ras_ih_if *ih_info)
2078 {
2079         if (!ras_block || !ih_info)
2080                 return;
2081
2082         amdgpu_ras_sysfs_remove(adev, ras_block);
2083         if (ih_info->cb)
2084                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2085         amdgpu_ras_feature_enable(adev, ras_block, 0);
2086 }
2087
2088 /* do some init work after IP late init as dependence.
2089  * and it runs in resume/gpu reset/booting up cases.
2090  */
2091 void amdgpu_ras_resume(struct amdgpu_device *adev)
2092 {
2093         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2094         struct ras_manager *obj, *tmp;
2095
2096         if (!con)
2097                 return;
2098
2099         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2100                 /* Set up all other IPs which are not implemented. There is a
2101                  * tricky thing that IP's actual ras error type should be
2102                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2103                  * ERROR_NONE make sense anyway.
2104                  */
2105                 amdgpu_ras_enable_all_features(adev, 1);
2106
2107                 /* We enable ras on all hw_supported block, but as boot
2108                  * parameter might disable some of them and one or more IP has
2109                  * not implemented yet. So we disable them on behalf.
2110                  */
2111                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2112                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2113                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2114                                 /* there should be no any reference. */
2115                                 WARN_ON(alive_obj(obj));
2116                         }
2117                 }
2118         }
2119
2120         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2121                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2122                 /* setup ras obj state as disabled.
2123                  * for init_by_vbios case.
2124                  * if we want to enable ras, just enable it in a normal way.
2125                  * If we want do disable it, need setup ras obj as enabled,
2126                  * then issue another TA disable cmd.
2127                  * See feature_enable_on_boot
2128                  */
2129                 amdgpu_ras_disable_all_features(adev, 1);
2130                 amdgpu_ras_reset_gpu(adev);
2131         }
2132 }
2133
2134 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2135 {
2136         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2137
2138         if (!con)
2139                 return;
2140
2141         amdgpu_ras_disable_all_features(adev, 0);
2142         /* Make sure all ras objects are disabled. */
2143         if (con->features)
2144                 amdgpu_ras_disable_all_features(adev, 1);
2145 }
2146
2147 /* do some fini work before IP fini as dependence */
2148 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2149 {
2150         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2151
2152         if (!con)
2153                 return 0;
2154
2155         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2156         amdgpu_ras_disable_all_features(adev, 0);
2157         amdgpu_ras_recovery_fini(adev);
2158         return 0;
2159 }
2160
2161 int amdgpu_ras_fini(struct amdgpu_device *adev)
2162 {
2163         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2164
2165         if (!con)
2166                 return 0;
2167
2168         amdgpu_ras_fs_fini(adev);
2169         amdgpu_ras_interrupt_remove_all(adev);
2170
2171         WARN(con->features, "Feature mask is not cleared");
2172
2173         if (con->features)
2174                 amdgpu_ras_disable_all_features(adev, 1);
2175
2176         amdgpu_ras_set_context(adev, NULL);
2177         kfree(con);
2178
2179         return 0;
2180 }
2181
2182 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2183 {
2184         uint32_t hw_supported, supported;
2185
2186         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2187         if (!hw_supported)
2188                 return;
2189
2190         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2191                 dev_info(adev->dev, "uncorrectable hardware error"
2192                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2193
2194                 amdgpu_ras_reset_gpu(adev);
2195         }
2196 }
2197
2198 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2199 {
2200         if (adev->asic_type == CHIP_VEGA20 &&
2201             adev->pm.fw_version <= 0x283400) {
2202                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2203                                 amdgpu_ras_intr_triggered();
2204         }
2205
2206         return false;
2207 }
2208
2209 bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev)
2210 {
2211         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2212         bool exc_err_limit = false;
2213
2214         if (con && (amdgpu_bad_page_threshold != 0))
2215                 amdgpu_ras_eeprom_check_err_threshold(&con->eeprom_control,
2216                                                 &exc_err_limit);
2217
2218         /*
2219          * We are only interested in variable exc_err_limit,
2220          * as it says if GPU is in bad state or not.
2221          */
2222         return exc_err_limit;
2223 }