1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/device.h>
25 #include <linux/export.h>
26 #include <linux/err.h>
28 #include <linux/file.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/compat.h>
33 #include <uapi/linux/kfd_ioctl.h>
34 #include <linux/time.h>
36 #include <linux/mman.h>
37 #include <linux/ptrace.h>
38 #include <linux/dma-buf.h>
39 #include <linux/processor.h>
41 #include "kfd_device_queue_manager.h"
43 #include "amdgpu_amdkfd.h"
44 #include "kfd_smi_events.h"
45 #include "amdgpu_dma_buf.h"
46 #include "kfd_debug.h"
48 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
49 static int kfd_open(struct inode *, struct file *);
50 static int kfd_release(struct inode *, struct file *);
51 static int kfd_mmap(struct file *, struct vm_area_struct *);
53 static const char kfd_dev_name[] = "kfd";
55 static const struct file_operations kfd_fops = {
57 .unlocked_ioctl = kfd_ioctl,
58 .compat_ioctl = compat_ptr_ioctl,
60 .release = kfd_release,
64 static int kfd_char_dev_major = -1;
65 struct device *kfd_device;
66 static const struct class kfd_class = {
70 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
72 struct kfd_process_device *pdd;
74 mutex_lock(&p->mutex);
75 pdd = kfd_process_device_data_by_id(p, gpu_id);
80 mutex_unlock(&p->mutex);
84 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
86 mutex_unlock(&pdd->process->mutex);
89 int kfd_chardev_init(void)
93 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
94 err = kfd_char_dev_major;
96 goto err_register_chrdev;
98 err = class_register(&kfd_class);
100 goto err_class_create;
102 kfd_device = device_create(&kfd_class, NULL,
103 MKDEV(kfd_char_dev_major, 0),
105 err = PTR_ERR(kfd_device);
106 if (IS_ERR(kfd_device))
107 goto err_device_create;
112 class_unregister(&kfd_class);
114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
119 void kfd_chardev_exit(void)
121 device_destroy(&kfd_class, MKDEV(kfd_char_dev_major, 0));
122 class_unregister(&kfd_class);
123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
128 static int kfd_open(struct inode *inode, struct file *filep)
130 struct kfd_process *process;
131 bool is_32bit_user_mode;
133 if (iminor(inode) != 0)
136 is_32bit_user_mode = in_compat_syscall();
138 if (is_32bit_user_mode) {
140 "Process %d (32-bit) failed to open /dev/kfd\n"
141 "32-bit processes are not supported by amdkfd\n",
146 process = kfd_create_process(current);
148 return PTR_ERR(process);
150 if (kfd_process_init_cwsr_apu(process, filep)) {
151 kfd_unref_process(process);
155 /* filep now owns the reference returned by kfd_create_process */
156 filep->private_data = process;
158 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
159 process->pasid, process->is_32bit_user_mode);
164 static int kfd_release(struct inode *inode, struct file *filep)
166 struct kfd_process *process = filep->private_data;
169 kfd_unref_process(process);
174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
177 struct kfd_ioctl_get_version_args *args = data;
179 args->major_version = KFD_IOCTL_MAJOR_VERSION;
180 args->minor_version = KFD_IOCTL_MINOR_VERSION;
185 static int set_queue_properties_from_user(struct queue_properties *q_properties,
186 struct kfd_ioctl_create_queue_args *args)
189 * Repurpose queue percentage to accommodate new features:
190 * bit 0-7: queue percentage
191 * bit 8-15: pm4_target_xcc
193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
203 if ((args->ring_base_address) &&
204 (!access_ok((const void __user *) args->ring_base_address,
205 sizeof(uint64_t)))) {
206 pr_err("Can't access ring base address\n");
210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
211 pr_err("Ring size must be a power of 2 or 0\n");
215 if (!access_ok((const void __user *) args->read_pointer_address,
217 pr_err("Can't access read pointer\n");
221 if (!access_ok((const void __user *) args->write_pointer_address,
223 pr_err("Can't access write pointer\n");
227 if (args->eop_buffer_address &&
228 !access_ok((const void __user *) args->eop_buffer_address,
230 pr_debug("Can't access eop buffer");
234 if (args->ctx_save_restore_address &&
235 !access_ok((const void __user *) args->ctx_save_restore_address,
237 pr_debug("Can't access ctx save restore buffer");
241 q_properties->is_interop = false;
242 q_properties->is_gws = false;
243 q_properties->queue_percent = args->queue_percentage & 0xFF;
244 /* bit 8-15 are repurposed to be PM4 target XCC */
245 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
246 q_properties->priority = args->queue_priority;
247 q_properties->queue_address = args->ring_base_address;
248 q_properties->queue_size = args->ring_size;
249 q_properties->read_ptr = (void __user *)args->read_pointer_address;
250 q_properties->write_ptr = (void __user *)args->write_pointer_address;
251 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
252 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
253 q_properties->ctx_save_restore_area_address =
254 args->ctx_save_restore_address;
255 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
256 q_properties->ctl_stack_size = args->ctl_stack_size;
257 q_properties->sdma_engine_id = args->sdma_engine_id;
258 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
259 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
260 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
261 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
262 q_properties->type = KFD_QUEUE_TYPE_SDMA;
263 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
264 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
265 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID)
266 q_properties->type = KFD_QUEUE_TYPE_SDMA_BY_ENG_ID;
270 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
271 q_properties->format = KFD_QUEUE_FORMAT_AQL;
273 q_properties->format = KFD_QUEUE_FORMAT_PM4;
275 pr_debug("Queue Percentage: %d, %d\n",
276 q_properties->queue_percent, args->queue_percentage);
278 pr_debug("Queue Priority: %d, %d\n",
279 q_properties->priority, args->queue_priority);
281 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
282 q_properties->queue_address, args->ring_base_address);
284 pr_debug("Queue Size: 0x%llX, %u\n",
285 q_properties->queue_size, args->ring_size);
287 pr_debug("Queue r/w Pointers: %px, %px\n",
288 q_properties->read_ptr,
289 q_properties->write_ptr);
291 pr_debug("Queue Format: %d\n", q_properties->format);
293 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
295 pr_debug("Queue CTX save area: 0x%llX\n",
296 q_properties->ctx_save_restore_area_address);
301 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
304 struct kfd_ioctl_create_queue_args *args = data;
305 struct kfd_node *dev;
307 unsigned int queue_id;
308 struct kfd_process_device *pdd;
309 struct queue_properties q_properties;
310 uint32_t doorbell_offset_in_process = 0;
312 memset(&q_properties, 0, sizeof(struct queue_properties));
314 pr_debug("Creating queue ioctl\n");
316 err = set_queue_properties_from_user(&q_properties, args);
320 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
322 mutex_lock(&p->mutex);
324 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
326 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
332 pdd = kfd_bind_process_to_device(dev, p);
335 goto err_bind_process;
338 if (q_properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) {
339 int max_sdma_eng_id = kfd_get_num_sdma_engines(dev) +
340 kfd_get_num_xgmi_sdma_engines(dev) - 1;
342 if (q_properties.sdma_engine_id > max_sdma_eng_id) {
344 pr_err("sdma_engine_id %i exceeds maximum id of %i\n",
345 q_properties.sdma_engine_id, max_sdma_eng_id);
346 goto err_sdma_engine_id;
350 if (!pdd->qpd.proc_doorbells) {
351 err = kfd_alloc_process_doorbells(dev->kfd, pdd);
353 pr_debug("failed to allocate process doorbells\n");
354 goto err_bind_process;
358 err = kfd_queue_acquire_buffers(pdd, &q_properties);
360 pr_debug("failed to acquire user queue buffers\n");
361 goto err_acquire_queue_buf;
364 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
368 err = pqm_create_queue(&p->pqm, dev, &q_properties, &queue_id,
369 NULL, NULL, NULL, &doorbell_offset_in_process);
371 goto err_create_queue;
373 args->queue_id = queue_id;
376 /* Return gpu_id as doorbell offset for mmap usage */
377 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
378 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
379 if (KFD_IS_SOC15(dev))
380 /* On SOC15 ASICs, include the doorbell offset within the
381 * process doorbell frame, which is 2 pages.
383 args->doorbell_offset |= doorbell_offset_in_process;
385 mutex_unlock(&p->mutex);
387 pr_debug("Queue id %d was created successfully\n", args->queue_id);
389 pr_debug("Ring buffer address == 0x%016llX\n",
390 args->ring_base_address);
392 pr_debug("Read ptr address == 0x%016llX\n",
393 args->read_pointer_address);
395 pr_debug("Write ptr address == 0x%016llX\n",
396 args->write_pointer_address);
398 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0);
402 kfd_queue_unref_bo_vas(pdd, &q_properties);
403 kfd_queue_release_buffers(pdd, &q_properties);
404 err_acquire_queue_buf:
408 mutex_unlock(&p->mutex);
412 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
416 struct kfd_ioctl_destroy_queue_args *args = data;
418 pr_debug("Destroying queue id %d for pasid 0x%x\n",
422 mutex_lock(&p->mutex);
424 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
426 mutex_unlock(&p->mutex);
430 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
434 struct kfd_ioctl_update_queue_args *args = data;
435 struct queue_properties properties;
438 * Repurpose queue percentage to accommodate new features:
439 * bit 0-7: queue percentage
440 * bit 8-15: pm4_target_xcc
442 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
443 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
447 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
448 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
452 if ((args->ring_base_address) &&
453 (!access_ok((const void __user *) args->ring_base_address,
454 sizeof(uint64_t)))) {
455 pr_err("Can't access ring base address\n");
459 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
460 pr_err("Ring size must be a power of 2 or 0\n");
464 properties.queue_address = args->ring_base_address;
465 properties.queue_size = args->ring_size;
466 properties.queue_percent = args->queue_percentage & 0xFF;
467 /* bit 8-15 are repurposed to be PM4 target XCC */
468 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
469 properties.priority = args->queue_priority;
471 pr_debug("Updating queue id %d for pasid 0x%x\n",
472 args->queue_id, p->pasid);
474 mutex_lock(&p->mutex);
476 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
478 mutex_unlock(&p->mutex);
483 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
487 const int max_num_cus = 1024;
488 struct kfd_ioctl_set_cu_mask_args *args = data;
489 struct mqd_update_info minfo = {0};
490 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
491 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
493 if ((args->num_cu_mask % 32) != 0) {
494 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
499 minfo.cu_mask.count = args->num_cu_mask;
500 if (minfo.cu_mask.count == 0) {
501 pr_debug("CU mask cannot be 0");
505 /* To prevent an unreasonably large CU mask size, set an arbitrary
506 * limit of max_num_cus bits. We can then just drop any CU mask bits
507 * past max_num_cus bits and just use the first max_num_cus bits.
509 if (minfo.cu_mask.count > max_num_cus) {
510 pr_debug("CU mask cannot be greater than 1024 bits");
511 minfo.cu_mask.count = max_num_cus;
512 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
515 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
516 if (!minfo.cu_mask.ptr)
519 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
521 pr_debug("Could not copy CU mask from userspace");
526 mutex_lock(&p->mutex);
528 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
530 mutex_unlock(&p->mutex);
533 kfree(minfo.cu_mask.ptr);
537 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
538 struct kfd_process *p, void *data)
540 struct kfd_ioctl_get_queue_wave_state_args *args = data;
543 mutex_lock(&p->mutex);
545 r = pqm_get_wave_state(&p->pqm, args->queue_id,
546 (void __user *)args->ctl_stack_address,
547 &args->ctl_stack_used_size,
548 &args->save_area_used_size);
550 mutex_unlock(&p->mutex);
555 static int kfd_ioctl_set_memory_policy(struct file *filep,
556 struct kfd_process *p, void *data)
558 struct kfd_ioctl_set_memory_policy_args *args = data;
560 struct kfd_process_device *pdd;
561 enum cache_policy default_policy, alternate_policy;
563 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
564 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
568 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
569 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
573 mutex_lock(&p->mutex);
574 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
576 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
581 pdd = kfd_bind_process_to_device(pdd->dev, p);
587 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
588 ? cache_policy_coherent : cache_policy_noncoherent;
591 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
592 ? cache_policy_coherent : cache_policy_noncoherent;
594 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
598 (void __user *)args->alternate_aperture_base,
599 args->alternate_aperture_size))
604 mutex_unlock(&p->mutex);
609 static int kfd_ioctl_set_trap_handler(struct file *filep,
610 struct kfd_process *p, void *data)
612 struct kfd_ioctl_set_trap_handler_args *args = data;
614 struct kfd_process_device *pdd;
616 mutex_lock(&p->mutex);
618 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
624 pdd = kfd_bind_process_to_device(pdd->dev, p);
630 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
634 mutex_unlock(&p->mutex);
639 static int kfd_ioctl_dbg_register(struct file *filep,
640 struct kfd_process *p, void *data)
645 static int kfd_ioctl_dbg_unregister(struct file *filep,
646 struct kfd_process *p, void *data)
651 static int kfd_ioctl_dbg_address_watch(struct file *filep,
652 struct kfd_process *p, void *data)
657 /* Parse and generate fixed size data structure for wave control */
658 static int kfd_ioctl_dbg_wave_control(struct file *filep,
659 struct kfd_process *p, void *data)
664 static int kfd_ioctl_get_clock_counters(struct file *filep,
665 struct kfd_process *p, void *data)
667 struct kfd_ioctl_get_clock_counters_args *args = data;
668 struct kfd_process_device *pdd;
670 mutex_lock(&p->mutex);
671 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
672 mutex_unlock(&p->mutex);
674 /* Reading GPU clock counter from KGD */
675 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
677 /* Node without GPU resource */
678 args->gpu_clock_counter = 0;
680 /* No access to rdtsc. Using raw monotonic time */
681 args->cpu_clock_counter = ktime_get_raw_ns();
682 args->system_clock_counter = ktime_get_boottime_ns();
684 /* Since the counter is in nano-seconds we use 1GHz frequency */
685 args->system_clock_freq = 1000000000;
691 static int kfd_ioctl_get_process_apertures(struct file *filp,
692 struct kfd_process *p, void *data)
694 struct kfd_ioctl_get_process_apertures_args *args = data;
695 struct kfd_process_device_apertures *pAperture;
698 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
700 args->num_of_nodes = 0;
702 mutex_lock(&p->mutex);
703 /* Run over all pdd of the process */
704 for (i = 0; i < p->n_pdds; i++) {
705 struct kfd_process_device *pdd = p->pdds[i];
708 &args->process_apertures[args->num_of_nodes];
709 pAperture->gpu_id = pdd->dev->id;
710 pAperture->lds_base = pdd->lds_base;
711 pAperture->lds_limit = pdd->lds_limit;
712 pAperture->gpuvm_base = pdd->gpuvm_base;
713 pAperture->gpuvm_limit = pdd->gpuvm_limit;
714 pAperture->scratch_base = pdd->scratch_base;
715 pAperture->scratch_limit = pdd->scratch_limit;
718 "node id %u\n", args->num_of_nodes);
720 "gpu id %u\n", pdd->dev->id);
722 "lds_base %llX\n", pdd->lds_base);
724 "lds_limit %llX\n", pdd->lds_limit);
726 "gpuvm_base %llX\n", pdd->gpuvm_base);
728 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
730 "scratch_base %llX\n", pdd->scratch_base);
732 "scratch_limit %llX\n", pdd->scratch_limit);
734 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
737 mutex_unlock(&p->mutex);
742 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
743 struct kfd_process *p, void *data)
745 struct kfd_ioctl_get_process_apertures_new_args *args = data;
746 struct kfd_process_device_apertures *pa;
750 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
752 if (args->num_of_nodes == 0) {
753 /* Return number of nodes, so that user space can alloacate
756 mutex_lock(&p->mutex);
757 args->num_of_nodes = p->n_pdds;
761 /* Fill in process-aperture information for all available
762 * nodes, but not more than args->num_of_nodes as that is
763 * the amount of memory allocated by user
765 pa = kcalloc(args->num_of_nodes, sizeof(struct kfd_process_device_apertures),
770 mutex_lock(&p->mutex);
773 args->num_of_nodes = 0;
778 /* Run over all pdd of the process */
779 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
780 struct kfd_process_device *pdd = p->pdds[i];
782 pa[i].gpu_id = pdd->dev->id;
783 pa[i].lds_base = pdd->lds_base;
784 pa[i].lds_limit = pdd->lds_limit;
785 pa[i].gpuvm_base = pdd->gpuvm_base;
786 pa[i].gpuvm_limit = pdd->gpuvm_limit;
787 pa[i].scratch_base = pdd->scratch_base;
788 pa[i].scratch_limit = pdd->scratch_limit;
791 "gpu id %u\n", pdd->dev->id);
793 "lds_base %llX\n", pdd->lds_base);
795 "lds_limit %llX\n", pdd->lds_limit);
797 "gpuvm_base %llX\n", pdd->gpuvm_base);
799 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
801 "scratch_base %llX\n", pdd->scratch_base);
803 "scratch_limit %llX\n", pdd->scratch_limit);
805 mutex_unlock(&p->mutex);
807 args->num_of_nodes = i;
809 (void __user *)args->kfd_process_device_apertures_ptr,
811 (i * sizeof(struct kfd_process_device_apertures)));
813 return ret ? -EFAULT : 0;
816 mutex_unlock(&p->mutex);
820 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
823 struct kfd_ioctl_create_event_args *args = data;
826 /* For dGPUs the event page is allocated in user mode. The
827 * handle is passed to KFD with the first call to this IOCTL
828 * through the event_page_offset field.
830 if (args->event_page_offset) {
831 mutex_lock(&p->mutex);
832 err = kfd_kmap_event_page(p, args->event_page_offset);
833 mutex_unlock(&p->mutex);
838 err = kfd_event_create(filp, p, args->event_type,
839 args->auto_reset != 0, args->node_id,
840 &args->event_id, &args->event_trigger_data,
841 &args->event_page_offset,
842 &args->event_slot_index);
844 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
848 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
851 struct kfd_ioctl_destroy_event_args *args = data;
853 return kfd_event_destroy(p, args->event_id);
856 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
859 struct kfd_ioctl_set_event_args *args = data;
861 return kfd_set_event(p, args->event_id);
864 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
867 struct kfd_ioctl_reset_event_args *args = data;
869 return kfd_reset_event(p, args->event_id);
872 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
875 struct kfd_ioctl_wait_events_args *args = data;
877 return kfd_wait_on_events(p, args->num_events,
878 (void __user *)args->events_ptr,
879 (args->wait_for_all != 0),
880 &args->timeout, &args->wait_result);
882 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
883 struct kfd_process *p, void *data)
885 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
886 struct kfd_process_device *pdd;
887 struct kfd_node *dev;
890 mutex_lock(&p->mutex);
891 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
898 pdd = kfd_bind_process_to_device(dev, p);
901 goto bind_process_to_device_fail;
904 pdd->qpd.sh_hidden_private_base = args->va_addr;
906 mutex_unlock(&p->mutex);
908 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
909 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
910 dev->kfd2kgd->set_scratch_backing_va(
911 dev->adev, args->va_addr, pdd->qpd.vmid);
915 bind_process_to_device_fail:
917 mutex_unlock(&p->mutex);
921 static int kfd_ioctl_get_tile_config(struct file *filep,
922 struct kfd_process *p, void *data)
924 struct kfd_ioctl_get_tile_config_args *args = data;
925 struct kfd_process_device *pdd;
926 struct tile_config config;
929 mutex_lock(&p->mutex);
930 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
931 mutex_unlock(&p->mutex);
935 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
937 args->gb_addr_config = config.gb_addr_config;
938 args->num_banks = config.num_banks;
939 args->num_ranks = config.num_ranks;
941 if (args->num_tile_configs > config.num_tile_configs)
942 args->num_tile_configs = config.num_tile_configs;
943 err = copy_to_user((void __user *)args->tile_config_ptr,
944 config.tile_config_ptr,
945 args->num_tile_configs * sizeof(uint32_t));
947 args->num_tile_configs = 0;
951 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
952 args->num_macro_tile_configs =
953 config.num_macro_tile_configs;
954 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
955 config.macro_tile_config_ptr,
956 args->num_macro_tile_configs * sizeof(uint32_t));
958 args->num_macro_tile_configs = 0;
965 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
968 struct kfd_ioctl_acquire_vm_args *args = data;
969 struct kfd_process_device *pdd;
970 struct file *drm_file;
973 drm_file = fget(args->drm_fd);
977 mutex_lock(&p->mutex);
978 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
985 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
989 ret = kfd_process_device_init_vm(pdd, drm_file);
993 /* On success, the PDD keeps the drm_file reference */
994 mutex_unlock(&p->mutex);
1001 mutex_unlock(&p->mutex);
1006 bool kfd_dev_is_large_bar(struct kfd_node *dev)
1008 if (dev->kfd->adev->debug_largebar) {
1009 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1013 if (dev->local_mem_info.local_mem_size_private == 0 &&
1014 dev->local_mem_info.local_mem_size_public > 0)
1017 if (dev->local_mem_info.local_mem_size_public == 0 &&
1018 dev->kfd->adev->gmc.is_app_apu) {
1019 pr_debug("APP APU, Consider like a large bar system\n");
1026 static int kfd_ioctl_get_available_memory(struct file *filep,
1027 struct kfd_process *p, void *data)
1029 struct kfd_ioctl_get_available_memory_args *args = data;
1030 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1034 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev,
1036 kfd_unlock_pdd(pdd);
1040 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1041 struct kfd_process *p, void *data)
1043 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1044 struct kfd_process_device *pdd;
1046 struct kfd_node *dev;
1049 uint64_t offset = args->mmap_offset;
1050 uint32_t flags = args->flags;
1052 if (args->size == 0)
1055 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1056 /* Flush pending deferred work to avoid racing with deferred actions
1057 * from previous memory map changes (e.g. munmap).
1059 svm_range_list_lock_and_flush_work(&p->svms, current->mm);
1060 mutex_lock(&p->svms.lock);
1061 mmap_write_unlock(current->mm);
1062 if (interval_tree_iter_first(&p->svms.objects,
1063 args->va_addr >> PAGE_SHIFT,
1064 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1065 pr_err("Address: 0x%llx already allocated by SVM\n",
1067 mutex_unlock(&p->svms.lock);
1071 /* When register user buffer check if it has been registered by svm by
1072 * buffer cpu virtual address.
1074 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) &&
1075 interval_tree_iter_first(&p->svms.objects,
1076 args->mmap_offset >> PAGE_SHIFT,
1077 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) {
1078 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n",
1080 mutex_unlock(&p->svms.lock);
1084 mutex_unlock(&p->svms.lock);
1086 mutex_lock(&p->mutex);
1087 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1095 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1096 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1097 !kfd_dev_is_large_bar(dev)) {
1098 pr_err("Alloc host visible vram on small bar is not allowed\n");
1103 pdd = kfd_bind_process_to_device(dev, p);
1109 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1110 if (args->size != kfd_doorbell_process_slice(dev->kfd)) {
1114 offset = kfd_get_process_doorbells(pdd);
1119 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1120 if (args->size != PAGE_SIZE) {
1124 offset = dev->adev->rmmio_remap.bus_addr;
1125 if (!offset || (PAGE_SIZE > 4096)) {
1131 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1132 dev->adev, args->va_addr, args->size,
1133 pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1139 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1140 if (idr_handle < 0) {
1145 /* Update the VRAM usage count */
1146 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1147 uint64_t size = args->size;
1149 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)
1151 atomic64_add(PAGE_ALIGN(size), &pdd->vram_usage);
1154 mutex_unlock(&p->mutex);
1156 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1157 args->mmap_offset = offset;
1159 /* MMIO is mapped through kfd device
1160 * Generate a kfd mmap offset
1162 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1163 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1164 | KFD_MMAP_GPU_ID(args->gpu_id);
1169 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1170 pdd->drm_priv, NULL);
1174 mutex_unlock(&p->mutex);
1178 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1179 struct kfd_process *p, void *data)
1181 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1182 struct kfd_process_device *pdd;
1187 mutex_lock(&p->mutex);
1189 * Safeguard to prevent user space from freeing signal BO.
1190 * It will be freed at process termination.
1192 if (p->signal_handle && (p->signal_handle == args->handle)) {
1193 pr_err("Free signal BO is not allowed\n");
1198 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1200 pr_err("Process device data doesn't exist\n");
1205 mem = kfd_process_device_translate_handle(
1206 pdd, GET_IDR_HANDLE(args->handle));
1212 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
1213 (struct kgd_mem *)mem, pdd->drm_priv, &size);
1215 /* If freeing the buffer failed, leave the handle in place for
1216 * clean-up during process tear-down.
1219 kfd_process_device_remove_obj_handle(
1220 pdd, GET_IDR_HANDLE(args->handle));
1222 atomic64_sub(size, &pdd->vram_usage);
1226 mutex_unlock(&p->mutex);
1230 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1231 struct kfd_process *p, void *data)
1233 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1234 struct kfd_process_device *pdd, *peer_pdd;
1236 struct kfd_node *dev;
1239 uint32_t *devices_arr = NULL;
1241 if (!args->n_devices) {
1242 pr_debug("Device IDs array empty\n");
1245 if (args->n_success > args->n_devices) {
1246 pr_debug("n_success exceeds n_devices\n");
1250 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1255 err = copy_from_user(devices_arr,
1256 (void __user *)args->device_ids_array_ptr,
1257 args->n_devices * sizeof(*devices_arr));
1260 goto copy_from_user_failed;
1263 mutex_lock(&p->mutex);
1264 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1267 goto get_process_device_data_failed;
1271 pdd = kfd_bind_process_to_device(dev, p);
1274 goto bind_process_to_device_failed;
1277 mem = kfd_process_device_translate_handle(pdd,
1278 GET_IDR_HANDLE(args->handle));
1281 goto get_mem_obj_from_handle_failed;
1284 for (i = args->n_success; i < args->n_devices; i++) {
1285 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1287 pr_debug("Getting device by id failed for 0x%x\n",
1290 goto get_mem_obj_from_handle_failed;
1293 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
1294 if (IS_ERR(peer_pdd)) {
1295 err = PTR_ERR(peer_pdd);
1296 goto get_mem_obj_from_handle_failed;
1299 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1300 peer_pdd->dev->adev, (struct kgd_mem *)mem,
1301 peer_pdd->drm_priv);
1303 struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
1305 dev_err(dev->adev->dev,
1306 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
1307 pci_domain_nr(pdev->bus),
1309 PCI_SLOT(pdev->devfn),
1310 PCI_FUNC(pdev->devfn),
1311 ((struct kgd_mem *)mem)->domain);
1312 goto map_memory_to_gpu_failed;
1314 args->n_success = i+1;
1317 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
1319 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1320 goto sync_memory_failed;
1323 mutex_unlock(&p->mutex);
1325 /* Flush TLBs after waiting for the page table updates to complete */
1326 for (i = 0; i < args->n_devices; i++) {
1327 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1328 if (WARN_ON_ONCE(!peer_pdd))
1330 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
1336 get_process_device_data_failed:
1337 bind_process_to_device_failed:
1338 get_mem_obj_from_handle_failed:
1339 map_memory_to_gpu_failed:
1341 mutex_unlock(&p->mutex);
1342 copy_from_user_failed:
1348 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1349 struct kfd_process *p, void *data)
1351 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1352 struct kfd_process_device *pdd, *peer_pdd;
1355 uint32_t *devices_arr = NULL, i;
1358 if (!args->n_devices) {
1359 pr_debug("Device IDs array empty\n");
1362 if (args->n_success > args->n_devices) {
1363 pr_debug("n_success exceeds n_devices\n");
1367 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1372 err = copy_from_user(devices_arr,
1373 (void __user *)args->device_ids_array_ptr,
1374 args->n_devices * sizeof(*devices_arr));
1377 goto copy_from_user_failed;
1380 mutex_lock(&p->mutex);
1381 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1384 goto bind_process_to_device_failed;
1387 mem = kfd_process_device_translate_handle(pdd,
1388 GET_IDR_HANDLE(args->handle));
1391 goto get_mem_obj_from_handle_failed;
1394 for (i = args->n_success; i < args->n_devices; i++) {
1395 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1398 goto get_mem_obj_from_handle_failed;
1400 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1401 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1403 pr_debug("Failed to unmap from gpu %d/%d\n", i, args->n_devices);
1404 goto unmap_memory_from_gpu_failed;
1406 args->n_success = i+1;
1409 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd);
1411 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
1412 (struct kgd_mem *) mem, true);
1414 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1415 goto sync_memory_failed;
1419 /* Flush TLBs after waiting for the page table updates to complete */
1420 for (i = 0; i < args->n_devices; i++) {
1421 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1422 if (WARN_ON_ONCE(!peer_pdd))
1425 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
1427 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */
1428 err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv);
1430 goto sync_memory_failed;
1433 mutex_unlock(&p->mutex);
1439 bind_process_to_device_failed:
1440 get_mem_obj_from_handle_failed:
1441 unmap_memory_from_gpu_failed:
1443 mutex_unlock(&p->mutex);
1444 copy_from_user_failed:
1449 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1450 struct kfd_process *p, void *data)
1453 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1455 struct kfd_node *dev;
1457 mutex_lock(&p->mutex);
1458 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1472 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1477 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) ||
1478 kfd_dbg_has_cwsr_workaround(dev))) {
1483 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1484 mutex_unlock(&p->mutex);
1486 args->first_gws = 0;
1490 mutex_unlock(&p->mutex);
1494 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1495 struct kfd_process *p, void *data)
1497 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1498 struct kfd_node *dev = NULL;
1499 struct amdgpu_device *dmabuf_adev;
1500 void *metadata_buffer = NULL;
1506 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1507 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1508 if (dev && !kfd_devcgroup_check_permission(dev))
1513 if (args->metadata_ptr) {
1514 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1515 if (!metadata_buffer)
1519 /* Get dmabuf info from KGD */
1520 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1521 &dmabuf_adev, &args->size,
1522 metadata_buffer, args->metadata_size,
1523 &args->metadata_size, &flags, &xcp_id);
1528 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
1530 args->gpu_id = dev->id;
1531 args->flags = flags;
1533 /* Copy metadata buffer to user mode */
1534 if (metadata_buffer) {
1535 r = copy_to_user((void __user *)args->metadata_ptr,
1536 metadata_buffer, args->metadata_size);
1542 kfree(metadata_buffer);
1547 static int kfd_ioctl_import_dmabuf(struct file *filep,
1548 struct kfd_process *p, void *data)
1550 struct kfd_ioctl_import_dmabuf_args *args = data;
1551 struct kfd_process_device *pdd;
1557 mutex_lock(&p->mutex);
1558 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1564 pdd = kfd_bind_process_to_device(pdd->dev, p);
1570 r = amdgpu_amdkfd_gpuvm_import_dmabuf_fd(pdd->dev->adev, args->dmabuf_fd,
1571 args->va_addr, pdd->drm_priv,
1572 (struct kgd_mem **)&mem, &size,
1577 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1578 if (idr_handle < 0) {
1583 mutex_unlock(&p->mutex);
1585 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1590 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
1591 pdd->drm_priv, NULL);
1593 mutex_unlock(&p->mutex);
1597 static int kfd_ioctl_export_dmabuf(struct file *filep,
1598 struct kfd_process *p, void *data)
1600 struct kfd_ioctl_export_dmabuf_args *args = data;
1601 struct kfd_process_device *pdd;
1602 struct dma_buf *dmabuf;
1603 struct kfd_node *dev;
1607 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1611 mutex_lock(&p->mutex);
1613 pdd = kfd_get_process_device_data(dev, p);
1619 mem = kfd_process_device_translate_handle(pdd,
1620 GET_IDR_HANDLE(args->handle));
1626 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1627 mutex_unlock(&p->mutex);
1631 ret = dma_buf_fd(dmabuf, args->flags);
1633 dma_buf_put(dmabuf);
1636 /* dma_buf_fd assigns the reference count to the fd, no need to
1637 * put the reference here.
1639 args->dmabuf_fd = ret;
1644 mutex_unlock(&p->mutex);
1649 /* Handle requests for watching SMI events */
1650 static int kfd_ioctl_smi_events(struct file *filep,
1651 struct kfd_process *p, void *data)
1653 struct kfd_ioctl_smi_events_args *args = data;
1654 struct kfd_process_device *pdd;
1656 mutex_lock(&p->mutex);
1658 pdd = kfd_process_device_data_by_id(p, args->gpuid);
1659 mutex_unlock(&p->mutex);
1663 return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1666 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1668 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1669 struct kfd_process *p, void *data)
1671 struct kfd_ioctl_set_xnack_mode_args *args = data;
1674 mutex_lock(&p->mutex);
1675 if (args->xnack_enabled >= 0) {
1676 if (!list_empty(&p->pqm.queues)) {
1677 pr_debug("Process has user queues running\n");
1682 if (p->xnack_enabled == args->xnack_enabled)
1685 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1690 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1692 args->xnack_enabled = p->xnack_enabled;
1696 mutex_unlock(&p->mutex);
1701 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1703 struct kfd_ioctl_svm_args *args = data;
1706 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
1707 args->start_addr, args->size, args->op, args->nattr);
1709 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
1711 if (!args->start_addr || !args->size)
1714 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1720 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1721 struct kfd_process *p, void *data)
1725 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1731 static int criu_checkpoint_process(struct kfd_process *p,
1732 uint8_t __user *user_priv_data,
1733 uint64_t *priv_offset)
1735 struct kfd_criu_process_priv_data process_priv;
1738 memset(&process_priv, 0, sizeof(process_priv));
1740 process_priv.version = KFD_CRIU_PRIV_VERSION;
1741 /* For CR, we don't consider negative xnack mode which is used for
1742 * querying without changing it, here 0 simply means disabled and 1
1743 * means enabled so retry for finding a valid PTE.
1745 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1747 ret = copy_to_user(user_priv_data + *priv_offset,
1748 &process_priv, sizeof(process_priv));
1751 pr_err("Failed to copy process information to user\n");
1755 *priv_offset += sizeof(process_priv);
1759 static int criu_checkpoint_devices(struct kfd_process *p,
1760 uint32_t num_devices,
1761 uint8_t __user *user_addr,
1762 uint8_t __user *user_priv_data,
1763 uint64_t *priv_offset)
1765 struct kfd_criu_device_priv_data *device_priv = NULL;
1766 struct kfd_criu_device_bucket *device_buckets = NULL;
1769 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1770 if (!device_buckets) {
1775 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1781 for (i = 0; i < num_devices; i++) {
1782 struct kfd_process_device *pdd = p->pdds[i];
1784 device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1785 device_buckets[i].actual_gpu_id = pdd->dev->id;
1788 * priv_data does not contain useful information for now and is reserved for
1789 * future use, so we do not set its contents.
1793 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1795 pr_err("Failed to copy device information to user\n");
1800 ret = copy_to_user(user_priv_data + *priv_offset,
1802 num_devices * sizeof(*device_priv));
1804 pr_err("Failed to copy device information to user\n");
1807 *priv_offset += num_devices * sizeof(*device_priv);
1810 kvfree(device_buckets);
1811 kvfree(device_priv);
1815 static uint32_t get_process_num_bos(struct kfd_process *p)
1817 uint32_t num_of_bos = 0;
1820 /* Run over all PDDs of the process */
1821 for (i = 0; i < p->n_pdds; i++) {
1822 struct kfd_process_device *pdd = p->pdds[i];
1826 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1827 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1829 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base)
1836 static int criu_get_prime_handle(struct kgd_mem *mem,
1837 int flags, u32 *shared_fd,
1840 struct dma_buf *dmabuf;
1843 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1845 pr_err("dmabuf export failed for the BO\n");
1849 ret = get_unused_fd_flags(flags);
1851 pr_err("dmabuf create fd failed, ret:%d\n", ret);
1852 goto out_free_dmabuf;
1856 *file = dmabuf->file;
1860 dma_buf_put(dmabuf);
1864 static void commit_files(struct file **files,
1865 struct kfd_criu_bo_bucket *bo_buckets,
1870 struct file *file = files[count];
1876 put_unused_fd(bo_buckets[count].dmabuf_fd);
1878 fd_install(bo_buckets[count].dmabuf_fd, file);
1883 static int criu_checkpoint_bos(struct kfd_process *p,
1885 uint8_t __user *user_bos,
1886 uint8_t __user *user_priv_data,
1887 uint64_t *priv_offset)
1889 struct kfd_criu_bo_bucket *bo_buckets;
1890 struct kfd_criu_bo_priv_data *bo_privs;
1891 struct file **files = NULL;
1892 int ret = 0, pdd_index, bo_index = 0, id;
1895 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1899 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1905 files = kvzalloc(num_bos * sizeof(struct file *), GFP_KERNEL);
1911 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1912 struct kfd_process_device *pdd = p->pdds[pdd_index];
1913 struct amdgpu_bo *dumper_bo;
1914 struct kgd_mem *kgd_mem;
1916 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1917 struct kfd_criu_bo_bucket *bo_bucket;
1918 struct kfd_criu_bo_priv_data *bo_priv;
1921 kgd_mem = (struct kgd_mem *)mem;
1922 dumper_bo = kgd_mem->bo;
1924 /* Skip checkpointing BOs that are used for Trap handler
1925 * code and state. Currently, these BOs have a VA that
1926 * is less GPUVM Base
1928 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base)
1931 bo_bucket = &bo_buckets[bo_index];
1932 bo_priv = &bo_privs[bo_index];
1934 bo_bucket->gpu_id = pdd->user_gpu_id;
1935 bo_bucket->addr = (uint64_t)kgd_mem->va;
1936 bo_bucket->size = amdgpu_bo_size(dumper_bo);
1937 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1938 bo_priv->idr_handle = id;
1940 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1941 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1942 &bo_priv->user_addr);
1944 pr_err("Failed to obtain user address for user-pointer bo\n");
1948 if (bo_bucket->alloc_flags
1949 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
1950 ret = criu_get_prime_handle(kgd_mem,
1951 bo_bucket->alloc_flags &
1952 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1953 &bo_bucket->dmabuf_fd, &files[bo_index]);
1957 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
1960 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1961 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1962 KFD_MMAP_GPU_ID(pdd->dev->id);
1963 else if (bo_bucket->alloc_flags &
1964 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1965 bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1966 KFD_MMAP_GPU_ID(pdd->dev->id);
1968 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1970 for (i = 0; i < p->n_pdds; i++) {
1971 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->drm_priv, kgd_mem))
1972 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1975 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1976 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1981 bo_bucket->alloc_flags,
1982 bo_priv->idr_handle);
1987 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1989 pr_err("Failed to copy BO information to user\n");
1994 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
1996 pr_err("Failed to copy BO priv information to user\n");
2001 *priv_offset += num_bos * sizeof(*bo_privs);
2004 commit_files(files, bo_buckets, bo_index, ret);
2011 static int criu_get_process_object_info(struct kfd_process *p,
2012 uint32_t *num_devices,
2014 uint32_t *num_objects,
2015 uint64_t *objs_priv_size)
2017 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
2018 uint32_t num_queues, num_events, num_svm_ranges;
2021 *num_devices = p->n_pdds;
2022 *num_bos = get_process_num_bos(p);
2024 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
2028 num_events = kfd_get_num_events(p);
2030 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
2034 *num_objects = num_queues + num_events + num_svm_ranges;
2036 if (objs_priv_size) {
2037 priv_size = sizeof(struct kfd_criu_process_priv_data);
2038 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
2039 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
2040 priv_size += queues_priv_data_size;
2041 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
2042 priv_size += svm_priv_data_size;
2043 *objs_priv_size = priv_size;
2048 static int criu_checkpoint(struct file *filep,
2049 struct kfd_process *p,
2050 struct kfd_ioctl_criu_args *args)
2053 uint32_t num_devices, num_bos, num_objects;
2054 uint64_t priv_size, priv_offset = 0, bo_priv_offset;
2056 if (!args->devices || !args->bos || !args->priv_data)
2059 mutex_lock(&p->mutex);
2062 pr_err("No pdd for given process\n");
2067 /* Confirm all process queues are evicted */
2068 if (!p->queues_paused) {
2069 pr_err("Cannot dump process when queues are not in evicted state\n");
2070 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */
2075 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
2079 if (num_devices != args->num_devices ||
2080 num_bos != args->num_bos ||
2081 num_objects != args->num_objects ||
2082 priv_size != args->priv_data_size) {
2088 /* each function will store private data inside priv_data and adjust priv_offset */
2089 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2093 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2094 (uint8_t __user *)args->priv_data, &priv_offset);
2098 /* Leave room for BOs in the private data. They need to be restored
2099 * before events, but we checkpoint them last to simplify the error
2102 bo_priv_offset = priv_offset;
2103 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2106 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2111 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2116 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2121 /* This must be the last thing in this function that can fail.
2122 * Otherwise we leak dmabuf file descriptors.
2124 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2125 (uint8_t __user *)args->priv_data, &bo_priv_offset);
2128 mutex_unlock(&p->mutex);
2130 pr_err("Failed to dump CRIU ret:%d\n", ret);
2132 pr_debug("CRIU dump ret:%d\n", ret);
2137 static int criu_restore_process(struct kfd_process *p,
2138 struct kfd_ioctl_criu_args *args,
2139 uint64_t *priv_offset,
2140 uint64_t max_priv_data_size)
2143 struct kfd_criu_process_priv_data process_priv;
2145 if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
2148 ret = copy_from_user(&process_priv,
2149 (void __user *)(args->priv_data + *priv_offset),
2150 sizeof(process_priv));
2152 pr_err("Failed to copy process private information from user\n");
2156 *priv_offset += sizeof(process_priv);
2158 if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
2159 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
2160 process_priv.version, KFD_CRIU_PRIV_VERSION);
2164 pr_debug("Setting XNACK mode\n");
2165 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
2166 pr_err("xnack mode cannot be set\n");
2170 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
2171 p->xnack_enabled = process_priv.xnack_mode;
2178 static int criu_restore_devices(struct kfd_process *p,
2179 struct kfd_ioctl_criu_args *args,
2180 uint64_t *priv_offset,
2181 uint64_t max_priv_data_size)
2183 struct kfd_criu_device_bucket *device_buckets;
2184 struct kfd_criu_device_priv_data *device_privs;
2188 if (args->num_devices != p->n_pdds)
2191 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2194 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2195 if (!device_buckets)
2198 ret = copy_from_user(device_buckets, (void __user *)args->devices,
2199 args->num_devices * sizeof(*device_buckets));
2201 pr_err("Failed to copy devices buckets from user\n");
2206 for (i = 0; i < args->num_devices; i++) {
2207 struct kfd_node *dev;
2208 struct kfd_process_device *pdd;
2209 struct file *drm_file;
2211 /* device private data is not currently used */
2213 if (!device_buckets[i].user_gpu_id) {
2214 pr_err("Invalid user gpu_id\n");
2219 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2221 pr_err("Failed to find device with gpu_id = %x\n",
2222 device_buckets[i].actual_gpu_id);
2227 pdd = kfd_get_process_device_data(dev, p);
2229 pr_err("Failed to get pdd for gpu_id = %x\n",
2230 device_buckets[i].actual_gpu_id);
2234 pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2236 drm_file = fget(device_buckets[i].drm_fd);
2238 pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2239 device_buckets[i].drm_fd);
2244 if (pdd->drm_file) {
2249 /* create the vm using render nodes for kfd pdd */
2250 if (kfd_process_device_init_vm(pdd, drm_file)) {
2251 pr_err("could not init vm for given pdd\n");
2252 /* On success, the PDD keeps the drm_file reference */
2258 * pdd now already has the vm bound to render node so below api won't create a new
2259 * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2260 * for iommu v2 binding and runtime pm.
2262 pdd = kfd_bind_process_to_device(dev, p);
2268 if (!pdd->qpd.proc_doorbells) {
2269 ret = kfd_alloc_process_doorbells(dev->kfd, pdd);
2276 * We are not copying device private data from user as we are not using the data for now,
2277 * but we still adjust for its private data.
2279 *priv_offset += args->num_devices * sizeof(*device_privs);
2282 kfree(device_buckets);
2286 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
2287 struct kfd_criu_bo_bucket *bo_bucket,
2288 struct kfd_criu_bo_priv_data *bo_priv,
2289 struct kgd_mem **kgd_mem)
2293 const bool criu_resume = true;
2296 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2297 if (bo_bucket->size !=
2298 kfd_doorbell_process_slice(pdd->dev->kfd))
2301 offset = kfd_get_process_doorbells(pdd);
2304 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2305 /* MMIO BOs need remapped bus address */
2306 if (bo_bucket->size != PAGE_SIZE) {
2307 pr_err("Invalid page size\n");
2310 offset = pdd->dev->adev->rmmio_remap.bus_addr;
2311 if (!offset || (PAGE_SIZE > 4096)) {
2312 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2315 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2316 offset = bo_priv->user_addr;
2319 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr,
2320 bo_bucket->size, pdd->drm_priv, kgd_mem,
2321 &offset, bo_bucket->alloc_flags, criu_resume);
2323 pr_err("Could not create the BO\n");
2326 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n",
2327 bo_bucket->size, bo_bucket->addr, offset);
2329 /* Restore previous IDR handle */
2330 pr_debug("Restoring old IDR handle for the BO");
2331 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle,
2332 bo_priv->idr_handle + 1, GFP_KERNEL);
2334 if (idr_handle < 0) {
2335 pr_err("Could not allocate idr\n");
2336 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv,
2341 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2342 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id);
2343 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2344 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id);
2345 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2346 bo_bucket->restored_offset = offset;
2347 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2348 bo_bucket->restored_offset = offset;
2349 /* Update the VRAM usage count */
2350 atomic64_add(bo_bucket->size, &pdd->vram_usage);
2355 static int criu_restore_bo(struct kfd_process *p,
2356 struct kfd_criu_bo_bucket *bo_bucket,
2357 struct kfd_criu_bo_priv_data *bo_priv,
2360 struct kfd_process_device *pdd;
2361 struct kgd_mem *kgd_mem;
2365 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n",
2366 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags,
2367 bo_priv->idr_handle);
2369 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2371 pr_err("Failed to get pdd\n");
2375 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem);
2379 /* now map these BOs to GPU/s */
2380 for (j = 0; j < p->n_pdds; j++) {
2381 struct kfd_node *peer;
2382 struct kfd_process_device *peer_pdd;
2384 if (!bo_priv->mapped_gpuids[j])
2387 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2391 peer = peer_pdd->dev;
2393 peer_pdd = kfd_bind_process_to_device(peer, p);
2394 if (IS_ERR(peer_pdd))
2395 return PTR_ERR(peer_pdd);
2397 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem,
2398 peer_pdd->drm_priv);
2400 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2405 pr_debug("map memory was successful for the BO\n");
2406 /* create the dmabuf object and export the bo */
2407 if (bo_bucket->alloc_flags
2408 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
2409 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR,
2410 &bo_bucket->dmabuf_fd, file);
2414 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
2420 static int criu_restore_bos(struct kfd_process *p,
2421 struct kfd_ioctl_criu_args *args,
2422 uint64_t *priv_offset,
2423 uint64_t max_priv_data_size)
2425 struct kfd_criu_bo_bucket *bo_buckets = NULL;
2426 struct kfd_criu_bo_priv_data *bo_privs = NULL;
2427 struct file **files = NULL;
2431 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2434 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2435 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2437 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2441 files = kvzalloc(args->num_bos * sizeof(struct file *), GFP_KERNEL);
2447 ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2448 args->num_bos * sizeof(*bo_buckets));
2450 pr_err("Failed to copy BOs information from user\n");
2455 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2461 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2462 args->num_bos * sizeof(*bo_privs));
2464 pr_err("Failed to copy BOs information from user\n");
2468 *priv_offset += args->num_bos * sizeof(*bo_privs);
2470 /* Create and map new BOs */
2471 for (; i < args->num_bos; i++) {
2472 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i], &files[i]);
2474 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
2479 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2480 ret = copy_to_user((void __user *)args->bos,
2482 (args->num_bos * sizeof(*bo_buckets)));
2487 commit_files(files, bo_buckets, i, ret);
2494 static int criu_restore_objects(struct file *filep,
2495 struct kfd_process *p,
2496 struct kfd_ioctl_criu_args *args,
2497 uint64_t *priv_offset,
2498 uint64_t max_priv_data_size)
2503 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2504 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2505 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2507 for (i = 0; i < args->num_objects; i++) {
2508 uint32_t object_type;
2510 if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2511 pr_err("Invalid private data size\n");
2515 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2517 pr_err("Failed to copy private information from user\n");
2521 switch (object_type) {
2522 case KFD_CRIU_OBJECT_TYPE_QUEUE:
2523 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2524 priv_offset, max_priv_data_size);
2528 case KFD_CRIU_OBJECT_TYPE_EVENT:
2529 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2530 priv_offset, max_priv_data_size);
2534 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2535 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2536 priv_offset, max_priv_data_size);
2541 pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2550 static int criu_restore(struct file *filep,
2551 struct kfd_process *p,
2552 struct kfd_ioctl_criu_args *args)
2554 uint64_t priv_offset = 0;
2557 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2558 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2560 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2561 !args->num_devices || !args->num_bos)
2564 mutex_lock(&p->mutex);
2567 * Set the process to evicted state to avoid running any new queues before all the memory
2568 * mappings are ready.
2570 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
2574 /* Each function will adjust priv_offset based on how many bytes they consumed */
2575 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2579 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2583 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2587 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2591 if (priv_offset != args->priv_data_size) {
2592 pr_err("Invalid private data size\n");
2597 mutex_unlock(&p->mutex);
2599 pr_err("Failed to restore CRIU ret:%d\n", ret);
2601 pr_debug("CRIU restore successful\n");
2606 static int criu_unpause(struct file *filep,
2607 struct kfd_process *p,
2608 struct kfd_ioctl_criu_args *args)
2612 mutex_lock(&p->mutex);
2614 if (!p->queues_paused) {
2615 mutex_unlock(&p->mutex);
2619 ret = kfd_process_restore_queues(p);
2621 pr_err("Failed to unpause queues ret:%d\n", ret);
2623 p->queues_paused = false;
2625 mutex_unlock(&p->mutex);
2630 static int criu_resume(struct file *filep,
2631 struct kfd_process *p,
2632 struct kfd_ioctl_criu_args *args)
2634 struct kfd_process *target = NULL;
2635 struct pid *pid = NULL;
2638 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2641 pid = find_get_pid(args->pid);
2643 pr_err("Cannot find pid info for %i\n", args->pid);
2647 pr_debug("calling kfd_lookup_process_by_pid\n");
2648 target = kfd_lookup_process_by_pid(pid);
2653 pr_debug("Cannot find process info for %i\n", args->pid);
2657 mutex_lock(&target->mutex);
2658 ret = kfd_criu_resume_svm(target);
2660 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2664 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2666 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2669 mutex_unlock(&target->mutex);
2671 kfd_unref_process(target);
2675 static int criu_process_info(struct file *filep,
2676 struct kfd_process *p,
2677 struct kfd_ioctl_criu_args *args)
2681 mutex_lock(&p->mutex);
2684 pr_err("No pdd for given process\n");
2689 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
2693 p->queues_paused = true;
2695 args->pid = task_pid_nr_ns(p->lead_thread,
2696 task_active_pid_ns(p->lead_thread));
2698 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2699 &args->num_objects, &args->priv_data_size);
2703 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2704 args->num_devices, args->num_bos, args->num_objects,
2705 args->priv_data_size);
2709 kfd_process_restore_queues(p);
2710 p->queues_paused = false;
2712 mutex_unlock(&p->mutex);
2716 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2718 struct kfd_ioctl_criu_args *args = data;
2721 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2723 case KFD_CRIU_OP_PROCESS_INFO:
2724 ret = criu_process_info(filep, p, args);
2726 case KFD_CRIU_OP_CHECKPOINT:
2727 ret = criu_checkpoint(filep, p, args);
2729 case KFD_CRIU_OP_UNPAUSE:
2730 ret = criu_unpause(filep, p, args);
2732 case KFD_CRIU_OP_RESTORE:
2733 ret = criu_restore(filep, p, args);
2735 case KFD_CRIU_OP_RESUME:
2736 ret = criu_resume(filep, p, args);
2739 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2745 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2750 static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
2751 bool enable_ttmp_setup)
2755 if (p->is_runtime_retry)
2758 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)
2761 for (i = 0; i < p->n_pdds; i++) {
2762 struct kfd_process_device *pdd = p->pdds[i];
2764 if (pdd->qpd.queue_count)
2768 * Setup TTMPs by default.
2769 * Note that this call must remain here for MES ADD QUEUE to
2770 * skip_process_ctx_clear unconditionally as the first call to
2771 * SET_SHADER_DEBUGGER clears any stale process context data
2774 if (pdd->dev->kfd->shared_resources.enable_mes)
2775 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev));
2778 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
2779 p->runtime_info.r_debug = r_debug;
2780 p->runtime_info.ttmp_setup = enable_ttmp_setup;
2782 if (p->runtime_info.ttmp_setup) {
2783 for (i = 0; i < p->n_pdds; i++) {
2784 struct kfd_process_device *pdd = p->pdds[i];
2786 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) {
2787 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
2788 pdd->dev->kfd2kgd->enable_debug_trap(
2791 pdd->dev->vm_info.last_vmid_kfd);
2792 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2793 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap(
2802 if (p->debug_trap_enabled) {
2803 if (!p->is_runtime_retry) {
2804 kfd_dbg_trap_activate(p);
2805 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2806 p, NULL, 0, false, NULL, 0);
2809 mutex_unlock(&p->mutex);
2810 ret = down_interruptible(&p->runtime_enable_sema);
2811 mutex_lock(&p->mutex);
2813 p->is_runtime_retry = !!ret;
2819 static int runtime_disable(struct kfd_process *p)
2822 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;
2824 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED;
2825 p->runtime_info.r_debug = 0;
2827 if (p->debug_trap_enabled) {
2829 kfd_dbg_trap_deactivate(p, false, 0);
2831 if (!p->is_runtime_retry)
2832 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2833 p, NULL, 0, false, NULL, 0);
2835 mutex_unlock(&p->mutex);
2836 ret = down_interruptible(&p->runtime_enable_sema);
2837 mutex_lock(&p->mutex);
2839 p->is_runtime_retry = !!ret;
2844 if (was_enabled && p->runtime_info.ttmp_setup) {
2845 for (i = 0; i < p->n_pdds; i++) {
2846 struct kfd_process_device *pdd = p->pdds[i];
2848 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev))
2849 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
2853 p->runtime_info.ttmp_setup = false;
2855 /* disable ttmp setup */
2856 for (i = 0; i < p->n_pdds; i++) {
2857 struct kfd_process_device *pdd = p->pdds[i];
2859 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2860 pdd->spi_dbg_override =
2861 pdd->dev->kfd2kgd->disable_debug_trap(
2864 pdd->dev->vm_info.last_vmid_kfd);
2866 if (!pdd->dev->kfd->shared_resources.enable_mes)
2867 debug_refresh_runlist(pdd->dev->dqm);
2869 kfd_dbg_set_mes_debug_mode(pdd,
2870 !kfd_dbg_has_cwsr_workaround(pdd->dev));
2877 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)
2879 struct kfd_ioctl_runtime_enable_args *args = data;
2882 mutex_lock(&p->mutex);
2884 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK)
2885 r = runtime_enable(p, args->r_debug,
2886 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK));
2888 r = runtime_disable(p);
2890 mutex_unlock(&p->mutex);
2895 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data)
2897 struct kfd_ioctl_dbg_trap_args *args = data;
2898 struct task_struct *thread = NULL;
2899 struct mm_struct *mm = NULL;
2900 struct pid *pid = NULL;
2901 struct kfd_process *target = NULL;
2902 struct kfd_process_device *pdd = NULL;
2905 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2906 pr_err("Debugging does not support sched_policy %i", sched_policy);
2910 pid = find_get_pid(args->pid);
2912 pr_debug("Cannot find pid info for %i\n", args->pid);
2917 thread = get_pid_task(pid, PIDTYPE_PID);
2923 mm = get_task_mm(thread);
2929 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) {
2930 bool create_process;
2933 create_process = thread && thread != current && ptrace_parent(thread) == current;
2936 target = create_process ? kfd_create_process(thread) :
2937 kfd_lookup_process_by_pid(pid);
2939 target = kfd_lookup_process_by_pid(pid);
2942 if (IS_ERR_OR_NULL(target)) {
2943 pr_debug("Cannot find process PID %i to debug\n", args->pid);
2944 r = target ? PTR_ERR(target) : -ESRCH;
2949 /* Check if target is still PTRACED. */
2951 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE
2952 && ptrace_parent(target->lead_thread) != current) {
2953 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid);
2961 mutex_lock(&target->mutex);
2963 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) {
2964 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op);
2969 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED &&
2970 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE ||
2971 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE ||
2972 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES ||
2973 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES ||
2974 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2975 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH ||
2976 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) {
2981 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2982 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) {
2983 int user_gpu_id = kfd_process_get_user_gpu_id(target,
2984 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ?
2985 args->set_node_address_watch.gpu_id :
2986 args->clear_node_address_watch.gpu_id);
2988 pdd = kfd_process_device_data_by_id(target, user_gpu_id);
2989 if (user_gpu_id == -EINVAL || !pdd) {
2996 case KFD_IOC_DBG_TRAP_ENABLE:
2998 target->debugger_process = p;
3000 r = kfd_dbg_trap_enable(target,
3001 args->enable.dbg_fd,
3002 (void __user *)args->enable.rinfo_ptr,
3003 &args->enable.rinfo_size);
3005 target->exception_enable_mask = args->enable.exception_mask;
3008 case KFD_IOC_DBG_TRAP_DISABLE:
3009 r = kfd_dbg_trap_disable(target);
3011 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
3012 r = kfd_dbg_send_exception_to_runtime(target,
3013 args->send_runtime_event.gpu_id,
3014 args->send_runtime_event.queue_id,
3015 args->send_runtime_event.exception_mask);
3017 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
3018 kfd_dbg_set_enabled_debug_exception_mask(target,
3019 args->set_exceptions_enabled.exception_mask);
3021 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
3022 r = kfd_dbg_trap_set_wave_launch_override(target,
3023 args->launch_override.override_mode,
3024 args->launch_override.enable_mask,
3025 args->launch_override.support_request_mask,
3026 &args->launch_override.enable_mask,
3027 &args->launch_override.support_request_mask);
3029 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
3030 r = kfd_dbg_trap_set_wave_launch_mode(target,
3031 args->launch_mode.launch_mode);
3033 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
3034 r = suspend_queues(target,
3035 args->suspend_queues.num_queues,
3036 args->suspend_queues.grace_period,
3037 args->suspend_queues.exception_mask,
3038 (uint32_t *)args->suspend_queues.queue_array_ptr);
3041 case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
3042 r = resume_queues(target, args->resume_queues.num_queues,
3043 (uint32_t *)args->resume_queues.queue_array_ptr);
3045 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
3046 r = kfd_dbg_trap_set_dev_address_watch(pdd,
3047 args->set_node_address_watch.address,
3048 args->set_node_address_watch.mask,
3049 &args->set_node_address_watch.id,
3050 args->set_node_address_watch.mode);
3052 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
3053 r = kfd_dbg_trap_clear_dev_address_watch(pdd,
3054 args->clear_node_address_watch.id);
3056 case KFD_IOC_DBG_TRAP_SET_FLAGS:
3057 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags);
3059 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
3060 r = kfd_dbg_ev_query_debug_event(target,
3061 &args->query_debug_event.queue_id,
3062 &args->query_debug_event.gpu_id,
3063 args->query_debug_event.exception_mask,
3064 &args->query_debug_event.exception_mask);
3066 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
3067 r = kfd_dbg_trap_query_exception_info(target,
3068 args->query_exception_info.source_id,
3069 args->query_exception_info.exception_code,
3070 args->query_exception_info.clear_exception,
3071 (void __user *)args->query_exception_info.info_ptr,
3072 &args->query_exception_info.info_size);
3074 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
3075 r = pqm_get_queue_snapshot(&target->pqm,
3076 args->queue_snapshot.exception_mask,
3077 (void __user *)args->queue_snapshot.snapshot_buf_ptr,
3078 &args->queue_snapshot.num_queues,
3079 &args->queue_snapshot.entry_size);
3081 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
3082 r = kfd_dbg_trap_device_snapshot(target,
3083 args->device_snapshot.exception_mask,
3084 (void __user *)args->device_snapshot.snapshot_buf_ptr,
3085 &args->device_snapshot.num_devices,
3086 &args->device_snapshot.entry_size);
3089 pr_err("Invalid option: %i\n", args->op);
3094 mutex_unlock(&target->mutex);
3098 put_task_struct(thread);
3107 kfd_unref_process(target);
3112 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
3113 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
3114 .cmd_drv = 0, .name = #ioctl}
3117 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
3118 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
3119 kfd_ioctl_get_version, 0),
3121 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
3122 kfd_ioctl_create_queue, 0),
3124 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
3125 kfd_ioctl_destroy_queue, 0),
3127 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
3128 kfd_ioctl_set_memory_policy, 0),
3130 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
3131 kfd_ioctl_get_clock_counters, 0),
3133 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
3134 kfd_ioctl_get_process_apertures, 0),
3136 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
3137 kfd_ioctl_update_queue, 0),
3139 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
3140 kfd_ioctl_create_event, 0),
3142 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
3143 kfd_ioctl_destroy_event, 0),
3145 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
3146 kfd_ioctl_set_event, 0),
3148 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
3149 kfd_ioctl_reset_event, 0),
3151 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
3152 kfd_ioctl_wait_events, 0),
3154 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
3155 kfd_ioctl_dbg_register, 0),
3157 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
3158 kfd_ioctl_dbg_unregister, 0),
3160 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
3161 kfd_ioctl_dbg_address_watch, 0),
3163 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
3164 kfd_ioctl_dbg_wave_control, 0),
3166 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
3167 kfd_ioctl_set_scratch_backing_va, 0),
3169 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
3170 kfd_ioctl_get_tile_config, 0),
3172 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
3173 kfd_ioctl_set_trap_handler, 0),
3175 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
3176 kfd_ioctl_get_process_apertures_new, 0),
3178 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
3179 kfd_ioctl_acquire_vm, 0),
3181 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
3182 kfd_ioctl_alloc_memory_of_gpu, 0),
3184 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
3185 kfd_ioctl_free_memory_of_gpu, 0),
3187 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
3188 kfd_ioctl_map_memory_to_gpu, 0),
3190 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
3191 kfd_ioctl_unmap_memory_from_gpu, 0),
3193 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
3194 kfd_ioctl_set_cu_mask, 0),
3196 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
3197 kfd_ioctl_get_queue_wave_state, 0),
3199 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
3200 kfd_ioctl_get_dmabuf_info, 0),
3202 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
3203 kfd_ioctl_import_dmabuf, 0),
3205 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
3206 kfd_ioctl_alloc_queue_gws, 0),
3208 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
3209 kfd_ioctl_smi_events, 0),
3211 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
3213 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
3214 kfd_ioctl_set_xnack_mode, 0),
3216 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
3217 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
3219 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
3220 kfd_ioctl_get_available_memory, 0),
3222 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
3223 kfd_ioctl_export_dmabuf, 0),
3225 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
3226 kfd_ioctl_runtime_enable, 0),
3228 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
3229 kfd_ioctl_set_debug_trap, 0),
3232 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
3234 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
3236 struct kfd_process *process;
3237 amdkfd_ioctl_t *func;
3238 const struct amdkfd_ioctl_desc *ioctl = NULL;
3239 unsigned int nr = _IOC_NR(cmd);
3240 char stack_kdata[128];
3242 unsigned int usize, asize;
3243 int retcode = -EINVAL;
3244 bool ptrace_attached = false;
3246 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
3249 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
3252 ioctl = &amdkfd_ioctls[nr];
3254 amdkfd_size = _IOC_SIZE(ioctl->cmd);
3255 usize = asize = _IOC_SIZE(cmd);
3256 if (amdkfd_size > asize)
3257 asize = amdkfd_size;
3263 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
3265 /* Get the process struct from the filep. Only the process
3266 * that opened /dev/kfd can use the file descriptor. Child
3267 * processes need to create their own KFD device context.
3269 process = filep->private_data;
3272 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
3273 ptrace_parent(process->lead_thread) == current)
3274 ptrace_attached = true;
3277 if (process->lead_thread != current->group_leader
3278 && !ptrace_attached) {
3279 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
3284 /* Do not trust userspace, use our own definition */
3287 if (unlikely(!func)) {
3288 dev_dbg(kfd_device, "no function\n");
3294 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
3295 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
3296 * more priviledged access.
3298 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
3299 if (!capable(CAP_CHECKPOINT_RESTORE) &&
3300 !capable(CAP_SYS_ADMIN)) {
3306 if (cmd & (IOC_IN | IOC_OUT)) {
3307 if (asize <= sizeof(stack_kdata)) {
3308 kdata = stack_kdata;
3310 kdata = kmalloc(asize, GFP_KERNEL);
3317 memset(kdata + usize, 0, asize - usize);
3321 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
3325 } else if (cmd & IOC_OUT) {
3326 memset(kdata, 0, usize);
3329 retcode = func(filep, process, kdata);
3332 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
3337 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
3338 task_pid_nr(current), cmd, nr);
3340 if (kdata != stack_kdata)
3344 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
3350 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
3351 struct vm_area_struct *vma)
3353 phys_addr_t address;
3355 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3358 if (PAGE_SIZE > 4096)
3361 address = dev->adev->rmmio_remap.bus_addr;
3363 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
3364 VM_DONTDUMP | VM_PFNMAP);
3366 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3368 pr_debug("pasid 0x%x mapping mmio page\n"
3369 " target user address == 0x%08llX\n"
3370 " physical address == 0x%08llX\n"
3371 " vm_flags == 0x%04lX\n"
3372 " size == 0x%04lX\n",
3373 process->pasid, (unsigned long long) vma->vm_start,
3374 address, vma->vm_flags, PAGE_SIZE);
3376 return io_remap_pfn_range(vma,
3378 address >> PAGE_SHIFT,
3384 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
3386 struct kfd_process *process;
3387 struct kfd_node *dev = NULL;
3388 unsigned long mmap_offset;
3389 unsigned int gpu_id;
3391 process = kfd_get_process(current);
3392 if (IS_ERR(process))
3393 return PTR_ERR(process);
3395 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
3396 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
3398 dev = kfd_device_by_id(gpu_id);
3400 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
3401 case KFD_MMAP_TYPE_DOORBELL:
3404 return kfd_doorbell_mmap(dev, process, vma);
3406 case KFD_MMAP_TYPE_EVENTS:
3407 return kfd_event_mmap(process, vma);
3409 case KFD_MMAP_TYPE_RESERVED_MEM:
3412 return kfd_reserved_mem_mmap(dev, process, vma);
3413 case KFD_MMAP_TYPE_MMIO:
3416 return kfd_mmio_mmap(dev, process, vma);